drivers/gpu/drm/vc4/vc4_vec.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2016 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 SDTV module
   8  *
   9  * The VEC encoder generates PAL or NTSC composite video output.
  10  *
  11  * TV mode selection is done by an atomic property on the encoder,
  12  * because a drm_mode_modeinfo is insufficient to distinguish between
  13  * PAL and PAL-M or NTSC and NTSC-J.
  14  */
  15
  16 #include <drm/drm_atomic_helper.h>
  17 #include <drm/drm_drv.h>
  18 #include <drm/drm_edid.h>
  19 #include <drm/drm_panel.h>
  20 #include <drm/drm_probe_helper.h>
  21 #include <drm/drm_simple_kms_helper.h>
  22 #include <linux/clk.h>
  23 #include <linux/component.h>
  24 #include <linux/of_graph.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/pm_runtime.h>
  27
  28 #include "vc4_drv.h"
  29 #include "vc4_regs.h"
  30
  31 /* WSE Registers */
  32 #define VEC_WSE_RESET                   0xc0
  33
  34 #define VEC_WSE_CONTROL                 0xc4
  35 #define VEC_WSE_WSS_ENABLE              BIT(7)
  36
  37 #define VEC_WSE_WSS_DATA                0xc8
  38 #define VEC_WSE_VPS_DATA1               0xcc
  39 #define VEC_WSE_VPS_CONTROL             0xd0
  40
  41 /* VEC Registers */
  42 #define VEC_REVID                       0x100
  43
  44 #define VEC_CONFIG0                     0x104
  45 #define VEC_CONFIG0_YDEL_MASK           GENMASK(28, 26)
  46 #define VEC_CONFIG0_YDEL(x)             ((x) << 26)
  47 #define VEC_CONFIG0_CDEL_MASK           GENMASK(25, 24)
  48 #define VEC_CONFIG0_CDEL(x)             ((x) << 24)
  49 #define VEC_CONFIG0_SECAM_STD           BIT(21)
  50 #define VEC_CONFIG0_PBPR_FIL            BIT(18)
  51 #define VEC_CONFIG0_CHROMA_GAIN_MASK    GENMASK(17, 16)
  52 #define VEC_CONFIG0_CHROMA_GAIN_UNITY   (0 << 16)
  53 #define VEC_CONFIG0_CHROMA_GAIN_1_32    (1 << 16)
  54 #define VEC_CONFIG0_CHROMA_GAIN_1_16    (2 << 16)
  55 #define VEC_CONFIG0_CHROMA_GAIN_1_8     (3 << 16)
  56 #define VEC_CONFIG0_CBURST_GAIN_MASK    GENMASK(14, 13)
  57 #define VEC_CONFIG0_CBURST_GAIN_UNITY   (0 << 13)
  58 #define VEC_CONFIG0_CBURST_GAIN_1_128   (1 << 13)
  59 #define VEC_CONFIG0_CBURST_GAIN_1_64    (2 << 13)
  60 #define VEC_CONFIG0_CBURST_GAIN_1_32    (3 << 13)
  61 #define VEC_CONFIG0_CHRBW1              BIT(11)
  62 #define VEC_CONFIG0_CHRBW0              BIT(10)
  63 #define VEC_CONFIG0_SYNCDIS             BIT(9)
  64 #define VEC_CONFIG0_BURDIS              BIT(8)
  65 #define VEC_CONFIG0_CHRDIS              BIT(7)
  66 #define VEC_CONFIG0_PDEN                BIT(6)
  67 #define VEC_CONFIG0_YCDELAY             BIT(4)
  68 #define VEC_CONFIG0_RAMPEN              BIT(2)
  69 #define VEC_CONFIG0_YCDIS               BIT(2)
  70 #define VEC_CONFIG0_STD_MASK            (VEC_CONFIG0_SECAM_STD | GENMASK(1, 0))
  71 #define VEC_CONFIG0_NTSC_STD            0
  72 #define VEC_CONFIG0_PAL_BDGHI_STD       1
  73 #define VEC_CONFIG0_PAL_M_STD           2
  74 #define VEC_CONFIG0_PAL_N_STD           3
  75
  76 #define VEC_SCHPH                       0x108
  77 #define VEC_SOFT_RESET                  0x10c
  78 #define VEC_CLMP0_START                 0x144
  79 #define VEC_CLMP0_END                   0x148
  80
  81 /*
  82  * These set the color subcarrier frequency
  83  * if VEC_CONFIG1_CUSTOM_FREQ is enabled.
  84  *
  85  * VEC_FREQ1_0 contains the most significant 16-bit half-word,
  86  * VEC_FREQ3_2 contains the least significant 16-bit half-word.
  87  * 0x80000000 seems to be equivalent to the pixel clock
  88  * (which itself is the VEC clock divided by 8).
  89  *
  90  * Reference values (with the default pixel clock of 13.5 MHz):
  91  *
  92  * NTSC  (3579545.[45] Hz)     - 0x21F07C1F
  93  * PAL   (4433618.75 Hz)       - 0x2A098ACB
  94  * PAL-M (3575611.[888111] Hz) - 0x21E6EFE3
  95  * PAL-N (3582056.25 Hz)       - 0x21F69446
  96  *
  97  * NOTE: For SECAM, it is used as the Dr center frequency,
  98  * regardless of whether VEC_CONFIG1_CUSTOM_FREQ is enabled or not;
  99  * that is specified as 4406250 Hz, which corresponds to 0x29C71C72.
 100  */
 101 #define VEC_FREQ3_2                     0x180
 102 #define VEC_FREQ1_0                     0x184
 103
 104 #define VEC_CONFIG1                     0x188
 105 #define VEC_CONFIG_VEC_RESYNC_OFF       BIT(18)
 106 #define VEC_CONFIG_RGB219               BIT(17)
 107 #define VEC_CONFIG_CBAR_EN              BIT(16)
 108 #define VEC_CONFIG_TC_OBB               BIT(15)
 109 #define VEC_CONFIG1_OUTPUT_MODE_MASK    GENMASK(12, 10)
 110 #define VEC_CONFIG1_C_Y_CVBS            (0 << 10)
 111 #define VEC_CONFIG1_CVBS_Y_C            (1 << 10)
 112 #define VEC_CONFIG1_PR_Y_PB             (2 << 10)
 113 #define VEC_CONFIG1_RGB                 (4 << 10)
 114 #define VEC_CONFIG1_Y_C_CVBS            (5 << 10)
 115 #define VEC_CONFIG1_C_CVBS_Y            (6 << 10)
 116 #define VEC_CONFIG1_C_CVBS_CVBS         (7 << 10)
 117 #define VEC_CONFIG1_DIS_CHR             BIT(9)
 118 #define VEC_CONFIG1_DIS_LUMA            BIT(8)
 119 #define VEC_CONFIG1_YCBCR_IN            BIT(6)
 120 #define VEC_CONFIG1_DITHER_TYPE_LFSR    0
 121 #define VEC_CONFIG1_DITHER_TYPE_COUNTER BIT(5)
 122 #define VEC_CONFIG1_DITHER_EN           BIT(4)
 123 #define VEC_CONFIG1_CYDELAY             BIT(3)
 124 #define VEC_CONFIG1_LUMADIS             BIT(2)
 125 #define VEC_CONFIG1_COMPDIS             BIT(1)
 126 #define VEC_CONFIG1_CUSTOM_FREQ         BIT(0)
 127
 128 #define VEC_CONFIG2                     0x18c
 129 #define VEC_CONFIG2_PROG_SCAN           BIT(15)
 130 #define VEC_CONFIG2_SYNC_ADJ_MASK       GENMASK(14, 12)
 131 #define VEC_CONFIG2_SYNC_ADJ(x)         (((x) / 2) << 12)
 132 #define VEC_CONFIG2_PBPR_EN             BIT(10)
 133 #define VEC_CONFIG2_UV_DIG_DIS          BIT(6)
 134 #define VEC_CONFIG2_RGB_DIG_DIS         BIT(5)
 135 #define VEC_CONFIG2_TMUX_MASK           GENMASK(3, 2)
 136 #define VEC_CONFIG2_TMUX_DRIVE0         (0 << 2)
 137 #define VEC_CONFIG2_TMUX_RG_COMP        (1 << 2)
 138 #define VEC_CONFIG2_TMUX_UV_YC          (2 << 2)
 139 #define VEC_CONFIG2_TMUX_SYNC_YC        (3 << 2)
 140
 141 #define VEC_INTERRUPT_CONTROL           0x190
 142 #define VEC_INTERRUPT_STATUS            0x194
 143
 144 /*
 145  * Db center frequency for SECAM; the clock for this is the same as for
 146  * VEC_FREQ3_2/VEC_FREQ1_0, which is used for Dr center frequency.
 147  *
 148  * This is specified as 4250000 Hz, which corresponds to 0x284BDA13.
 149  * That is also the default value, so no need to set it explicitly.
 150  */
 151 #define VEC_FCW_SECAM_B                 0x198
 152 #define VEC_SECAM_GAIN_VAL              0x19c
 153
 154 #define VEC_CONFIG3                     0x1a0
 155 #define VEC_CONFIG3_HORIZ_LEN_STD       (0 << 0)
 156 #define VEC_CONFIG3_HORIZ_LEN_MPEG1_SIF (1 << 0)
 157 #define VEC_CONFIG3_SHAPE_NON_LINEAR    BIT(1)
 158
 159 #define VEC_STATUS0                     0x200
 160 #define VEC_MASK0                       0x204
 161
 162 #define VEC_CFG                         0x208
 163 #define VEC_CFG_SG_MODE_MASK            GENMASK(6, 5)
 164 #define VEC_CFG_SG_MODE(x)              ((x) << 5)
 165 #define VEC_CFG_SG_EN                   BIT(4)
 166 #define VEC_CFG_VEC_EN                  BIT(3)
 167 #define VEC_CFG_MB_EN                   BIT(2)
 168 #define VEC_CFG_ENABLE                  BIT(1)
 169 #define VEC_CFG_TB_EN                   BIT(0)
 170
 171 #define VEC_DAC_TEST                    0x20c
 172
 173 #define VEC_DAC_CONFIG                  0x210
 174 #define VEC_DAC_CONFIG_LDO_BIAS_CTRL(x) ((x) << 24)
 175 #define VEC_DAC_CONFIG_DRIVER_CTRL(x)   ((x) << 16)
 176 #define VEC_DAC_CONFIG_DAC_CTRL(x)      (x)
 177
 178 #define VEC_DAC_MISC                    0x214
 179 #define VEC_DAC_MISC_VCD_CTRL_MASK      GENMASK(31, 16)
 180 #define VEC_DAC_MISC_VCD_CTRL(x)        ((x) << 16)
 181 #define VEC_DAC_MISC_VID_ACT            BIT(8)
 182 #define VEC_DAC_MISC_VCD_PWRDN          BIT(6)
 183 #define VEC_DAC_MISC_BIAS_PWRDN         BIT(5)
 184 #define VEC_DAC_MISC_DAC_PWRDN          BIT(2)
 185 #define VEC_DAC_MISC_LDO_PWRDN          BIT(1)
 186 #define VEC_DAC_MISC_DAC_RST_N          BIT(0)
 187
 188
 189 static char *vc4_vec_tv_norm;
 190
 191 struct vc4_vec_variant {
 192         u32 dac_config;
 193 };
 194
 195 /* General VEC hardware state. */
 196 struct vc4_vec {
 197         struct vc4_encoder encoder;
 198         struct drm_connector connector;
 199
 200         struct platform_device *pdev;
 201         const struct vc4_vec_variant *variant;
 202
 203         void __iomem *regs;
 204
 205         struct clk *clock;
 206
 207         struct debugfs_regset32 regset;
 208 };
 209
 210 #define VEC_READ(offset) readl(vec->regs + (offset))
 211 #define VEC_WRITE(offset, val) writel(val, vec->regs + (offset))
 212
 213 static inline struct vc4_vec *
 214 encoder_to_vc4_vec(struct drm_encoder *encoder)
 215 {
 216         return container_of(encoder, struct vc4_vec, encoder.base);
 217 }
 218
 219 enum vc4_vec_tv_mode_id {
 220         VC4_VEC_TV_MODE_NTSC,
 221         VC4_VEC_TV_MODE_NTSC_J,
 222         VC4_VEC_TV_MODE_NTSC_443,
 223         VC4_VEC_TV_MODE_PAL,
 224         VC4_VEC_TV_MODE_PAL_M,
 225         VC4_VEC_TV_MODE_PAL_N,
 226         VC4_VEC_TV_MODE_PAL60,
 227         VC4_VEC_TV_MODE_SECAM,
 228 };
 229
 230 struct vc4_vec_tv_mode {
 231         const struct drm_display_mode *interlaced_mode;
 232         const struct drm_display_mode *progressive_mode;
 233         u32 config0;
 234         u32 config1;
 235         u32 custom_freq;
 236 };
 237
 238 static const struct debugfs_reg32 vec_regs[] = {
 239         VC4_REG32(VEC_WSE_CONTROL),
 240         VC4_REG32(VEC_WSE_WSS_DATA),
 241         VC4_REG32(VEC_WSE_VPS_DATA1),
 242         VC4_REG32(VEC_WSE_VPS_CONTROL),
 243         VC4_REG32(VEC_REVID),
 244         VC4_REG32(VEC_CONFIG0),
 245         VC4_REG32(VEC_SCHPH),
 246         VC4_REG32(VEC_CLMP0_START),
 247         VC4_REG32(VEC_CLMP0_END),
 248         VC4_REG32(VEC_FREQ3_2),
 249         VC4_REG32(VEC_FREQ1_0),
 250         VC4_REG32(VEC_CONFIG1),
 251         VC4_REG32(VEC_CONFIG2),
 252         VC4_REG32(VEC_INTERRUPT_CONTROL),
 253         VC4_REG32(VEC_INTERRUPT_STATUS),
 254         VC4_REG32(VEC_FCW_SECAM_B),
 255         VC4_REG32(VEC_SECAM_GAIN_VAL),
 256         VC4_REG32(VEC_CONFIG3),
 257         VC4_REG32(VEC_STATUS0),
 258         VC4_REG32(VEC_MASK0),
 259         VC4_REG32(VEC_CFG),
 260         VC4_REG32(VEC_DAC_TEST),
 261         VC4_REG32(VEC_DAC_CONFIG),
 262         VC4_REG32(VEC_DAC_MISC),
 263 };
 264
 265 static const struct drm_display_mode drm_mode_480i = {
 266         DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500,
 267                  720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0,
 268                  480, 480 + 7, 480 + 7 + 6, 525, 0,
 269                  DRM_MODE_FLAG_INTERLACE)
 270 };
 271
 272 static const struct drm_display_mode drm_mode_240p = {
 273         DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500,
 274                  720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0,
 275                  240, 240 + 3, 240 + 3 + 3, 262, 0, 0)
 276 };
 277
 278 static const struct drm_display_mode drm_mode_576i = {
 279         DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500,
 280                  720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0,
 281                  576, 576 + 4, 576 + 4 + 6, 625, 0,
 282                  DRM_MODE_FLAG_INTERLACE)
 283 };
 284
 285 static const struct drm_display_mode drm_mode_288p = {
 286         DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500,
 287                  720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0,
 288                  288, 288 + 2, 288 + 2 + 3, 312, 0, 0)
 289 };
 290
 291 static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {
 292         [VC4_VEC_TV_MODE_NTSC] = {
 293                 .interlaced_mode = &drm_mode_480i,
 294                 .progressive_mode = &drm_mode_240p,
 295                 .config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN,
 296                 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
 297         },
 298         [VC4_VEC_TV_MODE_NTSC_J] = {
 299                 .interlaced_mode = &drm_mode_480i,
 300                 .progressive_mode = &drm_mode_240p,
 301                 .config0 = VEC_CONFIG0_NTSC_STD,
 302                 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
 303         },
 304         [VC4_VEC_TV_MODE_NTSC_443] = {
 305                 /* NTSC with PAL chroma frequency */
 306                 .interlaced_mode = &drm_mode_480i,
 307                 .progressive_mode = &drm_mode_240p,
 308                 .config0 = VEC_CONFIG0_NTSC_STD,
 309                 .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,
 310                 .custom_freq = 0x2a098acb,
 311         },
 312         [VC4_VEC_TV_MODE_PAL] = {
 313                 .interlaced_mode = &drm_mode_576i,
 314                 .progressive_mode = &drm_mode_288p,
 315                 .config0 = VEC_CONFIG0_PAL_BDGHI_STD,
 316                 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
 317         },
 318         [VC4_VEC_TV_MODE_PAL_M] = {
 319                 .interlaced_mode = &drm_mode_480i,
 320                 .progressive_mode = &drm_mode_240p,
 321                 .config0 = VEC_CONFIG0_PAL_M_STD,
 322                 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
 323         },
 324         [VC4_VEC_TV_MODE_PAL_N] = {
 325                 .interlaced_mode = &drm_mode_576i,
 326                 .progressive_mode = &drm_mode_288p,
 327                 .config0 = VEC_CONFIG0_PAL_N_STD,
 328                 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
 329         },
 330         [VC4_VEC_TV_MODE_PAL60] = {
 331                 /* PAL-M with chroma frequency of regular PAL */
 332                 .interlaced_mode = &drm_mode_480i,
 333                 .progressive_mode = &drm_mode_240p,
 334                 .config0 = VEC_CONFIG0_PAL_M_STD,
 335                 .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,
 336                 .custom_freq = 0x2a098acb,
 337         },
 338         [VC4_VEC_TV_MODE_SECAM] = {
 339                 .interlaced_mode = &drm_mode_576i,
 340                 .progressive_mode = &drm_mode_288p,
 341                 .config0 = VEC_CONFIG0_SECAM_STD,
 342                 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
 343                 .custom_freq = 0x29c71c72,
 344         },
 345 };
 346
 347 static const char * const tv_mode_names[] = {
 348         [VC4_VEC_TV_MODE_NTSC] = "NTSC",
 349         [VC4_VEC_TV_MODE_NTSC_J] = "NTSC-J",
 350         [VC4_VEC_TV_MODE_NTSC_443] = "NTSC-443",
 351         [VC4_VEC_TV_MODE_PAL] = "PAL",
 352         [VC4_VEC_TV_MODE_PAL_M] = "PAL-M",
 353         [VC4_VEC_TV_MODE_PAL_N] = "PAL-N",
 354         [VC4_VEC_TV_MODE_PAL60] = "PAL60",
 355         [VC4_VEC_TV_MODE_SECAM] = "SECAM",
 356 };
 357
 358 enum vc4_vec_tv_mode_id
 359 vc4_vec_get_default_mode(struct drm_connector *connector)
 360 {
 361         int i;
 362
 363         if (vc4_vec_tv_norm) {
 364                 for (i = 0; i < ARRAY_SIZE(tv_mode_names); i++)
 365                         if (strcmp(vc4_vec_tv_norm, tv_mode_names[i]) == 0)
 366                                 return (enum vc4_vec_tv_mode_id) i;
 367         } else if (connector->cmdline_mode.specified &&
 368                    ((connector->cmdline_mode.refresh_specified &&
 369                      (connector->cmdline_mode.refresh == 25 ||
 370                       connector->cmdline_mode.refresh == 50)) ||
 371                     (!connector->cmdline_mode.refresh_specified &&
 372                      (connector->cmdline_mode.yres == 288 ||
 373                       connector->cmdline_mode.yres == 576)))) {
 374                 /*
 375                  * no explicitly specified TV norm; use PAL if a mode that
 376                  * looks like PAL has been specified on the command line
 377                  */
 378                 return VC4_VEC_TV_MODE_PAL;
 379         }
 380
 381         /* in all other cases, default to NTSC */
 382         return VC4_VEC_TV_MODE_NTSC;
 383 }
 384
 385 static enum drm_connector_status
 386 vc4_vec_connector_detect(struct drm_connector *connector, bool force)
 387 {
 388         return connector_status_unknown;
 389 }
 390
 391 static int vc4_vec_connector_get_modes(struct drm_connector *connector)
 392 {
 393         struct drm_connector_state *state = connector->state;
 394         struct drm_display_mode *interlaced_mode, *progressive_mode;
 395
 396         interlaced_mode =
 397                 drm_mode_duplicate(connector->dev,
 398                                    vc4_vec_tv_modes[state->tv.mode].interlaced_mode);
 399         progressive_mode =
 400                 drm_mode_duplicate(connector->dev,
 401                                    vc4_vec_tv_modes[state->tv.mode].progressive_mode);
 402         if (!interlaced_mode || !progressive_mode) {
 403                 DRM_ERROR("Failed to create a new display mode\n");
 404                 drm_mode_destroy(connector->dev, interlaced_mode);
 405                 drm_mode_destroy(connector->dev, progressive_mode);
 406                 return -ENOMEM;
 407         }
 408
 409         if (connector->cmdline_mode.specified &&
 410             connector->cmdline_mode.refresh_specified &&
 411             !connector->cmdline_mode.interlace)
 412                 /* progressive mode set at boot, let's make it preferred */
 413                 progressive_mode->type |= DRM_MODE_TYPE_PREFERRED;
 414         else
 415                 /* otherwise, interlaced mode is preferred */
 416                 interlaced_mode->type |= DRM_MODE_TYPE_PREFERRED;
 417
 418         drm_mode_probed_add(connector, interlaced_mode);
 419         drm_mode_probed_add(connector, progressive_mode);
 420
 421         return 1;
 422 }
 423
 424 static void vc4_vec_connector_reset(struct drm_connector *connector)
 425 {
 426         drm_atomic_helper_connector_reset(connector);
 427         /* preserve TV standard */
 428         if (connector->state)
 429                 connector->state->tv.mode = vc4_vec_get_default_mode(connector);
 430 }
 431
 432 static int vc4_vec_connector_atomic_check(struct drm_connector *conn,
 433                                           struct drm_atomic_state *state)
 434 {
 435         struct drm_connector_state *old_state =
 436                 drm_atomic_get_old_connector_state(state, conn);
 437         struct drm_connector_state *new_state =
 438                 drm_atomic_get_new_connector_state(state, conn);
 439
 440         if (new_state->crtc && old_state->tv.mode != new_state->tv.mode) {
 441                 struct drm_crtc_state *crtc_state =
 442                         drm_atomic_get_new_crtc_state(state, new_state->crtc);
 443
 444                 crtc_state->mode_changed = true;
 445         }
 446
 447         return 0;
 448 }
 449
 450 static const struct drm_connector_funcs vc4_vec_connector_funcs = {
 451         .detect = vc4_vec_connector_detect,
 452         .fill_modes = drm_helper_probe_single_connector_modes,
 453         .reset = vc4_vec_connector_reset,
 454         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 455         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 456 };
 457
 458 static const struct drm_connector_helper_funcs vc4_vec_connector_helper_funcs = {
 459         .get_modes = vc4_vec_connector_get_modes,
 460         .atomic_check = vc4_vec_connector_atomic_check,
 461 };
 462
 463 static int vc4_vec_connector_init(struct drm_device *dev, struct vc4_vec *vec)
 464 {
 465         struct drm_connector *connector = &vec->connector;
 466         int ret;
 467
 468         connector->interlace_allowed = true;
 469
 470         ret = drmm_connector_init(dev, connector, &vc4_vec_connector_funcs,
 471                                  DRM_MODE_CONNECTOR_Composite, NULL);
 472         if (ret)
 473                 return ret;
 474
 475         drm_connector_helper_add(connector, &vc4_vec_connector_helper_funcs);
 476
 477         drm_object_attach_property(&connector->base,
 478                                    dev->mode_config.tv_mode_property,
 479                                    vc4_vec_get_default_mode(connector));
 480
 481         drm_connector_attach_encoder(connector, &vec->encoder.base);
 482
 483         return 0;
 484 }
 485
 486 static void vc4_vec_encoder_disable(struct drm_encoder *encoder)
 487 {
 488         struct drm_device *drm = encoder->dev;
 489         struct vc4_vec *vec = encoder_to_vc4_vec(encoder);
 490         int idx, ret;
 491
 492         if (!drm_dev_enter(drm, &idx))
 493                 return;
 494
 495         VEC_WRITE(VEC_CFG, 0);
 496         VEC_WRITE(VEC_DAC_MISC,
 497                   VEC_DAC_MISC_VCD_PWRDN |
 498                   VEC_DAC_MISC_BIAS_PWRDN |
 499                   VEC_DAC_MISC_DAC_PWRDN |
 500                   VEC_DAC_MISC_LDO_PWRDN);
 501
 502         clk_disable_unprepare(vec->clock);
 503
 504         ret = pm_runtime_put(&vec->pdev->dev);
 505         if (ret < 0) {
 506                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 507                 goto err_dev_exit;
 508         }
 509
 510         drm_dev_exit(idx);
 511         return;
 512
 513 err_dev_exit:
 514         drm_dev_exit(idx);
 515 }
 516
 517 static void vc4_vec_encoder_enable(struct drm_encoder *encoder)
 518 {
 519         struct drm_device *drm = encoder->dev;
 520         struct vc4_vec *vec = encoder_to_vc4_vec(encoder);
 521         unsigned int tv_mode = vec->connector.state->tv.mode;
 522         int idx, ret;
 523
 524         if (!drm_dev_enter(drm, &idx))
 525                 return;
 526
 527         ret = pm_runtime_get_sync(&vec->pdev->dev);
 528         if (ret < 0) {
 529                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
 530                 goto err_dev_exit;
 531         }
 532
 533         /*
 534          * We need to set the clock rate each time we enable the encoder
 535          * because there's a chance we share the same parent with the HDMI
 536          * clock, and both drivers are requesting different rates.
 537          * The good news is, these 2 encoders cannot be enabled at the same
 538          * time, thus preventing incompatible rate requests.
 539          */
 540         ret = clk_set_rate(vec->clock, 108000000);
 541         if (ret) {
 542                 DRM_ERROR("Failed to set clock rate: %d\n", ret);
 543                 goto err_put_runtime_pm;
 544         }
 545
 546         ret = clk_prepare_enable(vec->clock);
 547         if (ret) {
 548                 DRM_ERROR("Failed to turn on core clock: %d\n", ret);
 549                 goto err_put_runtime_pm;
 550         }
 551
 552         /* Reset the different blocks */
 553         VEC_WRITE(VEC_WSE_RESET, 1);
 554         VEC_WRITE(VEC_SOFT_RESET, 1);
 555
 556         /* Disable the CGSM-A and WSE blocks */
 557         VEC_WRITE(VEC_WSE_CONTROL, 0);
 558
 559         /* Write config common to all modes. */
 560
 561         /*
 562          * Color subcarrier phase: phase = 360 * SCHPH / 256.
 563          * 0x28 <=> 39.375 deg.
 564          */
 565         VEC_WRITE(VEC_SCHPH, 0x28);
 566
 567         /*
 568          * Reset to default values.
 569          */
 570         VEC_WRITE(VEC_CLMP0_START, 0xac);
 571         VEC_WRITE(VEC_CLMP0_END, 0xec);
 572         VEC_WRITE(VEC_CONFIG2,
 573                   VEC_CONFIG2_UV_DIG_DIS |
 574                   VEC_CONFIG2_RGB_DIG_DIS |
 575                   ((encoder->crtc->state->adjusted_mode.flags &
 576                     DRM_MODE_FLAG_INTERLACE) ? 0 : VEC_CONFIG2_PROG_SCAN));
 577         VEC_WRITE(VEC_CONFIG3, VEC_CONFIG3_HORIZ_LEN_STD);
 578         VEC_WRITE(VEC_DAC_CONFIG, vec->variant->dac_config);
 579
 580         /* Mask all interrupts. */
 581         VEC_WRITE(VEC_MASK0, 0);
 582
 583         VEC_WRITE(VEC_CONFIG0, vc4_vec_tv_modes[tv_mode].config0);
 584         VEC_WRITE(VEC_CONFIG1, vc4_vec_tv_modes[tv_mode].config1);
 585         if (vc4_vec_tv_modes[tv_mode].custom_freq != 0) {
 586                 VEC_WRITE(VEC_FREQ3_2,
 587                           (vc4_vec_tv_modes[tv_mode].custom_freq >> 16) &
 588                           0xffff);
 589                 VEC_WRITE(VEC_FREQ1_0,
 590                           vc4_vec_tv_modes[tv_mode].custom_freq & 0xffff);
 591         }
 592
 593         VEC_WRITE(VEC_DAC_MISC,
 594                   VEC_DAC_MISC_VID_ACT | VEC_DAC_MISC_DAC_RST_N);
 595         VEC_WRITE(VEC_CFG, VEC_CFG_VEC_EN);
 596
 597         drm_dev_exit(idx);
 598         return;
 599
 600 err_put_runtime_pm:
 601         pm_runtime_put(&vec->pdev->dev);
 602 err_dev_exit:
 603         drm_dev_exit(idx);
 604 }
 605
 606 static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder,
 607                                         struct drm_crtc_state *crtc_state,
 608                                         struct drm_connector_state *conn_state)
 609 {
 610         const struct drm_display_mode *reference_mode =
 611                 vc4_vec_tv_modes[conn_state->tv.mode].interlaced_mode;
 612
 613         if (crtc_state->adjusted_mode.crtc_clock != reference_mode->clock ||
 614             crtc_state->adjusted_mode.crtc_htotal != reference_mode->htotal ||
 615             crtc_state->adjusted_mode.crtc_hdisplay % 4 != 0 ||
 616             crtc_state->adjusted_mode.crtc_hsync_end -
 617                     crtc_state->adjusted_mode.crtc_hsync_start < 1)
 618                 return -EINVAL;
 619
 620         switch (reference_mode->vtotal) {
 621         case 525:
 622                 if (crtc_state->adjusted_mode.crtc_vdisplay < 1 ||
 623                     crtc_state->adjusted_mode.crtc_vdisplay > 253 ||
 624                     crtc_state->adjusted_mode.crtc_vsync_start -
 625                             crtc_state->adjusted_mode.crtc_vdisplay < 1 ||
 626                     crtc_state->adjusted_mode.crtc_vsync_end -
 627                             crtc_state->adjusted_mode.crtc_vsync_start != 3 ||
 628                     crtc_state->adjusted_mode.crtc_vtotal -
 629                             crtc_state->adjusted_mode.crtc_vsync_end < 4 ||
 630                     crtc_state->adjusted_mode.crtc_vtotal > 262)
 631                         return -EINVAL;
 632
 633                 if ((crtc_state->adjusted_mode.flags &
 634                      DRM_MODE_FLAG_INTERLACE) &&
 635                     (crtc_state->adjusted_mode.vdisplay % 2 != 0 ||
 636                      crtc_state->adjusted_mode.vsync_start % 2 != 1 ||
 637                      crtc_state->adjusted_mode.vsync_end % 2 != 1 ||
 638                      crtc_state->adjusted_mode.vtotal % 2 != 1))
 639                         return -EINVAL;
 640
 641                 /* progressive mode is hard-wired to 262 total lines */
 642                 if (!(crtc_state->adjusted_mode.flags &
 643                       DRM_MODE_FLAG_INTERLACE) &&
 644                     crtc_state->adjusted_mode.crtc_vtotal != 262)
 645                         return -EINVAL;
 646
 647                 break;
 648
 649         case 625:
 650                 if (crtc_state->adjusted_mode.crtc_vdisplay < 1 ||
 651                     crtc_state->adjusted_mode.crtc_vdisplay > 305 ||
 652                     crtc_state->adjusted_mode.crtc_vsync_start -
 653                             crtc_state->adjusted_mode.crtc_vdisplay < 1 ||
 654                     crtc_state->adjusted_mode.crtc_vsync_end -
 655                             crtc_state->adjusted_mode.crtc_vsync_start != 3 ||
 656                     crtc_state->adjusted_mode.crtc_vtotal -
 657                             crtc_state->adjusted_mode.crtc_vsync_end < 2 ||
 658                     crtc_state->adjusted_mode.crtc_vtotal > 312)
 659                         return -EINVAL;
 660
 661                 if ((crtc_state->adjusted_mode.flags &
 662                      DRM_MODE_FLAG_INTERLACE) &&
 663                     (crtc_state->adjusted_mode.vdisplay % 2 != 0 ||
 664                      crtc_state->adjusted_mode.vsync_start % 2 != 0 ||
 665                      crtc_state->adjusted_mode.vsync_end % 2 != 0 ||
 666                      crtc_state->adjusted_mode.vtotal % 2 != 1))
 667                         return -EINVAL;
 668
 669                 /* progressive mode is hard-wired to 312 total lines */
 670                 if (!(crtc_state->adjusted_mode.flags &
 671                       DRM_MODE_FLAG_INTERLACE) &&
 672                     crtc_state->adjusted_mode.crtc_vtotal != 312)
 673                         return -EINVAL;
 674
 675                 break;
 676
 677         default:
 678                 return -EINVAL;
 679         }
 680
 681         return 0;
 682 }
 683
 684 static const struct drm_encoder_helper_funcs vc4_vec_encoder_helper_funcs = {
 685         .disable = vc4_vec_encoder_disable,
 686         .enable = vc4_vec_encoder_enable,
 687         .atomic_check = vc4_vec_encoder_atomic_check,
 688 };
 689
 690 static int vc4_vec_late_register(struct drm_encoder *encoder)
 691 {
 692         struct drm_device *drm = encoder->dev;
 693         struct vc4_vec *vec = encoder_to_vc4_vec(encoder);
 694         int ret;
 695
 696         ret = vc4_debugfs_add_regset32(drm->primary, "vec_regs",
 697                                        &vec->regset);
 698         if (ret)
 699                 return ret;
 700
 701         return 0;
 702 }
 703
 704 static const struct drm_encoder_funcs vc4_vec_encoder_funcs = {
 705         .late_register = vc4_vec_late_register,
 706 };
 707
 708 static const struct vc4_vec_variant bcm2835_vec_variant = {
 709         .dac_config = VEC_DAC_CONFIG_DAC_CTRL(0xc) |
 710                       VEC_DAC_CONFIG_DRIVER_CTRL(0xc) |
 711                       VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x46)
 712 };
 713
 714 static const struct vc4_vec_variant bcm2711_vec_variant = {
 715         .dac_config = VEC_DAC_CONFIG_DAC_CTRL(0x0) |
 716                       VEC_DAC_CONFIG_DRIVER_CTRL(0x80) |
 717                       VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x61)
 718 };
 719
 720 static const struct of_device_id vc4_vec_dt_match[] = {
 721         { .compatible = "brcm,bcm2835-vec", .data = &bcm2835_vec_variant },
 722         { .compatible = "brcm,bcm2711-vec", .data = &bcm2711_vec_variant },
 723         { /* sentinel */ },
 724 };
 725
 726 static int vc4_vec_bind(struct device *dev, struct device *master, void *data)
 727 {
 728         struct platform_device *pdev = to_platform_device(dev);
 729         struct drm_device *drm = dev_get_drvdata(master);
 730         struct vc4_vec *vec;
 731         int ret;
 732
 733         ret = drm_mode_create_tv_properties(drm, ARRAY_SIZE(tv_mode_names),
 734                                             tv_mode_names);
 735         if (ret)
 736                 return ret;
 737
 738         vec = drmm_kzalloc(drm, sizeof(*vec), GFP_KERNEL);
 739         if (!vec)
 740                 return -ENOMEM;
 741
 742         vec->encoder.type = VC4_ENCODER_TYPE_VEC;
 743         vec->pdev = pdev;
 744         vec->variant = (const struct vc4_vec_variant *)
 745                 of_device_get_match_data(dev);
 746         vec->regs = vc4_ioremap_regs(pdev, 0);
 747         if (IS_ERR(vec->regs))
 748                 return PTR_ERR(vec->regs);
 749         vec->regset.base = vec->regs;
 750         vec->regset.regs = vec_regs;
 751         vec->regset.nregs = ARRAY_SIZE(vec_regs);
 752
 753         vec->clock = devm_clk_get(dev, NULL);
 754         if (IS_ERR(vec->clock)) {
 755                 ret = PTR_ERR(vec->clock);
 756                 if (ret != -EPROBE_DEFER)
 757                         DRM_ERROR("Failed to get clock: %d\n", ret);
 758                 return ret;
 759         }
 760
 761         ret = devm_pm_runtime_enable(dev);
 762         if (ret)
 763                 return ret;
 764
 765         ret = drmm_encoder_init(drm, &vec->encoder.base,
 766                                 &vc4_vec_encoder_funcs,
 767                                 DRM_MODE_ENCODER_TVDAC,
 768                                 NULL);
 769         if (ret)
 770                 return ret;
 771
 772         drm_encoder_helper_add(&vec->encoder.base, &vc4_vec_encoder_helper_funcs);
 773
 774         ret = vc4_vec_connector_init(drm, vec);
 775         if (ret)
 776                 return ret;
 777
 778         dev_set_drvdata(dev, vec);
 779
 780         return 0;
 781 }
 782
 783 static const struct component_ops vc4_vec_ops = {
 784         .bind   = vc4_vec_bind,
 785 };
 786
 787 static int vc4_vec_dev_probe(struct platform_device *pdev)
 788 {
 789         return component_add(&pdev->dev, &vc4_vec_ops);
 790 }
 791
 792 static int vc4_vec_dev_remove(struct platform_device *pdev)
 793 {
 794         component_del(&pdev->dev, &vc4_vec_ops);
 795         return 0;
 796 }
 797
 798 struct platform_driver vc4_vec_driver = {
 799         .probe = vc4_vec_dev_probe,
 800         .remove = vc4_vec_dev_remove,
 801         .driver = {
 802                 .name = "vc4_vec",
 803                 .of_match_table = vc4_vec_dt_match,
 804         },
 805 };
 806
 807 module_param_named(tv_norm, vc4_vec_tv_norm, charp, 0600);
 808 MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
 809                  "\t\tSupported: NTSC, NTSC-J, NTSC-443, PAL, PAL-M, PAL-N,\n"
 810                  "\t\t\tPAL60, SECAM.\n"
 811                  "\t\tDefault: PAL if a 50 Hz mode has been set via video=,\n"
 812                  "\t\t\tNTSC otherwise");