1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016 Broadcom
9 * The VEC encoder generates PAL or NTSC composite video output.
11 * TV mode selection is done by an atomic property on the encoder,
12 * because a drm_mode_modeinfo is insufficient to distinguish between
13 * PAL and PAL-M or NTSC and NTSC-J.
16 #include <drm/drm_atomic_helper.h>
17 #include <drm/drm_drv.h>
18 #include <drm/drm_edid.h>
19 #include <drm/drm_panel.h>
20 #include <drm/drm_probe_helper.h>
21 #include <drm/drm_simple_kms_helper.h>
22 #include <linux/clk.h>
23 #include <linux/component.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
32 #define VEC_WSE_RESET 0xc0
34 #define VEC_WSE_CONTROL 0xc4
35 #define VEC_WSE_WSS_ENABLE BIT(7)
37 #define VEC_WSE_WSS_DATA 0xc8
38 #define VEC_WSE_VPS_DATA1 0xcc
39 #define VEC_WSE_VPS_CONTROL 0xd0
42 #define VEC_REVID 0x100
44 #define VEC_CONFIG0 0x104
45 #define VEC_CONFIG0_YDEL_MASK GENMASK(28, 26)
46 #define VEC_CONFIG0_YDEL(x) ((x) << 26)
47 #define VEC_CONFIG0_CDEL_MASK GENMASK(25, 24)
48 #define VEC_CONFIG0_CDEL(x) ((x) << 24)
49 #define VEC_CONFIG0_SECAM_STD BIT(21)
50 #define VEC_CONFIG0_PBPR_FIL BIT(18)
51 #define VEC_CONFIG0_CHROMA_GAIN_MASK GENMASK(17, 16)
52 #define VEC_CONFIG0_CHROMA_GAIN_UNITY (0 << 16)
53 #define VEC_CONFIG0_CHROMA_GAIN_1_32 (1 << 16)
54 #define VEC_CONFIG0_CHROMA_GAIN_1_16 (2 << 16)
55 #define VEC_CONFIG0_CHROMA_GAIN_1_8 (3 << 16)
56 #define VEC_CONFIG0_CBURST_GAIN_MASK GENMASK(14, 13)
57 #define VEC_CONFIG0_CBURST_GAIN_UNITY (0 << 13)
58 #define VEC_CONFIG0_CBURST_GAIN_1_128 (1 << 13)
59 #define VEC_CONFIG0_CBURST_GAIN_1_64 (2 << 13)
60 #define VEC_CONFIG0_CBURST_GAIN_1_32 (3 << 13)
61 #define VEC_CONFIG0_CHRBW1 BIT(11)
62 #define VEC_CONFIG0_CHRBW0 BIT(10)
63 #define VEC_CONFIG0_SYNCDIS BIT(9)
64 #define VEC_CONFIG0_BURDIS BIT(8)
65 #define VEC_CONFIG0_CHRDIS BIT(7)
66 #define VEC_CONFIG0_PDEN BIT(6)
67 #define VEC_CONFIG0_YCDELAY BIT(4)
68 #define VEC_CONFIG0_RAMPEN BIT(2)
69 #define VEC_CONFIG0_YCDIS BIT(2)
70 #define VEC_CONFIG0_STD_MASK (VEC_CONFIG0_SECAM_STD | GENMASK(1, 0))
71 #define VEC_CONFIG0_NTSC_STD 0
72 #define VEC_CONFIG0_PAL_BDGHI_STD 1
73 #define VEC_CONFIG0_PAL_M_STD 2
74 #define VEC_CONFIG0_PAL_N_STD 3
76 #define VEC_SCHPH 0x108
77 #define VEC_SOFT_RESET 0x10c
78 #define VEC_CLMP0_START 0x144
79 #define VEC_CLMP0_END 0x148
82 * These set the color subcarrier frequency
83 * if VEC_CONFIG1_CUSTOM_FREQ is enabled.
85 * VEC_FREQ1_0 contains the most significant 16-bit half-word,
86 * VEC_FREQ3_2 contains the least significant 16-bit half-word.
87 * 0x80000000 seems to be equivalent to the pixel clock
88 * (which itself is the VEC clock divided by 8).
90 * Reference values (with the default pixel clock of 13.5 MHz):
92 * NTSC (3579545.[45] Hz) - 0x21F07C1F
93 * PAL (4433618.75 Hz) - 0x2A098ACB
94 * PAL-M (3575611.[888111] Hz) - 0x21E6EFE3
95 * PAL-N (3582056.25 Hz) - 0x21F69446
97 * NOTE: For SECAM, it is used as the Dr center frequency,
98 * regardless of whether VEC_CONFIG1_CUSTOM_FREQ is enabled or not;
99 * that is specified as 4406250 Hz, which corresponds to 0x29C71C72.
101 #define VEC_FREQ3_2 0x180
102 #define VEC_FREQ1_0 0x184
104 #define VEC_CONFIG1 0x188
105 #define VEC_CONFIG_VEC_RESYNC_OFF BIT(18)
106 #define VEC_CONFIG_RGB219 BIT(17)
107 #define VEC_CONFIG_CBAR_EN BIT(16)
108 #define VEC_CONFIG_TC_OBB BIT(15)
109 #define VEC_CONFIG1_OUTPUT_MODE_MASK GENMASK(12, 10)
110 #define VEC_CONFIG1_C_Y_CVBS (0 << 10)
111 #define VEC_CONFIG1_CVBS_Y_C (1 << 10)
112 #define VEC_CONFIG1_PR_Y_PB (2 << 10)
113 #define VEC_CONFIG1_RGB (4 << 10)
114 #define VEC_CONFIG1_Y_C_CVBS (5 << 10)
115 #define VEC_CONFIG1_C_CVBS_Y (6 << 10)
116 #define VEC_CONFIG1_C_CVBS_CVBS (7 << 10)
117 #define VEC_CONFIG1_DIS_CHR BIT(9)
118 #define VEC_CONFIG1_DIS_LUMA BIT(8)
119 #define VEC_CONFIG1_YCBCR_IN BIT(6)
120 #define VEC_CONFIG1_DITHER_TYPE_LFSR 0
121 #define VEC_CONFIG1_DITHER_TYPE_COUNTER BIT(5)
122 #define VEC_CONFIG1_DITHER_EN BIT(4)
123 #define VEC_CONFIG1_CYDELAY BIT(3)
124 #define VEC_CONFIG1_LUMADIS BIT(2)
125 #define VEC_CONFIG1_COMPDIS BIT(1)
126 #define VEC_CONFIG1_CUSTOM_FREQ BIT(0)
128 #define VEC_CONFIG2 0x18c
129 #define VEC_CONFIG2_PROG_SCAN BIT(15)
130 #define VEC_CONFIG2_SYNC_ADJ_MASK GENMASK(14, 12)
131 #define VEC_CONFIG2_SYNC_ADJ(x) (((x) / 2) << 12)
132 #define VEC_CONFIG2_PBPR_EN BIT(10)
133 #define VEC_CONFIG2_UV_DIG_DIS BIT(6)
134 #define VEC_CONFIG2_RGB_DIG_DIS BIT(5)
135 #define VEC_CONFIG2_TMUX_MASK GENMASK(3, 2)
136 #define VEC_CONFIG2_TMUX_DRIVE0 (0 << 2)
137 #define VEC_CONFIG2_TMUX_RG_COMP (1 << 2)
138 #define VEC_CONFIG2_TMUX_UV_YC (2 << 2)
139 #define VEC_CONFIG2_TMUX_SYNC_YC (3 << 2)
141 #define VEC_INTERRUPT_CONTROL 0x190
142 #define VEC_INTERRUPT_STATUS 0x194
145 * Db center frequency for SECAM; the clock for this is the same as for
146 * VEC_FREQ3_2/VEC_FREQ1_0, which is used for Dr center frequency.
148 * This is specified as 4250000 Hz, which corresponds to 0x284BDA13.
149 * That is also the default value, so no need to set it explicitly.
151 #define VEC_FCW_SECAM_B 0x198
152 #define VEC_SECAM_GAIN_VAL 0x19c
154 #define VEC_CONFIG3 0x1a0
155 #define VEC_CONFIG3_HORIZ_LEN_STD (0 << 0)
156 #define VEC_CONFIG3_HORIZ_LEN_MPEG1_SIF (1 << 0)
157 #define VEC_CONFIG3_SHAPE_NON_LINEAR BIT(1)
159 #define VEC_STATUS0 0x200
160 #define VEC_MASK0 0x204
162 #define VEC_CFG 0x208
163 #define VEC_CFG_SG_MODE_MASK GENMASK(6, 5)
164 #define VEC_CFG_SG_MODE(x) ((x) << 5)
165 #define VEC_CFG_SG_EN BIT(4)
166 #define VEC_CFG_VEC_EN BIT(3)
167 #define VEC_CFG_MB_EN BIT(2)
168 #define VEC_CFG_ENABLE BIT(1)
169 #define VEC_CFG_TB_EN BIT(0)
171 #define VEC_DAC_TEST 0x20c
173 #define VEC_DAC_CONFIG 0x210
174 #define VEC_DAC_CONFIG_LDO_BIAS_CTRL(x) ((x) << 24)
175 #define VEC_DAC_CONFIG_DRIVER_CTRL(x) ((x) << 16)
176 #define VEC_DAC_CONFIG_DAC_CTRL(x) (x)
178 #define VEC_DAC_MISC 0x214
179 #define VEC_DAC_MISC_VCD_CTRL_MASK GENMASK(31, 16)
180 #define VEC_DAC_MISC_VCD_CTRL(x) ((x) << 16)
181 #define VEC_DAC_MISC_VID_ACT BIT(8)
182 #define VEC_DAC_MISC_VCD_PWRDN BIT(6)
183 #define VEC_DAC_MISC_BIAS_PWRDN BIT(5)
184 #define VEC_DAC_MISC_DAC_PWRDN BIT(2)
185 #define VEC_DAC_MISC_LDO_PWRDN BIT(1)
186 #define VEC_DAC_MISC_DAC_RST_N BIT(0)
189 static char *vc4_vec_tv_norm;
191 struct vc4_vec_variant {
195 /* General VEC hardware state. */
197 struct vc4_encoder encoder;
198 struct drm_connector connector;
200 struct platform_device *pdev;
201 const struct vc4_vec_variant *variant;
207 struct drm_property *legacy_tv_mode_property;
209 struct debugfs_regset32 regset;
212 #define VEC_READ(offset) \
214 kunit_fail_current_test("Accessing a register in a unit test!\n"); \
215 readl(vec->regs + (offset)); \
218 #define VEC_WRITE(offset, val) \
220 kunit_fail_current_test("Accessing a register in a unit test!\n"); \
221 writel(val, vec->regs + (offset)); \
224 #define encoder_to_vc4_vec(_encoder) \
225 container_of_const(_encoder, struct vc4_vec, encoder.base)
227 #define connector_to_vc4_vec(_connector) \
228 container_of_const(_connector, struct vc4_vec, connector)
230 enum vc4_vec_tv_mode_id {
231 VC4_VEC_TV_MODE_NTSC,
232 VC4_VEC_TV_MODE_NTSC_J,
234 VC4_VEC_TV_MODE_PAL_M,
235 VC4_VEC_TV_MODE_NTSC_443,
236 VC4_VEC_TV_MODE_PAL_60,
237 VC4_VEC_TV_MODE_PAL_N,
238 VC4_VEC_TV_MODE_SECAM,
241 struct vc4_vec_tv_mode {
249 static const struct debugfs_reg32 vec_regs[] = {
250 VC4_REG32(VEC_WSE_CONTROL),
251 VC4_REG32(VEC_WSE_WSS_DATA),
252 VC4_REG32(VEC_WSE_VPS_DATA1),
253 VC4_REG32(VEC_WSE_VPS_CONTROL),
254 VC4_REG32(VEC_REVID),
255 VC4_REG32(VEC_CONFIG0),
256 VC4_REG32(VEC_SCHPH),
257 VC4_REG32(VEC_CLMP0_START),
258 VC4_REG32(VEC_CLMP0_END),
259 VC4_REG32(VEC_FREQ3_2),
260 VC4_REG32(VEC_FREQ1_0),
261 VC4_REG32(VEC_CONFIG1),
262 VC4_REG32(VEC_CONFIG2),
263 VC4_REG32(VEC_INTERRUPT_CONTROL),
264 VC4_REG32(VEC_INTERRUPT_STATUS),
265 VC4_REG32(VEC_FCW_SECAM_B),
266 VC4_REG32(VEC_SECAM_GAIN_VAL),
267 VC4_REG32(VEC_CONFIG3),
268 VC4_REG32(VEC_STATUS0),
269 VC4_REG32(VEC_MASK0),
271 VC4_REG32(VEC_DAC_TEST),
272 VC4_REG32(VEC_DAC_CONFIG),
273 VC4_REG32(VEC_DAC_MISC),
276 static const struct drm_display_mode drm_mode_240p = {
277 DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500,
278 720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0,
279 240, 240 + 3, 240 + 3 + 3, 262, 0, 0)
282 static const struct drm_display_mode drm_mode_288p = {
283 DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500,
284 720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0,
285 288, 288 + 2, 288 + 2 + 3, 312, 0, 0)
288 static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {
290 .mode = DRM_MODE_TV_MODE_NTSC,
291 .expected_htotal = 858,
292 .config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN,
293 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
296 .mode = DRM_MODE_TV_MODE_NTSC_443,
297 .expected_htotal = 858,
298 .config0 = VEC_CONFIG0_NTSC_STD,
299 .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,
300 .custom_freq = 0x2a098acb,
303 .mode = DRM_MODE_TV_MODE_NTSC_J,
304 .expected_htotal = 858,
305 .config0 = VEC_CONFIG0_NTSC_STD,
306 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
309 .mode = DRM_MODE_TV_MODE_PAL,
310 .expected_htotal = 864,
311 .config0 = VEC_CONFIG0_PAL_BDGHI_STD,
312 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
316 .mode = DRM_MODE_TV_MODE_PAL,
317 .expected_htotal = 858,
318 .config0 = VEC_CONFIG0_PAL_M_STD,
319 .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,
320 .custom_freq = 0x2a098acb,
323 .mode = DRM_MODE_TV_MODE_PAL_M,
324 .expected_htotal = 858,
325 .config0 = VEC_CONFIG0_PAL_M_STD,
326 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
329 .mode = DRM_MODE_TV_MODE_PAL_N,
330 .expected_htotal = 864,
331 .config0 = VEC_CONFIG0_PAL_N_STD,
332 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
335 .mode = DRM_MODE_TV_MODE_SECAM,
336 .expected_htotal = 864,
337 .config0 = VEC_CONFIG0_SECAM_STD,
338 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
339 .custom_freq = 0x29c71c72,
343 static inline const struct vc4_vec_tv_mode *
344 vc4_vec_tv_mode_lookup(unsigned int mode, u16 htotal)
348 for (i = 0; i < ARRAY_SIZE(vc4_vec_tv_modes); i++) {
349 const struct vc4_vec_tv_mode *tv_mode = &vc4_vec_tv_modes[i];
351 if (tv_mode->mode == mode &&
352 tv_mode->expected_htotal == htotal)
359 static const struct drm_prop_enum_list legacy_tv_mode_names[] = {
360 { VC4_VEC_TV_MODE_NTSC, "NTSC", },
361 { VC4_VEC_TV_MODE_NTSC_443, "NTSC-443", },
362 { VC4_VEC_TV_MODE_NTSC_J, "NTSC-J", },
363 { VC4_VEC_TV_MODE_PAL, "PAL", },
364 { VC4_VEC_TV_MODE_PAL_60, "PAL-60", },
365 { VC4_VEC_TV_MODE_PAL_M, "PAL-M", },
366 { VC4_VEC_TV_MODE_PAL_N, "PAL-N", },
367 { VC4_VEC_TV_MODE_SECAM, "SECAM", },
370 enum drm_connector_tv_mode
371 vc4_vec_get_default_mode(struct drm_connector *connector)
373 if (vc4_vec_tv_norm) {
376 ret = drm_get_tv_mode_from_name(vc4_vec_tv_norm, strlen(vc4_vec_tv_norm));
379 } else if (connector->cmdline_mode.specified &&
380 ((connector->cmdline_mode.refresh_specified &&
381 (connector->cmdline_mode.refresh == 25 ||
382 connector->cmdline_mode.refresh == 50)) ||
383 (!connector->cmdline_mode.refresh_specified &&
384 (connector->cmdline_mode.yres == 288 ||
385 connector->cmdline_mode.yres == 576)))) {
387 * no explicitly specified TV norm; use PAL if a mode that
388 * looks like PAL has been specified on the command line
390 return DRM_MODE_TV_MODE_PAL;
393 /* in all other cases, default to NTSC */
394 return DRM_MODE_TV_MODE_NTSC;
397 static enum drm_connector_status
398 vc4_vec_connector_detect(struct drm_connector *connector, bool force)
400 return connector_status_unknown;
403 static void vc4_vec_connector_reset(struct drm_connector *connector)
405 drm_atomic_helper_connector_reset(connector);
406 drm_atomic_helper_connector_tv_reset(connector);
408 /* preserve TV standard */
409 if (connector->state)
410 connector->state->tv.mode = vc4_vec_get_default_mode(connector);
414 vc4_vec_connector_set_property(struct drm_connector *connector,
415 struct drm_connector_state *state,
416 struct drm_property *property,
419 struct vc4_vec *vec = connector_to_vc4_vec(connector);
421 if (property != vec->legacy_tv_mode_property)
425 case VC4_VEC_TV_MODE_NTSC:
426 state->tv.mode = DRM_MODE_TV_MODE_NTSC;
429 case VC4_VEC_TV_MODE_NTSC_443:
430 state->tv.mode = DRM_MODE_TV_MODE_NTSC_443;
433 case VC4_VEC_TV_MODE_NTSC_J:
434 state->tv.mode = DRM_MODE_TV_MODE_NTSC_J;
437 case VC4_VEC_TV_MODE_PAL:
438 case VC4_VEC_TV_MODE_PAL_60:
439 state->tv.mode = DRM_MODE_TV_MODE_PAL;
442 case VC4_VEC_TV_MODE_PAL_M:
443 state->tv.mode = DRM_MODE_TV_MODE_PAL_M;
446 case VC4_VEC_TV_MODE_PAL_N:
447 state->tv.mode = DRM_MODE_TV_MODE_PAL_N;
450 case VC4_VEC_TV_MODE_SECAM:
451 state->tv.mode = DRM_MODE_TV_MODE_SECAM;
462 vc4_vec_generic_tv_mode_to_legacy(enum drm_connector_tv_mode tv_mode)
465 case DRM_MODE_TV_MODE_NTSC:
466 return VC4_VEC_TV_MODE_NTSC;
468 case DRM_MODE_TV_MODE_NTSC_443:
469 return VC4_VEC_TV_MODE_NTSC_443;
471 case DRM_MODE_TV_MODE_NTSC_J:
472 return VC4_VEC_TV_MODE_NTSC_J;
474 case DRM_MODE_TV_MODE_PAL:
475 return VC4_VEC_TV_MODE_PAL;
477 case DRM_MODE_TV_MODE_PAL_M:
478 return VC4_VEC_TV_MODE_PAL_M;
480 case DRM_MODE_TV_MODE_PAL_N:
481 return VC4_VEC_TV_MODE_PAL_N;
483 case DRM_MODE_TV_MODE_SECAM:
484 return VC4_VEC_TV_MODE_SECAM;
492 vc4_vec_connector_get_property(struct drm_connector *connector,
493 const struct drm_connector_state *state,
494 struct drm_property *property,
497 struct vc4_vec *vec = connector_to_vc4_vec(connector);
498 enum vc4_vec_tv_mode_id legacy_mode;
500 if (property != vec->legacy_tv_mode_property)
503 legacy_mode = vc4_vec_generic_tv_mode_to_legacy(state->tv.mode);
512 static const struct drm_connector_funcs vc4_vec_connector_funcs = {
513 .detect = vc4_vec_connector_detect,
514 .fill_modes = drm_helper_probe_single_connector_modes,
515 .reset = vc4_vec_connector_reset,
516 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
517 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
518 .atomic_get_property = vc4_vec_connector_get_property,
519 .atomic_set_property = vc4_vec_connector_set_property,
522 static int vc4_vec_connector_get_modes(struct drm_connector *connector)
524 struct drm_display_mode *mode;
525 int count = drm_connector_helper_tv_get_modes(connector);
527 mode = drm_mode_duplicate(connector->dev, &drm_mode_240p);
531 drm_mode_probed_add(connector, mode);
534 mode = drm_mode_duplicate(connector->dev, &drm_mode_288p);
538 drm_mode_probed_add(connector, mode);
544 static const struct drm_connector_helper_funcs vc4_vec_connector_helper_funcs = {
545 .atomic_check = drm_atomic_helper_connector_tv_check,
546 .get_modes = vc4_vec_connector_get_modes,
549 static int vc4_vec_connector_init(struct drm_device *dev, struct vc4_vec *vec)
551 struct drm_connector *connector = &vec->connector;
552 enum vc4_vec_tv_mode_id legacy_default_mode;
553 enum drm_connector_tv_mode default_mode;
554 struct drm_property *prop;
557 connector->interlace_allowed = true;
559 ret = drmm_connector_init(dev, connector, &vc4_vec_connector_funcs,
560 DRM_MODE_CONNECTOR_Composite, NULL);
564 drm_connector_helper_add(connector, &vc4_vec_connector_helper_funcs);
566 default_mode = vc4_vec_get_default_mode(connector);
567 if (default_mode < 0)
570 drm_object_attach_property(&connector->base,
571 dev->mode_config.tv_mode_property,
574 legacy_default_mode = vc4_vec_generic_tv_mode_to_legacy(default_mode);
575 if (legacy_default_mode < 0)
576 return legacy_default_mode;
578 prop = drm_property_create_enum(dev, 0, "mode",
579 legacy_tv_mode_names,
580 ARRAY_SIZE(legacy_tv_mode_names));
583 vec->legacy_tv_mode_property = prop;
585 drm_object_attach_property(&connector->base, prop, legacy_default_mode);
587 drm_connector_attach_tv_margin_properties(connector);
589 drm_connector_attach_encoder(connector, &vec->encoder.base);
594 static void vc4_vec_encoder_disable(struct drm_encoder *encoder,
595 struct drm_atomic_state *state)
597 struct drm_device *drm = encoder->dev;
598 struct vc4_vec *vec = encoder_to_vc4_vec(encoder);
601 if (!drm_dev_enter(drm, &idx))
604 VEC_WRITE(VEC_CFG, 0);
605 VEC_WRITE(VEC_DAC_MISC,
606 VEC_DAC_MISC_VCD_PWRDN |
607 VEC_DAC_MISC_BIAS_PWRDN |
608 VEC_DAC_MISC_DAC_PWRDN |
609 VEC_DAC_MISC_LDO_PWRDN);
611 clk_disable_unprepare(vec->clock);
613 ret = pm_runtime_put(&vec->pdev->dev);
615 DRM_ERROR("Failed to release power domain: %d\n", ret);
626 static void vc4_vec_encoder_enable(struct drm_encoder *encoder,
627 struct drm_atomic_state *state)
629 struct drm_device *drm = encoder->dev;
630 struct vc4_vec *vec = encoder_to_vc4_vec(encoder);
631 struct drm_connector *connector = &vec->connector;
632 struct drm_connector_state *conn_state =
633 drm_atomic_get_new_connector_state(state, connector);
634 struct drm_display_mode *adjusted_mode =
635 &encoder->crtc->state->adjusted_mode;
636 const struct vc4_vec_tv_mode *tv_mode;
639 if (!drm_dev_enter(drm, &idx))
642 tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode,
643 adjusted_mode->htotal);
647 ret = pm_runtime_resume_and_get(&vec->pdev->dev);
649 DRM_ERROR("Failed to retain power domain: %d\n", ret);
654 * We need to set the clock rate each time we enable the encoder
655 * because there's a chance we share the same parent with the HDMI
656 * clock, and both drivers are requesting different rates.
657 * The good news is, these 2 encoders cannot be enabled at the same
658 * time, thus preventing incompatible rate requests.
660 ret = clk_set_rate(vec->clock, 108000000);
662 DRM_ERROR("Failed to set clock rate: %d\n", ret);
663 goto err_put_runtime_pm;
666 ret = clk_prepare_enable(vec->clock);
668 DRM_ERROR("Failed to turn on core clock: %d\n", ret);
669 goto err_put_runtime_pm;
672 /* Reset the different blocks */
673 VEC_WRITE(VEC_WSE_RESET, 1);
674 VEC_WRITE(VEC_SOFT_RESET, 1);
676 /* Disable the CGSM-A and WSE blocks */
677 VEC_WRITE(VEC_WSE_CONTROL, 0);
679 /* Write config common to all modes. */
682 * Color subcarrier phase: phase = 360 * SCHPH / 256.
683 * 0x28 <=> 39.375 deg.
685 VEC_WRITE(VEC_SCHPH, 0x28);
688 * Reset to default values.
690 VEC_WRITE(VEC_CLMP0_START, 0xac);
691 VEC_WRITE(VEC_CLMP0_END, 0xec);
692 VEC_WRITE(VEC_CONFIG2,
693 VEC_CONFIG2_UV_DIG_DIS |
694 VEC_CONFIG2_RGB_DIG_DIS |
695 ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ? 0 : VEC_CONFIG2_PROG_SCAN));
696 VEC_WRITE(VEC_CONFIG3, VEC_CONFIG3_HORIZ_LEN_STD);
697 VEC_WRITE(VEC_DAC_CONFIG, vec->variant->dac_config);
699 /* Mask all interrupts. */
700 VEC_WRITE(VEC_MASK0, 0);
702 VEC_WRITE(VEC_CONFIG0, tv_mode->config0);
703 VEC_WRITE(VEC_CONFIG1, tv_mode->config1);
705 if (tv_mode->custom_freq) {
706 VEC_WRITE(VEC_FREQ3_2,
707 (tv_mode->custom_freq >> 16) & 0xffff);
708 VEC_WRITE(VEC_FREQ1_0,
709 tv_mode->custom_freq & 0xffff);
712 VEC_WRITE(VEC_DAC_MISC,
713 VEC_DAC_MISC_VID_ACT | VEC_DAC_MISC_DAC_RST_N);
714 VEC_WRITE(VEC_CFG, VEC_CFG_VEC_EN);
720 pm_runtime_put(&vec->pdev->dev);
725 static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder,
726 struct drm_crtc_state *crtc_state,
727 struct drm_connector_state *conn_state)
729 const struct drm_display_mode *mode = &crtc_state->adjusted_mode;
730 const struct vc4_vec_tv_mode *tv_mode;
732 tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode, mode->htotal);
736 if (mode->crtc_hdisplay % 4)
739 if (!(mode->crtc_hsync_end - mode->crtc_hsync_start))
742 switch (mode->htotal) {
745 if (mode->crtc_vtotal > 262)
748 if (mode->crtc_vdisplay < 1 || mode->crtc_vdisplay > 253)
751 if (!(mode->crtc_vsync_start - mode->crtc_vdisplay))
754 if ((mode->crtc_vsync_end - mode->crtc_vsync_start) != 3)
757 if ((mode->crtc_vtotal - mode->crtc_vsync_end) < 4)
760 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) &&
761 (mode->vdisplay % 2 != 0 ||
762 mode->vsync_start % 2 != 1 ||
763 mode->vsync_end % 2 != 1 ||
764 mode->vtotal % 2 != 1))
767 /* progressive mode is hard-wired to 262 total lines */
768 if (!(mode->flags & DRM_MODE_FLAG_INTERLACE) &&
769 mode->crtc_vtotal != 262)
776 if (mode->crtc_vtotal > 312)
779 if (mode->crtc_vdisplay < 1 || mode->crtc_vdisplay > 305)
782 if (!(mode->crtc_vsync_start - mode->crtc_vdisplay))
785 if ((mode->crtc_vsync_end - mode->crtc_vsync_start) != 3)
788 if ((mode->crtc_vtotal - mode->crtc_vsync_end) < 2)
791 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) &&
792 (mode->vdisplay % 2 != 0 ||
793 mode->vsync_start % 2 != 0 ||
794 mode->vsync_end % 2 != 0 ||
795 mode->vtotal % 2 != 1))
798 /* progressive mode is hard-wired to 312 total lines */
799 if (!(mode->flags & DRM_MODE_FLAG_INTERLACE) &&
800 mode->crtc_vtotal != 312)
812 static const struct drm_encoder_helper_funcs vc4_vec_encoder_helper_funcs = {
813 .atomic_check = vc4_vec_encoder_atomic_check,
814 .atomic_disable = vc4_vec_encoder_disable,
815 .atomic_enable = vc4_vec_encoder_enable,
818 static int vc4_vec_late_register(struct drm_encoder *encoder)
820 struct drm_device *drm = encoder->dev;
821 struct vc4_vec *vec = encoder_to_vc4_vec(encoder);
823 vc4_debugfs_add_regset32(drm, "vec_regs", &vec->regset);
828 static const struct drm_encoder_funcs vc4_vec_encoder_funcs = {
829 .late_register = vc4_vec_late_register,
832 static const struct vc4_vec_variant bcm2835_vec_variant = {
833 .dac_config = VEC_DAC_CONFIG_DAC_CTRL(0xc) |
834 VEC_DAC_CONFIG_DRIVER_CTRL(0xc) |
835 VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x46)
838 static const struct vc4_vec_variant bcm2711_vec_variant = {
839 .dac_config = VEC_DAC_CONFIG_DAC_CTRL(0x0) |
840 VEC_DAC_CONFIG_DRIVER_CTRL(0x80) |
841 VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x61)
844 static const struct of_device_id vc4_vec_dt_match[] = {
845 { .compatible = "brcm,bcm2835-vec", .data = &bcm2835_vec_variant },
846 { .compatible = "brcm,bcm2711-vec", .data = &bcm2711_vec_variant },
850 static int vc4_vec_bind(struct device *dev, struct device *master, void *data)
852 struct platform_device *pdev = to_platform_device(dev);
853 struct drm_device *drm = dev_get_drvdata(master);
857 ret = drm_mode_create_tv_properties(drm,
858 BIT(DRM_MODE_TV_MODE_NTSC) |
859 BIT(DRM_MODE_TV_MODE_NTSC_443) |
860 BIT(DRM_MODE_TV_MODE_NTSC_J) |
861 BIT(DRM_MODE_TV_MODE_PAL) |
862 BIT(DRM_MODE_TV_MODE_PAL_M) |
863 BIT(DRM_MODE_TV_MODE_PAL_N) |
864 BIT(DRM_MODE_TV_MODE_SECAM));
868 vec = drmm_kzalloc(drm, sizeof(*vec), GFP_KERNEL);
872 vec->encoder.type = VC4_ENCODER_TYPE_VEC;
874 vec->variant = (const struct vc4_vec_variant *)
875 of_device_get_match_data(dev);
876 vec->regs = vc4_ioremap_regs(pdev, 0);
877 if (IS_ERR(vec->regs))
878 return PTR_ERR(vec->regs);
879 vec->regset.base = vec->regs;
880 vec->regset.regs = vec_regs;
881 vec->regset.nregs = ARRAY_SIZE(vec_regs);
883 vec->clock = devm_clk_get(dev, NULL);
884 if (IS_ERR(vec->clock)) {
885 ret = PTR_ERR(vec->clock);
886 if (ret != -EPROBE_DEFER)
887 DRM_ERROR("Failed to get clock: %d\n", ret);
891 ret = devm_pm_runtime_enable(dev);
895 ret = drmm_encoder_init(drm, &vec->encoder.base,
896 &vc4_vec_encoder_funcs,
897 DRM_MODE_ENCODER_TVDAC,
902 drm_encoder_helper_add(&vec->encoder.base, &vc4_vec_encoder_helper_funcs);
904 ret = vc4_vec_connector_init(drm, vec);
908 dev_set_drvdata(dev, vec);
913 static const struct component_ops vc4_vec_ops = {
914 .bind = vc4_vec_bind,
917 static int vc4_vec_dev_probe(struct platform_device *pdev)
919 return component_add(&pdev->dev, &vc4_vec_ops);
922 static void vc4_vec_dev_remove(struct platform_device *pdev)
924 component_del(&pdev->dev, &vc4_vec_ops);
927 struct platform_driver vc4_vec_driver = {
928 .probe = vc4_vec_dev_probe,
929 .remove_new = vc4_vec_dev_remove,
932 .of_match_table = vc4_vec_dt_match,
936 module_param_named(tv_norm, vc4_vec_tv_norm, charp, 0600);
937 MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
938 "\t\tSupported: NTSC, NTSC-J, NTSC-443, PAL, PAL-M, PAL-N,\n"
939 "\t\t\tPAL60, SECAM.\n"
940 "\t\tDefault: PAL if a 50 Hz mode has been set via video=,\n"
941 "\t\t\tNTSC otherwise");