drivers/gpu/drm/vc4/vc4_v3d.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   4  * Copyright (C) 2013 Red Hat
   5  * Author: Rob Clark <robdclark@gmail.com>
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/component.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/pm_runtime.h>
  12
  13 #include "vc4_drv.h"
  14 #include "vc4_regs.h"
  15
  16 static const struct debugfs_reg32 v3d_regs[] = {
  17         VC4_REG32(V3D_IDENT0),
  18         VC4_REG32(V3D_IDENT1),
  19         VC4_REG32(V3D_IDENT2),
  20         VC4_REG32(V3D_SCRATCH),
  21         VC4_REG32(V3D_L2CACTL),
  22         VC4_REG32(V3D_SLCACTL),
  23         VC4_REG32(V3D_INTCTL),
  24         VC4_REG32(V3D_INTENA),
  25         VC4_REG32(V3D_INTDIS),
  26         VC4_REG32(V3D_CT0CS),
  27         VC4_REG32(V3D_CT1CS),
  28         VC4_REG32(V3D_CT0EA),
  29         VC4_REG32(V3D_CT1EA),
  30         VC4_REG32(V3D_CT0CA),
  31         VC4_REG32(V3D_CT1CA),
  32         VC4_REG32(V3D_CT00RA0),
  33         VC4_REG32(V3D_CT01RA0),
  34         VC4_REG32(V3D_CT0LC),
  35         VC4_REG32(V3D_CT1LC),
  36         VC4_REG32(V3D_CT0PC),
  37         VC4_REG32(V3D_CT1PC),
  38         VC4_REG32(V3D_PCS),
  39         VC4_REG32(V3D_BFC),
  40         VC4_REG32(V3D_RFC),
  41         VC4_REG32(V3D_BPCA),
  42         VC4_REG32(V3D_BPCS),
  43         VC4_REG32(V3D_BPOA),
  44         VC4_REG32(V3D_BPOS),
  45         VC4_REG32(V3D_BXCF),
  46         VC4_REG32(V3D_SQRSV0),
  47         VC4_REG32(V3D_SQRSV1),
  48         VC4_REG32(V3D_SQCNTL),
  49         VC4_REG32(V3D_SRQPC),
  50         VC4_REG32(V3D_SRQUA),
  51         VC4_REG32(V3D_SRQUL),
  52         VC4_REG32(V3D_SRQCS),
  53         VC4_REG32(V3D_VPACNTL),
  54         VC4_REG32(V3D_VPMBASE),
  55         VC4_REG32(V3D_PCTRC),
  56         VC4_REG32(V3D_PCTRE),
  57         VC4_REG32(V3D_PCTR(0)),
  58         VC4_REG32(V3D_PCTRS(0)),
  59         VC4_REG32(V3D_PCTR(1)),
  60         VC4_REG32(V3D_PCTRS(1)),
  61         VC4_REG32(V3D_PCTR(2)),
  62         VC4_REG32(V3D_PCTRS(2)),
  63         VC4_REG32(V3D_PCTR(3)),
  64         VC4_REG32(V3D_PCTRS(3)),
  65         VC4_REG32(V3D_PCTR(4)),
  66         VC4_REG32(V3D_PCTRS(4)),
  67         VC4_REG32(V3D_PCTR(5)),
  68         VC4_REG32(V3D_PCTRS(5)),
  69         VC4_REG32(V3D_PCTR(6)),
  70         VC4_REG32(V3D_PCTRS(6)),
  71         VC4_REG32(V3D_PCTR(7)),
  72         VC4_REG32(V3D_PCTRS(7)),
  73         VC4_REG32(V3D_PCTR(8)),
  74         VC4_REG32(V3D_PCTRS(8)),
  75         VC4_REG32(V3D_PCTR(9)),
  76         VC4_REG32(V3D_PCTRS(9)),
  77         VC4_REG32(V3D_PCTR(10)),
  78         VC4_REG32(V3D_PCTRS(10)),
  79         VC4_REG32(V3D_PCTR(11)),
  80         VC4_REG32(V3D_PCTRS(11)),
  81         VC4_REG32(V3D_PCTR(12)),
  82         VC4_REG32(V3D_PCTRS(12)),
  83         VC4_REG32(V3D_PCTR(13)),
  84         VC4_REG32(V3D_PCTRS(13)),
  85         VC4_REG32(V3D_PCTR(14)),
  86         VC4_REG32(V3D_PCTRS(14)),
  87         VC4_REG32(V3D_PCTR(15)),
  88         VC4_REG32(V3D_PCTRS(15)),
  89         VC4_REG32(V3D_DBGE),
  90         VC4_REG32(V3D_FDBGO),
  91         VC4_REG32(V3D_FDBGB),
  92         VC4_REG32(V3D_FDBGR),
  93         VC4_REG32(V3D_FDBGS),
  94         VC4_REG32(V3D_ERRSTAT),
  95 };
  96
  97 static int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused)
  98 {
  99         struct drm_info_node *node = (struct drm_info_node *)m->private;
 100         struct drm_device *dev = node->minor->dev;
 101         struct vc4_dev *vc4 = to_vc4_dev(dev);
 102         int ret = vc4_v3d_pm_get(vc4);
 103
 104         if (ret == 0) {
 105                 uint32_t ident1 = V3D_READ(V3D_IDENT1);
 106                 uint32_t nslc = VC4_GET_FIELD(ident1, V3D_IDENT1_NSLC);
 107                 uint32_t tups = VC4_GET_FIELD(ident1, V3D_IDENT1_TUPS);
 108                 uint32_t qups = VC4_GET_FIELD(ident1, V3D_IDENT1_QUPS);
 109
 110                 seq_printf(m, "Revision:   %d\n",
 111                            VC4_GET_FIELD(ident1, V3D_IDENT1_REV));
 112                 seq_printf(m, "Slices:     %d\n", nslc);
 113                 seq_printf(m, "TMUs:       %d\n", nslc * tups);
 114                 seq_printf(m, "QPUs:       %d\n", nslc * qups);
 115                 seq_printf(m, "Semaphores: %d\n",
 116                            VC4_GET_FIELD(ident1, V3D_IDENT1_NSEM));
 117                 vc4_v3d_pm_put(vc4);
 118         }
 119
 120         return 0;
 121 }
 122
 123 /*
 124  * Wraps pm_runtime_get_sync() in a refcount, so that we can reliably
 125  * get the pm_runtime refcount to 0 in vc4_reset().
 126  */
 127 int
 128 vc4_v3d_pm_get(struct vc4_dev *vc4)
 129 {
 130         mutex_lock(&vc4->power_lock);
 131         if (vc4->power_refcount++ == 0) {
 132                 int ret = pm_runtime_get_sync(&vc4->v3d->pdev->dev);
 133
 134                 if (ret < 0) {
 135                         vc4->power_refcount--;
 136                         mutex_unlock(&vc4->power_lock);
 137                         return ret;
 138                 }
 139         }
 140         mutex_unlock(&vc4->power_lock);
 141
 142         return 0;
 143 }
 144
 145 void
 146 vc4_v3d_pm_put(struct vc4_dev *vc4)
 147 {
 148         mutex_lock(&vc4->power_lock);
 149         if (--vc4->power_refcount == 0) {
 150                 pm_runtime_mark_last_busy(&vc4->v3d->pdev->dev);
 151                 pm_runtime_put_autosuspend(&vc4->v3d->pdev->dev);
 152         }
 153         mutex_unlock(&vc4->power_lock);
 154 }
 155
 156 static void vc4_v3d_init_hw(struct drm_device *dev)
 157 {
 158         struct vc4_dev *vc4 = to_vc4_dev(dev);
 159
 160         /* Take all the memory that would have been reserved for user
 161          * QPU programs, since we don't have an interface for running
 162          * them, anyway.
 163          */
 164         V3D_WRITE(V3D_VPMBASE, 0);
 165 }
 166
 167 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4)
 168 {
 169         struct drm_device *dev = &vc4->base;
 170         unsigned long irqflags;
 171         int slot;
 172         uint64_t seqno = 0;
 173         struct vc4_exec_info *exec;
 174
 175 try_again:
 176         spin_lock_irqsave(&vc4->job_lock, irqflags);
 177         slot = ffs(~vc4->bin_alloc_used);
 178         if (slot != 0) {
 179                 /* Switch from ffs() bit index to a 0-based index. */
 180                 slot--;
 181                 vc4->bin_alloc_used |= BIT(slot);
 182                 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
 183                 return slot;
 184         }
 185
 186         /* Couldn't find an open slot.  Wait for render to complete
 187          * and try again.
 188          */
 189         exec = vc4_last_render_job(vc4);
 190         if (exec)
 191                 seqno = exec->seqno;
 192         spin_unlock_irqrestore(&vc4->job_lock, irqflags);
 193
 194         if (seqno) {
 195                 int ret = vc4_wait_for_seqno(dev, seqno, ~0ull, true);
 196
 197                 if (ret == 0)
 198                         goto try_again;
 199
 200                 return ret;
 201         }
 202
 203         return -ENOMEM;
 204 }
 205
 206 /*
 207  * bin_bo_alloc() - allocates the memory that will be used for
 208  * tile binning.
 209  *
 210  * The binner has a limitation that the addresses in the tile state
 211  * buffer that point into the tile alloc buffer or binner overflow
 212  * memory only have 28 bits (256MB), and the top 4 on the bus for
 213  * tile alloc references end up coming from the tile state buffer's
 214  * address.
 215  *
 216  * To work around this, we allocate a single large buffer while V3D is
 217  * in use, make sure that it has the top 4 bits constant across its
 218  * entire extent, and then put the tile state, tile alloc, and binner
 219  * overflow memory inside that buffer.
 220  *
 221  * This creates a limitation where we may not be able to execute a job
 222  * if it doesn't fit within the buffer that we allocated up front.
 223  * However, it turns out that 16MB is "enough for anybody", and
 224  * real-world applications run into allocation failures from the
 225  * overall CMA pool before they make scenes complicated enough to run
 226  * out of bin space.
 227  */
 228 static int bin_bo_alloc(struct vc4_dev *vc4)
 229 {
 230         struct vc4_v3d *v3d = vc4->v3d;
 231         uint32_t size = 16 * 1024 * 1024;
 232         int ret = 0;
 233         struct list_head list;
 234
 235         if (!v3d)
 236                 return -ENODEV;
 237
 238         /* We may need to try allocating more than once to get a BO
 239          * that doesn't cross 256MB.  Track the ones we've allocated
 240          * that failed so far, so that we can free them when we've got
 241          * one that succeeded (if we freed them right away, our next
 242          * allocation would probably be the same chunk of memory).
 243          */
 244         INIT_LIST_HEAD(&list);
 245
 246         while (true) {
 247                 struct vc4_bo *bo = vc4_bo_create(&vc4->base, size, true,
 248                                                   VC4_BO_TYPE_BIN);
 249
 250                 if (IS_ERR(bo)) {
 251                         ret = PTR_ERR(bo);
 252
 253                         dev_err(&v3d->pdev->dev,
 254                                 "Failed to allocate memory for tile binning: "
 255                                 "%d. You may need to enable CMA or give it "
 256                                 "more memory.",
 257                                 ret);
 258                         break;
 259                 }
 260
 261                 /* Check if this BO won't trigger the addressing bug. */
 262                 if ((bo->base.paddr & 0xf0000000) ==
 263                     ((bo->base.paddr + bo->base.base.size - 1) & 0xf0000000)) {
 264                         vc4->bin_bo = bo;
 265
 266                         /* Set up for allocating 512KB chunks of
 267                          * binner memory.  The biggest allocation we
 268                          * need to do is for the initial tile alloc +
 269                          * tile state buffer.  We can render to a
 270                          * maximum of ((2048*2048) / (32*32) = 4096
 271                          * tiles in a frame (until we do floating
 272                          * point rendering, at which point it would be
 273                          * 8192).  Tile state is 48b/tile (rounded to
 274                          * a page), and tile alloc is 32b/tile
 275                          * (rounded to a page), plus a page of extra,
 276                          * for a total of 320kb for our worst-case.
 277                          * We choose 512kb so that it divides evenly
 278                          * into our 16MB, and the rest of the 512kb
 279                          * will be used as storage for the overflow
 280                          * from the initial 32b CL per bin.
 281                          */
 282                         vc4->bin_alloc_size = 512 * 1024;
 283                         vc4->bin_alloc_used = 0;
 284                         vc4->bin_alloc_overflow = 0;
 285                         WARN_ON_ONCE(sizeof(vc4->bin_alloc_used) * 8 !=
 286                                      bo->base.base.size / vc4->bin_alloc_size);
 287
 288                         kref_init(&vc4->bin_bo_kref);
 289
 290                         /* Enable the out-of-memory interrupt to set our
 291                          * newly-allocated binner BO, potentially from an
 292                          * already-pending-but-masked interrupt.
 293                          */
 294                         V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM);
 295
 296                         break;
 297                 }
 298
 299                 /* Put it on the list to free later, and try again. */
 300                 list_add(&bo->unref_head, &list);
 301         }
 302
 303         /* Free all the BOs we allocated but didn't choose. */
 304         while (!list_empty(&list)) {
 305                 struct vc4_bo *bo = list_last_entry(&list,
 306                                                     struct vc4_bo, unref_head);
 307
 308                 list_del(&bo->unref_head);
 309                 drm_gem_object_put(&bo->base.base);
 310         }
 311
 312         return ret;
 313 }
 314
 315 int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used)
 316 {
 317         int ret = 0;
 318
 319         mutex_lock(&vc4->bin_bo_lock);
 320
 321         if (used && *used)
 322                 goto complete;
 323
 324         if (vc4->bin_bo)
 325                 kref_get(&vc4->bin_bo_kref);
 326         else
 327                 ret = bin_bo_alloc(vc4);
 328
 329         if (ret == 0 && used)
 330                 *used = true;
 331
 332 complete:
 333         mutex_unlock(&vc4->bin_bo_lock);
 334
 335         return ret;
 336 }
 337
 338 static void bin_bo_release(struct kref *ref)
 339 {
 340         struct vc4_dev *vc4 = container_of(ref, struct vc4_dev, bin_bo_kref);
 341
 342         if (WARN_ON_ONCE(!vc4->bin_bo))
 343                 return;
 344
 345         drm_gem_object_put(&vc4->bin_bo->base.base);
 346         vc4->bin_bo = NULL;
 347 }
 348
 349 void vc4_v3d_bin_bo_put(struct vc4_dev *vc4)
 350 {
 351         mutex_lock(&vc4->bin_bo_lock);
 352         kref_put(&vc4->bin_bo_kref, bin_bo_release);
 353         mutex_unlock(&vc4->bin_bo_lock);
 354 }
 355
 356 #ifdef CONFIG_PM
 357 static int vc4_v3d_runtime_suspend(struct device *dev)
 358 {
 359         struct vc4_v3d *v3d = dev_get_drvdata(dev);
 360         struct vc4_dev *vc4 = v3d->vc4;
 361
 362         vc4_irq_disable(&vc4->base);
 363
 364         clk_disable_unprepare(v3d->clk);
 365
 366         return 0;
 367 }
 368
 369 static int vc4_v3d_runtime_resume(struct device *dev)
 370 {
 371         struct vc4_v3d *v3d = dev_get_drvdata(dev);
 372         struct vc4_dev *vc4 = v3d->vc4;
 373         int ret;
 374
 375         ret = clk_prepare_enable(v3d->clk);
 376         if (ret != 0)
 377                 return ret;
 378
 379         vc4_v3d_init_hw(&vc4->base);
 380
 381         /* We disabled the IRQ as part of vc4_irq_uninstall in suspend. */
 382         enable_irq(vc4->irq);
 383         vc4_irq_enable(&vc4->base);
 384
 385         return 0;
 386 }
 387 #endif
 388
 389 static int vc4_v3d_bind(struct device *dev, struct device *master, void *data)
 390 {
 391         struct platform_device *pdev = to_platform_device(dev);
 392         struct drm_device *drm = dev_get_drvdata(master);
 393         struct vc4_dev *vc4 = to_vc4_dev(drm);
 394         struct vc4_v3d *v3d = NULL;
 395         int ret;
 396
 397         v3d = devm_kzalloc(&pdev->dev, sizeof(*v3d), GFP_KERNEL);
 398         if (!v3d)
 399                 return -ENOMEM;
 400
 401         dev_set_drvdata(dev, v3d);
 402
 403         v3d->pdev = pdev;
 404
 405         v3d->regs = vc4_ioremap_regs(pdev, 0);
 406         if (IS_ERR(v3d->regs))
 407                 return PTR_ERR(v3d->regs);
 408         v3d->regset.base = v3d->regs;
 409         v3d->regset.regs = v3d_regs;
 410         v3d->regset.nregs = ARRAY_SIZE(v3d_regs);
 411
 412         vc4->v3d = v3d;
 413         v3d->vc4 = vc4;
 414
 415         v3d->clk = devm_clk_get(dev, NULL);
 416         if (IS_ERR(v3d->clk)) {
 417                 int ret = PTR_ERR(v3d->clk);
 418
 419                 if (ret == -ENOENT) {
 420                         /* bcm2835 didn't have a clock reference in the DT. */
 421                         ret = 0;
 422                         v3d->clk = NULL;
 423                 } else {
 424                         if (ret != -EPROBE_DEFER)
 425                                 dev_err(dev, "Failed to get V3D clock: %d\n",
 426                                         ret);
 427                         return ret;
 428                 }
 429         }
 430
 431         if (V3D_READ(V3D_IDENT0) != V3D_EXPECTED_IDENT0) {
 432                 DRM_ERROR("V3D_IDENT0 read 0x%08x instead of 0x%08x\n",
 433                           V3D_READ(V3D_IDENT0), V3D_EXPECTED_IDENT0);
 434                 return -EINVAL;
 435         }
 436
 437         ret = clk_prepare_enable(v3d->clk);
 438         if (ret != 0)
 439                 return ret;
 440
 441         /* Reset the binner overflow address/size at setup, to be sure
 442          * we don't reuse an old one.
 443          */
 444         V3D_WRITE(V3D_BPOA, 0);
 445         V3D_WRITE(V3D_BPOS, 0);
 446
 447         vc4_v3d_init_hw(drm);
 448
 449         ret = platform_get_irq(pdev, 0);
 450         if (ret < 0)
 451                 return ret;
 452         vc4->irq = ret;
 453
 454         ret = vc4_irq_install(drm, vc4->irq);
 455         if (ret) {
 456                 DRM_ERROR("Failed to install IRQ handler\n");
 457                 return ret;
 458         }
 459
 460         pm_runtime_set_active(dev);
 461         pm_runtime_use_autosuspend(dev);
 462         pm_runtime_set_autosuspend_delay(dev, 40); /* a little over 2 frames. */
 463         pm_runtime_enable(dev);
 464
 465         vc4_debugfs_add_file(drm, "v3d_ident", vc4_v3d_debugfs_ident, NULL);
 466         vc4_debugfs_add_regset32(drm, "v3d_regs", &v3d->regset);
 467
 468         return 0;
 469 }
 470
 471 static void vc4_v3d_unbind(struct device *dev, struct device *master,
 472                            void *data)
 473 {
 474         struct drm_device *drm = dev_get_drvdata(master);
 475         struct vc4_dev *vc4 = to_vc4_dev(drm);
 476
 477         pm_runtime_disable(dev);
 478
 479         vc4_irq_uninstall(drm);
 480
 481         /* Disable the binner's overflow memory address, so the next
 482          * driver probe (if any) doesn't try to reuse our old
 483          * allocation.
 484          */
 485         V3D_WRITE(V3D_BPOA, 0);
 486         V3D_WRITE(V3D_BPOS, 0);
 487
 488         vc4->v3d = NULL;
 489 }
 490
 491 static const struct dev_pm_ops vc4_v3d_pm_ops = {
 492         SET_RUNTIME_PM_OPS(vc4_v3d_runtime_suspend, vc4_v3d_runtime_resume, NULL)
 493 };
 494
 495 static const struct component_ops vc4_v3d_ops = {
 496         .bind   = vc4_v3d_bind,
 497         .unbind = vc4_v3d_unbind,
 498 };
 499
 500 static int vc4_v3d_dev_probe(struct platform_device *pdev)
 501 {
 502         return component_add(&pdev->dev, &vc4_v3d_ops);
 503 }
 504
 505 static int vc4_v3d_dev_remove(struct platform_device *pdev)
 506 {
 507         component_del(&pdev->dev, &vc4_v3d_ops);
 508         return 0;
 509 }
 510
 511 const struct of_device_id vc4_v3d_dt_match[] = {
 512         { .compatible = "brcm,bcm2835-v3d" },
 513         { .compatible = "brcm,cygnus-v3d" },
 514         { .compatible = "brcm,vc4-v3d" },
 515         {}
 516 };
 517
 518 struct platform_driver vc4_v3d_driver = {
 519         .probe = vc4_v3d_dev_probe,
 520         .remove = vc4_v3d_dev_remove,
 521         .driver = {
 522                 .name = "vc4_v3d",
 523                 .of_match_table = vc4_v3d_dt_match,
 524                 .pm = &vc4_v3d_pm_ops,
 525         },
 526 };