1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2018 Broadcom
6 * Eric Anholt <eric@anholt.net>
7 * Boris Brezillon <boris.brezillon@bootlin.com>
10 #include <linux/clk.h>
11 #include <linux/component.h>
12 #include <linux/mod_devicetable.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
16 #include <drm/drm_atomic.h>
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_drv.h>
19 #include <drm/drm_edid.h>
20 #include <drm/drm_fb_dma_helper.h>
21 #include <drm/drm_fourcc.h>
22 #include <drm/drm_framebuffer.h>
23 #include <drm/drm_panel.h>
24 #include <drm/drm_probe_helper.h>
25 #include <drm/drm_vblank.h>
26 #include <drm/drm_writeback.h>
31 /* Base address of the output. Raster formats must be 4-byte aligned,
32 * T and LT must be 16-byte aligned or maybe utile-aligned (docs are
33 * inconsistent, but probably utile).
35 #define TXP_DST_PTR 0x00
37 /* Pitch in bytes for raster images, 16-byte aligned. For tiled, it's
40 #define TXP_DST_PITCH 0x04
41 /* For T-tiled imgaes, DST_PITCH should be the number of tiles wide,
44 # define TXP_T_TILE_WIDTH_SHIFT 7
45 /* For LT-tiled images, DST_PITCH should be the number of utiles wide,
48 # define TXP_LT_TILE_WIDTH_SHIFT 4
50 /* Pre-rotation width/height of the image. Must match HVS config.
52 * If TFORMAT and 32-bit, limit is 1920 for 32-bit and 3840 to 16-bit
53 * and width/height must be tile or utile-aligned as appropriate. If
54 * transposing (rotating), width is limited to 1920.
56 * Height is limited to various numbers between 4088 and 4095. I'd
57 * just use 4088 to be safe.
60 # define TXP_HEIGHT_SHIFT 16
61 # define TXP_HEIGHT_MASK GENMASK(31, 16)
62 # define TXP_WIDTH_SHIFT 0
63 # define TXP_WIDTH_MASK GENMASK(15, 0)
65 #define TXP_DST_CTRL 0x0c
66 /* These bits are set to 0x54 */
67 #define TXP_PILOT_SHIFT 24
68 #define TXP_PILOT_MASK GENMASK(31, 24)
69 /* Bits 22-23 are set to 0x01 */
70 #define TXP_VERSION_SHIFT 22
71 #define TXP_VERSION_MASK GENMASK(23, 22)
73 /* Powers down the internal memory. */
74 # define TXP_POWERDOWN BIT(21)
76 /* Enables storing the alpha component in 8888/4444, instead of
77 * filling with ~ALPHA_INVERT.
79 # define TXP_ALPHA_ENABLE BIT(20)
81 /* 4 bits, each enables stores for a channel in each set of 4 bytes.
82 * Set to 0xf for normal operation.
84 # define TXP_BYTE_ENABLE_SHIFT 16
85 # define TXP_BYTE_ENABLE_MASK GENMASK(19, 16)
87 /* Debug: Generate VSTART again at EOF. */
88 # define TXP_VSTART_AT_EOF BIT(15)
90 /* Debug: Terminate the current frame immediately. Stops AXI
93 # define TXP_ABORT BIT(14)
95 # define TXP_DITHER BIT(13)
97 /* Inverts alpha if TXP_ALPHA_ENABLE, chooses fill value for
100 # define TXP_ALPHA_INVERT BIT(12)
102 /* Note: I've listed the channels here in high bit (in byte 3/2/1) to
103 * low bit (in byte 0) order.
105 # define TXP_FORMAT_SHIFT 8
106 # define TXP_FORMAT_MASK GENMASK(11, 8)
107 # define TXP_FORMAT_ABGR4444 0
108 # define TXP_FORMAT_ARGB4444 1
109 # define TXP_FORMAT_BGRA4444 2
110 # define TXP_FORMAT_RGBA4444 3
111 # define TXP_FORMAT_BGR565 6
112 # define TXP_FORMAT_RGB565 7
113 /* 888s are non-rotated, raster-only */
114 # define TXP_FORMAT_BGR888 8
115 # define TXP_FORMAT_RGB888 9
116 # define TXP_FORMAT_ABGR8888 12
117 # define TXP_FORMAT_ARGB8888 13
118 # define TXP_FORMAT_BGRA8888 14
119 # define TXP_FORMAT_RGBA8888 15
121 /* If TFORMAT is set, generates LT instead of T format. */
122 # define TXP_LINEAR_UTILE BIT(7)
124 /* Rotate output by 90 degrees. */
125 # define TXP_TRANSPOSE BIT(6)
127 /* Generate a tiled format for V3D. */
128 # define TXP_TFORMAT BIT(5)
130 /* Generates some undefined test mode output. */
131 # define TXP_TEST_MODE BIT(4)
133 /* Request odd field from HVS. */
134 # define TXP_FIELD BIT(3)
136 /* Raise interrupt when idle. */
137 # define TXP_EI BIT(2)
139 /* Set when generating a frame, clears when idle. */
140 # define TXP_BUSY BIT(1)
142 /* Starts a frame. Self-clearing. */
143 # define TXP_GO BIT(0)
145 /* Number of lines received and committed to memory. */
146 #define TXP_PROGRESS 0x10
148 #define TXP_DST_PTR_HIGH 0x1c
150 #define TXP_READ(offset) \
152 kunit_fail_current_test("Accessing a register in a unit test!\n"); \
153 readl(txp->regs + (offset)); \
156 #define TXP_WRITE(offset, val) \
158 kunit_fail_current_test("Accessing a register in a unit test!\n"); \
159 writel(val, txp->regs + (offset)); \
163 struct vc4_crtc base;
164 const struct vc4_txp_data *data;
166 struct platform_device *pdev;
168 struct vc4_encoder encoder;
169 struct drm_writeback_connector connector;
174 #define encoder_to_vc4_txp(_encoder) \
175 container_of_const(_encoder, struct vc4_txp, encoder.base)
177 #define connector_to_vc4_txp(_connector) \
178 container_of_const(_connector, struct vc4_txp, connector.base)
180 static const struct debugfs_reg32 txp_regs[] = {
181 VC4_REG32(TXP_DST_PTR),
182 VC4_REG32(TXP_DST_PITCH),
184 VC4_REG32(TXP_DST_CTRL),
185 VC4_REG32(TXP_PROGRESS),
188 static int vc4_txp_connector_get_modes(struct drm_connector *connector)
190 struct drm_device *dev = connector->dev;
192 return drm_add_modes_noedid(connector, dev->mode_config.max_width,
193 dev->mode_config.max_height);
196 static enum drm_mode_status
197 vc4_txp_connector_mode_valid(struct drm_connector *connector,
198 struct drm_display_mode *mode)
200 struct drm_device *dev = connector->dev;
201 struct drm_mode_config *mode_config = &dev->mode_config;
202 int w = mode->hdisplay, h = mode->vdisplay;
204 if (w < mode_config->min_width || w > mode_config->max_width)
205 return MODE_BAD_HVALUE;
207 if (h < mode_config->min_height || h > mode_config->max_height)
208 return MODE_BAD_VVALUE;
213 static const u32 drm_fmts[] = {
226 static const u32 txp_fmts[] = {
239 static void vc4_txp_armed(struct drm_crtc_state *state)
241 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
243 vc4_state->txp_armed = true;
246 static int vc4_txp_connector_atomic_check(struct drm_connector *conn,
247 struct drm_atomic_state *state)
249 struct drm_connector_state *conn_state;
250 struct drm_crtc_state *crtc_state;
251 struct drm_framebuffer *fb;
254 conn_state = drm_atomic_get_new_connector_state(state, conn);
255 if (!conn_state->writeback_job)
258 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
260 fb = conn_state->writeback_job->fb;
261 if (fb->width != crtc_state->mode.hdisplay ||
262 fb->height != crtc_state->mode.vdisplay) {
263 DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n",
264 fb->width, fb->height);
268 for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) {
269 if (fb->format->format == drm_fmts[i])
273 if (i == ARRAY_SIZE(drm_fmts))
276 /* Pitch must be aligned on 16 bytes. */
277 if (fb->pitches[0] & GENMASK(3, 0))
280 vc4_txp_armed(crtc_state);
285 static void vc4_txp_connector_atomic_commit(struct drm_connector *conn,
286 struct drm_atomic_state *state)
288 struct drm_device *drm = conn->dev;
289 struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(state,
291 struct vc4_txp *txp = connector_to_vc4_txp(conn);
292 const struct vc4_txp_data *txp_data = txp->data;
293 struct drm_gem_dma_object *gem;
294 struct drm_display_mode *mode;
295 struct drm_framebuffer *fb;
296 unsigned int hdisplay;
297 unsigned int vdisplay;
303 if (WARN_ON(!conn_state->writeback_job))
306 mode = &conn_state->crtc->state->adjusted_mode;
307 fb = conn_state->writeback_job->fb;
309 for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) {
310 if (fb->format->format == drm_fmts[i])
314 if (WARN_ON(i == ARRAY_SIZE(drm_fmts)))
317 ctrl = TXP_GO | TXP_EI |
318 VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT);
320 if (txp_data->has_byte_enable)
321 ctrl |= VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE);
323 if (fb->format->has_alpha)
324 ctrl |= TXP_ALPHA_ENABLE;
327 * If TXP_ALPHA_ENABLE isn't set and TXP_ALPHA_INVERT is, the
328 * hardware will force the output padding to be 0xff.
330 ctrl |= TXP_ALPHA_INVERT;
332 if (!drm_dev_enter(drm, &idx))
335 gem = drm_fb_dma_get_gem_obj(fb, 0);
336 addr = gem->dma_addr + fb->offsets[0];
337 TXP_WRITE(TXP_DST_PTR, lower_32_bits(addr));
339 if (txp_data->supports_40bit_addresses)
340 TXP_WRITE(TXP_DST_PTR_HIGH, upper_32_bits(addr) & 0xff);
342 TXP_WRITE(TXP_DST_PITCH, fb->pitches[0]);
344 hdisplay = mode->hdisplay ?: 1;
345 vdisplay = mode->vdisplay ?: 1;
346 if (txp_data->size_minus_one) {
352 VC4_SET_FIELD(hdisplay, TXP_WIDTH) |
353 VC4_SET_FIELD(vdisplay, TXP_HEIGHT));
355 TXP_WRITE(TXP_DST_CTRL, ctrl);
357 drm_writeback_queue_job(&txp->connector, conn_state);
362 static const struct drm_connector_helper_funcs vc4_txp_connector_helper_funcs = {
363 .get_modes = vc4_txp_connector_get_modes,
364 .mode_valid = vc4_txp_connector_mode_valid,
365 .atomic_check = vc4_txp_connector_atomic_check,
366 .atomic_commit = vc4_txp_connector_atomic_commit,
369 static enum drm_connector_status
370 vc4_txp_connector_detect(struct drm_connector *connector, bool force)
372 return connector_status_connected;
375 static const struct drm_connector_funcs vc4_txp_connector_funcs = {
376 .detect = vc4_txp_connector_detect,
377 .fill_modes = drm_helper_probe_single_connector_modes,
378 .destroy = drm_connector_cleanup,
379 .reset = drm_atomic_helper_connector_reset,
380 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
381 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
384 static void vc4_txp_encoder_disable(struct drm_encoder *encoder)
386 struct drm_device *drm = encoder->dev;
387 struct vc4_dev *vc4 = to_vc4_dev(drm);
388 struct vc4_txp *txp = encoder_to_vc4_txp(encoder);
391 if (!drm_dev_enter(drm, &idx))
394 if (TXP_READ(TXP_DST_CTRL) & TXP_BUSY) {
395 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
397 TXP_WRITE(TXP_DST_CTRL, TXP_ABORT);
399 while (TXP_READ(TXP_DST_CTRL) & TXP_BUSY &&
400 time_before(jiffies, timeout))
403 WARN_ON(TXP_READ(TXP_DST_CTRL) & TXP_BUSY);
406 if (vc4->gen < VC4_GEN_6)
407 TXP_WRITE(TXP_DST_CTRL, TXP_POWERDOWN);
412 static const struct drm_encoder_helper_funcs vc4_txp_encoder_helper_funcs = {
413 .disable = vc4_txp_encoder_disable,
416 static int vc4_txp_enable_vblank(struct drm_crtc *crtc)
421 static void vc4_txp_disable_vblank(struct drm_crtc *crtc) {}
423 static const struct drm_crtc_funcs vc4_txp_crtc_funcs = {
424 .set_config = drm_atomic_helper_set_config,
425 .page_flip = vc4_page_flip,
426 .reset = vc4_crtc_reset,
427 .atomic_duplicate_state = vc4_crtc_duplicate_state,
428 .atomic_destroy_state = vc4_crtc_destroy_state,
429 .enable_vblank = vc4_txp_enable_vblank,
430 .disable_vblank = vc4_txp_disable_vblank,
431 .late_register = vc4_crtc_late_register,
434 static int vc4_txp_atomic_check(struct drm_crtc *crtc,
435 struct drm_atomic_state *state)
437 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
441 ret = vc4_hvs_atomic_check(crtc, state);
445 crtc_state->no_vblank = true;
450 static void vc4_txp_atomic_enable(struct drm_crtc *crtc,
451 struct drm_atomic_state *state)
453 drm_crtc_vblank_on(crtc);
454 vc4_hvs_atomic_enable(crtc, state);
457 static void vc4_txp_atomic_disable(struct drm_crtc *crtc,
458 struct drm_atomic_state *state)
460 struct drm_device *dev = crtc->dev;
462 /* Disable vblank irq handling before crtc is disabled. */
463 drm_crtc_vblank_off(crtc);
465 vc4_hvs_atomic_disable(crtc, state);
468 * Make sure we issue a vblank event after disabling the CRTC if
469 * someone was waiting it.
471 if (crtc->state->event) {
474 spin_lock_irqsave(&dev->event_lock, flags);
475 drm_crtc_send_vblank_event(crtc, crtc->state->event);
476 crtc->state->event = NULL;
477 spin_unlock_irqrestore(&dev->event_lock, flags);
481 static const struct drm_crtc_helper_funcs vc4_txp_crtc_helper_funcs = {
482 .atomic_check = vc4_txp_atomic_check,
483 .atomic_begin = vc4_hvs_atomic_begin,
484 .atomic_flush = vc4_hvs_atomic_flush,
485 .atomic_enable = vc4_txp_atomic_enable,
486 .atomic_disable = vc4_txp_atomic_disable,
489 static irqreturn_t vc4_txp_interrupt(int irq, void *data)
491 struct vc4_txp *txp = data;
492 struct vc4_crtc *vc4_crtc = &txp->base;
495 * We don't need to protect the register access using
496 * drm_dev_enter() there because the interrupt handler lifetime
497 * is tied to the device itself, and not to the DRM device.
499 * So when the device will be gone, one of the first thing we
500 * will be doing will be to unregister the interrupt handler,
501 * and then unregister the DRM device. drm_dev_enter() would
502 * thus always succeed if we are here.
504 TXP_WRITE(TXP_DST_CTRL, TXP_READ(TXP_DST_CTRL) & ~TXP_EI);
505 vc4_crtc_handle_vblank(vc4_crtc);
506 drm_writeback_signal_completion(&txp->connector, 0);
511 const struct vc4_txp_data bcm2712_mop_data = {
514 .debugfs_name = "mop_regs",
515 .hvs_available_channels = BIT(2),
518 .encoder_type = VC4_ENCODER_TYPE_TXP0,
519 .has_byte_enable = true,
520 .size_minus_one = true,
521 .supports_40bit_addresses = true,
524 const struct vc4_txp_data bcm2712_moplet_data = {
527 .debugfs_name = "moplet_regs",
528 .hvs_available_channels = BIT(1),
531 .encoder_type = VC4_ENCODER_TYPE_TXP1,
532 .size_minus_one = true,
533 .supports_40bit_addresses = true,
536 const struct vc4_txp_data bcm2835_txp_data = {
539 .debugfs_name = "txp_regs",
540 .hvs_available_channels = BIT(2),
543 .encoder_type = VC4_ENCODER_TYPE_TXP0,
544 .has_byte_enable = true,
547 static int vc4_txp_bind(struct device *dev, struct device *master, void *data)
549 struct platform_device *pdev = to_platform_device(dev);
550 struct drm_device *drm = dev_get_drvdata(master);
551 const struct vc4_txp_data *txp_data;
552 struct vc4_encoder *vc4_encoder;
553 struct drm_encoder *encoder;
554 struct vc4_crtc *vc4_crtc;
558 irq = platform_get_irq(pdev, 0);
562 txp = drmm_kzalloc(drm, sizeof(*txp), GFP_KERNEL);
566 txp_data = of_device_get_match_data(dev);
570 txp->data = txp_data;
572 txp->regs = vc4_ioremap_regs(pdev, 0);
573 if (IS_ERR(txp->regs))
574 return PTR_ERR(txp->regs);
576 vc4_crtc = &txp->base;
577 vc4_crtc->regset.base = txp->regs;
578 vc4_crtc->regset.regs = txp_regs;
579 vc4_crtc->regset.nregs = ARRAY_SIZE(txp_regs);
581 ret = vc4_crtc_init(drm, pdev, vc4_crtc, &txp_data->base,
582 &vc4_txp_crtc_funcs, &vc4_txp_crtc_helper_funcs, true);
586 vc4_encoder = &txp->encoder;
587 txp->encoder.type = txp_data->encoder_type;
589 encoder = &vc4_encoder->base;
590 encoder->possible_crtcs = drm_crtc_mask(&vc4_crtc->base);
592 drm_encoder_helper_add(encoder, &vc4_txp_encoder_helper_funcs);
594 ret = drmm_encoder_init(drm, encoder, NULL, DRM_MODE_ENCODER_VIRTUAL, NULL);
598 drm_connector_helper_add(&txp->connector.base,
599 &vc4_txp_connector_helper_funcs);
600 ret = drm_writeback_connector_init_with_encoder(drm, &txp->connector,
602 &vc4_txp_connector_funcs,
603 drm_fmts, ARRAY_SIZE(drm_fmts));
607 ret = devm_request_irq(dev, irq, vc4_txp_interrupt, 0,
612 dev_set_drvdata(dev, txp);
617 static void vc4_txp_unbind(struct device *dev, struct device *master,
620 struct vc4_txp *txp = dev_get_drvdata(dev);
622 drm_connector_cleanup(&txp->connector.base);
625 static const struct component_ops vc4_txp_ops = {
626 .bind = vc4_txp_bind,
627 .unbind = vc4_txp_unbind,
630 static int vc4_txp_probe(struct platform_device *pdev)
632 return component_add(&pdev->dev, &vc4_txp_ops);
635 static void vc4_txp_remove(struct platform_device *pdev)
637 component_del(&pdev->dev, &vc4_txp_ops);
640 static const struct of_device_id vc4_txp_dt_match[] = {
641 { .compatible = "brcm,bcm2712-mop", .data = &bcm2712_mop_data },
642 { .compatible = "brcm,bcm2712-moplet", .data = &bcm2712_moplet_data },
643 { .compatible = "brcm,bcm2835-txp", .data = &bcm2835_txp_data },
647 struct platform_driver vc4_txp_driver = {
648 .probe = vc4_txp_probe,
649 .remove_new = vc4_txp_remove,
652 .of_match_table = vc4_txp_dt_match,