1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
9 #include <linux/bitfield.h>
10 #include <linux/bitops.h>
12 #define VC4_MASK(high, low) ((u32)GENMASK(high, low))
13 /* Using the GNU statement expression extension */
14 #define VC4_SET_FIELD(value, field) \
16 WARN_ON(!FIELD_FIT(field##_MASK, value)); \
17 FIELD_PREP(field##_MASK, value); \
20 #define VC4_GET_FIELD(word, field) FIELD_GET(field##_MASK, word)
22 #define V3D_IDENT0 0x00000
23 # define V3D_EXPECTED_IDENT0 \
29 #define V3D_IDENT1 0x00004
30 /* Multiples of 1kb */
31 # define V3D_IDENT1_VPM_SIZE_MASK VC4_MASK(31, 28)
32 # define V3D_IDENT1_VPM_SIZE_SHIFT 28
33 # define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16)
34 # define V3D_IDENT1_NSEM_SHIFT 16
35 # define V3D_IDENT1_TUPS_MASK VC4_MASK(15, 12)
36 # define V3D_IDENT1_TUPS_SHIFT 12
37 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)
38 # define V3D_IDENT1_QUPS_SHIFT 8
39 # define V3D_IDENT1_NSLC_MASK VC4_MASK(7, 4)
40 # define V3D_IDENT1_NSLC_SHIFT 4
41 # define V3D_IDENT1_REV_MASK VC4_MASK(3, 0)
42 # define V3D_IDENT1_REV_SHIFT 0
44 #define V3D_IDENT2 0x00008
45 #define V3D_SCRATCH 0x00010
46 #define V3D_L2CACTL 0x00020
47 # define V3D_L2CACTL_L2CCLR BIT(2)
48 # define V3D_L2CACTL_L2CDIS BIT(1)
49 # define V3D_L2CACTL_L2CENA BIT(0)
51 #define V3D_SLCACTL 0x00024
52 # define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24)
53 # define V3D_SLCACTL_T1CC_SHIFT 24
54 # define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16)
55 # define V3D_SLCACTL_T0CC_SHIFT 16
56 # define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8)
57 # define V3D_SLCACTL_UCC_SHIFT 8
58 # define V3D_SLCACTL_ICC_MASK VC4_MASK(3, 0)
59 # define V3D_SLCACTL_ICC_SHIFT 0
61 #define V3D_INTCTL 0x00030
62 #define V3D_INTENA 0x00034
63 #define V3D_INTDIS 0x00038
64 # define V3D_INT_SPILLUSE BIT(3)
65 # define V3D_INT_OUTOMEM BIT(2)
66 # define V3D_INT_FLDONE BIT(1)
67 # define V3D_INT_FRDONE BIT(0)
69 #define V3D_CT0CS 0x00100
70 #define V3D_CT1CS 0x00104
71 #define V3D_CTNCS(n) (V3D_CT0CS + 4 * n)
72 # define V3D_CTRSTA BIT(15)
73 # define V3D_CTSEMA BIT(12)
74 # define V3D_CTRTSD BIT(8)
75 # define V3D_CTRUN BIT(5)
76 # define V3D_CTSUBS BIT(4)
77 # define V3D_CTERR BIT(3)
78 # define V3D_CTMODE BIT(0)
80 #define V3D_CT0EA 0x00108
81 #define V3D_CT1EA 0x0010c
82 #define V3D_CTNEA(n) (V3D_CT0EA + 4 * (n))
83 #define V3D_CT0CA 0x00110
84 #define V3D_CT1CA 0x00114
85 #define V3D_CTNCA(n) (V3D_CT0CA + 4 * (n))
86 #define V3D_CT00RA0 0x00118
87 #define V3D_CT01RA0 0x0011c
88 #define V3D_CTNRA0(n) (V3D_CT00RA0 + 4 * (n))
89 #define V3D_CT0LC 0x00120
90 #define V3D_CT1LC 0x00124
91 #define V3D_CTNLC(n) (V3D_CT0LC + 4 * (n))
92 #define V3D_CT0PC 0x00128
93 #define V3D_CT1PC 0x0012c
94 #define V3D_CTNPC(n) (V3D_CT0PC + 4 * (n))
96 #define V3D_PCS 0x00130
97 # define V3D_BMOOM BIT(8)
98 # define V3D_RMBUSY BIT(3)
99 # define V3D_RMACTIVE BIT(2)
100 # define V3D_BMBUSY BIT(1)
101 # define V3D_BMACTIVE BIT(0)
103 #define V3D_BFC 0x00134
104 #define V3D_RFC 0x00138
105 #define V3D_BPCA 0x00300
106 #define V3D_BPCS 0x00304
107 #define V3D_BPOA 0x00308
108 #define V3D_BPOS 0x0030c
109 #define V3D_BXCF 0x00310
110 #define V3D_SQRSV0 0x00410
111 #define V3D_SQRSV1 0x00414
112 #define V3D_SQCNTL 0x00418
113 #define V3D_SRQPC 0x00430
114 #define V3D_SRQUA 0x00434
115 #define V3D_SRQUL 0x00438
116 #define V3D_SRQCS 0x0043c
117 #define V3D_VPACNTL 0x00500
118 #define V3D_VPMBASE 0x00504
119 #define V3D_PCTRC 0x00670
120 #define V3D_PCTRE 0x00674
121 # define V3D_PCTRE_EN BIT(31)
122 #define V3D_PCTR(x) (0x00680 + ((x) * 8))
123 #define V3D_PCTRS(x) (0x00684 + ((x) * 8))
124 #define V3D_DBGE 0x00f00
125 #define V3D_FDBGO 0x00f04
126 #define V3D_FDBGB 0x00f08
127 #define V3D_FDBGR 0x00f0c
128 #define V3D_FDBGS 0x00f10
129 #define V3D_ERRSTAT 0x00f20
131 #define PV_CONTROL 0x00
132 # define PV5_CONTROL_FIFO_LEVEL_HIGH_MASK VC4_MASK(26, 25)
133 # define PV5_CONTROL_FIFO_LEVEL_HIGH_SHIFT 25
134 # define PV_CONTROL_FORMAT_MASK VC4_MASK(23, 21)
135 # define PV_CONTROL_FORMAT_SHIFT 21
136 # define PV_CONTROL_FORMAT_24 0
137 # define PV_CONTROL_FORMAT_DSIV_16 1
138 # define PV_CONTROL_FORMAT_DSIC_16 2
139 # define PV_CONTROL_FORMAT_DSIV_18 3
140 # define PV_CONTROL_FORMAT_DSIV_24 4
142 # define PV_CONTROL_FIFO_LEVEL_MASK VC4_MASK(20, 15)
143 # define PV_CONTROL_FIFO_LEVEL_SHIFT 15
144 # define PV_CONTROL_CLR_AT_START BIT(14)
145 # define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13)
146 # define PV_CONTROL_WAIT_HSTART BIT(12)
147 # define PV_CONTROL_PIXEL_REP_MASK VC4_MASK(5, 4)
148 # define PV_CONTROL_PIXEL_REP_SHIFT 4
149 # define PV_CONTROL_CLK_SELECT_DSI 0
150 # define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI 1
151 # define PV_CONTROL_CLK_SELECT_VEC 2
152 # define PV_CONTROL_CLK_SELECT_MASK VC4_MASK(3, 2)
153 # define PV_CONTROL_CLK_SELECT_SHIFT 2
154 # define PV_CONTROL_FIFO_CLR BIT(1)
155 # define PV_CONTROL_EN BIT(0)
157 #define PV_V_CONTROL 0x04
158 # define PV_VCONTROL_ODD_DELAY_MASK VC4_MASK(22, 6)
159 # define PV_VCONTROL_ODD_DELAY_SHIFT 6
160 # define PV_VCONTROL_ODD_FIRST BIT(5)
161 # define PV_VCONTROL_INTERLACE BIT(4)
162 # define PV_VCONTROL_DSI BIT(3)
163 # define PV_VCONTROL_COMMAND BIT(2)
164 # define PV_VCONTROL_CONTINUOUS BIT(1)
165 # define PV_VCONTROL_VIDEN BIT(0)
167 #define PV_VSYNCD_EVEN 0x08
169 #define PV_HORZA 0x0c
170 # define PV_HORZA_HBP_MASK VC4_MASK(31, 16)
171 # define PV_HORZA_HBP_SHIFT 16
172 # define PV_HORZA_HSYNC_MASK VC4_MASK(15, 0)
173 # define PV_HORZA_HSYNC_SHIFT 0
175 #define PV_HORZB 0x10
176 # define PV_HORZB_HFP_MASK VC4_MASK(31, 16)
177 # define PV_HORZB_HFP_SHIFT 16
178 # define PV_HORZB_HACTIVE_MASK VC4_MASK(15, 0)
179 # define PV_HORZB_HACTIVE_SHIFT 0
181 #define PV_VERTA 0x14
182 # define PV_VERTA_VBP_MASK VC4_MASK(31, 16)
183 # define PV_VERTA_VBP_SHIFT 16
184 # define PV_VERTA_VSYNC_MASK VC4_MASK(15, 0)
185 # define PV_VERTA_VSYNC_SHIFT 0
187 #define PV_VERTB 0x18
188 # define PV_VERTB_VFP_MASK VC4_MASK(31, 16)
189 # define PV_VERTB_VFP_SHIFT 16
190 # define PV_VERTB_VACTIVE_MASK VC4_MASK(15, 0)
191 # define PV_VERTB_VACTIVE_SHIFT 0
193 #define PV_VERTA_EVEN 0x1c
194 #define PV_VERTB_EVEN 0x20
196 #define PV_INTEN 0x24
197 #define PV_INTSTAT 0x28
198 # define PV_INT_VID_IDLE BIT(9)
199 # define PV_INT_VFP_END BIT(8)
200 # define PV_INT_VFP_START BIT(7)
201 # define PV_INT_VACT_START BIT(6)
202 # define PV_INT_VBP_START BIT(5)
203 # define PV_INT_VSYNC_START BIT(4)
204 # define PV_INT_HFP_START BIT(3)
205 # define PV_INT_HACT_START BIT(2)
206 # define PV_INT_HBP_START BIT(1)
207 # define PV_INT_HSYNC_START BIT(0)
211 #define PV_HACT_ACT 0x30
213 #define PV_MUX_CFG 0x34
214 # define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_MASK VC4_MASK(5, 2)
215 # define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_SHIFT 2
216 # define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP 8
218 #define SCALER_CHANNELS_COUNT 3
220 #define SCALER_DISPCTRL 0x00000000
221 /* Global register for clock gating the HVS */
222 # define SCALER_DISPCTRL_ENABLE BIT(31)
223 # define SCALER_DISPCTRL_DSP3_MUX_MASK VC4_MASK(19, 18)
224 # define SCALER_DISPCTRL_DSP3_MUX_SHIFT 18
226 /* Enables Display 0 short line and underrun contribution to
227 * SCALER_DISPSTAT_IRQDISP0. Note that short frame contributions are
230 # define SCALER_DISPCTRL_DSPEISLUR(x) BIT(13 + (x))
231 /* Enables Display 0 end-of-line-N contribution to
232 * SCALER_DISPSTAT_IRQDISP0
234 # define SCALER_DISPCTRL_DSPEIEOLN(x) BIT(8 + ((x) * 2))
235 /* Enables Display 0 EOF contribution to SCALER_DISPSTAT_IRQDISP0 */
236 # define SCALER_DISPCTRL_DSPEIEOF(x) BIT(7 + ((x) * 2))
238 # define SCALER_DISPCTRL_SLVRDEIRQ BIT(6)
239 # define SCALER_DISPCTRL_SLVWREIRQ BIT(5)
240 # define SCALER_DISPCTRL_DMAEIRQ BIT(4)
241 /* Enables interrupt generation on the enabled EOF/EOLN/EISLUR
242 * bits and short frames..
244 # define SCALER_DISPCTRL_DISPEIRQ(x) BIT(1 + (x))
245 /* Enables interrupt generation on scaler profiler interrupt. */
246 # define SCALER_DISPCTRL_SCLEIRQ BIT(0)
248 #define SCALER_DISPSTAT 0x00000004
249 # define SCALER_DISPSTAT_RESP_MASK VC4_MASK(15, 14)
250 # define SCALER_DISPSTAT_RESP_SHIFT 14
251 # define SCALER_DISPSTAT_RESP_OKAY 0
252 # define SCALER_DISPSTAT_RESP_EXOKAY 1
253 # define SCALER_DISPSTAT_RESP_SLVERR 2
254 # define SCALER_DISPSTAT_RESP_DECERR 3
256 # define SCALER_DISPSTAT_COBLOW(x) BIT(13 + ((x) * 8))
257 /* Set when the DISPEOLN line is done compositing. */
258 # define SCALER_DISPSTAT_EOLN(x) BIT(12 + ((x) * 8))
259 /* Set when VSTART is seen but there are still pixels in the current
262 # define SCALER_DISPSTAT_ESFRAME(x) BIT(11 + ((x) * 8))
263 /* Set when HSTART is seen but there are still pixels in the current
266 # define SCALER_DISPSTAT_ESLINE(x) BIT(10 + ((x) * 8))
267 /* Set when the the downstream tries to read from the display FIFO
270 # define SCALER_DISPSTAT_EUFLOW(x) BIT(9 + ((x) * 8))
271 /* Set when the display mode changes from RUN to EOF */
272 # define SCALER_DISPSTAT_EOF(x) BIT(8 + ((x) * 8))
274 # define SCALER_DISPSTAT_IRQMASK(x) VC4_MASK(13 + ((x) * 8), \
277 /* Set on AXI invalid DMA ID error. */
278 # define SCALER_DISPSTAT_DMA_ERROR BIT(7)
279 /* Set on AXI slave read decode error */
280 # define SCALER_DISPSTAT_IRQSLVRD BIT(6)
281 /* Set on AXI slave write decode error */
282 # define SCALER_DISPSTAT_IRQSLVWR BIT(5)
283 /* Set when SCALER_DISPSTAT_DMA_ERROR is set, or
284 * SCALER_DISPSTAT_RESP_ERROR is not SCALER_DISPSTAT_RESP_OKAY.
286 # define SCALER_DISPSTAT_IRQDMA BIT(4)
287 /* Set when any of the EOF/EOLN/ESFRAME/ESLINE bits are set and their
288 * corresponding interrupt bit is enabled in DISPCTRL.
290 # define SCALER_DISPSTAT_IRQDISP(x) BIT(1 + (x))
291 /* On read, the profiler interrupt. On write, clear *all* interrupt bits. */
292 # define SCALER_DISPSTAT_IRQSCL BIT(0)
294 #define SCALER_DISPID 0x00000008
295 #define SCALER_DISPECTRL 0x0000000c
296 # define SCALER_DISPECTRL_DSP2_MUX_SHIFT 31
297 # define SCALER_DISPECTRL_DSP2_MUX_MASK VC4_MASK(31, 31)
299 #define SCALER_DISPPROF 0x00000010
301 #define SCALER_DISPDITHER 0x00000014
302 # define SCALER_DISPDITHER_DSP5_MUX_SHIFT 30
303 # define SCALER_DISPDITHER_DSP5_MUX_MASK VC4_MASK(31, 30)
305 #define SCALER_DISPEOLN 0x00000018
306 # define SCALER_DISPEOLN_DSP4_MUX_SHIFT 30
307 # define SCALER_DISPEOLN_DSP4_MUX_MASK VC4_MASK(31, 30)
309 #define SCALER_DISPLIST0 0x00000020
310 #define SCALER_DISPLIST1 0x00000024
311 #define SCALER_DISPLIST2 0x00000028
312 #define SCALER_DISPLSTAT 0x0000002c
313 #define SCALER_DISPLISTX(x) (SCALER_DISPLIST0 + \
314 (x) * (SCALER_DISPLIST1 - \
317 #define SCALER_DISPLACT0 0x00000030
318 #define SCALER_DISPLACT1 0x00000034
319 #define SCALER_DISPLACT2 0x00000038
320 #define SCALER_DISPLACTX(x) (SCALER_DISPLACT0 + \
321 (x) * (SCALER_DISPLACT1 - \
324 #define SCALER_DISPCTRL0 0x00000040
325 # define SCALER_DISPCTRLX_ENABLE BIT(31)
326 # define SCALER_DISPCTRLX_RESET BIT(30)
327 /* Generates a single frame when VSTART is seen and stops at the last
328 * pixel read from the FIFO.
330 # define SCALER_DISPCTRLX_ONESHOT BIT(29)
331 /* Processes a single context in the dlist and then task switch,
332 * instead of an entire line.
334 # define SCALER_DISPCTRLX_ONECTX BIT(28)
335 /* Set to have DISPSLAVE return 2 16bpp pixels and no status data. */
336 # define SCALER_DISPCTRLX_FIFO32 BIT(27)
337 /* Turns on output to the DISPSLAVE register instead of the normal
340 # define SCALER_DISPCTRLX_FIFOREG BIT(26)
342 # define SCALER_DISPCTRLX_WIDTH_MASK VC4_MASK(23, 12)
343 # define SCALER_DISPCTRLX_WIDTH_SHIFT 12
344 # define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0)
345 # define SCALER_DISPCTRLX_HEIGHT_SHIFT 0
347 # define SCALER5_DISPCTRLX_WIDTH_MASK VC4_MASK(28, 16)
348 # define SCALER5_DISPCTRLX_WIDTH_SHIFT 16
349 /* Generates a single frame when VSTART is seen and stops at the last
350 * pixel read from the FIFO.
352 # define SCALER5_DISPCTRLX_ONESHOT BIT(15)
353 /* Processes a single context in the dlist and then task switch,
354 * instead of an entire line.
356 # define SCALER5_DISPCTRLX_ONECTX_MASK VC4_MASK(14, 13)
357 # define SCALER5_DISPCTRLX_ONECTX_SHIFT 13
358 # define SCALER5_DISPCTRLX_HEIGHT_MASK VC4_MASK(12, 0)
359 # define SCALER5_DISPCTRLX_HEIGHT_SHIFT 0
361 #define SCALER_DISPBKGND0 0x00000044
362 # define SCALER_DISPBKGND_AUTOHS BIT(31)
363 # define SCALER_DISPBKGND_INTERLACE BIT(30)
364 # define SCALER_DISPBKGND_GAMMA BIT(29)
365 # define SCALER_DISPBKGND_TESTMODE_MASK VC4_MASK(28, 25)
366 # define SCALER_DISPBKGND_TESTMODE_SHIFT 25
367 /* Enables filling the scaler line with the RGB value in the low 24
368 * bits before compositing. Costs cycles, so should be skipped if
369 * opaque display planes will cover everything.
371 # define SCALER_DISPBKGND_FILL BIT(24)
373 #define SCALER_DISPSTAT0 0x00000048
374 # define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30)
375 # define SCALER_DISPSTATX_MODE_SHIFT 30
376 # define SCALER_DISPSTATX_MODE_DISABLED 0
377 # define SCALER_DISPSTATX_MODE_INIT 1
378 # define SCALER_DISPSTATX_MODE_RUN 2
379 # define SCALER_DISPSTATX_MODE_EOF 3
380 # define SCALER_DISPSTATX_FULL BIT(29)
381 # define SCALER_DISPSTATX_EMPTY BIT(28)
382 # define SCALER_DISPSTATX_LINE_MASK VC4_MASK(11, 0)
383 # define SCALER_DISPSTATX_LINE_SHIFT 0
385 #define SCALER_DISPBASE0 0x0000004c
386 /* Last pixel in the COB (display FIFO memory) allocated to this HVS
387 * channel. Must be 4-pixel aligned (and thus 4 pixels less than the
390 # define SCALER_DISPBASEX_TOP_MASK VC4_MASK(31, 16)
391 # define SCALER_DISPBASEX_TOP_SHIFT 16
392 /* First pixel in the COB (display FIFO memory) allocated to this HVS
393 * channel. Must be 4-pixel aligned.
395 # define SCALER_DISPBASEX_BASE_MASK VC4_MASK(15, 0)
396 # define SCALER_DISPBASEX_BASE_SHIFT 0
398 #define SCALER_DISPCTRL1 0x00000050
399 #define SCALER_DISPBKGND1 0x00000054
400 #define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \
401 (x) * (SCALER_DISPBKGND1 - \
403 #define SCALER_DISPSTAT1 0x00000058
404 # define SCALER_DISPSTAT1_FRCNT0_MASK VC4_MASK(23, 18)
405 # define SCALER_DISPSTAT1_FRCNT0_SHIFT 18
406 # define SCALER_DISPSTAT1_FRCNT1_MASK VC4_MASK(17, 12)
407 # define SCALER_DISPSTAT1_FRCNT1_SHIFT 12
409 #define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \
410 (x) * (SCALER_DISPSTAT1 - \
413 #define SCALER_DISPBASE1 0x0000005c
414 #define SCALER_DISPBASEX(x) (SCALER_DISPBASE0 + \
415 (x) * (SCALER_DISPBASE1 - \
417 #define SCALER_DISPCTRL2 0x00000060
418 #define SCALER_DISPCTRLX(x) (SCALER_DISPCTRL0 + \
419 (x) * (SCALER_DISPCTRL1 - \
421 #define SCALER_DISPBKGND2 0x00000064
423 #define SCALER_DISPSTAT2 0x00000068
424 # define SCALER_DISPSTAT2_FRCNT2_MASK VC4_MASK(17, 12)
425 # define SCALER_DISPSTAT2_FRCNT2_SHIFT 12
427 #define SCALER_DISPBASE2 0x0000006c
428 #define SCALER_DISPALPHA2 0x00000070
429 #define SCALER_GAMADDR 0x00000078
430 # define SCALER_GAMADDR_AUTOINC BIT(31)
431 /* Enables all gamma ramp SRAMs, not just those of CRTCs with gamma
434 # define SCALER_GAMADDR_SRAMENB BIT(30)
436 #define SCALER_OLEDOFFS 0x00000080
437 /* Clamps R to [16,235] and G/B to [16,240]. */
438 # define SCALER_OLEDOFFS_YUVCLAMP BIT(31)
440 /* Chooses which display FIFO the matrix applies to. */
441 # define SCALER_OLEDOFFS_DISPFIFO_MASK VC4_MASK(25, 24)
442 # define SCALER_OLEDOFFS_DISPFIFO_SHIFT 24
443 # define SCALER_OLEDOFFS_DISPFIFO_DISABLED 0
444 # define SCALER_OLEDOFFS_DISPFIFO_0 1
445 # define SCALER_OLEDOFFS_DISPFIFO_1 2
446 # define SCALER_OLEDOFFS_DISPFIFO_2 3
448 /* Offsets are 8-bit 2s-complement. */
449 # define SCALER_OLEDOFFS_RED_MASK VC4_MASK(23, 16)
450 # define SCALER_OLEDOFFS_RED_SHIFT 16
451 # define SCALER_OLEDOFFS_GREEN_MASK VC4_MASK(15, 8)
452 # define SCALER_OLEDOFFS_GREEN_SHIFT 8
453 # define SCALER_OLEDOFFS_BLUE_MASK VC4_MASK(7, 0)
454 # define SCALER_OLEDOFFS_BLUE_SHIFT 0
456 /* The coefficients are S0.9 fractions. */
457 #define SCALER_OLEDCOEF0 0x00000084
458 # define SCALER_OLEDCOEF0_B_TO_R_MASK VC4_MASK(29, 20)
459 # define SCALER_OLEDCOEF0_B_TO_R_SHIFT 20
460 # define SCALER_OLEDCOEF0_B_TO_G_MASK VC4_MASK(19, 10)
461 # define SCALER_OLEDCOEF0_B_TO_G_SHIFT 10
462 # define SCALER_OLEDCOEF0_B_TO_B_MASK VC4_MASK(9, 0)
463 # define SCALER_OLEDCOEF0_B_TO_B_SHIFT 0
465 #define SCALER_OLEDCOEF1 0x00000088
466 # define SCALER_OLEDCOEF1_G_TO_R_MASK VC4_MASK(29, 20)
467 # define SCALER_OLEDCOEF1_G_TO_R_SHIFT 20
468 # define SCALER_OLEDCOEF1_G_TO_G_MASK VC4_MASK(19, 10)
469 # define SCALER_OLEDCOEF1_G_TO_G_SHIFT 10
470 # define SCALER_OLEDCOEF1_G_TO_B_MASK VC4_MASK(9, 0)
471 # define SCALER_OLEDCOEF1_G_TO_B_SHIFT 0
473 #define SCALER_OLEDCOEF2 0x0000008c
474 # define SCALER_OLEDCOEF2_R_TO_R_MASK VC4_MASK(29, 20)
475 # define SCALER_OLEDCOEF2_R_TO_R_SHIFT 20
476 # define SCALER_OLEDCOEF2_R_TO_G_MASK VC4_MASK(19, 10)
477 # define SCALER_OLEDCOEF2_R_TO_G_SHIFT 10
478 # define SCALER_OLEDCOEF2_R_TO_B_MASK VC4_MASK(9, 0)
479 # define SCALER_OLEDCOEF2_R_TO_B_SHIFT 0
481 /* Slave addresses for DMAing from HVS composition output to other
482 * devices. The top bits are valid only in !FIFO32 mode.
484 #define SCALER_DISPSLAVE0 0x000000c0
485 #define SCALER_DISPSLAVE1 0x000000c9
486 #define SCALER_DISPSLAVE2 0x000000d0
487 # define SCALER_DISPSLAVE_ISSUE_VSTART BIT(31)
488 # define SCALER_DISPSLAVE_ISSUE_HSTART BIT(30)
489 /* Set when the current line has been read and an HSTART is required. */
490 # define SCALER_DISPSLAVE_EOL BIT(26)
491 /* Set when the display FIFO is empty. */
492 # define SCALER_DISPSLAVE_EMPTY BIT(25)
493 /* Set when there is RGB data ready to read. */
494 # define SCALER_DISPSLAVE_VALID BIT(24)
495 # define SCALER_DISPSLAVE_RGB_MASK VC4_MASK(23, 0)
496 # define SCALER_DISPSLAVE_RGB_SHIFT 0
498 #define SCALER_GAMDATA 0x000000e0
499 #define SCALER_DLIST_START 0x00002000
500 #define SCALER_DLIST_SIZE 0x00004000
502 /* Gamma PWL for each channel. 16 points for each of 4 colour channels (alpha
503 * only on channel 2). 8 bytes per entry, offsets first, then gradient:
506 * Values for X and C are left justified, and vary depending on the width of
508 * 8-bit pipeline: X uses [31:24], C is U8.8 format, and GRAD is U4.8.
509 * 12-bit pipeline: X uses [31:20], C is U12.4 format, and GRAD is U4.8.
511 * The 3 HVS channels start at 0x400 offsets (ie chan 1 starts at 0x2400, and
514 #define SCALER5_DSPGAMMA_NUM_POINTS 16
515 #define SCALER5_DSPGAMMA_START 0x00002000
516 #define SCALER5_DSPGAMMA_CHAN_OFFSET 0x400
517 # define SCALER5_DSPGAMMA_OFF_X_MASK VC4_MASK(31, 20)
518 # define SCALER5_DSPGAMMA_OFF_X_SHIFT 20
519 # define SCALER5_DSPGAMMA_OFF_C_MASK VC4_MASK(15, 0)
520 # define SCALER5_DSPGAMMA_OFF_C_SHIFT 0
521 # define SCALER5_DSPGAMMA_GRAD_MASK VC4_MASK(11, 0)
522 # define SCALER5_DSPGAMMA_GRAD_SHIFT 0
524 #define SCALER5_DLIST_START 0x00004000
526 # define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1)
527 # define VC4_HDMI_SW_RESET_HDMI BIT(0)
529 # define VC4_HDMI_HOTPLUG_CONNECTED BIT(0)
531 # define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE BIT(27)
532 # define VC4_HDMI_MAI_CONFIG_BIT_REVERSE BIT(26)
533 # define VC4_HDMI_MAI_CHANNEL_MASK_MASK VC4_MASK(15, 0)
534 # define VC4_HDMI_MAI_CHANNEL_MASK_SHIFT 0
536 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT BIT(29)
537 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS BIT(24)
538 # define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT BIT(19)
539 # define VC4_HDMI_AUDIO_PACKET_FORCE_B_FRAME BIT(18)
540 # define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_MASK VC4_MASK(13, 10)
541 # define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_SHIFT 10
542 /* If set, then multichannel, otherwise 2 channel. */
543 # define VC4_HDMI_AUDIO_PACKET_AUDIO_LAYOUT BIT(9)
544 /* If set, then AUDIO_LAYOUT overrides audio_cea_mask */
545 # define VC4_HDMI_AUDIO_PACKET_FORCE_AUDIO_LAYOUT BIT(8)
546 # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_MASK VC4_MASK(7, 0)
547 # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_SHIFT 0
549 # define VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT_MASK VC4_MASK(23, 16)
550 # define VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT_SHIFT 16
553 VC4_HDMI_MAI_FORMAT_PCM = 2,
554 VC4_HDMI_MAI_FORMAT_HBR = 200,
557 # define VC4_HDMI_MAI_FORMAT_SAMPLE_RATE_MASK VC4_MASK(15, 8)
558 # define VC4_HDMI_MAI_FORMAT_SAMPLE_RATE_SHIFT 8
561 VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED = 0,
562 VC4_HDMI_MAI_SAMPLE_RATE_8000 = 1,
563 VC4_HDMI_MAI_SAMPLE_RATE_11025 = 2,
564 VC4_HDMI_MAI_SAMPLE_RATE_12000 = 3,
565 VC4_HDMI_MAI_SAMPLE_RATE_16000 = 4,
566 VC4_HDMI_MAI_SAMPLE_RATE_22050 = 5,
567 VC4_HDMI_MAI_SAMPLE_RATE_24000 = 6,
568 VC4_HDMI_MAI_SAMPLE_RATE_32000 = 7,
569 VC4_HDMI_MAI_SAMPLE_RATE_44100 = 8,
570 VC4_HDMI_MAI_SAMPLE_RATE_48000 = 9,
571 VC4_HDMI_MAI_SAMPLE_RATE_64000 = 10,
572 VC4_HDMI_MAI_SAMPLE_RATE_88200 = 11,
573 VC4_HDMI_MAI_SAMPLE_RATE_96000 = 12,
574 VC4_HDMI_MAI_SAMPLE_RATE_128000 = 13,
575 VC4_HDMI_MAI_SAMPLE_RATE_176400 = 14,
576 VC4_HDMI_MAI_SAMPLE_RATE_192000 = 15,
579 # define VC4_HDMI_RAM_PACKET_ENABLE BIT(16)
581 /* When set, the CTS_PERIOD counts based on MAI bus sync pulse instead
584 # define VC4_HDMI_CRP_USE_MAI_BUS_SYNC_FOR_CTS BIT(26)
585 /* When set, no CRP packets will be sent. */
586 # define VC4_HDMI_CRP_CFG_DISABLE BIT(25)
587 /* If set, generates CTS values based on N, audio clock, and video
588 * clock. N must be divisible by 128.
590 # define VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN BIT(24)
591 # define VC4_HDMI_CRP_CFG_N_MASK VC4_MASK(19, 0)
592 # define VC4_HDMI_CRP_CFG_N_SHIFT 0
594 # define VC4_HDMI_HORZA_VPOS BIT(14)
595 # define VC4_HDMI_HORZA_HPOS BIT(13)
596 /* Horizontal active pixels (hdisplay). */
597 # define VC4_HDMI_HORZA_HAP_MASK VC4_MASK(12, 0)
598 # define VC4_HDMI_HORZA_HAP_SHIFT 0
600 /* Horizontal pack porch (htotal - hsync_end). */
601 # define VC4_HDMI_HORZB_HBP_MASK VC4_MASK(29, 20)
602 # define VC4_HDMI_HORZB_HBP_SHIFT 20
603 /* Horizontal sync pulse (hsync_end - hsync_start). */
604 # define VC4_HDMI_HORZB_HSP_MASK VC4_MASK(19, 10)
605 # define VC4_HDMI_HORZB_HSP_SHIFT 10
606 /* Horizontal front porch (hsync_start - hdisplay). */
607 # define VC4_HDMI_HORZB_HFP_MASK VC4_MASK(9, 0)
608 # define VC4_HDMI_HORZB_HFP_SHIFT 0
610 # define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14)
611 # define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13)
612 # define VC4_HDMI_FIFO_CTL_ON_VB BIT(7)
613 # define VC4_HDMI_FIFO_CTL_RECENTER BIT(6)
614 # define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5)
615 # define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4)
616 # define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3)
617 # define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2)
618 # define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1)
619 # define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0)
620 # define VC4_HDMI_FIFO_VALID_WRITE_MASK 0xefff
622 # define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15)
623 # define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5)
624 # define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3)
625 # define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1)
626 # define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0)
628 /* Vertical sync pulse (vsync_end - vsync_start). */
629 # define VC4_HDMI_VERTA_VSP_MASK VC4_MASK(24, 20)
630 # define VC4_HDMI_VERTA_VSP_SHIFT 20
631 /* Vertical front porch (vsync_start - vdisplay). */
632 # define VC4_HDMI_VERTA_VFP_MASK VC4_MASK(19, 13)
633 # define VC4_HDMI_VERTA_VFP_SHIFT 13
634 /* Vertical active lines (vdisplay). */
635 # define VC4_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
636 # define VC4_HDMI_VERTA_VAL_SHIFT 0
638 /* Vertical sync pulse offset (for interlaced) */
639 # define VC4_HDMI_VERTB_VSPO_MASK VC4_MASK(21, 9)
640 # define VC4_HDMI_VERTB_VSPO_SHIFT 9
641 /* Vertical pack porch (vtotal - vsync_end). */
642 # define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0)
643 # define VC4_HDMI_VERTB_VBP_SHIFT 0
645 /* Set when the transmission has ended. */
646 # define VC4_HDMI_CEC_TX_EOM BIT(31)
647 /* If set, transmission was acked on the 1st or 2nd attempt (only one
648 * retry is attempted). If in continuous mode, this means TX needs to
649 * be filled if !TX_EOM.
651 # define VC4_HDMI_CEC_TX_STATUS_GOOD BIT(30)
652 # define VC4_HDMI_CEC_RX_EOM BIT(29)
653 # define VC4_HDMI_CEC_RX_STATUS_GOOD BIT(28)
654 /* Number of bytes received for the message. */
655 # define VC4_HDMI_CEC_REC_WRD_CNT_MASK VC4_MASK(27, 24)
656 # define VC4_HDMI_CEC_REC_WRD_CNT_SHIFT 24
657 /* Sets continuous receive mode. Generates interrupt after each 8
658 * bytes to signal that RX_DATA should be consumed, and at RX_EOM.
660 * If disabled, maximum 16 bytes will be received (including header),
661 * and interrupt at RX_EOM. Later bytes will be acked but not put
664 # define VC4_HDMI_CEC_RX_CONTINUE BIT(23)
665 # define VC4_HDMI_CEC_TX_CONTINUE BIT(22)
666 /* Set this after a CEC interrupt. */
667 # define VC4_HDMI_CEC_CLEAR_RECEIVE_OFF BIT(21)
668 /* Starts a TX. Will wait for appropriate idel time before CEC
669 * activity. Must be cleared in between transmits.
671 # define VC4_HDMI_CEC_START_XMIT_BEGIN BIT(20)
672 # define VC4_HDMI_CEC_MESSAGE_LENGTH_MASK VC4_MASK(19, 16)
673 # define VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT 16
674 /* Device's CEC address */
675 # define VC4_HDMI_CEC_ADDR_MASK VC4_MASK(15, 12)
676 # define VC4_HDMI_CEC_ADDR_SHIFT 12
677 /* Divides off of HSM clock to generate CEC bit clock. */
678 /* With the current defaults the CEC bit clock is 40 kHz = 25 usec */
679 # define VC4_HDMI_CEC_DIV_CLK_CNT_MASK VC4_MASK(11, 0)
680 # define VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT 0
682 /* Set these fields to how many bit clock cycles get to that many
685 # define VC4_HDMI_CEC_CNT_TO_1500_US_MASK VC4_MASK(30, 24)
686 # define VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT 24
687 # define VC4_HDMI_CEC_CNT_TO_1300_US_MASK VC4_MASK(23, 17)
688 # define VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT 17
689 # define VC4_HDMI_CEC_CNT_TO_800_US_MASK VC4_MASK(16, 11)
690 # define VC4_HDMI_CEC_CNT_TO_800_US_SHIFT 11
691 # define VC4_HDMI_CEC_CNT_TO_600_US_MASK VC4_MASK(10, 5)
692 # define VC4_HDMI_CEC_CNT_TO_600_US_SHIFT 5
693 # define VC4_HDMI_CEC_CNT_TO_400_US_MASK VC4_MASK(4, 0)
694 # define VC4_HDMI_CEC_CNT_TO_400_US_SHIFT 0
696 # define VC4_HDMI_CEC_CNT_TO_2750_US_MASK VC4_MASK(31, 24)
697 # define VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT 24
698 # define VC4_HDMI_CEC_CNT_TO_2400_US_MASK VC4_MASK(23, 16)
699 # define VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT 16
700 # define VC4_HDMI_CEC_CNT_TO_2050_US_MASK VC4_MASK(15, 8)
701 # define VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT 8
702 # define VC4_HDMI_CEC_CNT_TO_1700_US_MASK VC4_MASK(7, 0)
703 # define VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT 0
705 # define VC4_HDMI_CEC_CNT_TO_4300_US_MASK VC4_MASK(31, 24)
706 # define VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT 24
707 # define VC4_HDMI_CEC_CNT_TO_3900_US_MASK VC4_MASK(23, 16)
708 # define VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT 16
709 # define VC4_HDMI_CEC_CNT_TO_3600_US_MASK VC4_MASK(15, 8)
710 # define VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT 8
711 # define VC4_HDMI_CEC_CNT_TO_3500_US_MASK VC4_MASK(7, 0)
712 # define VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT 0
714 # define VC4_HDMI_CEC_TX_SW_RESET BIT(27)
715 # define VC4_HDMI_CEC_RX_SW_RESET BIT(26)
716 # define VC4_HDMI_CEC_PAD_SW_RESET BIT(25)
717 # define VC4_HDMI_CEC_MUX_TP_OUT_CEC BIT(24)
718 # define VC4_HDMI_CEC_RX_CEC_INT BIT(23)
719 # define VC4_HDMI_CEC_CLK_PRELOAD_MASK VC4_MASK(22, 16)
720 # define VC4_HDMI_CEC_CLK_PRELOAD_SHIFT 16
721 # define VC4_HDMI_CEC_CNT_TO_4700_US_MASK VC4_MASK(15, 8)
722 # define VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT 8
723 # define VC4_HDMI_CEC_CNT_TO_4500_US_MASK VC4_MASK(7, 0)
724 # define VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT 0
726 # define VC4_HDMI_TX_PHY_RNG_PWRDN BIT(25)
728 # define VC4_HDMI_CPU_CEC BIT(6)
729 # define VC4_HDMI_CPU_HOTPLUG BIT(0)
731 /* Debug: Current receive value on the CEC pad. */
732 # define VC4_HD_CECRXD BIT(9)
733 /* Debug: Override CEC output to 0. */
734 # define VC4_HD_CECOVR BIT(8)
735 # define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6)
736 # define VC4_HD_M_RAM_STANDBY (3 << 4)
737 # define VC4_HD_M_SW_RST BIT(2)
738 # define VC4_HD_M_ENABLE BIT(0)
740 /* Set when audio stream is received at a slower rate than the
741 * sampling period, so MAI fifo goes empty. Write 1 to clear.
743 # define VC4_HD_MAI_CTL_DLATE BIT(15)
744 # define VC4_HD_MAI_CTL_BUSY BIT(14)
745 # define VC4_HD_MAI_CTL_CHALIGN BIT(13)
746 # define VC4_HD_MAI_CTL_WHOLSMP BIT(12)
747 # define VC4_HD_MAI_CTL_FULL BIT(11)
748 # define VC4_HD_MAI_CTL_EMPTY BIT(10)
749 # define VC4_HD_MAI_CTL_FLUSH BIT(9)
750 /* If set, MAI bus generates SPDIF (bit 31) parity instead of passing
753 # define VC4_HD_MAI_CTL_PAREN BIT(8)
754 # define VC4_HD_MAI_CTL_CHNUM_MASK VC4_MASK(7, 4)
755 # define VC4_HD_MAI_CTL_CHNUM_SHIFT 4
756 # define VC4_HD_MAI_CTL_ENABLE BIT(3)
757 /* Underflow error status bit, write 1 to clear. */
758 # define VC4_HD_MAI_CTL_ERRORE BIT(2)
759 /* Overflow error status bit, write 1 to clear. */
760 # define VC4_HD_MAI_CTL_ERRORF BIT(1)
761 /* Single-shot reset bit. Read value is undefined. */
762 # define VC4_HD_MAI_CTL_RESET BIT(0)
764 # define VC4_HD_MAI_THR_PANICHIGH_MASK VC4_MASK(29, 24)
765 # define VC4_HD_MAI_THR_PANICHIGH_SHIFT 24
766 # define VC4_HD_MAI_THR_PANICLOW_MASK VC4_MASK(21, 16)
767 # define VC4_HD_MAI_THR_PANICLOW_SHIFT 16
768 # define VC4_HD_MAI_THR_DREQHIGH_MASK VC4_MASK(13, 8)
769 # define VC4_HD_MAI_THR_DREQHIGH_SHIFT 8
770 # define VC4_HD_MAI_THR_DREQLOW_MASK VC4_MASK(5, 0)
771 # define VC4_HD_MAI_THR_DREQLOW_SHIFT 0
773 /* Divider from HDMI HSM clock to MAI serial clock. Sampling period
774 * converges to N / (M + 1) cycles.
776 # define VC4_HD_MAI_SMP_N_MASK VC4_MASK(31, 8)
777 # define VC4_HD_MAI_SMP_N_SHIFT 8
778 # define VC4_HD_MAI_SMP_M_MASK VC4_MASK(7, 0)
779 # define VC4_HD_MAI_SMP_M_SHIFT 0
781 # define VC4_HD_VID_CTL_ENABLE BIT(31)
782 # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30)
783 # define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29)
784 # define VC4_HD_VID_CTL_VSYNC_LOW BIT(28)
785 # define VC4_HD_VID_CTL_HSYNC_LOW BIT(27)
786 # define VC4_HD_VID_CTL_CLRSYNC BIT(24)
787 # define VC4_HD_VID_CTL_CLRRGB BIT(23)
788 # define VC4_HD_VID_CTL_BLANKPIX BIT(18)
790 # define VC4_HD_CSC_CTL_ORDER_MASK VC4_MASK(7, 5)
791 # define VC4_HD_CSC_CTL_ORDER_SHIFT 5
792 # define VC4_HD_CSC_CTL_ORDER_RGB 0
793 # define VC4_HD_CSC_CTL_ORDER_BGR 1
794 # define VC4_HD_CSC_CTL_ORDER_BRG 2
795 # define VC4_HD_CSC_CTL_ORDER_GRB 3
796 # define VC4_HD_CSC_CTL_ORDER_GBR 4
797 # define VC4_HD_CSC_CTL_ORDER_RBG 5
798 # define VC4_HD_CSC_CTL_PADMSB BIT(4)
799 # define VC4_HD_CSC_CTL_MODE_MASK VC4_MASK(3, 2)
800 # define VC4_HD_CSC_CTL_MODE_SHIFT 2
801 # define VC4_HD_CSC_CTL_MODE_RGB_TO_SD_YPRPB 0
802 # define VC4_HD_CSC_CTL_MODE_RGB_TO_HD_YPRPB 1
803 # define VC4_HD_CSC_CTL_MODE_CUSTOM 3
804 # define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
805 # define VC4_HD_CSC_CTL_ENABLE BIT(0)
807 # define VC5_MT_CP_CSC_CTL_USE_444_TO_422 BIT(6)
808 # define VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_MASK \
810 # define VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD \
812 # define VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION BIT(3)
813 # define VC5_MT_CP_CSC_CTL_ENABLE BIT(2)
814 # define VC5_MT_CP_CSC_CTL_MODE_MASK VC4_MASK(1, 0)
816 # define VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_MASK \
818 # define VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE \
821 # define VC4_DVP_HT_CLOCK_STOP_PIXEL BIT(1)
823 # define VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_MASK \
825 # define VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY \
828 /* HVS display list information. */
829 #define HVS_BOOTLOADER_DLIST_END 32
831 enum hvs_pixel_format {
833 HVS_PIXEL_FORMAT_RGB332 = 0,
835 HVS_PIXEL_FORMAT_RGBA4444 = 1,
836 HVS_PIXEL_FORMAT_RGB555 = 2,
837 HVS_PIXEL_FORMAT_RGBA5551 = 3,
838 HVS_PIXEL_FORMAT_RGB565 = 4,
840 HVS_PIXEL_FORMAT_RGB888 = 5,
841 HVS_PIXEL_FORMAT_RGBA6666 = 6,
843 HVS_PIXEL_FORMAT_RGBA8888 = 7,
845 HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE = 8,
846 HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE = 9,
847 HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE = 10,
848 HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE = 11,
849 HVS_PIXEL_FORMAT_H264 = 12,
850 HVS_PIXEL_FORMAT_PALETTE = 13,
851 HVS_PIXEL_FORMAT_YUV444_RGB = 14,
852 HVS_PIXEL_FORMAT_AYUV444_RGB = 15,
853 HVS_PIXEL_FORMAT_RGBA1010102 = 16,
854 HVS_PIXEL_FORMAT_YCBCR_10BIT = 17,
857 /* Note: the LSB is the rightmost character shown. Only valid for
858 * HVS_PIXEL_FORMAT_RGB8888, not RGB888.
860 /* For modes 332, 4444, 555, 5551, 6666, 8888, 10:10:10:2 */
861 #define HVS_PIXEL_ORDER_RGBA 0
862 #define HVS_PIXEL_ORDER_BGRA 1
863 #define HVS_PIXEL_ORDER_ARGB 2
864 #define HVS_PIXEL_ORDER_ABGR 3
866 /* For modes 666 and 888 (4 & 5) */
867 #define HVS_PIXEL_ORDER_XBRG 0
868 #define HVS_PIXEL_ORDER_XRBG 1
869 #define HVS_PIXEL_ORDER_XRGB 2
870 #define HVS_PIXEL_ORDER_XBGR 3
872 /* For YCbCr modes (8-12, and 17) */
873 #define HVS_PIXEL_ORDER_XYCBCR 0
874 #define HVS_PIXEL_ORDER_XYCRCB 1
875 #define HVS_PIXEL_ORDER_YXCBCR 2
876 #define HVS_PIXEL_ORDER_YXCRCB 3
878 #define SCALER_CTL0_END BIT(31)
879 #define SCALER_CTL0_VALID BIT(30)
881 #define SCALER_CTL0_SIZE_MASK VC4_MASK(29, 24)
882 #define SCALER_CTL0_SIZE_SHIFT 24
884 #define SCALER_CTL0_TILING_MASK VC4_MASK(21, 20)
885 #define SCALER_CTL0_TILING_SHIFT 20
886 #define SCALER_CTL0_TILING_LINEAR 0
887 #define SCALER_CTL0_TILING_64B 1
888 #define SCALER_CTL0_TILING_128B 2
889 #define SCALER_CTL0_TILING_256B_OR_T 3
891 #define SCALER_CTL0_ALPHA_MASK BIT(19)
892 #define SCALER_CTL0_HFLIP BIT(16)
893 #define SCALER_CTL0_VFLIP BIT(15)
895 #define SCALER_CTL0_KEY_MODE_MASK VC4_MASK(18, 17)
896 #define SCALER_CTL0_KEY_MODE_SHIFT 17
897 #define SCALER_CTL0_KEY_DISABLED 0
898 #define SCALER_CTL0_KEY_LUMA_OR_COMMON_RGB 1
899 #define SCALER_CTL0_KEY_MATCH 2 /* turn transparent */
900 #define SCALER_CTL0_KEY_REPLACE 3 /* replace with value from key mask word 2 */
902 #define SCALER_CTL0_ORDER_MASK VC4_MASK(14, 13)
903 #define SCALER_CTL0_ORDER_SHIFT 13
905 #define SCALER_CTL0_RGBA_EXPAND_MASK VC4_MASK(12, 11)
906 #define SCALER_CTL0_RGBA_EXPAND_SHIFT 11
907 #define SCALER_CTL0_RGBA_EXPAND_ZERO 0
908 #define SCALER_CTL0_RGBA_EXPAND_LSB 1
909 #define SCALER_CTL0_RGBA_EXPAND_MSB 2
910 #define SCALER_CTL0_RGBA_EXPAND_ROUND 3
912 #define SCALER5_CTL0_ALPHA_EXPAND BIT(12)
914 #define SCALER5_CTL0_RGB_EXPAND BIT(11)
916 #define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)
917 #define SCALER_CTL0_SCL1_SHIFT 8
919 #define SCALER_CTL0_SCL0_MASK VC4_MASK(7, 5)
920 #define SCALER_CTL0_SCL0_SHIFT 5
922 #define SCALER_CTL0_SCL_H_PPF_V_PPF 0
923 #define SCALER_CTL0_SCL_H_TPZ_V_PPF 1
924 #define SCALER_CTL0_SCL_H_PPF_V_TPZ 2
925 #define SCALER_CTL0_SCL_H_TPZ_V_TPZ 3
926 #define SCALER_CTL0_SCL_H_PPF_V_NONE 4
927 #define SCALER_CTL0_SCL_H_NONE_V_PPF 5
928 #define SCALER_CTL0_SCL_H_NONE_V_TPZ 6
929 #define SCALER_CTL0_SCL_H_TPZ_V_NONE 7
931 /* Set to indicate no scaling. */
932 #define SCALER_CTL0_UNITY BIT(4)
933 #define SCALER5_CTL0_UNITY BIT(15)
935 #define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0)
936 #define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0
938 #define SCALER5_CTL0_PIXEL_FORMAT_MASK VC4_MASK(4, 0)
940 #define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24)
941 #define SCALER_POS0_FIXED_ALPHA_SHIFT 24
943 #define SCALER_POS0_START_Y_MASK VC4_MASK(23, 12)
944 #define SCALER_POS0_START_Y_SHIFT 12
946 #define SCALER_POS0_START_X_MASK VC4_MASK(11, 0)
947 #define SCALER_POS0_START_X_SHIFT 0
949 #define SCALER5_POS0_START_Y_MASK VC4_MASK(27, 16)
950 #define SCALER5_POS0_START_Y_SHIFT 16
952 #define SCALER5_POS0_START_X_MASK VC4_MASK(13, 0)
953 #define SCALER5_POS0_START_X_SHIFT 0
955 #define SCALER5_POS0_VFLIP BIT(31)
956 #define SCALER5_POS0_HFLIP BIT(15)
958 #define SCALER5_CTL2_ALPHA_MODE_MASK VC4_MASK(31, 30)
959 #define SCALER5_CTL2_ALPHA_MODE_SHIFT 30
960 #define SCALER5_CTL2_ALPHA_MODE_PIPELINE 0
961 #define SCALER5_CTL2_ALPHA_MODE_FIXED 1
962 #define SCALER5_CTL2_ALPHA_MODE_FIXED_NONZERO 2
963 #define SCALER5_CTL2_ALPHA_MODE_FIXED_OVER_0x07 3
965 #define SCALER5_CTL2_ALPHA_PREMULT BIT(29)
967 #define SCALER5_CTL2_ALPHA_MIX BIT(28)
969 #define SCALER5_CTL2_ALPHA_LOC BIT(25)
971 #define SCALER5_CTL2_MAP_SEL_MASK VC4_MASK(18, 17)
972 #define SCALER5_CTL2_MAP_SEL_SHIFT 17
974 #define SCALER5_CTL2_GAMMA BIT(16)
976 #define SCALER5_CTL2_ALPHA_MASK VC4_MASK(15, 4)
977 #define SCALER5_CTL2_ALPHA_SHIFT 4
979 #define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16)
980 #define SCALER_POS1_SCL_HEIGHT_SHIFT 16
982 #define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0)
983 #define SCALER_POS1_SCL_WIDTH_SHIFT 0
985 #define SCALER5_POS1_SCL_HEIGHT_MASK VC4_MASK(28, 16)
986 #define SCALER5_POS1_SCL_HEIGHT_SHIFT 16
988 #define SCALER5_POS1_SCL_WIDTH_MASK VC4_MASK(12, 0)
989 #define SCALER5_POS1_SCL_WIDTH_SHIFT 0
991 #define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)
992 #define SCALER_POS2_ALPHA_MODE_SHIFT 30
993 #define SCALER_POS2_ALPHA_MODE_PIPELINE 0
994 #define SCALER_POS2_ALPHA_MODE_FIXED 1
995 #define SCALER_POS2_ALPHA_MODE_FIXED_NONZERO 2
996 #define SCALER_POS2_ALPHA_MODE_FIXED_OVER_0x07 3
997 #define SCALER_POS2_ALPHA_PREMULT BIT(29)
998 #define SCALER_POS2_ALPHA_MIX BIT(28)
1000 #define SCALER_POS2_HEIGHT_MASK VC4_MASK(27, 16)
1001 #define SCALER_POS2_HEIGHT_SHIFT 16
1003 #define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0)
1004 #define SCALER_POS2_WIDTH_SHIFT 0
1006 #define SCALER5_POS2_HEIGHT_MASK VC4_MASK(28, 16)
1007 #define SCALER5_POS2_HEIGHT_SHIFT 16
1009 #define SCALER5_POS2_WIDTH_MASK VC4_MASK(12, 0)
1010 #define SCALER5_POS2_WIDTH_SHIFT 0
1012 /* Color Space Conversion words. Some values are S2.8 signed
1013 * integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1,
1016 /* bottom 8 bits of S2.8 contribution of Cr to Blue */
1017 #define SCALER_CSC0_COEF_CR_BLU_MASK VC4_MASK(31, 24)
1018 #define SCALER_CSC0_COEF_CR_BLU_SHIFT 24
1019 /* Signed offset to apply to Y before CSC. (Y' = Y + YY_OFS) */
1020 #define SCALER_CSC0_COEF_YY_OFS_MASK VC4_MASK(23, 16)
1021 #define SCALER_CSC0_COEF_YY_OFS_SHIFT 16
1022 /* Signed offset to apply to CB before CSC (Cb' = Cb - 128 + CB_OFS). */
1023 #define SCALER_CSC0_COEF_CB_OFS_MASK VC4_MASK(15, 8)
1024 #define SCALER_CSC0_COEF_CB_OFS_SHIFT 8
1025 /* Signed offset to apply to CB before CSC (Cr' = Cr - 128 + CR_OFS). */
1026 #define SCALER_CSC0_COEF_CR_OFS_MASK VC4_MASK(7, 0)
1027 #define SCALER_CSC0_COEF_CR_OFS_SHIFT 0
1028 #define SCALER_CSC0_ITR_R_601_5 0x00f00000
1029 #define SCALER_CSC0_ITR_R_709_3 0x00f00000
1030 #define SCALER_CSC0_ITR_R_2020 0x00f00000
1031 #define SCALER_CSC0_JPEG_JFIF 0x00000000
1032 #define SCALER_CSC0_ITR_R_709_3_FR 0x00000000
1033 #define SCALER_CSC0_ITR_R_2020_FR 0x00000000
1035 /* S2.8 contribution of Cb to Green */
1036 #define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22)
1037 #define SCALER_CSC1_COEF_CB_GRN_SHIFT 22
1038 /* S2.8 contribution of Cr to Green */
1039 #define SCALER_CSC1_COEF_CR_GRN_MASK VC4_MASK(21, 12)
1040 #define SCALER_CSC1_COEF_CR_GRN_SHIFT 12
1041 /* S2.8 contribution of Y to all of RGB */
1042 #define SCALER_CSC1_COEF_YY_ALL_MASK VC4_MASK(11, 2)
1043 #define SCALER_CSC1_COEF_YY_ALL_SHIFT 2
1044 /* top 2 bits of S2.8 contribution of Cr to Blue */
1045 #define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0)
1046 #define SCALER_CSC1_COEF_CR_BLU_SHIFT 0
1047 #define SCALER_CSC1_ITR_R_601_5 0xe73304a8
1048 #define SCALER_CSC1_ITR_R_709_3 0xf27784a8
1049 #define SCALER_CSC1_ITR_R_2020 0xf43594a8
1050 #define SCALER_CSC1_JPEG_JFIF 0xea349400
1051 #define SCALER_CSC1_ITR_R_709_3_FR 0xf4388400
1052 #define SCALER_CSC1_ITR_R_2020_FR 0xf5b6d400
1054 /* S2.8 contribution of Cb to Red */
1055 #define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20)
1056 #define SCALER_CSC2_COEF_CB_RED_SHIFT 20
1057 /* S2.8 contribution of Cr to Red */
1058 #define SCALER_CSC2_COEF_CR_RED_MASK VC4_MASK(19, 10)
1059 #define SCALER_CSC2_COEF_CR_RED_SHIFT 10
1060 /* S2.8 contribution of Cb to Blue */
1061 #define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10)
1062 #define SCALER_CSC2_COEF_CB_BLU_SHIFT 10
1063 #define SCALER_CSC2_ITR_R_601_5 0x00066604
1064 #define SCALER_CSC2_ITR_R_709_3 0x00072e1d
1065 #define SCALER_CSC2_ITR_R_2020 0x0006b624
1066 #define SCALER_CSC2_JPEG_JFIF 0x00059dc6
1067 #define SCALER_CSC2_ITR_R_709_3_FR 0x00064ddb
1068 #define SCALER_CSC2_ITR_R_2020_FR 0x0005e5e2
1070 #define SCALER_TPZ0_VERT_RECALC BIT(31)
1071 #define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)
1072 #define SCALER_TPZ0_SCALE_SHIFT 8
1073 #define SCALER_TPZ0_IPHASE_MASK VC4_MASK(7, 0)
1074 #define SCALER_TPZ0_IPHASE_SHIFT 0
1075 #define SCALER_TPZ1_RECIP_MASK VC4_MASK(15, 0)
1076 #define SCALER_TPZ1_RECIP_SHIFT 0
1078 /* Skips interpolating coefficients to 64 phases, so just 8 are used.
1079 * Required for nearest neighbor.
1081 #define SCALER_PPF_NOINTERP BIT(31)
1082 /* Replaes the highest valued coefficient with one that makes all 4
1085 #define SCALER_PPF_AGC BIT(30)
1086 #define SCALER_PPF_SCALE_MASK VC4_MASK(24, 8)
1087 #define SCALER_PPF_SCALE_SHIFT 8
1088 #define SCALER_PPF_IPHASE_MASK VC4_MASK(6, 0)
1089 #define SCALER_PPF_IPHASE_SHIFT 0
1091 #define SCALER_PPF_KERNEL_OFFSET_MASK VC4_MASK(13, 0)
1092 #define SCALER_PPF_KERNEL_OFFSET_SHIFT 0
1093 #define SCALER_PPF_KERNEL_UNCACHED BIT(31)
1095 /* PITCH0/1/2 fields for raster. */
1096 #define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0)
1097 #define SCALER_SRC_PITCH_SHIFT 0
1099 /* PITCH0/1/2 fields for tiled (SAND). */
1100 #define SCALER_TILE_SKIP_0_MASK VC4_MASK(18, 16)
1101 #define SCALER_TILE_SKIP_0_SHIFT 16
1102 #define SCALER_TILE_HEIGHT_MASK VC4_MASK(15, 0)
1103 #define SCALER_TILE_HEIGHT_SHIFT 0
1105 /* Common PITCH0 fields */
1106 #define SCALER_PITCH0_SINK_PIX_MASK VC4_MASK(31, 26)
1107 #define SCALER_PITCH0_SINK_PIX_SHIFT 26
1109 /* PITCH0 fields for T-tiled. */
1110 #define SCALER_PITCH0_TILE_WIDTH_L_MASK VC4_MASK(22, 16)
1111 #define SCALER_PITCH0_TILE_WIDTH_L_SHIFT 16
1112 #define SCALER_PITCH0_TILE_LINE_DIR BIT(15)
1113 #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14)
1114 /* Y offset within a tile. */
1115 #define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 8)
1116 #define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 8
1117 #define SCALER_PITCH0_TILE_WIDTH_R_MASK VC4_MASK(6, 0)
1118 #define SCALER_PITCH0_TILE_WIDTH_R_SHIFT 0
1120 #endif /* VC4_REGS_H */