1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
9 #include <linux/bitfield.h>
10 #include <linux/bitops.h>
12 #define VC4_MASK(high, low) ((u32)GENMASK(high, low))
13 /* Using the GNU statement expression extension */
14 #define VC4_SET_FIELD(value, field) \
16 WARN_ON(!FIELD_FIT(field ## _MASK, value)); \
17 FIELD_PREP(field ## _MASK, value); \
20 #define VC4_GET_FIELD(word, field) FIELD_GET(field ## _MASK, word)
22 #define VC4_SET_FIELD6(value, field) \
24 WARN_ON(!FIELD_FIT(hvs->vc4->step_d0 ? \
25 SCALER6D0_ ## field ## _MASK : \
26 SCALER6_ ## field ## _MASK, value));\
27 FIELD_PREP(hvs->vc4->step_d0 ? \
28 SCALER6D0_ ## field ## _MASK : \
29 SCALER6_ ## field ## _MASK, value); \
32 #define VC4_GET_FIELD6(word, field) FIELD_GET(hvs->vc4->step_d0 ? \
33 SCALER6D0_ ## field ## _MASK : SCALER6_ ## field ## _MASK, word)
35 #define V3D_IDENT0 0x00000
36 # define V3D_EXPECTED_IDENT0 \
42 #define V3D_IDENT1 0x00004
43 /* Multiples of 1kb */
44 # define V3D_IDENT1_VPM_SIZE_MASK VC4_MASK(31, 28)
45 # define V3D_IDENT1_VPM_SIZE_SHIFT 28
46 # define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16)
47 # define V3D_IDENT1_NSEM_SHIFT 16
48 # define V3D_IDENT1_TUPS_MASK VC4_MASK(15, 12)
49 # define V3D_IDENT1_TUPS_SHIFT 12
50 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)
51 # define V3D_IDENT1_QUPS_SHIFT 8
52 # define V3D_IDENT1_NSLC_MASK VC4_MASK(7, 4)
53 # define V3D_IDENT1_NSLC_SHIFT 4
54 # define V3D_IDENT1_REV_MASK VC4_MASK(3, 0)
55 # define V3D_IDENT1_REV_SHIFT 0
57 #define V3D_IDENT2 0x00008
58 #define V3D_SCRATCH 0x00010
59 #define V3D_L2CACTL 0x00020
60 # define V3D_L2CACTL_L2CCLR BIT(2)
61 # define V3D_L2CACTL_L2CDIS BIT(1)
62 # define V3D_L2CACTL_L2CENA BIT(0)
64 #define V3D_SLCACTL 0x00024
65 # define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24)
66 # define V3D_SLCACTL_T1CC_SHIFT 24
67 # define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16)
68 # define V3D_SLCACTL_T0CC_SHIFT 16
69 # define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8)
70 # define V3D_SLCACTL_UCC_SHIFT 8
71 # define V3D_SLCACTL_ICC_MASK VC4_MASK(3, 0)
72 # define V3D_SLCACTL_ICC_SHIFT 0
74 #define V3D_INTCTL 0x00030
75 #define V3D_INTENA 0x00034
76 #define V3D_INTDIS 0x00038
77 # define V3D_INT_SPILLUSE BIT(3)
78 # define V3D_INT_OUTOMEM BIT(2)
79 # define V3D_INT_FLDONE BIT(1)
80 # define V3D_INT_FRDONE BIT(0)
82 #define V3D_CT0CS 0x00100
83 #define V3D_CT1CS 0x00104
84 #define V3D_CTNCS(n) (V3D_CT0CS + 4 * n)
85 # define V3D_CTRSTA BIT(15)
86 # define V3D_CTSEMA BIT(12)
87 # define V3D_CTRTSD BIT(8)
88 # define V3D_CTRUN BIT(5)
89 # define V3D_CTSUBS BIT(4)
90 # define V3D_CTERR BIT(3)
91 # define V3D_CTMODE BIT(0)
93 #define V3D_CT0EA 0x00108
94 #define V3D_CT1EA 0x0010c
95 #define V3D_CTNEA(n) (V3D_CT0EA + 4 * (n))
96 #define V3D_CT0CA 0x00110
97 #define V3D_CT1CA 0x00114
98 #define V3D_CTNCA(n) (V3D_CT0CA + 4 * (n))
99 #define V3D_CT00RA0 0x00118
100 #define V3D_CT01RA0 0x0011c
101 #define V3D_CTNRA0(n) (V3D_CT00RA0 + 4 * (n))
102 #define V3D_CT0LC 0x00120
103 #define V3D_CT1LC 0x00124
104 #define V3D_CTNLC(n) (V3D_CT0LC + 4 * (n))
105 #define V3D_CT0PC 0x00128
106 #define V3D_CT1PC 0x0012c
107 #define V3D_CTNPC(n) (V3D_CT0PC + 4 * (n))
109 #define V3D_PCS 0x00130
110 # define V3D_BMOOM BIT(8)
111 # define V3D_RMBUSY BIT(3)
112 # define V3D_RMACTIVE BIT(2)
113 # define V3D_BMBUSY BIT(1)
114 # define V3D_BMACTIVE BIT(0)
116 #define V3D_BFC 0x00134
117 #define V3D_RFC 0x00138
118 #define V3D_BPCA 0x00300
119 #define V3D_BPCS 0x00304
120 #define V3D_BPOA 0x00308
121 #define V3D_BPOS 0x0030c
122 #define V3D_BXCF 0x00310
123 #define V3D_SQRSV0 0x00410
124 #define V3D_SQRSV1 0x00414
125 #define V3D_SQCNTL 0x00418
126 #define V3D_SRQPC 0x00430
127 #define V3D_SRQUA 0x00434
128 #define V3D_SRQUL 0x00438
129 #define V3D_SRQCS 0x0043c
130 #define V3D_VPACNTL 0x00500
131 #define V3D_VPMBASE 0x00504
132 #define V3D_PCTRC 0x00670
133 #define V3D_PCTRE 0x00674
134 # define V3D_PCTRE_EN BIT(31)
135 #define V3D_PCTR(x) (0x00680 + ((x) * 8))
136 #define V3D_PCTRS(x) (0x00684 + ((x) * 8))
137 #define V3D_DBGE 0x00f00
138 #define V3D_FDBGO 0x00f04
139 #define V3D_FDBGB 0x00f08
140 #define V3D_FDBGR 0x00f0c
141 #define V3D_FDBGS 0x00f10
142 #define V3D_ERRSTAT 0x00f20
144 #define PV_CONTROL 0x00
145 # define PV5_CONTROL_FIFO_LEVEL_HIGH_MASK VC4_MASK(26, 25)
146 # define PV5_CONTROL_FIFO_LEVEL_HIGH_SHIFT 25
147 # define PV_CONTROL_FORMAT_MASK VC4_MASK(23, 21)
148 # define PV_CONTROL_FORMAT_SHIFT 21
149 # define PV_CONTROL_FORMAT_24 0
150 # define PV_CONTROL_FORMAT_DSIV_16 1
151 # define PV_CONTROL_FORMAT_DSIC_16 2
152 # define PV_CONTROL_FORMAT_DSIV_18 3
153 # define PV_CONTROL_FORMAT_DSIV_24 4
155 # define PV_CONTROL_FIFO_LEVEL_MASK VC4_MASK(20, 15)
156 # define PV_CONTROL_FIFO_LEVEL_SHIFT 15
157 # define PV_CONTROL_CLR_AT_START BIT(14)
158 # define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13)
159 # define PV_CONTROL_WAIT_HSTART BIT(12)
160 # define PV_CONTROL_PIXEL_REP_MASK VC4_MASK(5, 4)
161 # define PV_CONTROL_PIXEL_REP_SHIFT 4
162 # define PV_CONTROL_CLK_SELECT_DSI 0
163 # define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI 1
164 # define PV_CONTROL_CLK_SELECT_VEC 2
165 # define PV_CONTROL_CLK_SELECT_MASK VC4_MASK(3, 2)
166 # define PV_CONTROL_CLK_SELECT_SHIFT 2
167 # define PV_CONTROL_FIFO_CLR BIT(1)
168 # define PV_CONTROL_EN BIT(0)
170 #define PV_V_CONTROL 0x04
171 # define PV_VCONTROL_ODD_TIMING BIT(29)
172 # define PV_VCONTROL_ODD_DELAY_MASK VC4_MASK(22, 6)
173 # define PV_VCONTROL_ODD_DELAY_SHIFT 6
174 # define PV_VCONTROL_ODD_FIRST BIT(5)
175 # define PV_VCONTROL_INTERLACE BIT(4)
176 # define PV_VCONTROL_DSI BIT(3)
177 # define PV_VCONTROL_COMMAND BIT(2)
178 # define PV_VCONTROL_CONTINUOUS BIT(1)
179 # define PV_VCONTROL_VIDEN BIT(0)
181 #define PV_VSYNCD_EVEN 0x08
183 #define PV_HORZA 0x0c
184 # define PV_HORZA_HBP_MASK VC4_MASK(31, 16)
185 # define PV_HORZA_HBP_SHIFT 16
186 # define PV_HORZA_HSYNC_MASK VC4_MASK(15, 0)
187 # define PV_HORZA_HSYNC_SHIFT 0
189 #define PV_HORZB 0x10
190 # define PV_HORZB_HFP_MASK VC4_MASK(31, 16)
191 # define PV_HORZB_HFP_SHIFT 16
192 # define PV_HORZB_HACTIVE_MASK VC4_MASK(15, 0)
193 # define PV_HORZB_HACTIVE_SHIFT 0
195 #define PV_VERTA 0x14
196 # define PV_VERTA_VBP_MASK VC4_MASK(31, 16)
197 # define PV_VERTA_VBP_SHIFT 16
198 # define PV_VERTA_VSYNC_MASK VC4_MASK(15, 0)
199 # define PV_VERTA_VSYNC_SHIFT 0
201 #define PV_VERTB 0x18
202 # define PV_VERTB_VFP_MASK VC4_MASK(31, 16)
203 # define PV_VERTB_VFP_SHIFT 16
204 # define PV_VERTB_VACTIVE_MASK VC4_MASK(15, 0)
205 # define PV_VERTB_VACTIVE_SHIFT 0
207 #define PV_VERTA_EVEN 0x1c
208 #define PV_VERTB_EVEN 0x20
210 #define PV_INTEN 0x24
211 #define PV_INTSTAT 0x28
212 # define PV_INT_VID_IDLE BIT(9)
213 # define PV_INT_VFP_END BIT(8)
214 # define PV_INT_VFP_START BIT(7)
215 # define PV_INT_VACT_START BIT(6)
216 # define PV_INT_VBP_START BIT(5)
217 # define PV_INT_VSYNC_START BIT(4)
218 # define PV_INT_HFP_START BIT(3)
219 # define PV_INT_HACT_START BIT(2)
220 # define PV_INT_HBP_START BIT(1)
221 # define PV_INT_HSYNC_START BIT(0)
225 #define PV_HACT_ACT 0x30
227 #define PV_MUX_CFG 0x34
228 # define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_MASK VC4_MASK(5, 2)
229 # define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_SHIFT 2
230 # define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP 8
232 #define PV_PIPE_INIT_CTRL 0x94
233 # define PV_PIPE_INIT_CTRL_PV_INIT_WIDTH_MASK VC4_MASK(11, 8)
234 # define PV_PIPE_INIT_CTRL_PV_INIT_IDLE_MASK VC4_MASK(7, 4)
235 # define PV_PIPE_INIT_CTRL_PV_INIT_EN BIT(0)
237 #define SCALER_CHANNELS_COUNT 3
239 #define SCALER_DISPCTRL 0x00000000
240 /* Global register for clock gating the HVS */
241 # define SCALER_DISPCTRL_ENABLE BIT(31)
242 # define SCALER_DISPCTRL_PANIC0_MASK VC4_MASK(25, 24)
243 # define SCALER_DISPCTRL_PANIC0_SHIFT 24
244 # define SCALER_DISPCTRL_PANIC1_MASK VC4_MASK(27, 26)
245 # define SCALER_DISPCTRL_PANIC1_SHIFT 26
246 # define SCALER_DISPCTRL_PANIC2_MASK VC4_MASK(29, 28)
247 # define SCALER_DISPCTRL_PANIC2_SHIFT 28
248 # define SCALER_DISPCTRL_DSP3_MUX_MASK VC4_MASK(19, 18)
249 # define SCALER_DISPCTRL_DSP3_MUX_SHIFT 18
251 /* Enables Display 0 short line and underrun contribution to
252 * SCALER_DISPSTAT_IRQDISP0. Note that short frame contributions are
255 # define SCALER_DISPCTRL_DSPEISLUR(x) BIT(13 + (x))
256 # define SCALER5_DISPCTRL_DSPEISLUR(x) BIT(9 + ((x) * 4))
257 /* Enables Display 0 end-of-line-N contribution to
258 * SCALER_DISPSTAT_IRQDISP0
260 # define SCALER_DISPCTRL_DSPEIEOLN(x) BIT(8 + ((x) * 2))
261 # define SCALER5_DISPCTRL_DSPEIEOLN(x) BIT(8 + ((x) * 4))
262 /* Enables Display 0 EOF contribution to SCALER_DISPSTAT_IRQDISP0 */
263 # define SCALER_DISPCTRL_DSPEIEOF(x) BIT(7 + ((x) * 2))
264 # define SCALER5_DISPCTRL_DSPEIEOF(x) BIT(7 + ((x) * 4))
266 # define SCALER5_DISPCTRL_DSPEIVST(x) BIT(6 + ((x) * 4))
268 # define SCALER_DISPCTRL_SLVRDEIRQ BIT(6) /* HVS4 only */
269 # define SCALER_DISPCTRL_SLVWREIRQ BIT(5) /* HVS4 only */
270 # define SCALER5_DISPCTRL_SLVEIRQ BIT(5)
271 # define SCALER_DISPCTRL_DMAEIRQ BIT(4)
272 /* Enables interrupt generation on the enabled EOF/EOLN/EISLUR
273 * bits and short frames..
275 # define SCALER_DISPCTRL_DISPEIRQ(x) BIT(1 + (x))
276 /* Enables interrupt generation on scaler profiler interrupt. */
277 # define SCALER_DISPCTRL_SCLEIRQ BIT(0)
279 #define SCALER_DISPSTAT 0x00000004
280 # define SCALER_DISPSTAT_RESP_MASK VC4_MASK(15, 14)
281 # define SCALER_DISPSTAT_RESP_SHIFT 14
282 # define SCALER_DISPSTAT_RESP_OKAY 0
283 # define SCALER_DISPSTAT_RESP_EXOKAY 1
284 # define SCALER_DISPSTAT_RESP_SLVERR 2
285 # define SCALER_DISPSTAT_RESP_DECERR 3
287 # define SCALER_DISPSTAT_COBLOW(x) BIT(13 + ((x) * 8))
288 /* Set when the DISPEOLN line is done compositing. */
289 # define SCALER_DISPSTAT_EOLN(x) BIT(12 + ((x) * 8))
290 /* Set when VSTART is seen but there are still pixels in the current
293 # define SCALER_DISPSTAT_ESFRAME(x) BIT(11 + ((x) * 8))
294 /* Set when HSTART is seen but there are still pixels in the current
297 # define SCALER_DISPSTAT_ESLINE(x) BIT(10 + ((x) * 8))
298 /* Set when the downstream tries to read from the display FIFO
301 # define SCALER_DISPSTAT_EUFLOW(x) BIT(9 + ((x) * 8))
302 /* Set when the display mode changes from RUN to EOF */
303 # define SCALER_DISPSTAT_EOF(x) BIT(8 + ((x) * 8))
305 # define SCALER_DISPSTAT_IRQMASK(x) VC4_MASK(13 + ((x) * 8), \
308 /* Set on AXI invalid DMA ID error. */
309 # define SCALER_DISPSTAT_DMA_ERROR BIT(7)
310 /* Set on AXI slave read decode error */
311 # define SCALER_DISPSTAT_IRQSLVRD BIT(6)
312 /* Set on AXI slave write decode error */
313 # define SCALER_DISPSTAT_IRQSLVWR BIT(5)
314 /* Set when SCALER_DISPSTAT_DMA_ERROR is set, or
315 * SCALER_DISPSTAT_RESP_ERROR is not SCALER_DISPSTAT_RESP_OKAY.
317 # define SCALER_DISPSTAT_IRQDMA BIT(4)
318 /* Set when any of the EOF/EOLN/ESFRAME/ESLINE bits are set and their
319 * corresponding interrupt bit is enabled in DISPCTRL.
321 # define SCALER_DISPSTAT_IRQDISP(x) BIT(1 + (x))
322 /* On read, the profiler interrupt. On write, clear *all* interrupt bits. */
323 # define SCALER_DISPSTAT_IRQSCL BIT(0)
325 #define SCALER_DISPID 0x00000008
326 #define SCALER_DISPECTRL 0x0000000c
327 # define SCALER_DISPECTRL_DSP2_MUX_SHIFT 31
328 # define SCALER_DISPECTRL_DSP2_MUX_MASK VC4_MASK(31, 31)
330 #define SCALER_DISPPROF 0x00000010
332 #define SCALER_DISPDITHER 0x00000014
333 # define SCALER_DISPDITHER_DSP5_MUX_SHIFT 30
334 # define SCALER_DISPDITHER_DSP5_MUX_MASK VC4_MASK(31, 30)
336 #define SCALER_DISPEOLN 0x00000018
337 # define SCALER_DISPEOLN_DSP4_MUX_SHIFT 30
338 # define SCALER_DISPEOLN_DSP4_MUX_MASK VC4_MASK(31, 30)
340 #define SCALER_DISPLIST0 0x00000020
341 #define SCALER_DISPLIST1 0x00000024
342 #define SCALER_DISPLIST2 0x00000028
343 #define SCALER_DISPLSTAT 0x0000002c
344 #define SCALER_DISPLISTX(x) (SCALER_DISPLIST0 + \
345 (x) * (SCALER_DISPLIST1 - \
348 #define SCALER_DISPLACT0 0x00000030
349 #define SCALER_DISPLACT1 0x00000034
350 #define SCALER_DISPLACT2 0x00000038
351 #define SCALER_DISPLACTX(x) (SCALER_DISPLACT0 + \
352 (x) * (SCALER_DISPLACT1 - \
355 #define SCALER_DISPCTRL0 0x00000040
356 # define SCALER_DISPCTRLX_ENABLE BIT(31)
357 # define SCALER_DISPCTRLX_RESET BIT(30)
358 /* Generates a single frame when VSTART is seen and stops at the last
359 * pixel read from the FIFO.
361 # define SCALER_DISPCTRLX_ONESHOT BIT(29)
362 /* Processes a single context in the dlist and then task switch,
363 * instead of an entire line.
365 # define SCALER_DISPCTRLX_ONECTX BIT(28)
366 /* Set to have DISPSLAVE return 2 16bpp pixels and no status data. */
367 # define SCALER_DISPCTRLX_FIFO32 BIT(27)
368 /* Turns on output to the DISPSLAVE register instead of the normal
371 # define SCALER_DISPCTRLX_FIFOREG BIT(26)
373 # define SCALER_DISPCTRLX_WIDTH_MASK VC4_MASK(23, 12)
374 # define SCALER_DISPCTRLX_WIDTH_SHIFT 12
375 # define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0)
376 # define SCALER_DISPCTRLX_HEIGHT_SHIFT 0
378 # define SCALER5_DISPCTRLX_WIDTH_MASK VC4_MASK(28, 16)
379 # define SCALER5_DISPCTRLX_WIDTH_SHIFT 16
380 /* Generates a single frame when VSTART is seen and stops at the last
381 * pixel read from the FIFO.
383 # define SCALER5_DISPCTRLX_ONESHOT BIT(15)
384 /* Processes a single context in the dlist and then task switch,
385 * instead of an entire line.
387 # define SCALER5_DISPCTRLX_ONECTX_MASK VC4_MASK(14, 13)
388 # define SCALER5_DISPCTRLX_ONECTX_SHIFT 13
389 # define SCALER5_DISPCTRLX_HEIGHT_MASK VC4_MASK(12, 0)
390 # define SCALER5_DISPCTRLX_HEIGHT_SHIFT 0
392 #define SCALER_DISPBKGND0 0x00000044
393 # define SCALER_DISPBKGND_AUTOHS BIT(31)
394 # define SCALER5_DISPBKGND_BCK2BCK BIT(31)
395 # define SCALER_DISPBKGND_INTERLACE BIT(30)
396 # define SCALER_DISPBKGND_GAMMA BIT(29)
397 # define SCALER_DISPBKGND_TESTMODE_MASK VC4_MASK(28, 25)
398 # define SCALER_DISPBKGND_TESTMODE_SHIFT 25
399 /* Enables filling the scaler line with the RGB value in the low 24
400 * bits before compositing. Costs cycles, so should be skipped if
401 * opaque display planes will cover everything.
403 # define SCALER_DISPBKGND_FILL BIT(24)
405 #define SCALER_DISPSTAT0 0x00000048
406 # define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30)
407 # define SCALER_DISPSTATX_MODE_SHIFT 30
408 # define SCALER_DISPSTATX_MODE_DISABLED 0
409 # define SCALER_DISPSTATX_MODE_INIT 1
410 # define SCALER_DISPSTATX_MODE_RUN 2
411 # define SCALER_DISPSTATX_MODE_EOF 3
412 # define SCALER_DISPSTATX_FULL BIT(29)
413 # define SCALER_DISPSTATX_EMPTY BIT(28)
414 # define SCALER_DISPSTATX_LINE_MASK VC4_MASK(11, 0)
415 # define SCALER_DISPSTATX_LINE_SHIFT 0
417 #define SCALER_DISPBASE0 0x0000004c
418 /* Last pixel in the COB (display FIFO memory) allocated to this HVS
419 * channel. Must be 4-pixel aligned (and thus 4 pixels less than the
422 # define SCALER_DISPBASEX_TOP_MASK VC4_MASK(31, 16)
423 # define SCALER_DISPBASEX_TOP_SHIFT 16
424 /* First pixel in the COB (display FIFO memory) allocated to this HVS
425 * channel. Must be 4-pixel aligned.
427 # define SCALER_DISPBASEX_BASE_MASK VC4_MASK(15, 0)
428 # define SCALER_DISPBASEX_BASE_SHIFT 0
430 #define SCALER_DISPCTRL1 0x00000050
431 #define SCALER_DISPBKGND1 0x00000054
432 #define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \
433 (x) * (SCALER_DISPBKGND1 - \
435 #define SCALER_DISPSTAT1 0x00000058
436 # define SCALER_DISPSTAT1_FRCNT0_MASK VC4_MASK(23, 18)
437 # define SCALER_DISPSTAT1_FRCNT0_SHIFT 18
438 # define SCALER_DISPSTAT1_FRCNT1_MASK VC4_MASK(17, 12)
439 # define SCALER_DISPSTAT1_FRCNT1_SHIFT 12
440 # define SCALER5_DISPSTAT1_FRCNT0_MASK VC4_MASK(25, 20)
441 # define SCALER5_DISPSTAT1_FRCNT0_SHIFT 20
442 # define SCALER5_DISPSTAT1_FRCNT1_MASK VC4_MASK(19, 14)
443 # define SCALER5_DISPSTAT1_FRCNT1_SHIFT 14
445 #define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \
446 (x) * (SCALER_DISPSTAT1 - \
449 #define SCALER_DISPBASE1 0x0000005c
450 #define SCALER_DISPBASEX(x) (SCALER_DISPBASE0 + \
451 (x) * (SCALER_DISPBASE1 - \
453 #define SCALER_DISPCTRL2 0x00000060
454 #define SCALER_DISPCTRLX(x) (SCALER_DISPCTRL0 + \
455 (x) * (SCALER_DISPCTRL1 - \
457 #define SCALER_DISPBKGND2 0x00000064
459 #define SCALER_DISPSTAT2 0x00000068
460 # define SCALER_DISPSTAT2_FRCNT2_MASK VC4_MASK(17, 12)
461 # define SCALER_DISPSTAT2_FRCNT2_SHIFT 12
462 # define SCALER5_DISPSTAT2_FRCNT2_MASK VC4_MASK(19, 14)
463 # define SCALER5_DISPSTAT2_FRCNT2_SHIFT 14
465 #define SCALER_DISPBASE2 0x0000006c
466 #define SCALER_DISPALPHA2 0x00000070
467 #define SCALER_GAMADDR 0x00000078
468 # define SCALER_GAMADDR_AUTOINC BIT(31)
469 /* Enables all gamma ramp SRAMs, not just those of CRTCs with gamma
472 # define SCALER_GAMADDR_SRAMENB BIT(30)
474 #define SCALER_OLEDOFFS 0x00000080
475 /* Clamps R to [16,235] and G/B to [16,240]. */
476 # define SCALER_OLEDOFFS_YUVCLAMP BIT(31)
478 /* Chooses which display FIFO the matrix applies to. */
479 # define SCALER_OLEDOFFS_DISPFIFO_MASK VC4_MASK(25, 24)
480 # define SCALER_OLEDOFFS_DISPFIFO_SHIFT 24
481 # define SCALER_OLEDOFFS_DISPFIFO_DISABLED 0
482 # define SCALER_OLEDOFFS_DISPFIFO_0 1
483 # define SCALER_OLEDOFFS_DISPFIFO_1 2
484 # define SCALER_OLEDOFFS_DISPFIFO_2 3
486 /* Offsets are 8-bit 2s-complement. */
487 # define SCALER_OLEDOFFS_RED_MASK VC4_MASK(23, 16)
488 # define SCALER_OLEDOFFS_RED_SHIFT 16
489 # define SCALER_OLEDOFFS_GREEN_MASK VC4_MASK(15, 8)
490 # define SCALER_OLEDOFFS_GREEN_SHIFT 8
491 # define SCALER_OLEDOFFS_BLUE_MASK VC4_MASK(7, 0)
492 # define SCALER_OLEDOFFS_BLUE_SHIFT 0
494 /* The coefficients are S0.9 fractions. */
495 #define SCALER_OLEDCOEF0 0x00000084
496 # define SCALER_OLEDCOEF0_B_TO_R_MASK VC4_MASK(29, 20)
497 # define SCALER_OLEDCOEF0_B_TO_R_SHIFT 20
498 # define SCALER_OLEDCOEF0_B_TO_G_MASK VC4_MASK(19, 10)
499 # define SCALER_OLEDCOEF0_B_TO_G_SHIFT 10
500 # define SCALER_OLEDCOEF0_B_TO_B_MASK VC4_MASK(9, 0)
501 # define SCALER_OLEDCOEF0_B_TO_B_SHIFT 0
503 #define SCALER_OLEDCOEF1 0x00000088
504 # define SCALER_OLEDCOEF1_G_TO_R_MASK VC4_MASK(29, 20)
505 # define SCALER_OLEDCOEF1_G_TO_R_SHIFT 20
506 # define SCALER_OLEDCOEF1_G_TO_G_MASK VC4_MASK(19, 10)
507 # define SCALER_OLEDCOEF1_G_TO_G_SHIFT 10
508 # define SCALER_OLEDCOEF1_G_TO_B_MASK VC4_MASK(9, 0)
509 # define SCALER_OLEDCOEF1_G_TO_B_SHIFT 0
511 #define SCALER_OLEDCOEF2 0x0000008c
512 # define SCALER_OLEDCOEF2_R_TO_R_MASK VC4_MASK(29, 20)
513 # define SCALER_OLEDCOEF2_R_TO_R_SHIFT 20
514 # define SCALER_OLEDCOEF2_R_TO_G_MASK VC4_MASK(19, 10)
515 # define SCALER_OLEDCOEF2_R_TO_G_SHIFT 10
516 # define SCALER_OLEDCOEF2_R_TO_B_MASK VC4_MASK(9, 0)
517 # define SCALER_OLEDCOEF2_R_TO_B_SHIFT 0
519 /* Slave addresses for DMAing from HVS composition output to other
520 * devices. The top bits are valid only in !FIFO32 mode.
522 #define SCALER_DISPSLAVE0 0x000000c0
523 #define SCALER_DISPSLAVE1 0x000000c9
524 #define SCALER_DISPSLAVE2 0x000000d0
525 # define SCALER_DISPSLAVE_ISSUE_VSTART BIT(31)
526 # define SCALER_DISPSLAVE_ISSUE_HSTART BIT(30)
527 /* Set when the current line has been read and an HSTART is required. */
528 # define SCALER_DISPSLAVE_EOL BIT(26)
529 /* Set when the display FIFO is empty. */
530 # define SCALER_DISPSLAVE_EMPTY BIT(25)
531 /* Set when there is RGB data ready to read. */
532 # define SCALER_DISPSLAVE_VALID BIT(24)
533 # define SCALER_DISPSLAVE_RGB_MASK VC4_MASK(23, 0)
534 # define SCALER_DISPSLAVE_RGB_SHIFT 0
536 #define SCALER_GAMDATA 0x000000e0
537 #define SCALER_DLIST_START 0x00002000
538 #define SCALER_DLIST_SIZE 0x00004000
540 /* Gamma PWL for each channel. 16 points for each of 4 colour channels (alpha
541 * only on channel 2). 8 bytes per entry, offsets first, then gradient:
544 * Values for X and C are left justified, and vary depending on the width of
546 * 8-bit pipeline: X uses [31:24], C is U8.8 format, and GRAD is U4.8.
547 * 12-bit pipeline: X uses [31:20], C is U12.4 format, and GRAD is U4.8.
549 * The 3 HVS channels start at 0x400 offsets (ie chan 1 starts at 0x2400, and
552 #define SCALER5_DSPGAMMA_NUM_POINTS 16
553 #define SCALER5_DSPGAMMA_START 0x00002000
554 #define SCALER5_DSPGAMMA_CHAN_OFFSET 0x400
555 # define SCALER5_DSPGAMMA_OFF_X_MASK VC4_MASK(31, 20)
556 # define SCALER5_DSPGAMMA_OFF_X_SHIFT 20
557 # define SCALER5_DSPGAMMA_OFF_C_MASK VC4_MASK(15, 0)
558 # define SCALER5_DSPGAMMA_OFF_C_SHIFT 0
559 # define SCALER5_DSPGAMMA_GRAD_MASK VC4_MASK(11, 0)
560 # define SCALER5_DSPGAMMA_GRAD_SHIFT 0
562 #define SCALER5_DLIST_START 0x00004000
564 #define SCALER6_VERSION 0x00000000
565 #define SCALER6_CXM_SIZE 0x00000004
566 #define SCALER6_LBM_SIZE 0x00000008
567 #define SCALER6_UBM_SIZE 0x0000000c
568 #define SCALER6_COBA_SIZE 0x00000010
569 #define SCALER6_COB_SIZE 0x00000014
571 #define SCALER6_CONTROL 0x00000020
572 # define SCALER6_CONTROL_HVS_EN BIT(31)
573 # define SCALER6_CONTROL_PF_LINES_MASK VC4_MASK(22, 18)
574 # define SCALER6_CONTROL_ABORT_ON_EMPTY BIT(16)
575 # define SCALER6_CONTROL_DSP1_TARGET_MASK VC4_MASK(13, 12)
576 # define SCALER6_CONTROL_MAX_REQS_MASK VC4_MASK(7, 4)
578 #define SCALER6_FETCHER_STATUS 0x00000024
579 #define SCALER6_FETCH_STATUS 0x00000028
580 #define SCALER6_HANDLE_ERROR 0x0000002c
582 #define SCALER6_DISP0_CTRL0 0x00000030
583 #define SCALER6_DISPX_CTRL0(x) ((hvs->vc4->step_d0) ? \
584 (SCALER6D0_DISP0_CTRL0 + ((x) * (SCALER6D0_DISP1_CTRL0 - SCALER6D0_DISP0_CTRL0))) : \
585 (SCALER6_DISP0_CTRL0 + ((x) * (SCALER6_DISP1_CTRL0 - SCALER6_DISP0_CTRL0))))
586 # define SCALER6_DISPX_CTRL0_ENB BIT(31)
587 # define SCALER6_DISPX_CTRL0_RESET BIT(30)
588 # define SCALER6_DISPX_CTRL0_FWIDTH_MASK VC4_MASK(28, 16)
589 # define SCALER6_DISPX_CTRL0_ONESHOT BIT(15)
590 # define SCALER6_DISPX_CTRL0_ONECTX_MASK VC4_MASK(14, 13)
591 # define SCALER6_DISPX_CTRL0_LINES_MASK VC4_MASK(12, 0)
593 #define SCALER6_DISP0_CTRL1 0x00000034
594 #define SCALER6_DISPX_CTRL1(x) ((hvs->vc4->step_d0) ? \
595 (SCALER6D0_DISP0_CTRL1 + ((x) * (SCALER6D0_DISP1_CTRL1 - SCALER6D0_DISP0_CTRL1))) : \
596 (SCALER6_DISP0_CTRL1 + ((x) * (SCALER6_DISP1_CTRL1 - SCALER6_DISP0_CTRL1))))
597 # define SCALER6_DISPX_CTRL1_BGENB BIT(8)
598 # define SCALER6_DISPX_CTRL1_INTLACE BIT(0)
600 #define SCALER6_DISP0_BGND 0x00000038
601 #define SCALER6_DISPX_BGND(x) ((hvs->vc4->step_d0) ? \
602 (SCALER6D0_DISP0_BGND + ((x) * (SCALER6D0_DISP1_BGND - SCALER6D0_DISP0_BGND))) : \
603 (SCALER6_DISP0_BGND + ((x) * (SCALER6_DISP1_BGND - SCALER6_DISP0_BGND))))
605 #define SCALER6_DISP0_LPTRS 0x0000003c
606 #define SCALER6_DISPX_LPTRS(x) ((hvs->vc4->step_d0) ? \
607 (SCALER6D0_DISP0_LPTRS + ((x) * (SCALER6D0_DISP1_LPTRS - SCALER6D0_DISP0_LPTRS))) : \
608 (SCALER6_DISP0_LPTRS + ((x) * (SCALER6_DISP1_LPTRS - SCALER6_DISP0_LPTRS))))
609 # define SCALER6_DISPX_LPTRS_HEADE_MASK VC4_MASK(11, 0)
611 #define SCALER6_DISP0_COB 0x00000040
612 #define SCALER6_DISPX_COB(x) ((hvs->vc4->step_d0) ? \
613 (SCALER6D0_DISP0_COB + ((x) * (SCALER6D0_DISP1_COB - SCALER6D0_DISP0_COB))) : \
614 (SCALER6_DISP0_COB + ((x) * (SCALER6_DISP1_COB - SCALER6_DISP0_COB))))
615 # define SCALER6_DISPX_COB_TOP_MASK VC4_MASK(31, 16)
616 # define SCALER6_DISPX_COB_BASE_MASK VC4_MASK(15, 0)
618 #define SCALER6_DISP0_STATUS 0x00000044
620 #define SCALER6_DISPX_STATUS(x) ((hvs->vc4->step_d0) ? \
621 (SCALER6D0_DISP0_STATUS + ((x) * (SCALER6D0_DISP1_STATUS - SCALER6D0_DISP0_STATUS))) : \
622 (SCALER6_DISP0_STATUS + ((x) * (SCALER6_DISP1_STATUS - SCALER6_DISP0_STATUS))))
623 # define SCALER6_DISPX_STATUS_EMPTY BIT(22)
624 # define SCALER6_DISPX_STATUS_FRCNT_MASK VC4_MASK(21, 16)
625 # define SCALER6_DISPX_STATUS_OFIELD BIT(15)
626 # define SCALER6_DISPX_STATUS_MODE_MASK VC4_MASK(14, 13)
627 # define SCALER6_DISPX_STATUS_MODE_DISABLED 0
628 # define SCALER6_DISPX_STATUS_MODE_INIT 1
629 # define SCALER6_DISPX_STATUS_MODE_RUN 2
630 # define SCALER6_DISPX_STATUS_MODE_EOF 3
631 # define SCALER6_DISPX_STATUS_YLINE_MASK VC4_MASK(12, 0)
633 #define SCALER6_DISP0_DL 0x00000048
635 #define SCALER6_DISPX_DL(x) ((hvs->vc4->step_d0) ? \
636 (SCALER6D0_DISP0_DL + ((x) * (SCALER6D0_DISP1_DL - SCALER6D0_DISP0_DL))) : \
637 (SCALER6_DISP0_DL + ((x) * (SCALER6_DISP1_DL - SCALER6_DISP0_DL))))
638 # define SCALER6_DISPX_DL_LACT_MASK VC4_MASK(11, 0)
640 #define SCALER6_DISP0_RUN 0x0000004c
641 #define SCALER6_DISP1_CTRL0 0x00000050
642 #define SCALER6_DISP1_CTRL1 0x00000054
643 #define SCALER6_DISP1_BGND 0x00000058
644 #define SCALER6_DISP1_LPTRS 0x0000005c
645 #define SCALER6_DISP1_COB 0x00000060
646 #define SCALER6_DISP1_STATUS 0x00000064
647 #define SCALER6_DISP1_DL 0x00000068
648 #define SCALER6_DISP1_RUN 0x0000006c
649 #define SCALER6_DISP2_CTRL0 0x00000070
650 #define SCALER6_DISP2_CTRL1 0x00000074
651 #define SCALER6_DISP2_BGND 0x00000078
652 #define SCALER6_DISP2_LPTRS 0x0000007c
653 #define SCALER6_DISP2_COB 0x00000080
654 #define SCALER6_DISP2_STATUS 0x00000084
655 #define SCALER6_DISP2_DL 0x00000088
656 #define SCALER6_DISP2_RUN 0x0000008c
657 #define SCALER6_EOLN 0x00000090
658 #define SCALER6_DL_STATUS 0x00000094
659 #define SCALER6_BFG_MISC 0x0000009c
660 #define SCALER6_QOS0 0x000000a0
661 #define SCALER6_PROF0 0x000000a4
662 #define SCALER6_QOS1 0x000000a8
663 #define SCALER6_PROF1 0x000000ac
664 #define SCALER6_QOS2 0x000000b0
665 #define SCALER6_PROF2 0x000000b4
666 #define SCALER6_PRI_MAP0 0x000000b8
667 #define SCALER6_PRI_MAP1 0x000000bc
668 #define SCALER6_HISTCTRL 0x000000c0
669 #define SCALER6_HISTBIN0 0x000000c4
670 #define SCALER6_HISTBIN1 0x000000c8
671 #define SCALER6_HISTBIN2 0x000000cc
672 #define SCALER6_HISTBIN3 0x000000d0
673 #define SCALER6_HISTBIN4 0x000000d4
674 #define SCALER6_HISTBIN5 0x000000d8
675 #define SCALER6_HISTBIN6 0x000000dc
676 #define SCALER6_HISTBIN7 0x000000e0
677 #define SCALER6_HDR_CFG_REMAP 0x000000f4
678 #define SCALER6_COL_SPACE 0x000000f8
679 #define SCALER6_HVS_ID 0x000000fc
680 #define SCALER6_CFC1 0x00000100
681 #define SCALER6_DISP_UPM_ISO0 0x00000200
682 #define SCALER6_DISP_UPM_ISO1 0x00000204
683 #define SCALER6_DISP_UPM_ISO2 0x00000208
684 #define SCALER6_DISP_LBM_ISO0 0x0000020c
685 #define SCALER6_DISP_LBM_ISO1 0x00000210
686 #define SCALER6_DISP_LBM_ISO2 0x00000214
687 #define SCALER6_DISP_COB_ISO0 0x00000218
688 #define SCALER6_DISP_COB_ISO1 0x0000021c
689 #define SCALER6_DISP_COB_ISO2 0x00000220
690 #define SCALER6_BAD_COB 0x00000224
691 #define SCALER6_BAD_LBM 0x00000228
692 #define SCALER6_BAD_UPM 0x0000022c
693 #define SCALER6_BAD_AXI 0x00000230
696 #define SCALER6D0_VERSION 0x00000000
697 #define SCALER6D0_CXM_SIZE 0x00000004
698 #define SCALER6D0_LBM_SIZE 0x00000008
699 #define SCALER6D0_UBM_SIZE 0x0000000c
700 #define SCALER6D0_COBA_SIZE 0x00000010
701 #define SCALER6D0_COB_SIZE 0x00000014
702 #define SCALER6D0_CONTROL 0x00000020
703 #define SCALER6D0_FETCHER_STATUS 0x00000024
704 #define SCALER6D0_FETCH_STATUS 0x00000028
705 #define SCALER6D0_HANDLE_ERROR 0x0000002c
707 #define SCALER6D0_EOLN 0x00000030
708 #define SCALER6D0_DL_STATUS 0x00000034
709 #define SCALER6D0_PRI_MAP0 0x00000038
710 #define SCALER6D0_PRI_MAP1 0x0000003c
711 #define SCALER6D0_HISTCTRL 0x000000d0
712 #define SCALER6D0_HISTBIN0 0x000000d4
713 #define SCALER6D0_HISTBIN1 0x000000d8
714 #define SCALER6D0_HISTBIN2 0x000000dc
715 #define SCALER6D0_HISTBIN3 0x000000e0
716 #define SCALER6D0_HISTBIN4 0x000000e4
717 #define SCALER6D0_HISTBIN5 0x000000e8
718 #define SCALER6D0_HISTBIN6 0x000000ec
719 #define SCALER6D0_HISTBIN7 0x000000f0
720 #define SCALER6D0_HVS_ID 0x000000fc
722 #define SCALER6D0_DISP0_CTRL0 0x00000100
723 # define SCALER6D0_DISPX_CTRL0_ENB BIT(31)
724 # define SCALER6D0_DISPX_CTRL0_RESET BIT(30)
725 # define SCALER6D0_DISPX_CTRL0_FWIDTH_MASK VC4_MASK(28, 16)
726 # define SCALER6D0_DISPX_CTRL0_ONESHOT BIT(15)
727 # define SCALER6D0_DISPX_CTRL0_ONECTX_MASK VC4_MASK(14, 13)
728 # define SCALER6D0_DISPX_CTRL0_LINES_MASK VC4_MASK(12, 0)
730 #define SCALER6D0_DISP0_CTRL1 0x00000104
731 # define SCALER6D0_DISPX_CTRL1_BGENB BIT(8)
732 # define SCALER6D0_DISPX_CTRL1_INTLACE BIT(0)
734 #define SCALER6D0_DISP0_BGND 0x00000108
736 #define SCALER6D0_DISP0_LPTRS 0x00000110
737 # define SCALER6D0_DISPX_LPTRS_HEADE_MASK VC4_MASK(11, 0)
739 #define SCALER6D0_DISP0_COB 0x00000114
740 # define SCALER6D0_DISPX_COB_TOP_MASK VC4_MASK(31, 16)
741 # define SCALER6D0_DISPX_COB_BASE_MASK VC4_MASK(15, 0)
743 #define SCALER6D0_DISP0_STATUS 0x00000118
745 # define SCALER6D0_DISPX_STATUS_EMPTY BIT(22)
746 # define SCALER6D0_DISPX_STATUS_FRCNT_MASK VC4_MASK(21, 16)
747 # define SCALER6D0_DISPX_STATUS_OFIELD BIT(15)
748 # define SCALER6D0_DISPX_STATUS_MODE_MASK VC4_MASK(14, 13)
749 # define SCALER6D0_DISPX_STATUS_MODE_DISABLED 0
750 # define SCALER6D0_DISPX_STATUS_MODE_INIT 1
751 # define SCALER6D0_DISPX_STATUS_MODE_RUN 2
752 # define SCALER6D0_DISPX_STATUS_MODE_EOF 3
753 # define SCALER6D0_DISPX_STATUS_YLINE_MASK VC4_MASK(12, 0)
756 #define SCALER6D0_DISP0_CTRL0 0x00000100
757 #define SCALER6D0_DISP0_CTRL1 0x00000104
758 #define SCALER6D0_DISP0_BGND0 0x00000108
759 #define SCALER6D0_DISP0_BGND1 0x0000010c
760 #define SCALER6D0_DISP0_LPTRS 0x00000110
761 #define SCALER6D0_DISP0_COB 0x00000114
762 #define SCALER6D0_DISP0_STATUS 0x00000118
763 #define SCALER6D0_DISP0_DL 0x0000011c
764 # define SCALER6D0_DISPX_DL_LACT_MASK VC4_MASK(11, 0)
765 #define SCALER6D0_DISP0_RUN 0x00000120
766 #define SCALER6D0_QOS0 0x00000124
767 #define SCALER6D0_PROF0 0x00000128
769 #define SCALER6D0_DISP1_CTRL0 0x00000140
770 #define SCALER6D0_DISP1_CTRL1 0x00000144
771 #define SCALER6D0_DISP1_BGND0 0x00000148
772 #define SCALER6D0_DISP1_BGND1 0x0000014c
773 #define SCALER6D0_DISP1_LPTRS 0x00000150
774 #define SCALER6D0_DISP1_COB 0x00000154
775 #define SCALER6D0_DISP1_STATUS 0x00000158
776 #define SCALER6D0_DISP1_DL 0x0000015c
777 #define SCALER6D0_DISP1_RUN 0x00000160
778 #define SCALER6D0_QOS1 0x00000164
779 #define SCALER6D0_PROF1 0x00000168
781 #define SCALER6D0_DISP2_CTRL0 0x00000180
782 #define SCALER6D0_DISP2_CTRL1 0x00000184
783 #define SCALER6D0_DISP2_BGND0 0x00000188
784 #define SCALER6D0_DISP2_BGND1 0x0000018c
785 #define SCALER6D0_DISP2_LPTRS 0x00000190
786 #define SCALER6D0_DISP2_COB 0x00000194
787 #define SCALER6D0_DISP2_STATUS 0x00000198
788 #define SCALER6D0_DISP2_DL 0x0000019c
789 #define SCALER6D0_DISP2_RUN 0x000001a0
790 #define SCALER6D0_QOS2 0x000001a4
791 #define SCALER6D0_PROF2 0x000001a8
793 #define SCALER6(x) ((hvs->vc4->step_d0) ? SCALER6D0_ ## x : SCALER6_ ## x)
795 # define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1)
796 # define VC4_HDMI_SW_RESET_HDMI BIT(0)
798 # define VC4_HDMI_HOTPLUG_CONNECTED BIT(0)
800 # define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE BIT(27)
801 # define VC4_HDMI_MAI_CONFIG_BIT_REVERSE BIT(26)
802 # define VC4_HDMI_MAI_CHANNEL_MASK_MASK VC4_MASK(15, 0)
803 # define VC4_HDMI_MAI_CHANNEL_MASK_SHIFT 0
805 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT BIT(29)
806 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS BIT(24)
807 # define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT BIT(19)
808 # define VC4_HDMI_AUDIO_PACKET_FORCE_B_FRAME BIT(18)
809 # define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_MASK VC4_MASK(13, 10)
810 # define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_SHIFT 10
811 /* If set, then multichannel, otherwise 2 channel. */
812 # define VC4_HDMI_AUDIO_PACKET_AUDIO_LAYOUT BIT(9)
813 /* If set, then AUDIO_LAYOUT overrides audio_cea_mask */
814 # define VC4_HDMI_AUDIO_PACKET_FORCE_AUDIO_LAYOUT BIT(8)
815 # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_MASK VC4_MASK(7, 0)
816 # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_SHIFT 0
818 # define VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT_MASK VC4_MASK(23, 16)
819 # define VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT_SHIFT 16
822 VC4_HDMI_MAI_FORMAT_PCM = 2,
823 VC4_HDMI_MAI_FORMAT_HBR = 200,
826 # define VC4_HDMI_MAI_FORMAT_SAMPLE_RATE_MASK VC4_MASK(15, 8)
827 # define VC4_HDMI_MAI_FORMAT_SAMPLE_RATE_SHIFT 8
830 VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED = 0,
831 VC4_HDMI_MAI_SAMPLE_RATE_8000 = 1,
832 VC4_HDMI_MAI_SAMPLE_RATE_11025 = 2,
833 VC4_HDMI_MAI_SAMPLE_RATE_12000 = 3,
834 VC4_HDMI_MAI_SAMPLE_RATE_16000 = 4,
835 VC4_HDMI_MAI_SAMPLE_RATE_22050 = 5,
836 VC4_HDMI_MAI_SAMPLE_RATE_24000 = 6,
837 VC4_HDMI_MAI_SAMPLE_RATE_32000 = 7,
838 VC4_HDMI_MAI_SAMPLE_RATE_44100 = 8,
839 VC4_HDMI_MAI_SAMPLE_RATE_48000 = 9,
840 VC4_HDMI_MAI_SAMPLE_RATE_64000 = 10,
841 VC4_HDMI_MAI_SAMPLE_RATE_88200 = 11,
842 VC4_HDMI_MAI_SAMPLE_RATE_96000 = 12,
843 VC4_HDMI_MAI_SAMPLE_RATE_128000 = 13,
844 VC4_HDMI_MAI_SAMPLE_RATE_176400 = 14,
845 VC4_HDMI_MAI_SAMPLE_RATE_192000 = 15,
848 # define VC4_HDMI_RAM_PACKET_ENABLE BIT(16)
850 /* When set, the CTS_PERIOD counts based on MAI bus sync pulse instead
853 # define VC4_HDMI_CRP_USE_MAI_BUS_SYNC_FOR_CTS BIT(26)
854 /* When set, no CRP packets will be sent. */
855 # define VC4_HDMI_CRP_CFG_DISABLE BIT(25)
856 /* If set, generates CTS values based on N, audio clock, and video
857 * clock. N must be divisible by 128.
859 # define VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN BIT(24)
860 # define VC4_HDMI_CRP_CFG_N_MASK VC4_MASK(19, 0)
861 # define VC4_HDMI_CRP_CFG_N_SHIFT 0
863 # define VC4_HDMI_HORZA_VPOS BIT(14)
864 # define VC4_HDMI_HORZA_HPOS BIT(13)
865 /* Horizontal active pixels (hdisplay). */
866 # define VC4_HDMI_HORZA_HAP_MASK VC4_MASK(12, 0)
867 # define VC4_HDMI_HORZA_HAP_SHIFT 0
869 /* Horizontal pack porch (htotal - hsync_end). */
870 # define VC4_HDMI_HORZB_HBP_MASK VC4_MASK(29, 20)
871 # define VC4_HDMI_HORZB_HBP_SHIFT 20
872 /* Horizontal sync pulse (hsync_end - hsync_start). */
873 # define VC4_HDMI_HORZB_HSP_MASK VC4_MASK(19, 10)
874 # define VC4_HDMI_HORZB_HSP_SHIFT 10
875 /* Horizontal front porch (hsync_start - hdisplay). */
876 # define VC4_HDMI_HORZB_HFP_MASK VC4_MASK(9, 0)
877 # define VC4_HDMI_HORZB_HFP_SHIFT 0
879 # define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14)
880 # define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13)
881 # define VC4_HDMI_FIFO_CTL_ON_VB BIT(7)
882 # define VC4_HDMI_FIFO_CTL_RECENTER BIT(6)
883 # define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5)
884 # define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4)
885 # define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3)
886 # define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2)
887 # define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1)
888 # define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0)
889 # define VC4_HDMI_FIFO_VALID_WRITE_MASK 0xefff
891 # define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15)
892 # define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5)
893 # define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3)
894 # define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1)
895 # define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0)
897 /* Vertical sync pulse (vsync_end - vsync_start). */
898 # define VC4_HDMI_VERTA_VSP_MASK VC4_MASK(24, 20)
899 # define VC4_HDMI_VERTA_VSP_SHIFT 20
900 /* Vertical front porch (vsync_start - vdisplay). */
901 # define VC4_HDMI_VERTA_VFP_MASK VC4_MASK(19, 13)
902 # define VC4_HDMI_VERTA_VFP_SHIFT 13
903 /* Vertical active lines (vdisplay). */
904 # define VC4_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
905 # define VC4_HDMI_VERTA_VAL_SHIFT 0
907 /* Vertical sync pulse offset (for interlaced) */
908 # define VC4_HDMI_VERTB_VSPO_MASK VC4_MASK(21, 9)
909 # define VC4_HDMI_VERTB_VSPO_SHIFT 9
910 /* Vertical pack porch (vtotal - vsync_end). */
911 # define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0)
912 # define VC4_HDMI_VERTB_VBP_SHIFT 0
914 /* Set when the transmission has ended. */
915 # define VC4_HDMI_CEC_TX_EOM BIT(31)
916 /* If set, transmission was acked on the 1st or 2nd attempt (only one
917 * retry is attempted). If in continuous mode, this means TX needs to
918 * be filled if !TX_EOM.
920 # define VC4_HDMI_CEC_TX_STATUS_GOOD BIT(30)
921 # define VC4_HDMI_CEC_RX_EOM BIT(29)
922 # define VC4_HDMI_CEC_RX_STATUS_GOOD BIT(28)
923 /* Number of bytes received for the message. */
924 # define VC4_HDMI_CEC_REC_WRD_CNT_MASK VC4_MASK(27, 24)
925 # define VC4_HDMI_CEC_REC_WRD_CNT_SHIFT 24
926 /* Sets continuous receive mode. Generates interrupt after each 8
927 * bytes to signal that RX_DATA should be consumed, and at RX_EOM.
929 * If disabled, maximum 16 bytes will be received (including header),
930 * and interrupt at RX_EOM. Later bytes will be acked but not put
933 # define VC4_HDMI_CEC_RX_CONTINUE BIT(23)
934 # define VC4_HDMI_CEC_TX_CONTINUE BIT(22)
935 /* Set this after a CEC interrupt. */
936 # define VC4_HDMI_CEC_CLEAR_RECEIVE_OFF BIT(21)
937 /* Starts a TX. Will wait for appropriate idel time before CEC
938 * activity. Must be cleared in between transmits.
940 # define VC4_HDMI_CEC_START_XMIT_BEGIN BIT(20)
941 # define VC4_HDMI_CEC_MESSAGE_LENGTH_MASK VC4_MASK(19, 16)
942 # define VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT 16
943 /* Device's CEC address */
944 # define VC4_HDMI_CEC_ADDR_MASK VC4_MASK(15, 12)
945 # define VC4_HDMI_CEC_ADDR_SHIFT 12
946 /* Divides off of HSM clock to generate CEC bit clock. */
947 /* With the current defaults the CEC bit clock is 40 kHz = 25 usec */
948 # define VC4_HDMI_CEC_DIV_CLK_CNT_MASK VC4_MASK(11, 0)
949 # define VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT 0
951 /* Set these fields to how many bit clock cycles get to that many
954 # define VC4_HDMI_CEC_CNT_TO_1500_US_MASK VC4_MASK(30, 24)
955 # define VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT 24
956 # define VC4_HDMI_CEC_CNT_TO_1300_US_MASK VC4_MASK(23, 17)
957 # define VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT 17
958 # define VC4_HDMI_CEC_CNT_TO_800_US_MASK VC4_MASK(16, 11)
959 # define VC4_HDMI_CEC_CNT_TO_800_US_SHIFT 11
960 # define VC4_HDMI_CEC_CNT_TO_600_US_MASK VC4_MASK(10, 5)
961 # define VC4_HDMI_CEC_CNT_TO_600_US_SHIFT 5
962 # define VC4_HDMI_CEC_CNT_TO_400_US_MASK VC4_MASK(4, 0)
963 # define VC4_HDMI_CEC_CNT_TO_400_US_SHIFT 0
965 # define VC4_HDMI_CEC_CNT_TO_2750_US_MASK VC4_MASK(31, 24)
966 # define VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT 24
967 # define VC4_HDMI_CEC_CNT_TO_2400_US_MASK VC4_MASK(23, 16)
968 # define VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT 16
969 # define VC4_HDMI_CEC_CNT_TO_2050_US_MASK VC4_MASK(15, 8)
970 # define VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT 8
971 # define VC4_HDMI_CEC_CNT_TO_1700_US_MASK VC4_MASK(7, 0)
972 # define VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT 0
974 # define VC4_HDMI_CEC_CNT_TO_4300_US_MASK VC4_MASK(31, 24)
975 # define VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT 24
976 # define VC4_HDMI_CEC_CNT_TO_3900_US_MASK VC4_MASK(23, 16)
977 # define VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT 16
978 # define VC4_HDMI_CEC_CNT_TO_3600_US_MASK VC4_MASK(15, 8)
979 # define VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT 8
980 # define VC4_HDMI_CEC_CNT_TO_3500_US_MASK VC4_MASK(7, 0)
981 # define VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT 0
983 # define VC4_HDMI_CEC_TX_SW_RESET BIT(27)
984 # define VC4_HDMI_CEC_RX_SW_RESET BIT(26)
985 # define VC4_HDMI_CEC_PAD_SW_RESET BIT(25)
986 # define VC4_HDMI_CEC_MUX_TP_OUT_CEC BIT(24)
987 # define VC4_HDMI_CEC_RX_CEC_INT BIT(23)
988 # define VC4_HDMI_CEC_CLK_PRELOAD_MASK VC4_MASK(22, 16)
989 # define VC4_HDMI_CEC_CLK_PRELOAD_SHIFT 16
990 # define VC4_HDMI_CEC_CNT_TO_4700_US_MASK VC4_MASK(15, 8)
991 # define VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT 8
992 # define VC4_HDMI_CEC_CNT_TO_4500_US_MASK VC4_MASK(7, 0)
993 # define VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT 0
995 # define VC4_HDMI_TX_PHY_RNG_PWRDN BIT(25)
997 # define VC4_HDMI_CPU_CEC BIT(6)
998 # define VC4_HDMI_CPU_HOTPLUG BIT(0)
1000 /* Debug: Current receive value on the CEC pad. */
1001 # define VC4_HD_CECRXD BIT(9)
1002 /* Debug: Override CEC output to 0. */
1003 # define VC4_HD_CECOVR BIT(8)
1004 # define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6)
1005 # define VC4_HD_M_RAM_STANDBY (3 << 4)
1006 # define VC4_HD_M_SW_RST BIT(2)
1007 # define VC4_HD_M_ENABLE BIT(0)
1009 /* Set when audio stream is received at a slower rate than the
1010 * sampling period, so MAI fifo goes empty. Write 1 to clear.
1012 # define VC4_HD_MAI_CTL_DLATE BIT(15)
1013 # define VC4_HD_MAI_CTL_BUSY BIT(14)
1014 # define VC4_HD_MAI_CTL_CHALIGN BIT(13)
1015 # define VC4_HD_MAI_CTL_WHOLSMP BIT(12)
1016 # define VC4_HD_MAI_CTL_FULL BIT(11)
1017 # define VC4_HD_MAI_CTL_EMPTY BIT(10)
1018 # define VC4_HD_MAI_CTL_FLUSH BIT(9)
1019 /* If set, MAI bus generates SPDIF (bit 31) parity instead of passing
1022 # define VC4_HD_MAI_CTL_PAREN BIT(8)
1023 # define VC4_HD_MAI_CTL_CHNUM_MASK VC4_MASK(7, 4)
1024 # define VC4_HD_MAI_CTL_CHNUM_SHIFT 4
1025 # define VC4_HD_MAI_CTL_ENABLE BIT(3)
1026 /* Underflow error status bit, write 1 to clear. */
1027 # define VC4_HD_MAI_CTL_ERRORE BIT(2)
1028 /* Overflow error status bit, write 1 to clear. */
1029 # define VC4_HD_MAI_CTL_ERRORF BIT(1)
1030 /* Single-shot reset bit. Read value is undefined. */
1031 # define VC4_HD_MAI_CTL_RESET BIT(0)
1033 # define VC4_HD_MAI_THR_PANICHIGH_MASK VC4_MASK(29, 24)
1034 # define VC4_HD_MAI_THR_PANICHIGH_SHIFT 24
1035 # define VC4_HD_MAI_THR_PANICLOW_MASK VC4_MASK(21, 16)
1036 # define VC4_HD_MAI_THR_PANICLOW_SHIFT 16
1037 # define VC4_HD_MAI_THR_DREQHIGH_MASK VC4_MASK(13, 8)
1038 # define VC4_HD_MAI_THR_DREQHIGH_SHIFT 8
1039 # define VC4_HD_MAI_THR_DREQLOW_MASK VC4_MASK(5, 0)
1040 # define VC4_HD_MAI_THR_DREQLOW_SHIFT 0
1042 /* Divider from HDMI HSM clock to MAI serial clock. Sampling period
1043 * converges to N / (M + 1) cycles.
1045 # define VC4_HD_MAI_SMP_N_MASK VC4_MASK(31, 8)
1046 # define VC4_HD_MAI_SMP_N_SHIFT 8
1047 # define VC4_HD_MAI_SMP_M_MASK VC4_MASK(7, 0)
1048 # define VC4_HD_MAI_SMP_M_SHIFT 0
1050 # define VC4_HD_VID_CTL_ENABLE BIT(31)
1051 # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30)
1052 # define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29)
1053 # define VC4_HD_VID_CTL_VSYNC_LOW BIT(28)
1054 # define VC4_HD_VID_CTL_HSYNC_LOW BIT(27)
1055 # define VC4_HD_VID_CTL_CLRSYNC BIT(24)
1056 # define VC4_HD_VID_CTL_CLRRGB BIT(23)
1057 # define VC4_HD_VID_CTL_BLANKPIX BIT(18)
1058 # define VC4_HD_VID_CTL_BLANK_INSERT_EN BIT(16)
1060 # define VC4_HD_CSC_CTL_ORDER_MASK VC4_MASK(7, 5)
1061 # define VC4_HD_CSC_CTL_ORDER_SHIFT 5
1062 # define VC4_HD_CSC_CTL_ORDER_RGB 0
1063 # define VC4_HD_CSC_CTL_ORDER_BGR 1
1064 # define VC4_HD_CSC_CTL_ORDER_BRG 2
1065 # define VC4_HD_CSC_CTL_ORDER_GRB 3
1066 # define VC4_HD_CSC_CTL_ORDER_GBR 4
1067 # define VC4_HD_CSC_CTL_ORDER_RBG 5
1068 # define VC4_HD_CSC_CTL_PADMSB BIT(4)
1069 # define VC4_HD_CSC_CTL_MODE_MASK VC4_MASK(3, 2)
1070 # define VC4_HD_CSC_CTL_MODE_SHIFT 2
1071 # define VC4_HD_CSC_CTL_MODE_RGB_TO_SD_YPRPB 0
1072 # define VC4_HD_CSC_CTL_MODE_RGB_TO_HD_YPRPB 1
1073 # define VC4_HD_CSC_CTL_MODE_CUSTOM 3
1074 # define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
1075 # define VC4_HD_CSC_CTL_ENABLE BIT(0)
1077 # define VC5_MT_CP_CSC_CTL_USE_444_TO_422 BIT(6)
1078 # define VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_MASK \
1080 # define VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD \
1082 # define VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION BIT(3)
1083 # define VC5_MT_CP_CSC_CTL_ENABLE BIT(2)
1084 # define VC5_MT_CP_CSC_CTL_MODE_MASK VC4_MASK(1, 0)
1086 # define VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_MASK \
1088 # define VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE \
1091 # define VC4_DVP_HT_CLOCK_STOP_PIXEL BIT(1)
1093 # define VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_MASK \
1095 # define VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY \
1098 /* HVS display list information. */
1099 #define HVS_BOOTLOADER_DLIST_END 32
1101 enum hvs_pixel_format {
1103 HVS_PIXEL_FORMAT_RGB332 = 0,
1105 HVS_PIXEL_FORMAT_RGBA4444 = 1,
1106 HVS_PIXEL_FORMAT_RGB555 = 2,
1107 HVS_PIXEL_FORMAT_RGBA5551 = 3,
1108 HVS_PIXEL_FORMAT_RGB565 = 4,
1110 HVS_PIXEL_FORMAT_RGB888 = 5,
1111 HVS_PIXEL_FORMAT_RGBA6666 = 6,
1113 HVS_PIXEL_FORMAT_RGBA8888 = 7,
1115 HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE = 8,
1116 HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE = 9,
1117 HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE = 10,
1118 HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE = 11,
1119 HVS_PIXEL_FORMAT_H264 = 12,
1120 HVS_PIXEL_FORMAT_PALETTE = 13,
1121 HVS_PIXEL_FORMAT_YUV444_RGB = 14,
1122 HVS_PIXEL_FORMAT_AYUV444_RGB = 15,
1123 HVS_PIXEL_FORMAT_RGBA1010102 = 16,
1124 HVS_PIXEL_FORMAT_YCBCR_10BIT = 17,
1127 /* Note: the LSB is the rightmost character shown. Only valid for
1128 * HVS_PIXEL_FORMAT_RGB8888, not RGB888.
1130 /* For modes 332, 4444, 555, 5551, 6666, 8888, 10:10:10:2 */
1131 #define HVS_PIXEL_ORDER_RGBA 0
1132 #define HVS_PIXEL_ORDER_BGRA 1
1133 #define HVS_PIXEL_ORDER_ARGB 2
1134 #define HVS_PIXEL_ORDER_ABGR 3
1136 /* For modes 666 and 888 (4 & 5) */
1137 #define HVS_PIXEL_ORDER_XBRG 0
1138 #define HVS_PIXEL_ORDER_XRBG 1
1139 #define HVS_PIXEL_ORDER_XRGB 2
1140 #define HVS_PIXEL_ORDER_XBGR 3
1142 /* For YCbCr modes (8-12, and 17) */
1143 #define HVS_PIXEL_ORDER_XYCBCR 0
1144 #define HVS_PIXEL_ORDER_XYCRCB 1
1145 #define HVS_PIXEL_ORDER_YXCBCR 2
1146 #define HVS_PIXEL_ORDER_YXCRCB 3
1148 #define SCALER_CTL0_END BIT(31)
1149 #define SCALER_CTL0_VALID BIT(30)
1151 #define SCALER_CTL0_SIZE_MASK VC4_MASK(29, 24)
1152 #define SCALER_CTL0_SIZE_SHIFT 24
1154 #define SCALER_CTL0_TILING_MASK VC4_MASK(21, 20)
1155 #define SCALER_CTL0_TILING_SHIFT 20
1156 #define SCALER_CTL0_TILING_LINEAR 0
1157 #define SCALER_CTL0_TILING_64B 1
1158 #define SCALER_CTL0_TILING_128B 2
1159 #define SCALER_CTL0_TILING_256B_OR_T 3
1161 #define SCALER_CTL0_ALPHA_MASK BIT(19)
1162 #define SCALER_CTL0_HFLIP BIT(16)
1163 #define SCALER_CTL0_VFLIP BIT(15)
1165 #define SCALER_CTL0_KEY_MODE_MASK VC4_MASK(18, 17)
1166 #define SCALER_CTL0_KEY_MODE_SHIFT 17
1167 #define SCALER_CTL0_KEY_DISABLED 0
1168 #define SCALER_CTL0_KEY_LUMA_OR_COMMON_RGB 1
1169 #define SCALER_CTL0_KEY_MATCH 2 /* turn transparent */
1170 #define SCALER_CTL0_KEY_REPLACE 3 /* replace with value from key mask word 2 */
1172 #define SCALER_CTL0_ORDER_MASK VC4_MASK(14, 13)
1173 #define SCALER_CTL0_ORDER_SHIFT 13
1175 #define SCALER_CTL0_RGBA_EXPAND_MASK VC4_MASK(12, 11)
1176 #define SCALER_CTL0_RGBA_EXPAND_SHIFT 11
1177 #define SCALER_CTL0_RGBA_EXPAND_ZERO 0
1178 #define SCALER_CTL0_RGBA_EXPAND_LSB 1
1179 #define SCALER_CTL0_RGBA_EXPAND_MSB 2
1180 #define SCALER_CTL0_RGBA_EXPAND_ROUND 3
1182 #define SCALER5_CTL0_ALPHA_EXPAND BIT(12)
1184 #define SCALER5_CTL0_RGB_EXPAND BIT(11)
1186 #define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)
1187 #define SCALER_CTL0_SCL1_SHIFT 8
1189 #define SCALER_CTL0_SCL0_MASK VC4_MASK(7, 5)
1190 #define SCALER_CTL0_SCL0_SHIFT 5
1192 #define SCALER_CTL0_SCL_H_PPF_V_PPF 0
1193 #define SCALER_CTL0_SCL_H_TPZ_V_PPF 1
1194 #define SCALER_CTL0_SCL_H_PPF_V_TPZ 2
1195 #define SCALER_CTL0_SCL_H_TPZ_V_TPZ 3
1196 #define SCALER_CTL0_SCL_H_PPF_V_NONE 4
1197 #define SCALER_CTL0_SCL_H_NONE_V_PPF 5
1198 #define SCALER_CTL0_SCL_H_NONE_V_TPZ 6
1199 #define SCALER_CTL0_SCL_H_TPZ_V_NONE 7
1201 /* Set to indicate no scaling. */
1202 #define SCALER_CTL0_UNITY BIT(4)
1203 #define SCALER5_CTL0_UNITY BIT(15)
1205 #define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0)
1206 #define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0
1208 #define SCALER5_CTL0_PIXEL_FORMAT_MASK VC4_MASK(4, 0)
1210 #define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24)
1211 #define SCALER_POS0_FIXED_ALPHA_SHIFT 24
1213 #define SCALER_POS0_START_Y_MASK VC4_MASK(23, 12)
1214 #define SCALER_POS0_START_Y_SHIFT 12
1216 #define SCALER_POS0_START_X_MASK VC4_MASK(11, 0)
1217 #define SCALER_POS0_START_X_SHIFT 0
1219 #define SCALER5_POS0_START_Y_MASK VC4_MASK(27, 16)
1220 #define SCALER5_POS0_START_Y_SHIFT 16
1222 #define SCALER5_POS0_START_X_MASK VC4_MASK(13, 0)
1223 #define SCALER5_POS0_START_X_SHIFT 0
1225 #define SCALER5_POS0_VFLIP BIT(31)
1226 #define SCALER5_POS0_HFLIP BIT(15)
1228 #define SCALER5_CTL2_ALPHA_MODE_MASK VC4_MASK(31, 30)
1229 #define SCALER5_CTL2_ALPHA_MODE_SHIFT 30
1230 #define SCALER5_CTL2_ALPHA_MODE_PIPELINE 0
1231 #define SCALER5_CTL2_ALPHA_MODE_FIXED 1
1232 #define SCALER5_CTL2_ALPHA_MODE_FIXED_NONZERO 2
1233 #define SCALER5_CTL2_ALPHA_MODE_FIXED_OVER_0x07 3
1235 #define SCALER5_CTL2_ALPHA_PREMULT BIT(29)
1237 #define SCALER5_CTL2_ALPHA_MIX BIT(28)
1239 #define SCALER5_CTL2_ALPHA_LOC BIT(25)
1241 #define SCALER5_CTL2_MAP_SEL_MASK VC4_MASK(18, 17)
1242 #define SCALER5_CTL2_MAP_SEL_SHIFT 17
1244 #define SCALER5_CTL2_GAMMA BIT(16)
1246 #define SCALER5_CTL2_ALPHA_MASK VC4_MASK(15, 4)
1247 #define SCALER5_CTL2_ALPHA_SHIFT 4
1249 #define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16)
1250 #define SCALER_POS1_SCL_HEIGHT_SHIFT 16
1252 #define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0)
1253 #define SCALER_POS1_SCL_WIDTH_SHIFT 0
1255 #define SCALER5_POS1_SCL_HEIGHT_MASK VC4_MASK(28, 16)
1256 #define SCALER5_POS1_SCL_HEIGHT_SHIFT 16
1258 #define SCALER5_POS1_SCL_WIDTH_MASK VC4_MASK(12, 0)
1259 #define SCALER5_POS1_SCL_WIDTH_SHIFT 0
1261 #define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)
1262 #define SCALER_POS2_ALPHA_MODE_SHIFT 30
1263 #define SCALER_POS2_ALPHA_MODE_PIPELINE 0
1264 #define SCALER_POS2_ALPHA_MODE_FIXED 1
1265 #define SCALER_POS2_ALPHA_MODE_FIXED_NONZERO 2
1266 #define SCALER_POS2_ALPHA_MODE_FIXED_OVER_0x07 3
1267 #define SCALER_POS2_ALPHA_PREMULT BIT(29)
1268 #define SCALER_POS2_ALPHA_MIX BIT(28)
1270 #define SCALER_POS2_HEIGHT_MASK VC4_MASK(27, 16)
1271 #define SCALER_POS2_HEIGHT_SHIFT 16
1273 #define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0)
1274 #define SCALER_POS2_WIDTH_SHIFT 0
1276 #define SCALER5_POS2_HEIGHT_MASK VC4_MASK(28, 16)
1277 #define SCALER5_POS2_HEIGHT_SHIFT 16
1279 #define SCALER5_POS2_WIDTH_MASK VC4_MASK(12, 0)
1280 #define SCALER5_POS2_WIDTH_SHIFT 0
1282 /* Color Space Conversion words. Some values are S2.8 signed
1283 * integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1,
1286 /* bottom 8 bits of S2.8 contribution of Cr to Blue */
1287 #define SCALER_CSC0_COEF_CR_BLU_MASK VC4_MASK(31, 24)
1288 #define SCALER_CSC0_COEF_CR_BLU_SHIFT 24
1289 /* Signed offset to apply to Y before CSC. (Y' = Y + YY_OFS) */
1290 #define SCALER_CSC0_COEF_YY_OFS_MASK VC4_MASK(23, 16)
1291 #define SCALER_CSC0_COEF_YY_OFS_SHIFT 16
1292 /* Signed offset to apply to CB before CSC (Cb' = Cb - 128 + CB_OFS). */
1293 #define SCALER_CSC0_COEF_CB_OFS_MASK VC4_MASK(15, 8)
1294 #define SCALER_CSC0_COEF_CB_OFS_SHIFT 8
1295 /* Signed offset to apply to CB before CSC (Cr' = Cr - 128 + CR_OFS). */
1296 #define SCALER_CSC0_COEF_CR_OFS_MASK VC4_MASK(7, 0)
1297 #define SCALER_CSC0_COEF_CR_OFS_SHIFT 0
1298 #define SCALER_CSC0_ITR_R_601_5 0x00f00000
1299 #define SCALER_CSC0_ITR_R_709_3 0x00f00000
1300 #define SCALER_CSC0_ITR_R_2020 0x00f00000
1301 #define SCALER_CSC0_JPEG_JFIF 0x00000000
1302 #define SCALER_CSC0_ITR_R_709_3_FR 0x00000000
1303 #define SCALER_CSC0_ITR_R_2020_FR 0x00000000
1305 /* S2.8 contribution of Cb to Green */
1306 #define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22)
1307 #define SCALER_CSC1_COEF_CB_GRN_SHIFT 22
1308 /* S2.8 contribution of Cr to Green */
1309 #define SCALER_CSC1_COEF_CR_GRN_MASK VC4_MASK(21, 12)
1310 #define SCALER_CSC1_COEF_CR_GRN_SHIFT 12
1311 /* S2.8 contribution of Y to all of RGB */
1312 #define SCALER_CSC1_COEF_YY_ALL_MASK VC4_MASK(11, 2)
1313 #define SCALER_CSC1_COEF_YY_ALL_SHIFT 2
1314 /* top 2 bits of S2.8 contribution of Cr to Blue */
1315 #define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0)
1316 #define SCALER_CSC1_COEF_CR_BLU_SHIFT 0
1317 #define SCALER_CSC1_ITR_R_601_5 0xe73304a8
1318 #define SCALER_CSC1_ITR_R_709_3 0xf27784a8
1319 #define SCALER_CSC1_ITR_R_2020 0xf43594a8
1320 #define SCALER_CSC1_JPEG_JFIF 0xea349400
1321 #define SCALER_CSC1_ITR_R_709_3_FR 0xf4388400
1322 #define SCALER_CSC1_ITR_R_2020_FR 0xf5b6d400
1324 /* S2.8 contribution of Cb to Red */
1325 #define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20)
1326 #define SCALER_CSC2_COEF_CB_RED_SHIFT 20
1327 /* S2.8 contribution of Cr to Red */
1328 #define SCALER_CSC2_COEF_CR_RED_MASK VC4_MASK(19, 10)
1329 #define SCALER_CSC2_COEF_CR_RED_SHIFT 10
1330 /* S2.8 contribution of Cb to Blue */
1331 #define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10)
1332 #define SCALER_CSC2_COEF_CB_BLU_SHIFT 10
1333 #define SCALER_CSC2_ITR_R_601_5 0x00066604
1334 #define SCALER_CSC2_ITR_R_709_3 0x00072e1d
1335 #define SCALER_CSC2_ITR_R_2020 0x0006b624
1336 #define SCALER_CSC2_JPEG_JFIF 0x00059dc6
1337 #define SCALER_CSC2_ITR_R_709_3_FR 0x00064ddb
1338 #define SCALER_CSC2_ITR_R_2020_FR 0x0005e5e2
1340 #define SCALER_TPZ0_VERT_RECALC BIT(31)
1341 #define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)
1342 #define SCALER_TPZ0_SCALE_SHIFT 8
1343 #define SCALER_TPZ0_IPHASE_MASK VC4_MASK(7, 0)
1344 #define SCALER_TPZ0_IPHASE_SHIFT 0
1345 #define SCALER_TPZ1_RECIP_MASK VC4_MASK(15, 0)
1346 #define SCALER_TPZ1_RECIP_SHIFT 0
1348 /* Skips interpolating coefficients to 64 phases, so just 8 are used.
1349 * Required for nearest neighbor.
1351 #define SCALER_PPF_NOINTERP BIT(31)
1352 /* Replaes the highest valued coefficient with one that makes all 4
1355 #define SCALER_PPF_AGC BIT(30)
1356 #define SCALER_PPF_SCALE_MASK VC4_MASK(24, 8)
1357 #define SCALER_PPF_SCALE_SHIFT 8
1358 #define SCALER_PPF_IPHASE_MASK VC4_MASK(6, 0)
1359 #define SCALER_PPF_IPHASE_SHIFT 0
1361 #define SCALER_PPF_KERNEL_OFFSET_MASK VC4_MASK(13, 0)
1362 #define SCALER_PPF_KERNEL_OFFSET_SHIFT 0
1363 #define SCALER_PPF_KERNEL_UNCACHED BIT(31)
1365 /* PITCH0/1/2 fields for raster. */
1366 #define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0)
1367 #define SCALER_SRC_PITCH_SHIFT 0
1369 /* PITCH0/1/2 fields for tiled (SAND). */
1370 #define SCALER_TILE_SKIP_0_MASK VC4_MASK(18, 16)
1371 #define SCALER_TILE_SKIP_0_SHIFT 16
1372 #define SCALER_TILE_HEIGHT_MASK VC4_MASK(15, 0)
1373 #define SCALER_TILE_HEIGHT_SHIFT 0
1375 /* Common PITCH0 fields */
1376 #define SCALER_PITCH0_SINK_PIX_MASK VC4_MASK(31, 26)
1377 #define SCALER_PITCH0_SINK_PIX_SHIFT 26
1379 /* PITCH0 fields for T-tiled. */
1380 #define SCALER_PITCH0_TILE_WIDTH_L_MASK VC4_MASK(22, 16)
1381 #define SCALER_PITCH0_TILE_WIDTH_L_SHIFT 16
1382 #define SCALER_PITCH0_TILE_LINE_DIR BIT(15)
1383 #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14)
1384 /* Y offset within a tile. */
1385 #define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 8)
1386 #define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 8
1387 #define SCALER_PITCH0_TILE_WIDTH_R_MASK VC4_MASK(6, 0)
1388 #define SCALER_PITCH0_TILE_WIDTH_R_SHIFT 0
1390 #define SCALER6_CTL0_END BIT(31)
1391 #define SCALER6_CTL0_VALID BIT(30)
1392 #define SCALER6_CTL0_NEXT_MASK VC4_MASK(29, 24)
1393 #define SCALER6_CTL0_RGB_TRANS BIT(23)
1394 #define SCALER6_CTL0_ADDR_MODE_MASK VC4_MASK(22, 20)
1395 #define SCALER6_CTL0_ADDR_MODE_LINEAR 0
1396 #define SCALER6_CTL0_ADDR_MODE_128B 1
1397 #define SCALER6_CTL0_ADDR_MODE_256B 2
1398 #define SCALER6_CTL0_ADDR_MODE_MAP8 3
1399 #define SCALER6_CTL0_ADDR_MODE_UIF 4
1401 #define SCALER6_CTL0_ALPHA_MASK_MASK VC4_MASK(19, 18)
1402 #define SCALER6_CTL0_UNITY BIT(15)
1403 #define SCALER6_CTL0_ORDERRGBA_MASK VC4_MASK(14, 13)
1404 #define SCALER6_CTL0_SCL1_MODE_MASK VC4_MASK(10, 8)
1405 #define SCALER6_CTL0_SCL0_MODE_MASK VC4_MASK(7, 5)
1406 #define SCALER6_CTL0_PIXEL_FORMAT_MASK VC4_MASK(4, 0)
1408 #define SCALER6_POS0_START_Y_MASK VC4_MASK(28, 16)
1409 #define SCALER6_POS0_HFLIP BIT(15)
1410 #define SCALER6_POS0_START_X_MASK VC4_MASK(12, 0)
1412 #define SCALER6_CTL2_ALPHA_MODE_MASK VC4_MASK(31, 30)
1413 #define SCALER6_CTL2_ALPHA_PREMULT BIT(29)
1414 #define SCALER6_CTL2_ALPHA_MIX BIT(28)
1415 #define SCALER6_CTL2_BFG BIT(26)
1416 #define SCALER6_CTL2_CSC_ENABLE BIT(25)
1417 #define SCALER6_CTL2_BRCM_CFC_CONTROL_MASK VC4_MASK(18, 16)
1418 #define SCALER6_CTL2_ALPHA_MASK VC4_MASK(15, 4)
1420 #define SCALER6D0_CTL2_CSC_ENABLE BIT(19)
1421 #define SCALER6D0_CTL2_BRCM_CFC_CONTROL_MASK VC4_MASK(22, 20)
1423 #define SCALER6_POS1_SCL_LINES_MASK VC4_MASK(28, 16)
1424 #define SCALER6_POS1_SCL_WIDTH_MASK VC4_MASK(12, 0)
1426 #define SCALER6_POS2_SRC_LINES_MASK VC4_MASK(28, 16)
1427 #define SCALER6_POS2_SRC_WIDTH_MASK VC4_MASK(12, 0)
1429 #define SCALER6_PTR0_VFLIP BIT(31)
1430 #define SCALER6_PTR0_UPM_BASE_MASK VC4_MASK(28, 16)
1431 #define SCALER6_PTR0_UPM_HANDLE_MASK VC4_MASK(14, 10)
1432 #define SCALER6_PTR0_UPM_BUFF_SIZE_MASK VC4_MASK(9, 8)
1433 #define SCALER6_PTR0_UPM_BUFF_SIZE_16_LINES 3
1434 #define SCALER6_PTR0_UPM_BUFF_SIZE_8_LINES 2
1435 #define SCALER6_PTR0_UPM_BUFF_SIZE_4_LINES 1
1436 #define SCALER6_PTR0_UPM_BUFF_SIZE_2_LINES 0
1437 #define SCALER6_PTR0_UPPER_ADDR_MASK VC4_MASK(7, 0)
1439 #define SCALER6_PTR2_ALPHA_BPP_MASK VC4_MASK(31, 31)
1440 #define SCALER6_PTR2_ALPHA_BPP_1BPP 1
1441 #define SCALER6_PTR2_ALPHA_BPP_8BPP 0
1442 #define SCALER6_PTR2_ALPHA_ORDER_MASK VC4_MASK(30, 30)
1443 #define SCALER6_PTR2_ALPHA_ORDER_MSB_TO_LSB 1
1444 #define SCALER6_PTR2_ALPHA_ORDER_LSB_TO_MSB 0
1445 #define SCALER6_PTR2_ALPHA_OFFS_MASK VC4_MASK(29, 27)
1446 #define SCALER6_PTR2_LSKIP_MASK VC4_MASK(26, 24)
1447 #define SCALER6_PTR2_PITCH_MASK VC4_MASK(16, 0)
1448 #define SCALER6_PTR2_FETCH_COUNT_MASK VC4_MASK(26, 16)
1450 #endif /* VC4_REGS_H */