drivers/gpu/drm/vc4/vc4_plane.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 plane module
   8  *
   9  * Each DRM plane is a layer of pixels being scanned out by the HVS.
  10  *
  11  * At atomic modeset check time, we compute the HVS display element
  12  * state that would be necessary for displaying the plane (giving us a
  13  * chance to figure out if a plane configuration is invalid), then at
  14  * atomic flush time the CRTC will ask us to write our element state
  15  * into the region of the HVS that it has allocated for us.
  16  */
  17
  18 #include <drm/drm_atomic.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_atomic_uapi.h>
  21 #include <drm/drm_blend.h>
  22 #include <drm/drm_drv.h>
  23 #include <drm/drm_fb_dma_helper.h>
  24 #include <drm/drm_fourcc.h>
  25 #include <drm/drm_framebuffer.h>
  26 #include <drm/drm_gem_atomic_helper.h>
  27
  28 #include "uapi/drm/vc4_drm.h"
  29
  30 #include "vc4_drv.h"
  31 #include "vc4_regs.h"
  32
  33 static const struct hvs_format {
  34         u32 drm; /* DRM_FORMAT_* */
  35         u32 hvs; /* HVS_FORMAT_* */
  36         u32 pixel_order;
  37         u32 pixel_order_hvs5;
  38         bool hvs5_only;
  39 } hvs_formats[] = {
  40         {
  41                 .drm = DRM_FORMAT_XRGB8888,
  42                 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  43                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  44                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
  45         },
  46         {
  47                 .drm = DRM_FORMAT_ARGB8888,
  48                 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  49                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  50                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
  51         },
  52         {
  53                 .drm = DRM_FORMAT_ABGR8888,
  54                 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  55                 .pixel_order = HVS_PIXEL_ORDER_ARGB,
  56                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
  57         },
  58         {
  59                 .drm = DRM_FORMAT_XBGR8888,
  60                 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  61                 .pixel_order = HVS_PIXEL_ORDER_ARGB,
  62                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
  63         },
  64         {
  65                 .drm = DRM_FORMAT_RGB565,
  66                 .hvs = HVS_PIXEL_FORMAT_RGB565,
  67                 .pixel_order = HVS_PIXEL_ORDER_XRGB,
  68                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_XRGB,
  69         },
  70         {
  71                 .drm = DRM_FORMAT_BGR565,
  72                 .hvs = HVS_PIXEL_FORMAT_RGB565,
  73                 .pixel_order = HVS_PIXEL_ORDER_XBGR,
  74                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_XBGR,
  75         },
  76         {
  77                 .drm = DRM_FORMAT_ARGB1555,
  78                 .hvs = HVS_PIXEL_FORMAT_RGBA5551,
  79                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  80                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
  81         },
  82         {
  83                 .drm = DRM_FORMAT_XRGB1555,
  84                 .hvs = HVS_PIXEL_FORMAT_RGBA5551,
  85                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  86                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
  87         },
  88         {
  89                 .drm = DRM_FORMAT_RGB888,
  90                 .hvs = HVS_PIXEL_FORMAT_RGB888,
  91                 .pixel_order = HVS_PIXEL_ORDER_XRGB,
  92                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_XRGB,
  93         },
  94         {
  95                 .drm = DRM_FORMAT_BGR888,
  96                 .hvs = HVS_PIXEL_FORMAT_RGB888,
  97                 .pixel_order = HVS_PIXEL_ORDER_XBGR,
  98                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_XBGR,
  99         },
 100         {
 101                 .drm = DRM_FORMAT_YUV422,
 102                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
 103                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
 104                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,
 105         },
 106         {
 107                 .drm = DRM_FORMAT_YVU422,
 108                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
 109                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
 110                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCRCB,
 111         },
 112         {
 113                 .drm = DRM_FORMAT_YUV444,
 114                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
 115                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
 116                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,
 117         },
 118         {
 119                 .drm = DRM_FORMAT_YVU444,
 120                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
 121                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
 122                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCRCB,
 123         },
 124         {
 125                 .drm = DRM_FORMAT_YUV420,
 126                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
 127                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
 128                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,
 129         },
 130         {
 131                 .drm = DRM_FORMAT_YVU420,
 132                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
 133                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
 134                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCRCB,
 135         },
 136         {
 137                 .drm = DRM_FORMAT_NV12,
 138                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
 139                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
 140                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,
 141         },
 142         {
 143                 .drm = DRM_FORMAT_NV21,
 144                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
 145                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
 146                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCRCB,
 147         },
 148         {
 149                 .drm = DRM_FORMAT_NV16,
 150                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
 151                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
 152                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,
 153         },
 154         {
 155                 .drm = DRM_FORMAT_NV61,
 156                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
 157                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
 158                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCRCB,
 159         },
 160         {
 161                 .drm = DRM_FORMAT_P030,
 162                 .hvs = HVS_PIXEL_FORMAT_YCBCR_10BIT,
 163                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_XYCBCR,
 164                 .hvs5_only = true,
 165         },
 166         {
 167                 .drm = DRM_FORMAT_XRGB2101010,
 168                 .hvs = HVS_PIXEL_FORMAT_RGBA1010102,
 169                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
 170                 .hvs5_only = true,
 171         },
 172         {
 173                 .drm = DRM_FORMAT_ARGB2101010,
 174                 .hvs = HVS_PIXEL_FORMAT_RGBA1010102,
 175                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
 176                 .hvs5_only = true,
 177         },
 178         {
 179                 .drm = DRM_FORMAT_ABGR2101010,
 180                 .hvs = HVS_PIXEL_FORMAT_RGBA1010102,
 181                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
 182                 .hvs5_only = true,
 183         },
 184         {
 185                 .drm = DRM_FORMAT_XBGR2101010,
 186                 .hvs = HVS_PIXEL_FORMAT_RGBA1010102,
 187                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
 188                 .hvs5_only = true,
 189         },
 190         {
 191                 .drm = DRM_FORMAT_RGB332,
 192                 .hvs = HVS_PIXEL_FORMAT_RGB332,
 193                 .pixel_order = HVS_PIXEL_ORDER_ARGB,
 194                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
 195         },
 196         {
 197                 .drm = DRM_FORMAT_BGR233,
 198                 .hvs = HVS_PIXEL_FORMAT_RGB332,
 199                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
 200                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
 201         },
 202         {
 203                 .drm = DRM_FORMAT_XRGB4444,
 204                 .hvs = HVS_PIXEL_FORMAT_RGBA4444,
 205                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
 206                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
 207         },
 208         {
 209                 .drm = DRM_FORMAT_ARGB4444,
 210                 .hvs = HVS_PIXEL_FORMAT_RGBA4444,
 211                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
 212                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
 213         },
 214         {
 215                 .drm = DRM_FORMAT_XBGR4444,
 216                 .hvs = HVS_PIXEL_FORMAT_RGBA4444,
 217                 .pixel_order = HVS_PIXEL_ORDER_ARGB,
 218                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
 219         },
 220         {
 221                 .drm = DRM_FORMAT_ABGR4444,
 222                 .hvs = HVS_PIXEL_FORMAT_RGBA4444,
 223                 .pixel_order = HVS_PIXEL_ORDER_ARGB,
 224                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
 225         },
 226         {
 227                 .drm = DRM_FORMAT_BGRX4444,
 228                 .hvs = HVS_PIXEL_FORMAT_RGBA4444,
 229                 .pixel_order = HVS_PIXEL_ORDER_RGBA,
 230                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_BGRA,
 231         },
 232         {
 233                 .drm = DRM_FORMAT_BGRA4444,
 234                 .hvs = HVS_PIXEL_FORMAT_RGBA4444,
 235                 .pixel_order = HVS_PIXEL_ORDER_RGBA,
 236                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_BGRA,
 237         },
 238         {
 239                 .drm = DRM_FORMAT_RGBX4444,
 240                 .hvs = HVS_PIXEL_FORMAT_RGBA4444,
 241                 .pixel_order = HVS_PIXEL_ORDER_BGRA,
 242                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_RGBA,
 243         },
 244         {
 245                 .drm = DRM_FORMAT_RGBA4444,
 246                 .hvs = HVS_PIXEL_FORMAT_RGBA4444,
 247                 .pixel_order = HVS_PIXEL_ORDER_BGRA,
 248                 .pixel_order_hvs5 = HVS_PIXEL_ORDER_RGBA,
 249         },
 250 };
 251
 252 static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
 253 {
 254         unsigned i;
 255
 256         for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
 257                 if (hvs_formats[i].drm == drm_format)
 258                         return &hvs_formats[i];
 259         }
 260
 261         return NULL;
 262 }
 263
 264 static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst)
 265 {
 266         if (dst == src >> 16)
 267                 return VC4_SCALING_NONE;
 268         if (3 * dst >= 2 * (src >> 16))
 269                 return VC4_SCALING_PPF;
 270         else
 271                 return VC4_SCALING_TPZ;
 272 }
 273
 274 static bool plane_enabled(struct drm_plane_state *state)
 275 {
 276         return state->fb && !WARN_ON(!state->crtc);
 277 }
 278
 279 static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane)
 280 {
 281         struct vc4_plane_state *vc4_state;
 282
 283         if (WARN_ON(!plane->state))
 284                 return NULL;
 285
 286         vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL);
 287         if (!vc4_state)
 288                 return NULL;
 289
 290         memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm));
 291         vc4_state->dlist_initialized = 0;
 292
 293         __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base);
 294
 295         if (vc4_state->dlist) {
 296                 vc4_state->dlist = kmemdup(vc4_state->dlist,
 297                                            vc4_state->dlist_count * 4,
 298                                            GFP_KERNEL);
 299                 if (!vc4_state->dlist) {
 300                         kfree(vc4_state);
 301                         return NULL;
 302                 }
 303                 vc4_state->dlist_size = vc4_state->dlist_count;
 304         }
 305
 306         return &vc4_state->base;
 307 }
 308
 309 static void vc4_plane_destroy_state(struct drm_plane *plane,
 310                                     struct drm_plane_state *state)
 311 {
 312         struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
 313         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 314
 315         if (drm_mm_node_allocated(&vc4_state->lbm)) {
 316                 unsigned long irqflags;
 317
 318                 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
 319                 drm_mm_remove_node(&vc4_state->lbm);
 320                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
 321         }
 322
 323         kfree(vc4_state->dlist);
 324         __drm_atomic_helper_plane_destroy_state(&vc4_state->base);
 325         kfree(state);
 326 }
 327
 328 /* Called during init to allocate the plane's atomic state. */
 329 static void vc4_plane_reset(struct drm_plane *plane)
 330 {
 331         struct vc4_plane_state *vc4_state;
 332
 333         WARN_ON(plane->state);
 334
 335         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 336         if (!vc4_state)
 337                 return;
 338
 339         __drm_atomic_helper_plane_reset(plane, &vc4_state->base);
 340 }
 341
 342 static void vc4_dlist_counter_increment(struct vc4_plane_state *vc4_state)
 343 {
 344         if (vc4_state->dlist_count == vc4_state->dlist_size) {
 345                 u32 new_size = max(4u, vc4_state->dlist_count * 2);
 346                 u32 *new_dlist = kmalloc_array(new_size, 4, GFP_KERNEL);
 347
 348                 if (!new_dlist)
 349                         return;
 350                 memcpy(new_dlist, vc4_state->dlist, vc4_state->dlist_count * 4);
 351
 352                 kfree(vc4_state->dlist);
 353                 vc4_state->dlist = new_dlist;
 354                 vc4_state->dlist_size = new_size;
 355         }
 356
 357         vc4_state->dlist_count++;
 358 }
 359
 360 static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val)
 361 {
 362         unsigned int idx = vc4_state->dlist_count;
 363
 364         vc4_dlist_counter_increment(vc4_state);
 365         vc4_state->dlist[idx] = val;
 366 }
 367
 368 /* Returns the scl0/scl1 field based on whether the dimensions need to
 369  * be up/down/non-scaled.
 370  *
 371  * This is a replication of a table from the spec.
 372  */
 373 static u32 vc4_get_scl_field(struct drm_plane_state *state, int plane)
 374 {
 375         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 376
 377         switch (vc4_state->x_scaling[plane] << 2 | vc4_state->y_scaling[plane]) {
 378         case VC4_SCALING_PPF << 2 | VC4_SCALING_PPF:
 379                 return SCALER_CTL0_SCL_H_PPF_V_PPF;
 380         case VC4_SCALING_TPZ << 2 | VC4_SCALING_PPF:
 381                 return SCALER_CTL0_SCL_H_TPZ_V_PPF;
 382         case VC4_SCALING_PPF << 2 | VC4_SCALING_TPZ:
 383                 return SCALER_CTL0_SCL_H_PPF_V_TPZ;
 384         case VC4_SCALING_TPZ << 2 | VC4_SCALING_TPZ:
 385                 return SCALER_CTL0_SCL_H_TPZ_V_TPZ;
 386         case VC4_SCALING_PPF << 2 | VC4_SCALING_NONE:
 387                 return SCALER_CTL0_SCL_H_PPF_V_NONE;
 388         case VC4_SCALING_NONE << 2 | VC4_SCALING_PPF:
 389                 return SCALER_CTL0_SCL_H_NONE_V_PPF;
 390         case VC4_SCALING_NONE << 2 | VC4_SCALING_TPZ:
 391                 return SCALER_CTL0_SCL_H_NONE_V_TPZ;
 392         case VC4_SCALING_TPZ << 2 | VC4_SCALING_NONE:
 393                 return SCALER_CTL0_SCL_H_TPZ_V_NONE;
 394         default:
 395         case VC4_SCALING_NONE << 2 | VC4_SCALING_NONE:
 396                 /* The unity case is independently handled by
 397                  * SCALER_CTL0_UNITY.
 398                  */
 399                 return 0;
 400         }
 401 }
 402
 403 static int vc4_plane_margins_adj(struct drm_plane_state *pstate)
 404 {
 405         struct vc4_plane_state *vc4_pstate = to_vc4_plane_state(pstate);
 406         unsigned int left, right, top, bottom, adjhdisplay, adjvdisplay;
 407         struct drm_crtc_state *crtc_state;
 408
 409         crtc_state = drm_atomic_get_new_crtc_state(pstate->state,
 410                                                    pstate->crtc);
 411
 412         vc4_crtc_get_margins(crtc_state, &left, &right, &top, &bottom);
 413         if (!left && !right && !top && !bottom)
 414                 return 0;
 415
 416         if (left + right >= crtc_state->mode.hdisplay ||
 417             top + bottom >= crtc_state->mode.vdisplay)
 418                 return -EINVAL;
 419
 420         adjhdisplay = crtc_state->mode.hdisplay - (left + right);
 421         vc4_pstate->crtc_x = DIV_ROUND_CLOSEST(vc4_pstate->crtc_x *
 422                                                adjhdisplay,
 423                                                crtc_state->mode.hdisplay);
 424         vc4_pstate->crtc_x += left;
 425         if (vc4_pstate->crtc_x > crtc_state->mode.hdisplay - right)
 426                 vc4_pstate->crtc_x = crtc_state->mode.hdisplay - right;
 427
 428         adjvdisplay = crtc_state->mode.vdisplay - (top + bottom);
 429         vc4_pstate->crtc_y = DIV_ROUND_CLOSEST(vc4_pstate->crtc_y *
 430                                                adjvdisplay,
 431                                                crtc_state->mode.vdisplay);
 432         vc4_pstate->crtc_y += top;
 433         if (vc4_pstate->crtc_y > crtc_state->mode.vdisplay - bottom)
 434                 vc4_pstate->crtc_y = crtc_state->mode.vdisplay - bottom;
 435
 436         vc4_pstate->crtc_w = DIV_ROUND_CLOSEST(vc4_pstate->crtc_w *
 437                                                adjhdisplay,
 438                                                crtc_state->mode.hdisplay);
 439         vc4_pstate->crtc_h = DIV_ROUND_CLOSEST(vc4_pstate->crtc_h *
 440                                                adjvdisplay,
 441                                                crtc_state->mode.vdisplay);
 442
 443         if (!vc4_pstate->crtc_w || !vc4_pstate->crtc_h)
 444                 return -EINVAL;
 445
 446         return 0;
 447 }
 448
 449 static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
 450 {
 451         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 452         struct drm_framebuffer *fb = state->fb;
 453         int num_planes = fb->format->num_planes;
 454         struct drm_crtc_state *crtc_state;
 455         u32 h_subsample = fb->format->hsub;
 456         u32 v_subsample = fb->format->vsub;
 457         int ret;
 458
 459         crtc_state = drm_atomic_get_existing_crtc_state(state->state,
 460                                                         state->crtc);
 461         if (!crtc_state) {
 462                 DRM_DEBUG_KMS("Invalid crtc state\n");
 463                 return -EINVAL;
 464         }
 465
 466         ret = drm_atomic_helper_check_plane_state(state, crtc_state, 1,
 467                                                   INT_MAX, true, true);
 468         if (ret)
 469                 return ret;
 470
 471         vc4_state->src_x = state->src.x1;
 472         vc4_state->src_y = state->src.y1;
 473         vc4_state->src_w[0] = state->src.x2 - vc4_state->src_x;
 474         vc4_state->src_h[0] = state->src.y2 - vc4_state->src_y;
 475
 476         vc4_state->crtc_x = state->dst.x1;
 477         vc4_state->crtc_y = state->dst.y1;
 478         vc4_state->crtc_w = state->dst.x2 - state->dst.x1;
 479         vc4_state->crtc_h = state->dst.y2 - state->dst.y1;
 480
 481         if (!vc4_state->crtc_w)
 482                 vc4_state->crtc_w = state->crtc->mode.hdisplay;
 483         if (!vc4_state->crtc_h)
 484                 vc4_state->crtc_h = state->crtc->mode.vdisplay;
 485
 486         ret = vc4_plane_margins_adj(state);
 487         if (ret)
 488                 return ret;
 489
 490         vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0],
 491                                                        vc4_state->crtc_w);
 492         vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0],
 493                                                        vc4_state->crtc_h);
 494
 495         vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE &&
 496                                vc4_state->y_scaling[0] == VC4_SCALING_NONE);
 497
 498         if (num_planes > 1) {
 499                 vc4_state->is_yuv = true;
 500
 501                 vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample;
 502                 vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample;
 503
 504                 vc4_state->x_scaling[1] =
 505                         vc4_get_scaling_mode(vc4_state->src_w[1],
 506                                              vc4_state->crtc_w);
 507                 vc4_state->y_scaling[1] =
 508                         vc4_get_scaling_mode(vc4_state->src_h[1],
 509                                              vc4_state->crtc_h);
 510
 511                 /* YUV conversion requires that horizontal scaling be enabled
 512                  * on the UV plane even if vc4_get_scaling_mode() returned
 513                  * VC4_SCALING_NONE (which can happen when the down-scaling
 514                  * ratio is 0.5). Let's force it to VC4_SCALING_PPF in this
 515                  * case.
 516                  */
 517                 if (vc4_state->x_scaling[1] == VC4_SCALING_NONE)
 518                         vc4_state->x_scaling[1] = VC4_SCALING_PPF;
 519
 520                 /* Similarly UV needs vertical scaling to be enabled.
 521                  * Without this a 1:1 scaled YUV422 plane isn't rendered.
 522                  */
 523                 if (vc4_state->y_scaling[1] == VC4_SCALING_NONE)
 524                         vc4_state->y_scaling[1] = VC4_SCALING_PPF;
 525         } else {
 526                 vc4_state->is_yuv = false;
 527                 vc4_state->x_scaling[1] = VC4_SCALING_NONE;
 528                 vc4_state->y_scaling[1] = VC4_SCALING_NONE;
 529         }
 530
 531         return 0;
 532 }
 533
 534 static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
 535 {
 536         u32 scale, recip;
 537
 538         scale = src / dst;
 539
 540         /* The specs note that while the reciprocal would be defined
 541          * as (1<<32)/scale, ~0 is close enough.
 542          */
 543         recip = ~0 / scale;
 544
 545         vc4_dlist_write(vc4_state,
 546                         VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) |
 547                         VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE));
 548         vc4_dlist_write(vc4_state,
 549                         VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP));
 550 }
 551
 552 /* phase magnitude bits */
 553 #define PHASE_BITS 6
 554
 555 static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst, u32 xy, int channel, int chroma_offset)
 556 {
 557         u32 scale = src / dst;
 558         s32 offset, offset2;
 559         s32 phase;
 560
 561         /* Start the phase at 1/2 pixel from the 1st pixel at src_x.
 562            1/4 pixel for YUV, plus the offset for chroma siting */
 563         if (channel) {
 564                 /* the phase is relative to scale_src->x, so shift it for display list's x value */
 565                 offset = (xy & 0x1ffff) >> (16 - PHASE_BITS) >> 1;
 566                 offset -= chroma_offset >> (17 - PHASE_BITS);
 567                 offset += -(1 << PHASE_BITS >> 2);
 568         } else {
 569                 /* the phase is relative to scale_src->x, so shift it for display list's x value */
 570                 offset = (xy & 0xffff) >> (16 - PHASE_BITS);
 571                 offset += -(1 << PHASE_BITS >> 1);
 572
 573                 /* This is a kludge to make sure the scaling factors are consitent with YUV's luma scaling.
 574                    we lose 1bit precision because of this. */
 575                 scale &= ~1;
 576         }
 577
 578         /* There may be a also small error introduced by precision of scale.
 579            Add half of that as a compromise */
 580         offset2 = src - dst * scale;
 581         offset2 >>= 16 - PHASE_BITS;
 582         phase = offset + (offset2 >> 1);
 583
 584         /* Ensure +ve values don't touch the sign bit, then truncate negative values */
 585         if (phase >= 1 << PHASE_BITS)
 586                 phase = (1 << PHASE_BITS) - 1;
 587
 588         phase &= SCALER_PPF_IPHASE_MASK;
 589
 590         vc4_dlist_write(vc4_state,
 591                         SCALER_PPF_AGC |
 592                         VC4_SET_FIELD(scale, SCALER_PPF_SCALE) |
 593                         VC4_SET_FIELD(phase, SCALER_PPF_IPHASE));
 594 }
 595
 596 static u32 vc4_lbm_size(struct drm_plane_state *state)
 597 {
 598         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 599         struct vc4_dev *vc4 = to_vc4_dev(state->plane->dev);
 600         u32 pix_per_line;
 601         u32 lbm;
 602
 603         /* LBM is not needed when there's no vertical scaling. */
 604         if (vc4_state->y_scaling[0] == VC4_SCALING_NONE &&
 605             vc4_state->y_scaling[1] == VC4_SCALING_NONE)
 606                 return 0;
 607
 608         /*
 609          * This can be further optimized in the RGB/YUV444 case if the PPF
 610          * decimation factor is between 0.5 and 1.0 by using crtc_w.
 611          *
 612          * It's not an issue though, since in that case since src_w[0] is going
 613          * to be greater than or equal to crtc_w.
 614          */
 615         if (vc4_state->x_scaling[0] == VC4_SCALING_TPZ)
 616                 pix_per_line = vc4_state->crtc_w;
 617         else
 618                 pix_per_line = vc4_state->src_w[0] >> 16;
 619
 620         if (!vc4_state->is_yuv) {
 621                 if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ)
 622                         lbm = pix_per_line * 8;
 623                 else {
 624                         /* In special cases, this multiplier might be 12. */
 625                         lbm = pix_per_line * 16;
 626                 }
 627         } else {
 628                 /* There are cases for this going down to a multiplier
 629                  * of 2, but according to the firmware source, the
 630                  * table in the docs is somewhat wrong.
 631                  */
 632                 lbm = pix_per_line * 16;
 633         }
 634
 635         /* Align it to 64 or 128 (hvs5) bytes */
 636         lbm = roundup(lbm, vc4->gen == VC4_GEN_5 ? 128 : 64);
 637
 638         /* Each "word" of the LBM memory contains 2 or 4 (hvs5) pixels */
 639         lbm /= vc4->gen == VC4_GEN_5 ? 4 : 2;
 640
 641         return lbm;
 642 }
 643
 644 static void vc4_write_scaling_parameters(struct drm_plane_state *state,
 645                                          int channel)
 646 {
 647         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 648
 649         /* Ch0 H-PPF Word 0: Scaling Parameters */
 650         if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
 651                 vc4_write_ppf(vc4_state,
 652                               vc4_state->src_w[channel], vc4_state->crtc_w, vc4_state->src_x, channel,
 653                               state->chroma_siting_h);
 654         }
 655
 656         /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */
 657         if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) {
 658                 vc4_write_ppf(vc4_state,
 659                               vc4_state->src_h[channel], vc4_state->crtc_h, vc4_state->src_y, channel,
 660                               state->chroma_siting_v);
 661                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 662         }
 663
 664         /* Ch0 H-TPZ Words 0-1: Scaling Parameters, Recip */
 665         if (vc4_state->x_scaling[channel] == VC4_SCALING_TPZ) {
 666                 vc4_write_tpz(vc4_state,
 667                               vc4_state->src_w[channel], vc4_state->crtc_w);
 668         }
 669
 670         /* Ch0 V-TPZ Words 0-2: Scaling Parameters, Recip, Context */
 671         if (vc4_state->y_scaling[channel] == VC4_SCALING_TPZ) {
 672                 vc4_write_tpz(vc4_state,
 673                               vc4_state->src_h[channel], vc4_state->crtc_h);
 674                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 675         }
 676 }
 677
 678 static void vc4_plane_calc_load(struct drm_plane_state *state)
 679 {
 680         unsigned int hvs_load_shift, vrefresh, i;
 681         struct drm_framebuffer *fb = state->fb;
 682         struct vc4_plane_state *vc4_state;
 683         struct drm_crtc_state *crtc_state;
 684         unsigned int vscale_factor;
 685
 686         vc4_state = to_vc4_plane_state(state);
 687         crtc_state = drm_atomic_get_existing_crtc_state(state->state,
 688                                                         state->crtc);
 689         vrefresh = drm_mode_vrefresh(&crtc_state->adjusted_mode);
 690
 691         /* The HVS is able to process 2 pixels/cycle when scaling the source,
 692          * 4 pixels/cycle otherwise.
 693          * Alpha blending step seems to be pipelined and it's always operating
 694          * at 4 pixels/cycle, so the limiting aspect here seems to be the
 695          * scaler block.
 696          * HVS load is expressed in clk-cycles/sec (AKA Hz).
 697          */
 698         if (vc4_state->x_scaling[0] != VC4_SCALING_NONE ||
 699             vc4_state->x_scaling[1] != VC4_SCALING_NONE ||
 700             vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
 701             vc4_state->y_scaling[1] != VC4_SCALING_NONE)
 702                 hvs_load_shift = 1;
 703         else
 704                 hvs_load_shift = 2;
 705
 706         vc4_state->membus_load = 0;
 707         vc4_state->hvs_load = 0;
 708         for (i = 0; i < fb->format->num_planes; i++) {
 709                 /* Even if the bandwidth/plane required for a single frame is
 710                  *
 711                  * (vc4_state->src_w[i] >> 16) * (vc4_state->src_h[i] >> 16) *
 712                  *  cpp * vrefresh
 713                  *
 714                  * when downscaling, we have to read more pixels per line in
 715                  * the time frame reserved for a single line, so the bandwidth
 716                  * demand can be punctually higher. To account for that, we
 717                  * calculate the down-scaling factor and multiply the plane
 718                  * load by this number. We're likely over-estimating the read
 719                  * demand, but that's better than under-estimating it.
 720                  */
 721                 vscale_factor = DIV_ROUND_UP(vc4_state->src_h[i] >> 16,
 722                                              vc4_state->crtc_h);
 723                 vc4_state->membus_load += (vc4_state->src_w[i] >> 16) *
 724                                           (vc4_state->src_h[i] >> 16) *
 725                                           vscale_factor * fb->format->cpp[i];
 726                 vc4_state->hvs_load += vc4_state->crtc_h * vc4_state->crtc_w;
 727         }
 728
 729         vc4_state->hvs_load *= vrefresh;
 730         vc4_state->hvs_load >>= hvs_load_shift;
 731         vc4_state->membus_load *= vrefresh;
 732 }
 733
 734 static int vc4_plane_allocate_lbm(struct drm_plane_state *state)
 735 {
 736         struct drm_device *drm = state->plane->dev;
 737         struct vc4_dev *vc4 = to_vc4_dev(drm);
 738         struct drm_plane *plane = state->plane;
 739         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 740         unsigned long irqflags;
 741         u32 lbm_size;
 742
 743         lbm_size = vc4_lbm_size(state);
 744         if (!lbm_size)
 745                 return 0;
 746
 747         if (vc4->gen == VC4_GEN_5)
 748                 lbm_size = ALIGN(lbm_size, 64);
 749         else if (vc4->gen == VC4_GEN_4)
 750                 lbm_size = ALIGN(lbm_size, 32);
 751
 752         drm_dbg_driver(drm, "[PLANE:%d:%s] LBM Allocation Size: %u\n",
 753                        plane->base.id, plane->name, lbm_size);
 754
 755         if (WARN_ON(!vc4_state->lbm_offset))
 756                 return -EINVAL;
 757
 758         /* Allocate the LBM memory that the HVS will use for temporary
 759          * storage due to our scaling/format conversion.
 760          */
 761         if (!drm_mm_node_allocated(&vc4_state->lbm)) {
 762                 int ret;
 763
 764                 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
 765                 ret = drm_mm_insert_node_generic(&vc4->hvs->lbm_mm,
 766                                                  &vc4_state->lbm,
 767                                                  lbm_size, 1,
 768                                                  0, 0);
 769                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
 770
 771                 if (ret) {
 772                         drm_err(drm, "Failed to allocate LBM entry: %d\n", ret);
 773                         return ret;
 774                 }
 775         } else {
 776                 WARN_ON_ONCE(lbm_size != vc4_state->lbm.size);
 777         }
 778
 779         vc4_state->dlist[vc4_state->lbm_offset] = vc4_state->lbm.start;
 780
 781         return 0;
 782 }
 783
 784 /*
 785  * The colorspace conversion matrices are held in 3 entries in the dlist.
 786  * Create an array of them, with entries for each full and limited mode, and
 787  * each supported colorspace.
 788  */
 789 static const u32 colorspace_coeffs[2][DRM_COLOR_ENCODING_MAX][3] = {
 790         {
 791                 /* Limited range */
 792                 {
 793                         /* BT601 */
 794                         SCALER_CSC0_ITR_R_601_5,
 795                         SCALER_CSC1_ITR_R_601_5,
 796                         SCALER_CSC2_ITR_R_601_5,
 797                 }, {
 798                         /* BT709 */
 799                         SCALER_CSC0_ITR_R_709_3,
 800                         SCALER_CSC1_ITR_R_709_3,
 801                         SCALER_CSC2_ITR_R_709_3,
 802                 }, {
 803                         /* BT2020 */
 804                         SCALER_CSC0_ITR_R_2020,
 805                         SCALER_CSC1_ITR_R_2020,
 806                         SCALER_CSC2_ITR_R_2020,
 807                 }
 808         }, {
 809                 /* Full range */
 810                 {
 811                         /* JFIF */
 812                         SCALER_CSC0_JPEG_JFIF,
 813                         SCALER_CSC1_JPEG_JFIF,
 814                         SCALER_CSC2_JPEG_JFIF,
 815                 }, {
 816                         /* BT709 */
 817                         SCALER_CSC0_ITR_R_709_3_FR,
 818                         SCALER_CSC1_ITR_R_709_3_FR,
 819                         SCALER_CSC2_ITR_R_709_3_FR,
 820                 }, {
 821                         /* BT2020 */
 822                         SCALER_CSC0_ITR_R_2020_FR,
 823                         SCALER_CSC1_ITR_R_2020_FR,
 824                         SCALER_CSC2_ITR_R_2020_FR,
 825                 }
 826         }
 827 };
 828
 829 static u32 vc4_hvs4_get_alpha_blend_mode(struct drm_plane_state *state)
 830 {
 831         if (!state->fb->format->has_alpha)
 832                 return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_FIXED,
 833                                      SCALER_POS2_ALPHA_MODE);
 834
 835         switch (state->pixel_blend_mode) {
 836         case DRM_MODE_BLEND_PIXEL_NONE:
 837                 return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_FIXED,
 838                                      SCALER_POS2_ALPHA_MODE);
 839         default:
 840         case DRM_MODE_BLEND_PREMULTI:
 841                 return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_PIPELINE,
 842                                      SCALER_POS2_ALPHA_MODE) |
 843                         SCALER_POS2_ALPHA_PREMULT;
 844         case DRM_MODE_BLEND_COVERAGE:
 845                 return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_PIPELINE,
 846                                      SCALER_POS2_ALPHA_MODE);
 847         }
 848 }
 849
 850 static u32 vc4_hvs5_get_alpha_blend_mode(struct drm_plane_state *state)
 851 {
 852         if (!state->fb->format->has_alpha)
 853                 return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_FIXED,
 854                                      SCALER5_CTL2_ALPHA_MODE);
 855
 856         switch (state->pixel_blend_mode) {
 857         case DRM_MODE_BLEND_PIXEL_NONE:
 858                 return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_FIXED,
 859                                      SCALER5_CTL2_ALPHA_MODE);
 860         default:
 861         case DRM_MODE_BLEND_PREMULTI:
 862                 return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_PIPELINE,
 863                                      SCALER5_CTL2_ALPHA_MODE) |
 864                         SCALER5_CTL2_ALPHA_PREMULT;
 865         case DRM_MODE_BLEND_COVERAGE:
 866                 return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_PIPELINE,
 867                                      SCALER5_CTL2_ALPHA_MODE);
 868         }
 869 }
 870
 871 /* Writes out a full display list for an active plane to the plane's
 872  * private dlist state.
 873  */
 874 static int vc4_plane_mode_set(struct drm_plane *plane,
 875                               struct drm_plane_state *state)
 876 {
 877         struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
 878         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 879         struct drm_framebuffer *fb = state->fb;
 880         u32 ctl0_offset = vc4_state->dlist_count;
 881         const struct hvs_format *format = vc4_get_hvs_format(fb->format->format);
 882         u64 base_format_mod = fourcc_mod_broadcom_mod(fb->modifier);
 883         int num_planes = fb->format->num_planes;
 884         u32 h_subsample = fb->format->hsub;
 885         u32 v_subsample = fb->format->vsub;
 886         bool mix_plane_alpha;
 887         bool covers_screen;
 888         u32 scl0, scl1, pitch0;
 889         u32 tiling, src_x, src_y;
 890         u32 width, height;
 891         u32 hvs_format = format->hvs;
 892         unsigned int rotation;
 893         u32 offsets[3] = { 0 };
 894         int ret, i;
 895
 896         if (vc4_state->dlist_initialized)
 897                 return 0;
 898
 899         ret = vc4_plane_setup_clipping_and_scaling(state);
 900         if (ret)
 901                 return ret;
 902
 903         width = vc4_state->src_w[0] >> 16;
 904         height = vc4_state->src_h[0] >> 16;
 905
 906         /* SCL1 is used for Cb/Cr scaling of planar formats.  For RGB
 907          * and 4:4:4, scl1 should be set to scl0 so both channels of
 908          * the scaler do the same thing.  For YUV, the Y plane needs
 909          * to be put in channel 1 and Cb/Cr in channel 0, so we swap
 910          * the scl fields here.
 911          */
 912         if (num_planes == 1) {
 913                 scl0 = vc4_get_scl_field(state, 0);
 914                 scl1 = scl0;
 915         } else {
 916                 scl0 = vc4_get_scl_field(state, 1);
 917                 scl1 = vc4_get_scl_field(state, 0);
 918         }
 919
 920         rotation = drm_rotation_simplify(state->rotation,
 921                                          DRM_MODE_ROTATE_0 |
 922                                          DRM_MODE_REFLECT_X |
 923                                          DRM_MODE_REFLECT_Y);
 924
 925         /* We must point to the last line when Y reflection is enabled. */
 926         src_y = vc4_state->src_y >> 16;
 927         if (rotation & DRM_MODE_REFLECT_Y)
 928                 src_y += height - 1;
 929
 930         src_x = vc4_state->src_x >> 16;
 931
 932         switch (base_format_mod) {
 933         case DRM_FORMAT_MOD_LINEAR:
 934                 tiling = SCALER_CTL0_TILING_LINEAR;
 935                 pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
 936
 937                 /* Adjust the base pointer to the first pixel to be scanned
 938                  * out.
 939                  */
 940                 for (i = 0; i < num_planes; i++) {
 941                         offsets[i] += src_y / (i ? v_subsample : 1) * fb->pitches[i];
 942                         offsets[i] += src_x / (i ? h_subsample : 1) * fb->format->cpp[i];
 943                 }
 944
 945                 break;
 946
 947         case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
 948                 u32 tile_size_shift = 12; /* T tiles are 4kb */
 949                 /* Whole-tile offsets, mostly for setting the pitch. */
 950                 u32 tile_w_shift = fb->format->cpp[0] == 2 ? 6 : 5;
 951                 u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */
 952                 u32 tile_w_mask = (1 << tile_w_shift) - 1;
 953                 /* The height mask on 32-bit-per-pixel tiles is 63, i.e. twice
 954                  * the height (in pixels) of a 4k tile.
 955                  */
 956                 u32 tile_h_mask = (2 << tile_h_shift) - 1;
 957                 /* For T-tiled, the FB pitch is "how many bytes from one row to
 958                  * the next, such that
 959                  *
 960                  *      pitch * tile_h == tile_size * tiles_per_row
 961                  */
 962                 u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
 963                 u32 tiles_l = src_x >> tile_w_shift;
 964                 u32 tiles_r = tiles_w - tiles_l;
 965                 u32 tiles_t = src_y >> tile_h_shift;
 966                 /* Intra-tile offsets, which modify the base address (the
 967                  * SCALER_PITCH0_TILE_Y_OFFSET tells HVS how to walk from that
 968                  * base address).
 969                  */
 970                 u32 tile_y = (src_y >> 4) & 1;
 971                 u32 subtile_y = (src_y >> 2) & 3;
 972                 u32 utile_y = src_y & 3;
 973                 u32 x_off = src_x & tile_w_mask;
 974                 u32 y_off = src_y & tile_h_mask;
 975
 976                 /* When Y reflection is requested we must set the
 977                  * SCALER_PITCH0_TILE_LINE_DIR flag to tell HVS that all lines
 978                  * after the initial one should be fetched in descending order,
 979                  * which makes sense since we start from the last line and go
 980                  * backward.
 981                  * Don't know why we need y_off = max_y_off - y_off, but it's
 982                  * definitely required (I guess it's also related to the "going
 983                  * backward" situation).
 984                  */
 985                 if (rotation & DRM_MODE_REFLECT_Y) {
 986                         y_off = tile_h_mask - y_off;
 987                         pitch0 = SCALER_PITCH0_TILE_LINE_DIR;
 988                 } else {
 989                         pitch0 = 0;
 990                 }
 991
 992                 tiling = SCALER_CTL0_TILING_256B_OR_T;
 993                 pitch0 |= (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) |
 994                            VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) |
 995                            VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) |
 996                            VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R));
 997                 offsets[0] += tiles_t * (tiles_w << tile_size_shift);
 998                 offsets[0] += subtile_y << 8;
 999                 offsets[0] += utile_y << 4;
1000
1001                 /* Rows of tiles alternate left-to-right and right-to-left. */
1002                 if (tiles_t & 1) {
1003                         pitch0 |= SCALER_PITCH0_TILE_INITIAL_LINE_DIR;
1004                         offsets[0] += (tiles_w - tiles_l) << tile_size_shift;
1005                         offsets[0] -= (1 + !tile_y) << 10;
1006                 } else {
1007                         offsets[0] += tiles_l << tile_size_shift;
1008                         offsets[0] += tile_y << 10;
1009                 }
1010
1011                 break;
1012         }
1013
1014         case DRM_FORMAT_MOD_BROADCOM_SAND64:
1015         case DRM_FORMAT_MOD_BROADCOM_SAND128:
1016         case DRM_FORMAT_MOD_BROADCOM_SAND256: {
1017                 uint32_t param = fourcc_mod_broadcom_param(fb->modifier);
1018
1019                 if (param > SCALER_TILE_HEIGHT_MASK) {
1020                         DRM_DEBUG_KMS("SAND height too large (%d)\n",
1021                                       param);
1022                         return -EINVAL;
1023                 }
1024
1025                 if (fb->format->format == DRM_FORMAT_P030) {
1026                         hvs_format = HVS_PIXEL_FORMAT_YCBCR_10BIT;
1027                         tiling = SCALER_CTL0_TILING_128B;
1028                 } else {
1029                         hvs_format = HVS_PIXEL_FORMAT_H264;
1030
1031                         switch (base_format_mod) {
1032                         case DRM_FORMAT_MOD_BROADCOM_SAND64:
1033                                 tiling = SCALER_CTL0_TILING_64B;
1034                                 break;
1035                         case DRM_FORMAT_MOD_BROADCOM_SAND128:
1036                                 tiling = SCALER_CTL0_TILING_128B;
1037                                 break;
1038                         case DRM_FORMAT_MOD_BROADCOM_SAND256:
1039                                 tiling = SCALER_CTL0_TILING_256B_OR_T;
1040                                 break;
1041                         default:
1042                                 return -EINVAL;
1043                         }
1044                 }
1045
1046                 /* Adjust the base pointer to the first pixel to be scanned
1047                  * out.
1048                  *
1049                  * For P030, y_ptr [31:4] is the 128bit word for the start pixel
1050                  * y_ptr [3:0] is the pixel (0-11) contained within that 128bit
1051                  * word that should be taken as the first pixel.
1052                  * Ditto uv_ptr [31:4] vs [3:0], however [3:0] contains the
1053                  * element within the 128bit word, eg for pixel 3 the value
1054                  * should be 6.
1055                  */
1056                 for (i = 0; i < num_planes; i++) {
1057                         u32 tile_w, tile, x_off, pix_per_tile;
1058
1059                         if (fb->format->format == DRM_FORMAT_P030) {
1060                                 /*
1061                                  * Spec says: bits [31:4] of the given address
1062                                  * should point to the 128-bit word containing
1063                                  * the desired starting pixel, and bits[3:0]
1064                                  * should be between 0 and 11, indicating which
1065                                  * of the 12-pixels in that 128-bit word is the
1066                                  * first pixel to be used
1067                                  */
1068                                 u32 remaining_pixels = src_x % 96;
1069                                 u32 aligned = remaining_pixels / 12;
1070                                 u32 last_bits = remaining_pixels % 12;
1071
1072                                 x_off = aligned * 16 + last_bits;
1073                                 tile_w = 128;
1074                                 pix_per_tile = 96;
1075                         } else {
1076                                 switch (base_format_mod) {
1077                                 case DRM_FORMAT_MOD_BROADCOM_SAND64:
1078                                         tile_w = 64;
1079                                         break;
1080                                 case DRM_FORMAT_MOD_BROADCOM_SAND128:
1081                                         tile_w = 128;
1082                                         break;
1083                                 case DRM_FORMAT_MOD_BROADCOM_SAND256:
1084                                         tile_w = 256;
1085                                         break;
1086                                 default:
1087                                         return -EINVAL;
1088                                 }
1089                                 pix_per_tile = tile_w / fb->format->cpp[0];
1090                                 x_off = (src_x % pix_per_tile) /
1091                                         (i ? h_subsample : 1) *
1092                                         fb->format->cpp[i];
1093                         }
1094
1095                         tile = src_x / pix_per_tile;
1096
1097                         offsets[i] += param * tile_w * tile;
1098                         offsets[i] += src_y / (i ? v_subsample : 1) * tile_w;
1099                         offsets[i] += x_off & ~(i ? 1 : 0);
1100                 }
1101
1102                 pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);
1103                 break;
1104         }
1105
1106         default:
1107                 DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
1108                               (long long)fb->modifier);
1109                 return -EINVAL;
1110         }
1111
1112         /* fetch an extra pixel if we don't actually line up with the left edge. */
1113         if ((vc4_state->src_x & 0xffff) && vc4_state->src_x < (state->fb->width << 16))
1114                 width++;
1115
1116         /* same for the right side */
1117         if (((vc4_state->src_x + vc4_state->src_w[0]) & 0xffff) &&
1118                vc4_state->src_x + vc4_state->src_w[0] < (state->fb->width << 16))
1119                 width++;
1120
1121         /* now for the top */
1122         if ((vc4_state->src_y & 0xffff) && vc4_state->src_y < (state->fb->height << 16))
1123                 height++;
1124
1125         /* and the bottom */
1126         if (((vc4_state->src_y + vc4_state->src_h[0]) & 0xffff) &&
1127                vc4_state->src_y + vc4_state->src_h[0] < (state->fb->height << 16))
1128                 height++;
1129
1130         /* for YUV444 hardware wants double the width, otherwise it doesn't fetch full width of chroma */
1131         if (format->drm == DRM_FORMAT_YUV444 || format->drm == DRM_FORMAT_YVU444)
1132                 width <<= 1;
1133
1134         /* Don't waste cycles mixing with plane alpha if the set alpha
1135          * is opaque or there is no per-pixel alpha information.
1136          * In any case we use the alpha property value as the fixed alpha.
1137          */
1138         mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
1139                           fb->format->has_alpha;
1140
1141         if (vc4->gen == VC4_GEN_4) {
1142         /* Control word */
1143                 vc4_dlist_write(vc4_state,
1144                                 SCALER_CTL0_VALID |
1145                                 (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
1146                                 (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
1147                                 VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
1148                                 (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
1149                                 (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
1150                                 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
1151                                 (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
1152                                 VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
1153                                 VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
1154
1155                 /* Position Word 0: Image Positions and Alpha Value */
1156                 vc4_state->pos0_offset = vc4_state->dlist_count;
1157                 vc4_dlist_write(vc4_state,
1158                                 VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
1159                                 VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
1160                                 VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
1161
1162                 /* Position Word 1: Scaled Image Dimensions. */
1163                 if (!vc4_state->is_unity) {
1164                         vc4_dlist_write(vc4_state,
1165                                         VC4_SET_FIELD(vc4_state->crtc_w,
1166                                                       SCALER_POS1_SCL_WIDTH) |
1167                                         VC4_SET_FIELD(vc4_state->crtc_h,
1168                                                       SCALER_POS1_SCL_HEIGHT));
1169                 }
1170
1171                 /* Position Word 2: Source Image Size, Alpha */
1172                 vc4_state->pos2_offset = vc4_state->dlist_count;
1173                 vc4_dlist_write(vc4_state,
1174                                 (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
1175                                 vc4_hvs4_get_alpha_blend_mode(state) |
1176                                 VC4_SET_FIELD(width, SCALER_POS2_WIDTH) |
1177                                 VC4_SET_FIELD(height, SCALER_POS2_HEIGHT));
1178
1179                 /* Position Word 3: Context.  Written by the HVS. */
1180                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
1181
1182         } else {
1183                 /* Control word */
1184                 vc4_dlist_write(vc4_state,
1185                                 SCALER_CTL0_VALID |
1186                                 (format->pixel_order_hvs5 << SCALER_CTL0_ORDER_SHIFT) |
1187                                 (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
1188                                 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
1189                                 (vc4_state->is_unity ?
1190                                                 SCALER5_CTL0_UNITY : 0) |
1191                                 VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
1192                                 VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1) |
1193                                 SCALER5_CTL0_ALPHA_EXPAND |
1194                                 SCALER5_CTL0_RGB_EXPAND);
1195
1196                 /* Position Word 0: Image Positions and Alpha Value */
1197                 vc4_state->pos0_offset = vc4_state->dlist_count;
1198                 vc4_dlist_write(vc4_state,
1199                                 (rotation & DRM_MODE_REFLECT_Y ?
1200                                                 SCALER5_POS0_VFLIP : 0) |
1201                                 VC4_SET_FIELD(vc4_state->crtc_x,
1202                                               SCALER_POS0_START_X) |
1203                                 (rotation & DRM_MODE_REFLECT_X ?
1204                                               SCALER5_POS0_HFLIP : 0) |
1205                                 VC4_SET_FIELD(vc4_state->crtc_y,
1206                                               SCALER5_POS0_START_Y)
1207                                );
1208
1209                 /* Control Word 2 */
1210                 vc4_dlist_write(vc4_state,
1211                                 VC4_SET_FIELD(state->alpha >> 4,
1212                                               SCALER5_CTL2_ALPHA) |
1213                                 vc4_hvs5_get_alpha_blend_mode(state) |
1214                                 (mix_plane_alpha ?
1215                                         SCALER5_CTL2_ALPHA_MIX : 0)
1216                                );
1217
1218                 /* Position Word 1: Scaled Image Dimensions. */
1219                 if (!vc4_state->is_unity) {
1220                         vc4_dlist_write(vc4_state,
1221                                         VC4_SET_FIELD(vc4_state->crtc_w,
1222                                                       SCALER5_POS1_SCL_WIDTH) |
1223                                         VC4_SET_FIELD(vc4_state->crtc_h,
1224                                                       SCALER5_POS1_SCL_HEIGHT));
1225                 }
1226
1227                 /* Position Word 2: Source Image Size */
1228                 vc4_state->pos2_offset = vc4_state->dlist_count;
1229                 vc4_dlist_write(vc4_state,
1230                                 VC4_SET_FIELD(width, SCALER5_POS2_WIDTH) |
1231                                 VC4_SET_FIELD(height, SCALER5_POS2_HEIGHT));
1232
1233                 /* Position Word 3: Context.  Written by the HVS. */
1234                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
1235         }
1236
1237
1238         /* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
1239          *
1240          * The pointers may be any byte address.
1241          */
1242         vc4_state->ptr0_offset[0] = vc4_state->dlist_count;
1243
1244         for (i = 0; i < num_planes; i++) {
1245                 dma_addr_t paddr = drm_fb_dma_get_gem_addr(fb, state, i);
1246
1247                 vc4_dlist_write(vc4_state, paddr + offsets[i]);
1248         }
1249
1250         /* Pointer Context Word 0/1/2: Written by the HVS */
1251         for (i = 0; i < num_planes; i++)
1252                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
1253
1254         /* Pitch word 0 */
1255         vc4_dlist_write(vc4_state, pitch0);
1256
1257         /* Pitch word 1/2 */
1258         for (i = 1; i < num_planes; i++) {
1259                 if (hvs_format != HVS_PIXEL_FORMAT_H264 &&
1260                     hvs_format != HVS_PIXEL_FORMAT_YCBCR_10BIT) {
1261                         vc4_dlist_write(vc4_state,
1262                                         VC4_SET_FIELD(fb->pitches[i],
1263                                                       SCALER_SRC_PITCH));
1264                 } else {
1265                         vc4_dlist_write(vc4_state, pitch0);
1266                 }
1267         }
1268
1269         /* Colorspace conversion words */
1270         if (vc4_state->is_yuv) {
1271                 enum drm_color_encoding color_encoding = state->color_encoding;
1272                 enum drm_color_range color_range = state->color_range;
1273                 const u32 *ccm;
1274
1275                 if (color_encoding >= DRM_COLOR_ENCODING_MAX)
1276                         color_encoding = DRM_COLOR_YCBCR_BT601;
1277                 if (color_range >= DRM_COLOR_RANGE_MAX)
1278                         color_range = DRM_COLOR_YCBCR_LIMITED_RANGE;
1279
1280                 ccm = colorspace_coeffs[color_range][color_encoding];
1281
1282                 vc4_dlist_write(vc4_state, ccm[0]);
1283                 vc4_dlist_write(vc4_state, ccm[1]);
1284                 vc4_dlist_write(vc4_state, ccm[2]);
1285         }
1286
1287         vc4_state->lbm_offset = 0;
1288
1289         if (vc4_state->x_scaling[0] != VC4_SCALING_NONE ||
1290             vc4_state->x_scaling[1] != VC4_SCALING_NONE ||
1291             vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
1292             vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
1293                 /* Reserve a slot for the LBM Base Address. The real value will
1294                  * be set when calling vc4_plane_allocate_lbm().
1295                  */
1296                 if (vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
1297                     vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
1298                         vc4_state->lbm_offset = vc4_state->dlist_count;
1299                         vc4_dlist_counter_increment(vc4_state);
1300                 }
1301
1302                 if (num_planes > 1) {
1303                         /* Emit Cb/Cr as channel 0 and Y as channel
1304                          * 1. This matches how we set up scl0/scl1
1305                          * above.
1306                          */
1307                         vc4_write_scaling_parameters(state, 1);
1308                 }
1309                 vc4_write_scaling_parameters(state, 0);
1310
1311                 /* If any PPF setup was done, then all the kernel
1312                  * pointers get uploaded.
1313                  */
1314                 if (vc4_state->x_scaling[0] == VC4_SCALING_PPF ||
1315                     vc4_state->y_scaling[0] == VC4_SCALING_PPF ||
1316                     vc4_state->x_scaling[1] == VC4_SCALING_PPF ||
1317                     vc4_state->y_scaling[1] == VC4_SCALING_PPF) {
1318                         u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start,
1319                                                    SCALER_PPF_KERNEL_OFFSET);
1320
1321                         /* HPPF plane 0 */
1322                         vc4_dlist_write(vc4_state, kernel);
1323                         /* VPPF plane 0 */
1324                         vc4_dlist_write(vc4_state, kernel);
1325                         /* HPPF plane 1 */
1326                         vc4_dlist_write(vc4_state, kernel);
1327                         /* VPPF plane 1 */
1328                         vc4_dlist_write(vc4_state, kernel);
1329                 }
1330         }
1331
1332         vc4_state->dlist[ctl0_offset] |=
1333                 VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
1334
1335         /* crtc_* are already clipped coordinates. */
1336         covers_screen = vc4_state->crtc_x == 0 && vc4_state->crtc_y == 0 &&
1337                         vc4_state->crtc_w == state->crtc->mode.hdisplay &&
1338                         vc4_state->crtc_h == state->crtc->mode.vdisplay;
1339         /* Background fill might be necessary when the plane has per-pixel
1340          * alpha content or a non-opaque plane alpha and could blend from the
1341          * background or does not cover the entire screen.
1342          */
1343         vc4_state->needs_bg_fill = fb->format->has_alpha || !covers_screen ||
1344                                    state->alpha != DRM_BLEND_ALPHA_OPAQUE;
1345
1346         /* Flag the dlist as initialized to avoid checking it twice in case
1347          * the async update check already called vc4_plane_mode_set() and
1348          * decided to fallback to sync update because async update was not
1349          * possible.
1350          */
1351         vc4_state->dlist_initialized = 1;
1352
1353         vc4_plane_calc_load(state);
1354
1355         return 0;
1356 }
1357
1358 /* If a modeset involves changing the setup of a plane, the atomic
1359  * infrastructure will call this to validate a proposed plane setup.
1360  * However, if a plane isn't getting updated, this (and the
1361  * corresponding vc4_plane_atomic_update) won't get called.  Thus, we
1362  * compute the dlist here and have all active plane dlists get updated
1363  * in the CRTC's flush.
1364  */
1365 static int vc4_plane_atomic_check(struct drm_plane *plane,
1366                                   struct drm_atomic_state *state)
1367 {
1368         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
1369                                                                                  plane);
1370         struct vc4_plane_state *vc4_state = to_vc4_plane_state(new_plane_state);
1371         int ret;
1372
1373         vc4_state->dlist_count = 0;
1374
1375         if (!plane_enabled(new_plane_state))
1376                 return 0;
1377
1378         ret = vc4_plane_mode_set(plane, new_plane_state);
1379         if (ret)
1380                 return ret;
1381
1382         ret = vc4_plane_allocate_lbm(new_plane_state);
1383         if (ret)
1384                 return ret;
1385
1386         return 0;
1387 }
1388
1389 static void vc4_plane_atomic_update(struct drm_plane *plane,
1390                                     struct drm_atomic_state *state)
1391 {
1392         /* No contents here.  Since we don't know where in the CRTC's
1393          * dlist we should be stored, our dlist is uploaded to the
1394          * hardware with vc4_plane_write_dlist() at CRTC atomic_flush
1395          * time.
1396          */
1397 }
1398
1399 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist)
1400 {
1401         struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
1402         int i;
1403         int idx;
1404
1405         if (!drm_dev_enter(plane->dev, &idx))
1406                 goto out;
1407
1408         vc4_state->hw_dlist = dlist;
1409
1410         /* Can't memcpy_toio() because it needs to be 32-bit writes. */
1411         for (i = 0; i < vc4_state->dlist_count; i++)
1412                 writel(vc4_state->dlist[i], &dlist[i]);
1413
1414         drm_dev_exit(idx);
1415
1416 out:
1417         return vc4_state->dlist_count;
1418 }
1419
1420 u32 vc4_plane_dlist_size(const struct drm_plane_state *state)
1421 {
1422         const struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
1423
1424         return vc4_state->dlist_count;
1425 }
1426
1427 /* Updates the plane to immediately (well, once the FIFO needs
1428  * refilling) scan out from at a new framebuffer.
1429  */
1430 void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb)
1431 {
1432         struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
1433         struct drm_gem_dma_object *bo = drm_fb_dma_get_gem_obj(fb, 0);
1434         uint32_t addr;
1435         int idx;
1436
1437         if (!drm_dev_enter(plane->dev, &idx))
1438                 return;
1439
1440         /* We're skipping the address adjustment for negative origin,
1441          * because this is only called on the primary plane.
1442          */
1443         WARN_ON_ONCE(plane->state->crtc_x < 0 || plane->state->crtc_y < 0);
1444         addr = bo->dma_addr + fb->offsets[0];
1445
1446         /* Write the new address into the hardware immediately.  The
1447          * scanout will start from this address as soon as the FIFO
1448          * needs to refill with pixels.
1449          */
1450         writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset[0]]);
1451
1452         /* Also update the CPU-side dlist copy, so that any later
1453          * atomic updates that don't do a new modeset on our plane
1454          * also use our updated address.
1455          */
1456         vc4_state->dlist[vc4_state->ptr0_offset[0]] = addr;
1457
1458         drm_dev_exit(idx);
1459 }
1460
1461 static void vc4_plane_atomic_async_update(struct drm_plane *plane,
1462                                           struct drm_atomic_state *state)
1463 {
1464         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
1465                                                                                  plane);
1466         struct vc4_plane_state *vc4_state, *new_vc4_state;
1467         int idx;
1468
1469         if (!drm_dev_enter(plane->dev, &idx))
1470                 return;
1471
1472         swap(plane->state->fb, new_plane_state->fb);
1473         plane->state->crtc_x = new_plane_state->crtc_x;
1474         plane->state->crtc_y = new_plane_state->crtc_y;
1475         plane->state->crtc_w = new_plane_state->crtc_w;
1476         plane->state->crtc_h = new_plane_state->crtc_h;
1477         plane->state->src_x = new_plane_state->src_x;
1478         plane->state->src_y = new_plane_state->src_y;
1479         plane->state->src_w = new_plane_state->src_w;
1480         plane->state->src_h = new_plane_state->src_h;
1481         plane->state->alpha = new_plane_state->alpha;
1482         plane->state->pixel_blend_mode = new_plane_state->pixel_blend_mode;
1483         plane->state->rotation = new_plane_state->rotation;
1484         plane->state->zpos = new_plane_state->zpos;
1485         plane->state->normalized_zpos = new_plane_state->normalized_zpos;
1486         plane->state->color_encoding = new_plane_state->color_encoding;
1487         plane->state->color_range = new_plane_state->color_range;
1488         plane->state->src = new_plane_state->src;
1489         plane->state->dst = new_plane_state->dst;
1490         plane->state->visible = new_plane_state->visible;
1491
1492         new_vc4_state = to_vc4_plane_state(new_plane_state);
1493         vc4_state = to_vc4_plane_state(plane->state);
1494
1495         vc4_state->crtc_x = new_vc4_state->crtc_x;
1496         vc4_state->crtc_y = new_vc4_state->crtc_y;
1497         vc4_state->crtc_h = new_vc4_state->crtc_h;
1498         vc4_state->crtc_w = new_vc4_state->crtc_w;
1499         vc4_state->src_x = new_vc4_state->src_x;
1500         vc4_state->src_y = new_vc4_state->src_y;
1501         memcpy(vc4_state->src_w, new_vc4_state->src_w,
1502                sizeof(vc4_state->src_w));
1503         memcpy(vc4_state->src_h, new_vc4_state->src_h,
1504                sizeof(vc4_state->src_h));
1505         memcpy(vc4_state->x_scaling, new_vc4_state->x_scaling,
1506                sizeof(vc4_state->x_scaling));
1507         memcpy(vc4_state->y_scaling, new_vc4_state->y_scaling,
1508                sizeof(vc4_state->y_scaling));
1509         vc4_state->is_unity = new_vc4_state->is_unity;
1510         vc4_state->is_yuv = new_vc4_state->is_yuv;
1511         vc4_state->needs_bg_fill = new_vc4_state->needs_bg_fill;
1512
1513         /* Update the current vc4_state pos0, pos2 and ptr0 dlist entries. */
1514         vc4_state->dlist[vc4_state->pos0_offset] =
1515                 new_vc4_state->dlist[vc4_state->pos0_offset];
1516         vc4_state->dlist[vc4_state->pos2_offset] =
1517                 new_vc4_state->dlist[vc4_state->pos2_offset];
1518         vc4_state->dlist[vc4_state->ptr0_offset[0]] =
1519                 new_vc4_state->dlist[vc4_state->ptr0_offset[0]];
1520
1521         /* Note that we can't just call vc4_plane_write_dlist()
1522          * because that would smash the context data that the HVS is
1523          * currently using.
1524          */
1525         writel(vc4_state->dlist[vc4_state->pos0_offset],
1526                &vc4_state->hw_dlist[vc4_state->pos0_offset]);
1527         writel(vc4_state->dlist[vc4_state->pos2_offset],
1528                &vc4_state->hw_dlist[vc4_state->pos2_offset]);
1529         writel(vc4_state->dlist[vc4_state->ptr0_offset[0]],
1530                &vc4_state->hw_dlist[vc4_state->ptr0_offset[0]]);
1531
1532         drm_dev_exit(idx);
1533 }
1534
1535 static int vc4_plane_atomic_async_check(struct drm_plane *plane,
1536                                         struct drm_atomic_state *state)
1537 {
1538         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
1539                                                                                  plane);
1540         struct vc4_plane_state *old_vc4_state, *new_vc4_state;
1541         int ret;
1542         u32 i;
1543
1544         ret = vc4_plane_mode_set(plane, new_plane_state);
1545         if (ret)
1546                 return ret;
1547
1548         old_vc4_state = to_vc4_plane_state(plane->state);
1549         new_vc4_state = to_vc4_plane_state(new_plane_state);
1550
1551         if (!new_vc4_state->hw_dlist)
1552                 return -EINVAL;
1553
1554         if (old_vc4_state->dlist_count != new_vc4_state->dlist_count ||
1555             old_vc4_state->pos0_offset != new_vc4_state->pos0_offset ||
1556             old_vc4_state->pos2_offset != new_vc4_state->pos2_offset ||
1557             old_vc4_state->ptr0_offset[0] != new_vc4_state->ptr0_offset[0] ||
1558             vc4_lbm_size(plane->state) != vc4_lbm_size(new_plane_state))
1559                 return -EINVAL;
1560
1561         /* Only pos0, pos2 and ptr0 DWORDS can be updated in an async update
1562          * if anything else has changed, fallback to a sync update.
1563          */
1564         for (i = 0; i < new_vc4_state->dlist_count; i++) {
1565                 if (i == new_vc4_state->pos0_offset ||
1566                     i == new_vc4_state->pos2_offset ||
1567                     i == new_vc4_state->ptr0_offset[0] ||
1568                     (new_vc4_state->lbm_offset &&
1569                      i == new_vc4_state->lbm_offset))
1570                         continue;
1571
1572                 if (new_vc4_state->dlist[i] != old_vc4_state->dlist[i])
1573                         return -EINVAL;
1574         }
1575
1576         return 0;
1577 }
1578
1579 static int vc4_prepare_fb(struct drm_plane *plane,
1580                           struct drm_plane_state *state)
1581 {
1582         struct vc4_bo *bo;
1583
1584         if (!state->fb)
1585                 return 0;
1586
1587         bo = to_vc4_bo(&drm_fb_dma_get_gem_obj(state->fb, 0)->base);
1588
1589         drm_gem_plane_helper_prepare_fb(plane, state);
1590
1591         if (plane->state->fb == state->fb)
1592                 return 0;
1593
1594         return vc4_bo_inc_usecnt(bo);
1595 }
1596
1597 static void vc4_cleanup_fb(struct drm_plane *plane,
1598                            struct drm_plane_state *state)
1599 {
1600         struct vc4_bo *bo;
1601
1602         if (plane->state->fb == state->fb || !state->fb)
1603                 return;
1604
1605         bo = to_vc4_bo(&drm_fb_dma_get_gem_obj(state->fb, 0)->base);
1606         vc4_bo_dec_usecnt(bo);
1607 }
1608
1609 static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = {
1610         .atomic_check = vc4_plane_atomic_check,
1611         .atomic_update = vc4_plane_atomic_update,
1612         .prepare_fb = vc4_prepare_fb,
1613         .cleanup_fb = vc4_cleanup_fb,
1614         .atomic_async_check = vc4_plane_atomic_async_check,
1615         .atomic_async_update = vc4_plane_atomic_async_update,
1616 };
1617
1618 static const struct drm_plane_helper_funcs vc5_plane_helper_funcs = {
1619         .atomic_check = vc4_plane_atomic_check,
1620         .atomic_update = vc4_plane_atomic_update,
1621         .atomic_async_check = vc4_plane_atomic_async_check,
1622         .atomic_async_update = vc4_plane_atomic_async_update,
1623 };
1624
1625 static bool vc4_format_mod_supported(struct drm_plane *plane,
1626                                      uint32_t format,
1627                                      uint64_t modifier)
1628 {
1629         /* Support T_TILING for RGB formats only. */
1630         switch (format) {
1631         case DRM_FORMAT_XRGB8888:
1632         case DRM_FORMAT_ARGB8888:
1633         case DRM_FORMAT_ABGR8888:
1634         case DRM_FORMAT_XBGR8888:
1635         case DRM_FORMAT_RGB565:
1636         case DRM_FORMAT_BGR565:
1637         case DRM_FORMAT_ARGB1555:
1638         case DRM_FORMAT_XRGB1555:
1639                 switch (fourcc_mod_broadcom_mod(modifier)) {
1640                 case DRM_FORMAT_MOD_LINEAR:
1641                 case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
1642                         return true;
1643                 default:
1644                         return false;
1645                 }
1646         case DRM_FORMAT_NV12:
1647         case DRM_FORMAT_NV21:
1648                 switch (fourcc_mod_broadcom_mod(modifier)) {
1649                 case DRM_FORMAT_MOD_LINEAR:
1650                 case DRM_FORMAT_MOD_BROADCOM_SAND64:
1651                 case DRM_FORMAT_MOD_BROADCOM_SAND128:
1652                 case DRM_FORMAT_MOD_BROADCOM_SAND256:
1653                         return true;
1654                 default:
1655                         return false;
1656                 }
1657         case DRM_FORMAT_P030:
1658                 switch (fourcc_mod_broadcom_mod(modifier)) {
1659                 case DRM_FORMAT_MOD_BROADCOM_SAND128:
1660                         return true;
1661                 default:
1662                         return false;
1663                 }
1664         case DRM_FORMAT_RGBX1010102:
1665         case DRM_FORMAT_BGRX1010102:
1666         case DRM_FORMAT_RGBA1010102:
1667         case DRM_FORMAT_BGRA1010102:
1668         case DRM_FORMAT_XRGB4444:
1669         case DRM_FORMAT_ARGB4444:
1670         case DRM_FORMAT_XBGR4444:
1671         case DRM_FORMAT_ABGR4444:
1672         case DRM_FORMAT_RGBX4444:
1673         case DRM_FORMAT_RGBA4444:
1674         case DRM_FORMAT_BGRX4444:
1675         case DRM_FORMAT_BGRA4444:
1676         case DRM_FORMAT_RGB332:
1677         case DRM_FORMAT_BGR233:
1678         case DRM_FORMAT_YUV422:
1679         case DRM_FORMAT_YVU422:
1680         case DRM_FORMAT_YUV420:
1681         case DRM_FORMAT_YVU420:
1682         case DRM_FORMAT_NV16:
1683         case DRM_FORMAT_NV61:
1684         default:
1685                 return (modifier == DRM_FORMAT_MOD_LINEAR);
1686         }
1687 }
1688
1689 static const struct drm_plane_funcs vc4_plane_funcs = {
1690         .update_plane = drm_atomic_helper_update_plane,
1691         .disable_plane = drm_atomic_helper_disable_plane,
1692         .reset = vc4_plane_reset,
1693         .atomic_duplicate_state = vc4_plane_duplicate_state,
1694         .atomic_destroy_state = vc4_plane_destroy_state,
1695         .format_mod_supported = vc4_format_mod_supported,
1696 };
1697
1698 struct drm_plane *vc4_plane_init(struct drm_device *dev,
1699                                  enum drm_plane_type type,
1700                                  uint32_t possible_crtcs)
1701 {
1702         struct vc4_dev *vc4 = to_vc4_dev(dev);
1703         struct drm_plane *plane;
1704         struct vc4_plane *vc4_plane;
1705         u32 formats[ARRAY_SIZE(hvs_formats)];
1706         int num_formats = 0;
1707         unsigned i;
1708         static const uint64_t modifiers[] = {
1709                 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
1710                 DRM_FORMAT_MOD_BROADCOM_SAND128,
1711                 DRM_FORMAT_MOD_BROADCOM_SAND64,
1712                 DRM_FORMAT_MOD_BROADCOM_SAND256,
1713                 DRM_FORMAT_MOD_LINEAR,
1714                 DRM_FORMAT_MOD_INVALID
1715         };
1716
1717         for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
1718                 if (!hvs_formats[i].hvs5_only || vc4->gen == VC4_GEN_5) {
1719                         formats[num_formats] = hvs_formats[i].drm;
1720                         num_formats++;
1721                 }
1722         }
1723
1724         vc4_plane = drmm_universal_plane_alloc(dev, struct vc4_plane, base,
1725                                                possible_crtcs,
1726                                                &vc4_plane_funcs,
1727                                                formats, num_formats,
1728                                                modifiers, type, NULL);
1729         if (IS_ERR(vc4_plane))
1730                 return ERR_CAST(vc4_plane);
1731         plane = &vc4_plane->base;
1732
1733         if (vc4->gen == VC4_GEN_5)
1734                 drm_plane_helper_add(plane, &vc5_plane_helper_funcs);
1735         else
1736                 drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
1737
1738         drm_plane_create_alpha_property(plane);
1739         drm_plane_create_blend_mode_property(plane,
1740                                              BIT(DRM_MODE_BLEND_PIXEL_NONE) |
1741                                              BIT(DRM_MODE_BLEND_PREMULTI) |
1742                                              BIT(DRM_MODE_BLEND_COVERAGE));
1743         drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1744                                            DRM_MODE_ROTATE_0 |
1745                                            DRM_MODE_ROTATE_180 |
1746                                            DRM_MODE_REFLECT_X |
1747                                            DRM_MODE_REFLECT_Y);
1748
1749         drm_plane_create_color_properties(plane,
1750                                           BIT(DRM_COLOR_YCBCR_BT601) |
1751                                           BIT(DRM_COLOR_YCBCR_BT709) |
1752                                           BIT(DRM_COLOR_YCBCR_BT2020),
1753                                           BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
1754                                           BIT(DRM_COLOR_YCBCR_FULL_RANGE),
1755                                           DRM_COLOR_YCBCR_BT709,
1756                                           DRM_COLOR_YCBCR_LIMITED_RANGE);
1757
1758         drm_plane_create_chroma_siting_properties(plane, 0, 0);
1759
1760         if (type == DRM_PLANE_TYPE_PRIMARY)
1761                 drm_plane_create_zpos_immutable_property(plane, 0);
1762
1763         return plane;
1764 }
1765
1766 #define VC4_NUM_OVERLAY_PLANES  16
1767
1768 int vc4_plane_create_additional_planes(struct drm_device *drm)
1769 {
1770         struct drm_plane *cursor_plane;
1771         struct drm_crtc *crtc;
1772         unsigned int i;
1773
1774         /* Set up some arbitrary number of planes.  We're not limited
1775          * by a set number of physical registers, just the space in
1776          * the HVS (16k) and how small an plane can be (28 bytes).
1777          * However, each plane we set up takes up some memory, and
1778          * increases the cost of looping over planes, which atomic
1779          * modesetting does quite a bit.  As a result, we pick a
1780          * modest number of planes to expose, that should hopefully
1781          * still cover any sane usecase.
1782          */
1783         for (i = 0; i < VC4_NUM_OVERLAY_PLANES; i++) {
1784                 struct drm_plane *plane =
1785                         vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY,
1786                                        GENMASK(drm->mode_config.num_crtc - 1, 0));
1787
1788                 if (IS_ERR(plane))
1789                         continue;
1790
1791                 /* Create zpos property. Max of all the overlays + 1 primary +
1792                  * 1 cursor plane on a crtc.
1793                  */
1794                 drm_plane_create_zpos_property(plane, i + 1, 1,
1795                                                VC4_NUM_OVERLAY_PLANES + 1);
1796         }
1797
1798         drm_for_each_crtc(crtc, drm) {
1799                 /* Set up the legacy cursor after overlay initialization,
1800                  * since the zpos fallback is that planes are rendered by plane
1801                  * ID order, and that then puts the cursor on top.
1802                  */
1803                 cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR,
1804                                               drm_crtc_mask(crtc));
1805                 if (!IS_ERR(cursor_plane)) {
1806                         crtc->cursor = cursor_plane;
1807
1808                         drm_plane_create_zpos_property(cursor_plane,
1809                                                        VC4_NUM_OVERLAY_PLANES + 1,
1810                                                        1,
1811                                                        VC4_NUM_OVERLAY_PLANES + 1);
1812                 }
1813         }
1814
1815         return 0;
1816 }