drivers/gpu/drm/vc4/vc4_plane.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /**
  10  * DOC: VC4 plane module
  11  *
  12  * Each DRM plane is a layer of pixels being scanned out by the HVS.
  13  *
  14  * At atomic modeset check time, we compute the HVS display element
  15  * state that would be necessary for displaying the plane (giving us a
  16  * chance to figure out if a plane configuration is invalid), then at
  17  * atomic flush time the CRTC will ask us to write our element state
  18  * into the region of the HVS that it has allocated for us.
  19  */
  20
  21 #include <drm/drm_atomic.h>
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_fb_cma_helper.h>
  24 #include <drm/drm_plane_helper.h>
  25
  26 #include "uapi/drm/vc4_drm.h"
  27 #include "vc4_drv.h"
  28 #include "vc4_regs.h"
  29
  30 static const struct hvs_format {
  31         u32 drm; /* DRM_FORMAT_* */
  32         u32 hvs; /* HVS_FORMAT_* */
  33         u32 pixel_order;
  34 } hvs_formats[] = {
  35         {
  36                 .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  37                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  38         },
  39         {
  40                 .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  41                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  42         },
  43         {
  44                 .drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  45                 .pixel_order = HVS_PIXEL_ORDER_ARGB,
  46         },
  47         {
  48                 .drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  49                 .pixel_order = HVS_PIXEL_ORDER_ARGB,
  50         },
  51         {
  52                 .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565,
  53                 .pixel_order = HVS_PIXEL_ORDER_XRGB,
  54         },
  55         {
  56                 .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565,
  57                 .pixel_order = HVS_PIXEL_ORDER_XBGR,
  58         },
  59         {
  60                 .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
  61                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  62         },
  63         {
  64                 .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
  65                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  66         },
  67         {
  68                 .drm = DRM_FORMAT_RGB888, .hvs = HVS_PIXEL_FORMAT_RGB888,
  69                 .pixel_order = HVS_PIXEL_ORDER_XRGB,
  70         },
  71         {
  72                 .drm = DRM_FORMAT_BGR888, .hvs = HVS_PIXEL_FORMAT_RGB888,
  73                 .pixel_order = HVS_PIXEL_ORDER_XBGR,
  74         },
  75         {
  76                 .drm = DRM_FORMAT_YUV422,
  77                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
  78                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
  79         },
  80         {
  81                 .drm = DRM_FORMAT_YVU422,
  82                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
  83                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
  84         },
  85         {
  86                 .drm = DRM_FORMAT_YUV420,
  87                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
  88                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
  89         },
  90         {
  91                 .drm = DRM_FORMAT_YVU420,
  92                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
  93                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
  94         },
  95         {
  96                 .drm = DRM_FORMAT_NV12,
  97                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
  98                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
  99         },
 100         {
 101                 .drm = DRM_FORMAT_NV21,
 102                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
 103                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
 104         },
 105         {
 106                 .drm = DRM_FORMAT_NV16,
 107                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
 108                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
 109         },
 110         {
 111                 .drm = DRM_FORMAT_NV61,
 112                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
 113                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
 114         },
 115 };
 116
 117 static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
 118 {
 119         unsigned i;
 120
 121         for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
 122                 if (hvs_formats[i].drm == drm_format)
 123                         return &hvs_formats[i];
 124         }
 125
 126         return NULL;
 127 }
 128
 129 static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst)
 130 {
 131         if (dst > src)
 132                 return VC4_SCALING_PPF;
 133         else if (dst < src)
 134                 return VC4_SCALING_TPZ;
 135         else
 136                 return VC4_SCALING_NONE;
 137 }
 138
 139 static bool plane_enabled(struct drm_plane_state *state)
 140 {
 141         return state->fb && state->crtc;
 142 }
 143
 144 static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane)
 145 {
 146         struct vc4_plane_state *vc4_state;
 147
 148         if (WARN_ON(!plane->state))
 149                 return NULL;
 150
 151         vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL);
 152         if (!vc4_state)
 153                 return NULL;
 154
 155         memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm));
 156
 157         __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base);
 158
 159         if (vc4_state->dlist) {
 160                 vc4_state->dlist = kmemdup(vc4_state->dlist,
 161                                            vc4_state->dlist_count * 4,
 162                                            GFP_KERNEL);
 163                 if (!vc4_state->dlist) {
 164                         kfree(vc4_state);
 165                         return NULL;
 166                 }
 167                 vc4_state->dlist_size = vc4_state->dlist_count;
 168         }
 169
 170         return &vc4_state->base;
 171 }
 172
 173 static void vc4_plane_destroy_state(struct drm_plane *plane,
 174                                     struct drm_plane_state *state)
 175 {
 176         struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
 177         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 178
 179         if (vc4_state->lbm.allocated) {
 180                 unsigned long irqflags;
 181
 182                 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
 183                 drm_mm_remove_node(&vc4_state->lbm);
 184                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
 185         }
 186
 187         kfree(vc4_state->dlist);
 188         __drm_atomic_helper_plane_destroy_state(&vc4_state->base);
 189         kfree(state);
 190 }
 191
 192 /* Called during init to allocate the plane's atomic state. */
 193 static void vc4_plane_reset(struct drm_plane *plane)
 194 {
 195         struct vc4_plane_state *vc4_state;
 196
 197         WARN_ON(plane->state);
 198
 199         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 200         if (!vc4_state)
 201                 return;
 202
 203         plane->state = &vc4_state->base;
 204         plane->state->alpha = DRM_BLEND_ALPHA_OPAQUE;
 205         vc4_state->base.plane = plane;
 206 }
 207
 208 static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val)
 209 {
 210         if (vc4_state->dlist_count == vc4_state->dlist_size) {
 211                 u32 new_size = max(4u, vc4_state->dlist_count * 2);
 212                 u32 *new_dlist = kmalloc_array(new_size, 4, GFP_KERNEL);
 213
 214                 if (!new_dlist)
 215                         return;
 216                 memcpy(new_dlist, vc4_state->dlist, vc4_state->dlist_count * 4);
 217
 218                 kfree(vc4_state->dlist);
 219                 vc4_state->dlist = new_dlist;
 220                 vc4_state->dlist_size = new_size;
 221         }
 222
 223         vc4_state->dlist[vc4_state->dlist_count++] = val;
 224 }
 225
 226 /* Returns the scl0/scl1 field based on whether the dimensions need to
 227  * be up/down/non-scaled.
 228  *
 229  * This is a replication of a table from the spec.
 230  */
 231 static u32 vc4_get_scl_field(struct drm_plane_state *state, int plane)
 232 {
 233         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 234
 235         switch (vc4_state->x_scaling[plane] << 2 | vc4_state->y_scaling[plane]) {
 236         case VC4_SCALING_PPF << 2 | VC4_SCALING_PPF:
 237                 return SCALER_CTL0_SCL_H_PPF_V_PPF;
 238         case VC4_SCALING_TPZ << 2 | VC4_SCALING_PPF:
 239                 return SCALER_CTL0_SCL_H_TPZ_V_PPF;
 240         case VC4_SCALING_PPF << 2 | VC4_SCALING_TPZ:
 241                 return SCALER_CTL0_SCL_H_PPF_V_TPZ;
 242         case VC4_SCALING_TPZ << 2 | VC4_SCALING_TPZ:
 243                 return SCALER_CTL0_SCL_H_TPZ_V_TPZ;
 244         case VC4_SCALING_PPF << 2 | VC4_SCALING_NONE:
 245                 return SCALER_CTL0_SCL_H_PPF_V_NONE;
 246         case VC4_SCALING_NONE << 2 | VC4_SCALING_PPF:
 247                 return SCALER_CTL0_SCL_H_NONE_V_PPF;
 248         case VC4_SCALING_NONE << 2 | VC4_SCALING_TPZ:
 249                 return SCALER_CTL0_SCL_H_NONE_V_TPZ;
 250         case VC4_SCALING_TPZ << 2 | VC4_SCALING_NONE:
 251                 return SCALER_CTL0_SCL_H_TPZ_V_NONE;
 252         default:
 253         case VC4_SCALING_NONE << 2 | VC4_SCALING_NONE:
 254                 /* The unity case is independently handled by
 255                  * SCALER_CTL0_UNITY.
 256                  */
 257                 return 0;
 258         }
 259 }
 260
 261 static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
 262 {
 263         struct drm_plane *plane = state->plane;
 264         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 265         struct drm_framebuffer *fb = state->fb;
 266         struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
 267         u32 subpixel_src_mask = (1 << 16) - 1;
 268         u32 format = fb->format->format;
 269         int num_planes = fb->format->num_planes;
 270         u32 h_subsample = 1;
 271         u32 v_subsample = 1;
 272         int i;
 273
 274         for (i = 0; i < num_planes; i++)
 275                 vc4_state->offsets[i] = bo->paddr + fb->offsets[i];
 276
 277         /* We don't support subpixel source positioning for scaling. */
 278         if ((state->src_x & subpixel_src_mask) ||
 279             (state->src_y & subpixel_src_mask) ||
 280             (state->src_w & subpixel_src_mask) ||
 281             (state->src_h & subpixel_src_mask)) {
 282                 return -EINVAL;
 283         }
 284
 285         vc4_state->src_x = state->src_x >> 16;
 286         vc4_state->src_y = state->src_y >> 16;
 287         vc4_state->src_w[0] = state->src_w >> 16;
 288         vc4_state->src_h[0] = state->src_h >> 16;
 289
 290         vc4_state->crtc_x = state->crtc_x;
 291         vc4_state->crtc_y = state->crtc_y;
 292         vc4_state->crtc_w = state->crtc_w;
 293         vc4_state->crtc_h = state->crtc_h;
 294
 295         vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0],
 296                                                        vc4_state->crtc_w);
 297         vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0],
 298                                                        vc4_state->crtc_h);
 299
 300         vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE &&
 301                                vc4_state->y_scaling[0] == VC4_SCALING_NONE);
 302
 303         if (num_planes > 1) {
 304                 vc4_state->is_yuv = true;
 305
 306                 h_subsample = drm_format_horz_chroma_subsampling(format);
 307                 v_subsample = drm_format_vert_chroma_subsampling(format);
 308                 vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample;
 309                 vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample;
 310
 311                 vc4_state->x_scaling[1] =
 312                         vc4_get_scaling_mode(vc4_state->src_w[1],
 313                                              vc4_state->crtc_w);
 314                 vc4_state->y_scaling[1] =
 315                         vc4_get_scaling_mode(vc4_state->src_h[1],
 316                                              vc4_state->crtc_h);
 317
 318                 /* YUV conversion requires that horizontal scaling be enabled
 319                  * on the UV plane even if vc4_get_scaling_mode() returned
 320                  * VC4_SCALING_NONE (which can happen when the down-scaling
 321                  * ratio is 0.5). Let's force it to VC4_SCALING_PPF in this
 322                  * case.
 323                  */
 324                 if (vc4_state->x_scaling[1] == VC4_SCALING_NONE)
 325                         vc4_state->x_scaling[1] = VC4_SCALING_PPF;
 326         } else {
 327                 vc4_state->is_yuv = false;
 328                 vc4_state->x_scaling[1] = VC4_SCALING_NONE;
 329                 vc4_state->y_scaling[1] = VC4_SCALING_NONE;
 330         }
 331
 332         /* No configuring scaling on the cursor plane, since it gets
 333            non-vblank-synced updates, and scaling requires requires
 334            LBM changes which have to be vblank-synced.
 335          */
 336         if (plane->type == DRM_PLANE_TYPE_CURSOR && !vc4_state->is_unity)
 337                 return -EINVAL;
 338
 339         /* Clamp the on-screen start x/y to 0.  The hardware doesn't
 340          * support negative y, and negative x wastes bandwidth.
 341          */
 342         if (vc4_state->crtc_x < 0) {
 343                 for (i = 0; i < num_planes; i++) {
 344                         u32 cpp = fb->format->cpp[i];
 345                         u32 subs = ((i == 0) ? 1 : h_subsample);
 346
 347                         vc4_state->offsets[i] += (cpp *
 348                                                   (-vc4_state->crtc_x) / subs);
 349                 }
 350                 vc4_state->src_w[0] += vc4_state->crtc_x;
 351                 vc4_state->src_w[1] += vc4_state->crtc_x / h_subsample;
 352                 vc4_state->crtc_x = 0;
 353         }
 354
 355         if (vc4_state->crtc_y < 0) {
 356                 for (i = 0; i < num_planes; i++) {
 357                         u32 subs = ((i == 0) ? 1 : v_subsample);
 358
 359                         vc4_state->offsets[i] += (fb->pitches[i] *
 360                                                   (-vc4_state->crtc_y) / subs);
 361                 }
 362                 vc4_state->src_h[0] += vc4_state->crtc_y;
 363                 vc4_state->src_h[1] += vc4_state->crtc_y / v_subsample;
 364                 vc4_state->crtc_y = 0;
 365         }
 366
 367         return 0;
 368 }
 369
 370 static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
 371 {
 372         u32 scale, recip;
 373
 374         scale = (1 << 16) * src / dst;
 375
 376         /* The specs note that while the reciprocal would be defined
 377          * as (1<<32)/scale, ~0 is close enough.
 378          */
 379         recip = ~0 / scale;
 380
 381         vc4_dlist_write(vc4_state,
 382                         VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) |
 383                         VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE));
 384         vc4_dlist_write(vc4_state,
 385                         VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP));
 386 }
 387
 388 static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
 389 {
 390         u32 scale = (1 << 16) * src / dst;
 391
 392         vc4_dlist_write(vc4_state,
 393                         SCALER_PPF_AGC |
 394                         VC4_SET_FIELD(scale, SCALER_PPF_SCALE) |
 395                         VC4_SET_FIELD(0, SCALER_PPF_IPHASE));
 396 }
 397
 398 static u32 vc4_lbm_size(struct drm_plane_state *state)
 399 {
 400         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 401         /* This is the worst case number.  One of the two sizes will
 402          * be used depending on the scaling configuration.
 403          */
 404         u32 pix_per_line = max(vc4_state->src_w[0], (u32)vc4_state->crtc_w);
 405         u32 lbm;
 406
 407         if (!vc4_state->is_yuv) {
 408                 if (vc4_state->is_unity)
 409                         return 0;
 410                 else if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ)
 411                         lbm = pix_per_line * 8;
 412                 else {
 413                         /* In special cases, this multiplier might be 12. */
 414                         lbm = pix_per_line * 16;
 415                 }
 416         } else {
 417                 /* There are cases for this going down to a multiplier
 418                  * of 2, but according to the firmware source, the
 419                  * table in the docs is somewhat wrong.
 420                  */
 421                 lbm = pix_per_line * 16;
 422         }
 423
 424         lbm = roundup(lbm, 32);
 425
 426         return lbm;
 427 }
 428
 429 static void vc4_write_scaling_parameters(struct drm_plane_state *state,
 430                                          int channel)
 431 {
 432         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 433
 434         /* Ch0 H-PPF Word 0: Scaling Parameters */
 435         if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
 436                 vc4_write_ppf(vc4_state,
 437                               vc4_state->src_w[channel], vc4_state->crtc_w);
 438         }
 439
 440         /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */
 441         if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) {
 442                 vc4_write_ppf(vc4_state,
 443                               vc4_state->src_h[channel], vc4_state->crtc_h);
 444                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 445         }
 446
 447         /* Ch0 H-TPZ Words 0-1: Scaling Parameters, Recip */
 448         if (vc4_state->x_scaling[channel] == VC4_SCALING_TPZ) {
 449                 vc4_write_tpz(vc4_state,
 450                               vc4_state->src_w[channel], vc4_state->crtc_w);
 451         }
 452
 453         /* Ch0 V-TPZ Words 0-2: Scaling Parameters, Recip, Context */
 454         if (vc4_state->y_scaling[channel] == VC4_SCALING_TPZ) {
 455                 vc4_write_tpz(vc4_state,
 456                               vc4_state->src_h[channel], vc4_state->crtc_h);
 457                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 458         }
 459 }
 460
 461 /* Writes out a full display list for an active plane to the plane's
 462  * private dlist state.
 463  */
 464 static int vc4_plane_mode_set(struct drm_plane *plane,
 465                               struct drm_plane_state *state)
 466 {
 467         struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
 468         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 469         struct drm_framebuffer *fb = state->fb;
 470         u32 ctl0_offset = vc4_state->dlist_count;
 471         const struct hvs_format *format = vc4_get_hvs_format(fb->format->format);
 472         u64 base_format_mod = fourcc_mod_broadcom_mod(fb->modifier);
 473         int num_planes = drm_format_num_planes(format->drm);
 474         bool mix_plane_alpha;
 475         bool covers_screen;
 476         u32 scl0, scl1, pitch0;
 477         u32 lbm_size, tiling;
 478         unsigned long irqflags;
 479         u32 hvs_format = format->hvs;
 480         int ret, i;
 481
 482         ret = vc4_plane_setup_clipping_and_scaling(state);
 483         if (ret)
 484                 return ret;
 485
 486         /* Allocate the LBM memory that the HVS will use for temporary
 487          * storage due to our scaling/format conversion.
 488          */
 489         lbm_size = vc4_lbm_size(state);
 490         if (lbm_size) {
 491                 if (!vc4_state->lbm.allocated) {
 492                         spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
 493                         ret = drm_mm_insert_node_generic(&vc4->hvs->lbm_mm,
 494                                                          &vc4_state->lbm,
 495                                                          lbm_size, 32, 0, 0);
 496                         spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
 497                 } else {
 498                         WARN_ON_ONCE(lbm_size != vc4_state->lbm.size);
 499                 }
 500         }
 501
 502         if (ret)
 503                 return ret;
 504
 505         /* SCL1 is used for Cb/Cr scaling of planar formats.  For RGB
 506          * and 4:4:4, scl1 should be set to scl0 so both channels of
 507          * the scaler do the same thing.  For YUV, the Y plane needs
 508          * to be put in channel 1 and Cb/Cr in channel 0, so we swap
 509          * the scl fields here.
 510          */
 511         if (num_planes == 1) {
 512                 scl0 = vc4_get_scl_field(state, 0);
 513                 scl1 = scl0;
 514         } else {
 515                 scl0 = vc4_get_scl_field(state, 1);
 516                 scl1 = vc4_get_scl_field(state, 0);
 517         }
 518
 519         switch (base_format_mod) {
 520         case DRM_FORMAT_MOD_LINEAR:
 521                 tiling = SCALER_CTL0_TILING_LINEAR;
 522                 pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
 523                 break;
 524
 525         case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
 526                 /* For T-tiled, the FB pitch is "how many bytes from
 527                  * one row to the next, such that pitch * tile_h ==
 528                  * tile_size * tiles_per_row."
 529                  */
 530                 u32 tile_size_shift = 12; /* T tiles are 4kb */
 531                 u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */
 532                 u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
 533
 534                 tiling = SCALER_CTL0_TILING_256B_OR_T;
 535
 536                 pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET) |
 537                           VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L) |
 538                           VC4_SET_FIELD(tiles_w, SCALER_PITCH0_TILE_WIDTH_R));
 539                 break;
 540         }
 541
 542         case DRM_FORMAT_MOD_BROADCOM_SAND64:
 543         case DRM_FORMAT_MOD_BROADCOM_SAND128:
 544         case DRM_FORMAT_MOD_BROADCOM_SAND256: {
 545                 uint32_t param = fourcc_mod_broadcom_param(fb->modifier);
 546
 547                 /* Column-based NV12 or RGBA.
 548                  */
 549                 if (fb->format->num_planes > 1) {
 550                         if (hvs_format != HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE) {
 551                                 DRM_DEBUG_KMS("SAND format only valid for NV12/21");
 552                                 return -EINVAL;
 553                         }
 554                         hvs_format = HVS_PIXEL_FORMAT_H264;
 555                 } else {
 556                         if (base_format_mod == DRM_FORMAT_MOD_BROADCOM_SAND256) {
 557                                 DRM_DEBUG_KMS("SAND256 format only valid for H.264");
 558                                 return -EINVAL;
 559                         }
 560                 }
 561
 562                 switch (base_format_mod) {
 563                 case DRM_FORMAT_MOD_BROADCOM_SAND64:
 564                         tiling = SCALER_CTL0_TILING_64B;
 565                         break;
 566                 case DRM_FORMAT_MOD_BROADCOM_SAND128:
 567                         tiling = SCALER_CTL0_TILING_128B;
 568                         break;
 569                 case DRM_FORMAT_MOD_BROADCOM_SAND256:
 570                         tiling = SCALER_CTL0_TILING_256B_OR_T;
 571                         break;
 572                 default:
 573                         break;
 574                 }
 575
 576                 if (param > SCALER_TILE_HEIGHT_MASK) {
 577                         DRM_DEBUG_KMS("SAND height too large (%d)\n", param);
 578                         return -EINVAL;
 579                 }
 580
 581                 pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);
 582                 break;
 583         }
 584
 585         default:
 586                 DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
 587                               (long long)fb->modifier);
 588                 return -EINVAL;
 589         }
 590
 591         /* Control word */
 592         vc4_dlist_write(vc4_state,
 593                         SCALER_CTL0_VALID |
 594                         VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
 595                         (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
 596                         (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
 597                         VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
 598                         (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
 599                         VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
 600                         VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
 601
 602         /* Position Word 0: Image Positions and Alpha Value */
 603         vc4_state->pos0_offset = vc4_state->dlist_count;
 604         vc4_dlist_write(vc4_state,
 605                         VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
 606                         VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
 607                         VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
 608
 609         /* Position Word 1: Scaled Image Dimensions. */
 610         if (!vc4_state->is_unity) {
 611                 vc4_dlist_write(vc4_state,
 612                                 VC4_SET_FIELD(vc4_state->crtc_w,
 613                                               SCALER_POS1_SCL_WIDTH) |
 614                                 VC4_SET_FIELD(vc4_state->crtc_h,
 615                                               SCALER_POS1_SCL_HEIGHT));
 616         }
 617
 618         /* Don't waste cycles mixing with plane alpha if the set alpha
 619          * is opaque or there is no per-pixel alpha information.
 620          * In any case we use the alpha property value as the fixed alpha.
 621          */
 622         mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
 623                           fb->format->has_alpha;
 624
 625         /* Position Word 2: Source Image Size, Alpha */
 626         vc4_state->pos2_offset = vc4_state->dlist_count;
 627         vc4_dlist_write(vc4_state,
 628                         VC4_SET_FIELD(fb->format->has_alpha ?
 629                                       SCALER_POS2_ALPHA_MODE_PIPELINE :
 630                                       SCALER_POS2_ALPHA_MODE_FIXED,
 631                                       SCALER_POS2_ALPHA_MODE) |
 632                         (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
 633                         (fb->format->has_alpha ? SCALER_POS2_ALPHA_PREMULT : 0) |
 634                         VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
 635                         VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
 636
 637         /* Position Word 3: Context.  Written by the HVS. */
 638         vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 639
 640
 641         /* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
 642          *
 643          * The pointers may be any byte address.
 644          */
 645         vc4_state->ptr0_offset = vc4_state->dlist_count;
 646         for (i = 0; i < num_planes; i++)
 647                 vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
 648
 649         /* Pointer Context Word 0/1/2: Written by the HVS */
 650         for (i = 0; i < num_planes; i++)
 651                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 652
 653         /* Pitch word 0 */
 654         vc4_dlist_write(vc4_state, pitch0);
 655
 656         /* Pitch word 1/2 */
 657         for (i = 1; i < num_planes; i++) {
 658                 if (hvs_format != HVS_PIXEL_FORMAT_H264) {
 659                         vc4_dlist_write(vc4_state,
 660                                         VC4_SET_FIELD(fb->pitches[i],
 661                                                       SCALER_SRC_PITCH));
 662                 } else {
 663                         vc4_dlist_write(vc4_state, pitch0);
 664                 }
 665         }
 666
 667         /* Colorspace conversion words */
 668         if (vc4_state->is_yuv) {
 669                 vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
 670                 vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
 671                 vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
 672         }
 673
 674         if (vc4_state->x_scaling[0] != VC4_SCALING_NONE ||
 675             vc4_state->x_scaling[1] != VC4_SCALING_NONE ||
 676             vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
 677             vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
 678                 /* LBM Base Address. */
 679                 if (vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
 680                     vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
 681                         vc4_dlist_write(vc4_state, vc4_state->lbm.start);
 682                 }
 683
 684                 if (num_planes > 1) {
 685                         /* Emit Cb/Cr as channel 0 and Y as channel
 686                          * 1. This matches how we set up scl0/scl1
 687                          * above.
 688                          */
 689                         vc4_write_scaling_parameters(state, 1);
 690                 }
 691                 vc4_write_scaling_parameters(state, 0);
 692
 693                 /* If any PPF setup was done, then all the kernel
 694                  * pointers get uploaded.
 695                  */
 696                 if (vc4_state->x_scaling[0] == VC4_SCALING_PPF ||
 697                     vc4_state->y_scaling[0] == VC4_SCALING_PPF ||
 698                     vc4_state->x_scaling[1] == VC4_SCALING_PPF ||
 699                     vc4_state->y_scaling[1] == VC4_SCALING_PPF) {
 700                         u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start,
 701                                                    SCALER_PPF_KERNEL_OFFSET);
 702
 703                         /* HPPF plane 0 */
 704                         vc4_dlist_write(vc4_state, kernel);
 705                         /* VPPF plane 0 */
 706                         vc4_dlist_write(vc4_state, kernel);
 707                         /* HPPF plane 1 */
 708                         vc4_dlist_write(vc4_state, kernel);
 709                         /* VPPF plane 1 */
 710                         vc4_dlist_write(vc4_state, kernel);
 711                 }
 712         }
 713
 714         vc4_state->dlist[ctl0_offset] |=
 715                 VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
 716
 717         /* crtc_* are already clipped coordinates. */
 718         covers_screen = vc4_state->crtc_x == 0 && vc4_state->crtc_y == 0 &&
 719                         vc4_state->crtc_w == state->crtc->mode.hdisplay &&
 720                         vc4_state->crtc_h == state->crtc->mode.vdisplay;
 721         /* Background fill might be necessary when the plane has per-pixel
 722          * alpha content or a non-opaque plane alpha and could blend from the
 723          * background or does not cover the entire screen.
 724          */
 725         vc4_state->needs_bg_fill = fb->format->has_alpha || !covers_screen ||
 726                                    state->alpha != DRM_BLEND_ALPHA_OPAQUE;
 727
 728         return 0;
 729 }
 730
 731 /* If a modeset involves changing the setup of a plane, the atomic
 732  * infrastructure will call this to validate a proposed plane setup.
 733  * However, if a plane isn't getting updated, this (and the
 734  * corresponding vc4_plane_atomic_update) won't get called.  Thus, we
 735  * compute the dlist here and have all active plane dlists get updated
 736  * in the CRTC's flush.
 737  */
 738 static int vc4_plane_atomic_check(struct drm_plane *plane,
 739                                   struct drm_plane_state *state)
 740 {
 741         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 742
 743         vc4_state->dlist_count = 0;
 744
 745         if (plane_enabled(state))
 746                 return vc4_plane_mode_set(plane, state);
 747         else
 748                 return 0;
 749 }
 750
 751 static void vc4_plane_atomic_update(struct drm_plane *plane,
 752                                     struct drm_plane_state *old_state)
 753 {
 754         /* No contents here.  Since we don't know where in the CRTC's
 755          * dlist we should be stored, our dlist is uploaded to the
 756          * hardware with vc4_plane_write_dlist() at CRTC atomic_flush
 757          * time.
 758          */
 759 }
 760
 761 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist)
 762 {
 763         struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
 764         int i;
 765
 766         vc4_state->hw_dlist = dlist;
 767
 768         /* Can't memcpy_toio() because it needs to be 32-bit writes. */
 769         for (i = 0; i < vc4_state->dlist_count; i++)
 770                 writel(vc4_state->dlist[i], &dlist[i]);
 771
 772         return vc4_state->dlist_count;
 773 }
 774
 775 u32 vc4_plane_dlist_size(const struct drm_plane_state *state)
 776 {
 777         const struct vc4_plane_state *vc4_state =
 778                 container_of(state, typeof(*vc4_state), base);
 779
 780         return vc4_state->dlist_count;
 781 }
 782
 783 /* Updates the plane to immediately (well, once the FIFO needs
 784  * refilling) scan out from at a new framebuffer.
 785  */
 786 void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb)
 787 {
 788         struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
 789         struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
 790         uint32_t addr;
 791
 792         /* We're skipping the address adjustment for negative origin,
 793          * because this is only called on the primary plane.
 794          */
 795         WARN_ON_ONCE(plane->state->crtc_x < 0 || plane->state->crtc_y < 0);
 796         addr = bo->paddr + fb->offsets[0];
 797
 798         /* Write the new address into the hardware immediately.  The
 799          * scanout will start from this address as soon as the FIFO
 800          * needs to refill with pixels.
 801          */
 802         writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
 803
 804         /* Also update the CPU-side dlist copy, so that any later
 805          * atomic updates that don't do a new modeset on our plane
 806          * also use our updated address.
 807          */
 808         vc4_state->dlist[vc4_state->ptr0_offset] = addr;
 809 }
 810
 811 static void vc4_plane_atomic_async_update(struct drm_plane *plane,
 812                                           struct drm_plane_state *state)
 813 {
 814         struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
 815
 816         if (plane->state->fb != state->fb) {
 817                 vc4_plane_async_set_fb(plane, state->fb);
 818                 drm_atomic_set_fb_for_plane(plane->state, state->fb);
 819         }
 820
 821         /* Set the cursor's position on the screen.  This is the
 822          * expected change from the drm_mode_cursor_universal()
 823          * helper.
 824          */
 825         plane->state->crtc_x = state->crtc_x;
 826         plane->state->crtc_y = state->crtc_y;
 827
 828         /* Allow changing the start position within the cursor BO, if
 829          * that matters.
 830          */
 831         plane->state->src_x = state->src_x;
 832         plane->state->src_y = state->src_y;
 833
 834         /* Update the display list based on the new crtc_x/y. */
 835         vc4_plane_atomic_check(plane, plane->state);
 836
 837         /* Note that we can't just call vc4_plane_write_dlist()
 838          * because that would smash the context data that the HVS is
 839          * currently using.
 840          */
 841         writel(vc4_state->dlist[vc4_state->pos0_offset],
 842                &vc4_state->hw_dlist[vc4_state->pos0_offset]);
 843         writel(vc4_state->dlist[vc4_state->pos2_offset],
 844                &vc4_state->hw_dlist[vc4_state->pos2_offset]);
 845         writel(vc4_state->dlist[vc4_state->ptr0_offset],
 846                &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
 847 }
 848
 849 static int vc4_plane_atomic_async_check(struct drm_plane *plane,
 850                                         struct drm_plane_state *state)
 851 {
 852         /* No configuring new scaling in the fast path. */
 853         if (plane->state->crtc_w != state->crtc_w ||
 854             plane->state->crtc_h != state->crtc_h ||
 855             plane->state->src_w != state->src_w ||
 856             plane->state->src_h != state->src_h)
 857                 return -EINVAL;
 858
 859         return 0;
 860 }
 861
 862 static int vc4_prepare_fb(struct drm_plane *plane,
 863                           struct drm_plane_state *state)
 864 {
 865         struct vc4_bo *bo;
 866         struct dma_fence *fence;
 867         int ret;
 868
 869         if (!state->fb)
 870                 return 0;
 871
 872         bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base);
 873
 874         fence = reservation_object_get_excl_rcu(bo->resv);
 875         drm_atomic_set_fence_for_plane(state, fence);
 876
 877         if (plane->state->fb == state->fb)
 878                 return 0;
 879
 880         ret = vc4_bo_inc_usecnt(bo);
 881         if (ret)
 882                 return ret;
 883
 884         return 0;
 885 }
 886
 887 static void vc4_cleanup_fb(struct drm_plane *plane,
 888                            struct drm_plane_state *state)
 889 {
 890         struct vc4_bo *bo;
 891
 892         if (plane->state->fb == state->fb || !state->fb)
 893                 return;
 894
 895         bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base);
 896         vc4_bo_dec_usecnt(bo);
 897 }
 898
 899 static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = {
 900         .atomic_check = vc4_plane_atomic_check,
 901         .atomic_update = vc4_plane_atomic_update,
 902         .prepare_fb = vc4_prepare_fb,
 903         .cleanup_fb = vc4_cleanup_fb,
 904         .atomic_async_check = vc4_plane_atomic_async_check,
 905         .atomic_async_update = vc4_plane_atomic_async_update,
 906 };
 907
 908 static void vc4_plane_destroy(struct drm_plane *plane)
 909 {
 910         drm_plane_helper_disable(plane, NULL);
 911         drm_plane_cleanup(plane);
 912 }
 913
 914 static bool vc4_format_mod_supported(struct drm_plane *plane,
 915                                      uint32_t format,
 916                                      uint64_t modifier)
 917 {
 918         /* Support T_TILING for RGB formats only. */
 919         switch (format) {
 920         case DRM_FORMAT_XRGB8888:
 921         case DRM_FORMAT_ARGB8888:
 922         case DRM_FORMAT_ABGR8888:
 923         case DRM_FORMAT_XBGR8888:
 924         case DRM_FORMAT_RGB565:
 925         case DRM_FORMAT_BGR565:
 926         case DRM_FORMAT_ARGB1555:
 927         case DRM_FORMAT_XRGB1555:
 928                 switch (fourcc_mod_broadcom_mod(modifier)) {
 929                 case DRM_FORMAT_MOD_LINEAR:
 930                 case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
 931                 case DRM_FORMAT_MOD_BROADCOM_SAND64:
 932                 case DRM_FORMAT_MOD_BROADCOM_SAND128:
 933                         return true;
 934                 default:
 935                         return false;
 936                 }
 937         case DRM_FORMAT_NV12:
 938         case DRM_FORMAT_NV21:
 939                 switch (fourcc_mod_broadcom_mod(modifier)) {
 940                 case DRM_FORMAT_MOD_LINEAR:
 941                 case DRM_FORMAT_MOD_BROADCOM_SAND64:
 942                 case DRM_FORMAT_MOD_BROADCOM_SAND128:
 943                 case DRM_FORMAT_MOD_BROADCOM_SAND256:
 944                         return true;
 945                 default:
 946                         return false;
 947                 }
 948         case DRM_FORMAT_YUV422:
 949         case DRM_FORMAT_YVU422:
 950         case DRM_FORMAT_YUV420:
 951         case DRM_FORMAT_YVU420:
 952         case DRM_FORMAT_NV16:
 953         case DRM_FORMAT_NV61:
 954         default:
 955                 return (modifier == DRM_FORMAT_MOD_LINEAR);
 956         }
 957 }
 958
 959 static const struct drm_plane_funcs vc4_plane_funcs = {
 960         .update_plane = drm_atomic_helper_update_plane,
 961         .disable_plane = drm_atomic_helper_disable_plane,
 962         .destroy = vc4_plane_destroy,
 963         .set_property = NULL,
 964         .reset = vc4_plane_reset,
 965         .atomic_duplicate_state = vc4_plane_duplicate_state,
 966         .atomic_destroy_state = vc4_plane_destroy_state,
 967         .format_mod_supported = vc4_format_mod_supported,
 968 };
 969
 970 struct drm_plane *vc4_plane_init(struct drm_device *dev,
 971                                  enum drm_plane_type type)
 972 {
 973         struct drm_plane *plane = NULL;
 974         struct vc4_plane *vc4_plane;
 975         u32 formats[ARRAY_SIZE(hvs_formats)];
 976         u32 num_formats = 0;
 977         int ret = 0;
 978         unsigned i;
 979         static const uint64_t modifiers[] = {
 980                 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
 981                 DRM_FORMAT_MOD_BROADCOM_SAND128,
 982                 DRM_FORMAT_MOD_BROADCOM_SAND64,
 983                 DRM_FORMAT_MOD_BROADCOM_SAND256,
 984                 DRM_FORMAT_MOD_LINEAR,
 985                 DRM_FORMAT_MOD_INVALID
 986         };
 987
 988         vc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane),
 989                                  GFP_KERNEL);
 990         if (!vc4_plane)
 991                 return ERR_PTR(-ENOMEM);
 992
 993         for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
 994                 /* Don't allow YUV in cursor planes, since that means
 995                  * tuning on the scaler, which we don't allow for the
 996                  * cursor.
 997                  */
 998                 if (type != DRM_PLANE_TYPE_CURSOR ||
 999                     hvs_formats[i].hvs < HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE) {
1000                         formats[num_formats++] = hvs_formats[i].drm;
1001                 }
1002         }
1003         plane = &vc4_plane->base;
1004         ret = drm_universal_plane_init(dev, plane, 0,
1005                                        &vc4_plane_funcs,
1006                                        formats, num_formats,
1007                                        modifiers, type, NULL);
1008
1009         drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
1010
1011         drm_plane_create_alpha_property(plane);
1012
1013         return plane;
1014 }