1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Broadcom
9 * This is the general code for implementing KMS mode setting that
10 * doesn't clearly associate with any of the other objects (plane,
11 * crtc, HDMI encoder).
14 #include <linux/bitfield.h>
15 #include <linux/bitops.h>
16 #include <linux/clk.h>
18 #include <drm/drm_atomic.h>
19 #include <drm/drm_atomic_helper.h>
20 #include <drm/drm_crtc.h>
21 #include <drm/drm_gem_framebuffer_helper.h>
22 #include <drm/drm_plane_helper.h>
23 #include <drm/drm_probe_helper.h>
24 #include <drm/drm_vblank.h>
25 #include <drm/drm_drv.h>
30 struct vc4_ctm_state {
31 struct drm_private_state base;
32 struct drm_color_ctm *ctm;
36 static struct vc4_ctm_state *to_vc4_ctm_state(struct drm_private_state *priv)
38 return container_of(priv, struct vc4_ctm_state, base);
41 struct vc4_load_tracker_state {
42 struct drm_private_state base;
47 static struct vc4_load_tracker_state *
48 to_vc4_load_tracker_state(struct drm_private_state *priv)
50 return container_of(priv, struct vc4_load_tracker_state, base);
53 static struct vc4_ctm_state *vc4_get_ctm_state(struct drm_atomic_state *state,
54 struct drm_private_obj *manager)
56 struct drm_device *dev = state->dev;
57 struct vc4_dev *vc4 = dev->dev_private;
58 struct drm_private_state *priv_state;
61 ret = drm_modeset_lock(&vc4->ctm_state_lock, state->acquire_ctx);
65 priv_state = drm_atomic_get_private_obj_state(state, manager);
66 if (IS_ERR(priv_state))
67 return ERR_CAST(priv_state);
69 return to_vc4_ctm_state(priv_state);
72 static struct drm_private_state *
73 vc4_ctm_duplicate_state(struct drm_private_obj *obj)
75 struct vc4_ctm_state *state;
77 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
81 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
86 static void vc4_ctm_destroy_state(struct drm_private_obj *obj,
87 struct drm_private_state *state)
89 struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(state);
94 static const struct drm_private_state_funcs vc4_ctm_state_funcs = {
95 .atomic_duplicate_state = vc4_ctm_duplicate_state,
96 .atomic_destroy_state = vc4_ctm_destroy_state,
99 /* Converts a DRM S31.32 value to the HW S0.9 format. */
100 static u16 vc4_ctm_s31_32_to_s0_9(u64 in)
105 r = in & BIT_ULL(63) ? BIT(9) : 0;
107 if ((in & GENMASK_ULL(62, 32)) > 0) {
108 /* We have zero integer bits so we can only saturate here. */
111 /* Otherwise take the 9 most important fractional bits. */
112 r |= (in >> 23) & GENMASK(8, 0);
119 vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state)
121 struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state);
122 struct drm_color_ctm *ctm = ctm_state->ctm;
124 if (vc4->firmware_kms)
127 if (ctm_state->fifo) {
128 HVS_WRITE(SCALER_OLEDCOEF2,
129 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]),
130 SCALER_OLEDCOEF2_R_TO_R) |
131 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]),
132 SCALER_OLEDCOEF2_R_TO_G) |
133 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]),
134 SCALER_OLEDCOEF2_R_TO_B));
135 HVS_WRITE(SCALER_OLEDCOEF1,
136 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]),
137 SCALER_OLEDCOEF1_G_TO_R) |
138 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]),
139 SCALER_OLEDCOEF1_G_TO_G) |
140 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]),
141 SCALER_OLEDCOEF1_G_TO_B));
142 HVS_WRITE(SCALER_OLEDCOEF0,
143 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]),
144 SCALER_OLEDCOEF0_B_TO_R) |
145 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]),
146 SCALER_OLEDCOEF0_B_TO_G) |
147 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]),
148 SCALER_OLEDCOEF0_B_TO_B));
151 HVS_WRITE(SCALER_OLEDOFFS,
152 VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO));
155 static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4,
156 struct drm_atomic_state *state)
158 struct drm_crtc_state *crtc_state;
159 struct drm_crtc *crtc;
162 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
163 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
167 if (!crtc_state->active)
170 if (vc4_state->assigned_channel != 2)
174 * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
176 * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
178 * DSP3 is connected to FIFO2 unless the transposer is
179 * enabled. In this case, FIFO 2 is directly accessed by the
180 * TXP IP, and we need to disable the FIFO2 -> pixelvalve1
183 if (vc4_state->feed_txp)
184 dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
186 dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
188 dispctrl = HVS_READ(SCALER_DISPCTRL) &
189 ~SCALER_DISPCTRL_DSP3_MUX_MASK;
190 HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
194 static struct drm_crtc_state *
195 drm_atomic_get_new_or_current_crtc_state(struct drm_atomic_state *state,
196 struct drm_crtc *crtc)
198 struct drm_crtc_state *crtc_state;
200 crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
207 #define for_each_new_or_current_crtc_state(__state, crtc, crtc_state) \
208 list_for_each_entry(crtc, &__state->dev->mode_config.crtc_list, head) \
209 for_each_if(crtc_state = drm_atomic_get_new_or_current_crtc_state(__state, crtc))
211 static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4,
212 struct drm_atomic_state *state)
214 struct drm_crtc_state *crtc_state;
215 struct drm_crtc *crtc;
216 unsigned char dsp2_mux = 0;
217 unsigned char dsp3_mux = 3;
218 unsigned char dsp4_mux = 3;
219 unsigned char dsp5_mux = 3;
222 for_each_new_or_current_crtc_state(state, crtc, crtc_state) {
223 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
224 struct vc4_crtc_state *vc4_state;
226 if (!crtc_state->active)
229 vc4_state = to_vc4_crtc_state(crtc_state);
230 switch (vc4_crtc->data->hvs_output) {
232 dsp2_mux = (vc4_state->assigned_channel == 2) ? 0 : 1;
236 dsp3_mux = vc4_state->assigned_channel;
240 dsp4_mux = vc4_state->assigned_channel;
244 dsp5_mux = vc4_state->assigned_channel;
252 reg = HVS_READ(SCALER_DISPECTRL);
253 HVS_WRITE(SCALER_DISPECTRL,
254 (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) |
255 VC4_SET_FIELD(dsp2_mux, SCALER_DISPECTRL_DSP2_MUX));
257 reg = HVS_READ(SCALER_DISPCTRL);
258 HVS_WRITE(SCALER_DISPCTRL,
259 (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) |
260 VC4_SET_FIELD(dsp3_mux, SCALER_DISPCTRL_DSP3_MUX));
262 reg = HVS_READ(SCALER_DISPEOLN);
263 HVS_WRITE(SCALER_DISPEOLN,
264 (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) |
265 VC4_SET_FIELD(dsp4_mux, SCALER_DISPEOLN_DSP4_MUX));
267 reg = HVS_READ(SCALER_DISPDITHER);
268 HVS_WRITE(SCALER_DISPDITHER,
269 (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) |
270 VC4_SET_FIELD(dsp5_mux, SCALER_DISPDITHER_DSP5_MUX));
275 vc4_atomic_complete_commit(struct drm_atomic_state *state)
277 struct drm_device *dev = state->dev;
278 struct vc4_dev *vc4 = to_vc4_dev(dev);
279 struct vc4_hvs *hvs = vc4->hvs;
280 struct vc4_crtc *vc4_crtc;
283 for (i = 0; vc4->hvs && i < dev->mode_config.num_crtc; i++) {
284 struct __drm_crtcs_state *_state = &state->crtcs[i];
285 struct vc4_crtc_state *vc4_crtc_state;
287 if (!_state->ptr || !_state->commit)
290 vc4_crtc = to_vc4_crtc(_state->ptr);
291 vc4_crtc_state = to_vc4_crtc_state(_state->state);
292 vc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel);
296 clk_set_min_rate(hvs->core_clk, 500000000);
298 drm_atomic_helper_wait_for_fences(dev, state, false);
300 drm_atomic_helper_wait_for_dependencies(state);
302 drm_atomic_helper_commit_modeset_disables(dev, state);
304 vc4_ctm_commit(vc4, state);
307 vc5_hvs_pv_muxing_commit(vc4, state);
309 vc4_hvs_pv_muxing_commit(vc4, state);
311 drm_atomic_helper_commit_planes(dev, state, 0);
313 drm_atomic_helper_commit_modeset_enables(dev, state);
315 drm_atomic_helper_fake_vblank(state);
317 drm_atomic_helper_commit_hw_done(state);
319 drm_atomic_helper_wait_for_flip_done(dev, state);
321 drm_atomic_helper_cleanup_planes(dev, state);
323 drm_atomic_helper_commit_cleanup_done(state);
325 drm_atomic_state_put(state);
327 up(&vc4->async_modeset);
330 static void commit_work(struct work_struct *work)
332 struct drm_atomic_state *state = container_of(work,
333 struct drm_atomic_state,
335 vc4_atomic_complete_commit(state);
339 * vc4_atomic_commit - commit validated state object
341 * @state: the driver state object
342 * @nonblock: nonblocking commit
344 * This function commits a with drm_atomic_helper_check() pre-validated state
345 * object. This can still fail when e.g. the framebuffer reservation fails. For
346 * now this doesn't implement asynchronous commits.
349 * Zero for success or -errno.
351 static int vc4_atomic_commit(struct drm_device *dev,
352 struct drm_atomic_state *state,
355 struct vc4_dev *vc4 = to_vc4_dev(dev);
358 if (state->async_update) {
359 ret = down_interruptible(&vc4->async_modeset);
363 ret = drm_atomic_helper_prepare_planes(dev, state);
365 up(&vc4->async_modeset);
369 drm_atomic_helper_async_commit(dev, state);
371 drm_atomic_helper_cleanup_planes(dev, state);
373 up(&vc4->async_modeset);
378 /* We know for sure we don't want an async update here. Set
379 * state->legacy_cursor_update to false to prevent
380 * drm_atomic_helper_setup_commit() from auto-completing
383 if (!vc4->firmware_kms)
384 state->legacy_cursor_update = false;
385 ret = drm_atomic_helper_setup_commit(state, nonblock);
389 INIT_WORK(&state->commit_work, commit_work);
391 ret = down_interruptible(&vc4->async_modeset);
395 ret = drm_atomic_helper_prepare_planes(dev, state);
397 up(&vc4->async_modeset);
402 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
404 drm_atomic_helper_cleanup_planes(dev, state);
405 up(&vc4->async_modeset);
411 * This is the point of no return - everything below never fails except
412 * when the hw goes bonghits. Which means we can commit the new state on
413 * the software side now.
416 BUG_ON(drm_atomic_helper_swap_state(state, false) < 0);
419 * Everything below can be run asynchronously without the need to grab
420 * any modeset locks at all under one condition: It must be guaranteed
421 * that the asynchronous work has either been cancelled (if the driver
422 * supports it, which at least requires that the framebuffers get
423 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
424 * before the new state gets committed on the software side with
425 * drm_atomic_helper_swap_state().
427 * This scheme allows new atomic state updates to be prepared and
428 * checked in parallel to the asynchronous completion of the previous
429 * update. Which is important since compositors need to figure out the
430 * composition of the next frame right after having submitted the
434 drm_atomic_state_get(state);
436 queue_work(system_unbound_wq, &state->commit_work);
438 vc4_atomic_complete_commit(state);
443 static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev,
444 struct drm_file *file_priv,
445 const struct drm_mode_fb_cmd2 *mode_cmd)
447 struct drm_mode_fb_cmd2 mode_cmd_local;
449 /* If the user didn't specify a modifier, use the
450 * vc4_set_tiling_ioctl() state for the BO.
452 if (!(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) {
453 struct drm_gem_object *gem_obj;
456 gem_obj = drm_gem_object_lookup(file_priv,
457 mode_cmd->handles[0]);
459 DRM_DEBUG("Failed to look up GEM BO %d\n",
460 mode_cmd->handles[0]);
461 return ERR_PTR(-ENOENT);
463 bo = to_vc4_bo(gem_obj);
465 mode_cmd_local = *mode_cmd;
468 mode_cmd_local.modifier[0] =
469 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED;
471 mode_cmd_local.modifier[0] = DRM_FORMAT_MOD_NONE;
474 drm_gem_object_put_unlocked(gem_obj);
476 mode_cmd = &mode_cmd_local;
479 return drm_gem_fb_create(dev, file_priv, mode_cmd);
482 /* Our CTM has some peculiar limitations: we can only enable it for one CRTC
483 * at a time and the HW only supports S0.9 scalars. To account for the latter,
484 * we don't allow userland to set a CTM that we have no hope of approximating.
487 vc4_ctm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
489 struct vc4_dev *vc4 = to_vc4_dev(dev);
490 struct vc4_ctm_state *ctm_state = NULL;
491 struct drm_crtc *crtc;
492 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
493 struct drm_color_ctm *ctm;
496 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
497 /* CTM is being disabled. */
498 if (!new_crtc_state->ctm && old_crtc_state->ctm) {
499 ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
500 if (IS_ERR(ctm_state))
501 return PTR_ERR(ctm_state);
506 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
507 if (new_crtc_state->ctm == old_crtc_state->ctm)
511 ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
512 if (IS_ERR(ctm_state))
513 return PTR_ERR(ctm_state);
516 /* CTM is being enabled or the matrix changed. */
517 if (new_crtc_state->ctm) {
518 struct vc4_crtc_state *vc4_crtc_state =
519 to_vc4_crtc_state(new_crtc_state);
521 /* fifo is 1-based since 0 disables CTM. */
522 int fifo = vc4_crtc_state->assigned_channel + 1;
524 /* Check userland isn't trying to turn on CTM for more
525 * than one CRTC at a time.
527 if (ctm_state->fifo && ctm_state->fifo != fifo) {
528 DRM_DEBUG_DRIVER("Too many CTM configured\n");
532 /* Check we can approximate the specified CTM.
533 * We disallow scalars |c| > 1.0 since the HW has
536 ctm = new_crtc_state->ctm->data;
537 for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) {
538 u64 val = ctm->matrix[i];
541 if (val > BIT_ULL(32))
545 ctm_state->fifo = fifo;
546 ctm_state->ctm = ctm;
553 static int vc4_load_tracker_atomic_check(struct drm_atomic_state *state)
555 struct drm_plane_state *old_plane_state, *new_plane_state;
556 struct vc4_dev *vc4 = to_vc4_dev(state->dev);
557 struct vc4_load_tracker_state *load_state;
558 struct drm_private_state *priv_state;
559 struct drm_plane *plane;
562 if (!vc4->load_tracker_available)
565 priv_state = drm_atomic_get_private_obj_state(state,
567 if (IS_ERR(priv_state))
568 return PTR_ERR(priv_state);
570 load_state = to_vc4_load_tracker_state(priv_state);
571 for_each_oldnew_plane_in_state(state, plane, old_plane_state,
572 new_plane_state, i) {
573 struct vc4_plane_state *vc4_plane_state;
575 if (old_plane_state->fb && old_plane_state->crtc) {
576 vc4_plane_state = to_vc4_plane_state(old_plane_state);
577 load_state->membus_load -= vc4_plane_state->membus_load;
578 load_state->hvs_load -= vc4_plane_state->hvs_load;
581 if (new_plane_state->fb && new_plane_state->crtc) {
582 vc4_plane_state = to_vc4_plane_state(new_plane_state);
583 load_state->membus_load += vc4_plane_state->membus_load;
584 load_state->hvs_load += vc4_plane_state->hvs_load;
588 /* Don't check the load when the tracker is disabled. */
589 if (!vc4->load_tracker_enabled)
592 /* The absolute limit is 2Gbyte/sec, but let's take a margin to let
593 * the system work when other blocks are accessing the memory.
595 if (load_state->membus_load > SZ_1G + SZ_512M)
598 /* HVS clock is supposed to run @ 250Mhz, let's take a margin and
599 * consider the maximum number of cycles is 240M.
601 if (load_state->hvs_load > 240000000ULL)
607 static struct drm_private_state *
608 vc4_load_tracker_duplicate_state(struct drm_private_obj *obj)
610 struct vc4_load_tracker_state *state;
612 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
616 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
621 static void vc4_load_tracker_destroy_state(struct drm_private_obj *obj,
622 struct drm_private_state *state)
624 struct vc4_load_tracker_state *load_state;
626 load_state = to_vc4_load_tracker_state(state);
630 static const struct drm_private_state_funcs vc4_load_tracker_state_funcs = {
631 .atomic_duplicate_state = vc4_load_tracker_duplicate_state,
632 .atomic_destroy_state = vc4_load_tracker_destroy_state,
635 #define NUM_OUTPUTS 6
636 #define NUM_CHANNELS 3
639 * The BCM2711 HVS has up to 7 output connected to the pixelvalves and
640 * the TXP (and therefore all the CRTCs found on that platform).
642 * The naive (and our initial) implementation would just iterate over
643 * all the active CRTCs, try to find a suitable FIFO, and then remove it
644 * from the available FIFOs pool. However, there's a few corner cases
645 * that need to be considered:
647 * - When running in a dual-display setup (so with two CRTCs involved),
648 * we can update the state of a single CRTC (for example by changing
649 * its mode using xrandr under X11) without affecting the other. In
650 * this case, the other CRTC wouldn't be in the state at all, so we
651 * need to consider all the running CRTCs in the DRM device to assign
652 * a FIFO, not just the one in the state.
654 * - To fix the above, we can't use drm_atomic_get_crtc_state on all
655 * enabled CRTCs to pull their CRTC state into the global state, since
656 * a page flip would start considering their vblank to complete. Since
657 * we don't have a guarantee that they are actually active, that
658 * vblank might never happen, and shouldn't even be considered if we
659 * want to do a page flip on a single CRTC. That can be tested by
660 * doing a modetest -v first on HDMI1 and then on HDMI0.
662 * - Since we need the pixelvalve to be disabled and enabled back when
663 * the FIFO is changed, we should keep the FIFO assigned for as long
664 * as the CRTC is enabled, only considering it free again once that
665 * CRTC has been disabled. This can be tested by booting X11 on a
666 * single display, and changing the resolution down and then back up.
668 static int vc4_pv_muxing_atomic_check(struct drm_device *dev,
669 struct drm_atomic_state *state)
671 unsigned long unassigned_channels = GENMASK(NUM_CHANNELS - 1, 0);
672 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
673 struct drm_crtc_state *crtc_state;
674 struct drm_crtc *crtc;
678 * Since the HVS FIFOs are shared across all the pixelvalves and
679 * the TXP (and thus all the CRTCs), we need to pull the current
680 * state of all the enabled CRTCs so that an update to a single
681 * CRTC still keeps the previous FIFOs enabled and assigned to
682 * the same CRTCs, instead of evaluating only the CRTC being
685 for_each_new_or_current_crtc_state(state, crtc, crtc_state) {
686 struct vc4_crtc_state *vc4_crtc_state;
687 if (!crtc_state->enable)
690 vc4_crtc_state = to_vc4_crtc_state(crtc_state);
691 unassigned_channels &= ~BIT(vc4_crtc_state->assigned_channel);
694 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
695 struct vc4_crtc_state *new_vc4_crtc_state =
696 to_vc4_crtc_state(new_crtc_state);
697 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
698 bool is_assigned = false;
699 unsigned int channel;
701 if (old_crtc_state->enable && !new_crtc_state->enable)
702 new_vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
704 if (!new_crtc_state->enable)
707 if (new_vc4_crtc_state->assigned_channel != VC4_HVS_CHANNEL_DISABLED)
711 * The problem we have to solve here is that we have
712 * up to 7 encoders, connected to up to 6 CRTCs.
714 * Those CRTCs, depending on the instance, can be
715 * routed to 1, 2 or 3 HVS FIFOs, and we need to set
716 * the change the muxing between FIFOs and outputs in
717 * the HVS accordingly.
719 * It would be pretty hard to come up with an
720 * algorithm that would generically solve
721 * this. However, the current routing trees we support
722 * allow us to simplify a bit the problem.
724 * Indeed, with the current supported layouts, if we
725 * try to assign in the ascending crtc index order the
726 * FIFOs, we can't fall into the situation where an
727 * earlier CRTC that had multiple routes is assigned
728 * one that was the only option for a later CRTC.
730 * If the layout changes and doesn't give us that in
731 * the future, we will need to have something smarter,
732 * but it works so far.
734 for_each_set_bit(channel, &unassigned_channels,
735 sizeof(unassigned_channels)) {
737 if (!(BIT(channel) & vc4_crtc->data->hvs_available_channels))
740 new_vc4_crtc_state->assigned_channel = channel;
741 unassigned_channels &= ~BIT(channel);
754 vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
758 ret = vc4_pv_muxing_atomic_check(dev, state);
762 ret = vc4_ctm_atomic_check(dev, state);
766 ret = drm_atomic_helper_check(dev, state);
770 return vc4_load_tracker_atomic_check(state);
773 static const struct drm_mode_config_funcs vc4_mode_funcs = {
774 .atomic_check = vc4_atomic_check,
775 .atomic_commit = vc4_atomic_commit,
776 .fb_create = vc4_fb_create,
779 int vc4_kms_load(struct drm_device *dev)
781 struct vc4_dev *vc4 = to_vc4_dev(dev);
782 struct vc4_ctm_state *ctm_state;
783 struct vc4_load_tracker_state *load_state;
786 if (!of_device_is_compatible(dev->dev->of_node, "brcm,bcm2711-vc5")) {
787 vc4->load_tracker_available = true;
789 /* Start with the load tracker enabled. Can be
790 * disabled through the debugfs load_tracker file.
792 vc4->load_tracker_enabled = true;
795 sema_init(&vc4->async_modeset, 1);
797 /* Set support for vblank irq fast disable, before drm_vblank_init() */
798 dev->vblank_disable_immediate = true;
800 dev->irq_enabled = true;
801 ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
803 dev_err(dev->dev, "failed to initialize vblank\n");
807 if (!drm_core_check_feature(dev, DRIVER_RENDER)) {
808 /* No V3D as part of vc4. Assume this is Pi4. */
809 dev->mode_config.max_width = 7680;
810 dev->mode_config.max_height = 7680;
812 dev->mode_config.max_width = 2048;
813 dev->mode_config.max_height = 2048;
815 dev->mode_config.funcs = &vc4_mode_funcs;
816 dev->mode_config.preferred_depth = 24;
817 dev->mode_config.async_page_flip = true;
818 dev->mode_config.allow_fb_modifiers = true;
819 dev->mode_config.normalize_zpos = true;
821 drm_modeset_lock_init(&vc4->ctm_state_lock);
823 ctm_state = kzalloc(sizeof(*ctm_state), GFP_KERNEL);
827 drm_atomic_private_obj_init(dev, &vc4->ctm_manager, &ctm_state->base,
828 &vc4_ctm_state_funcs);
830 if (vc4->load_tracker_available) {
831 load_state = kzalloc(sizeof(*load_state), GFP_KERNEL);
833 drm_atomic_private_obj_fini(&vc4->ctm_manager);
837 drm_atomic_private_obj_init(dev, &vc4->load_tracker,
839 &vc4_load_tracker_state_funcs);
842 drm_mode_config_reset(dev);
844 drm_kms_helper_poll_init(dev);