drivers/gpu/drm/vc4/vc4_kms.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 KMS
   8  *
   9  * This is the general code for implementing KMS mode setting that
  10  * doesn't clearly associate with any of the other objects (plane,
  11  * crtc, HDMI encoder).
  12  */
  13
  14 #include <linux/bitfield.h>
  15 #include <linux/bitops.h>
  16 #include <linux/clk.h>
  17
  18 #include <drm/drm_atomic.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_crtc.h>
  21 #include <drm/drm_gem_framebuffer_helper.h>
  22 #include <drm/drm_plane_helper.h>
  23 #include <drm/drm_probe_helper.h>
  24 #include <drm/drm_vblank.h>
  25 #include <drm/drm_drv.h>
  26
  27 #include "vc4_drv.h"
  28 #include "vc4_regs.h"
  29
  30 struct vc4_ctm_state {
  31         struct drm_private_state base;
  32         struct drm_color_ctm *ctm;
  33         int fifo;
  34 };
  35
  36 static struct vc4_ctm_state *to_vc4_ctm_state(struct drm_private_state *priv)
  37 {
  38         return container_of(priv, struct vc4_ctm_state, base);
  39 }
  40
  41 struct vc4_load_tracker_state {
  42         struct drm_private_state base;
  43         u64 hvs_load;
  44         u64 membus_load;
  45 };
  46
  47 static struct vc4_load_tracker_state *
  48 to_vc4_load_tracker_state(struct drm_private_state *priv)
  49 {
  50         return container_of(priv, struct vc4_load_tracker_state, base);
  51 }
  52
  53 static struct vc4_ctm_state *vc4_get_ctm_state(struct drm_atomic_state *state,
  54                                                struct drm_private_obj *manager)
  55 {
  56         struct drm_device *dev = state->dev;
  57         struct vc4_dev *vc4 = dev->dev_private;
  58         struct drm_private_state *priv_state;
  59         int ret;
  60
  61         ret = drm_modeset_lock(&vc4->ctm_state_lock, state->acquire_ctx);
  62         if (ret)
  63                 return ERR_PTR(ret);
  64
  65         priv_state = drm_atomic_get_private_obj_state(state, manager);
  66         if (IS_ERR(priv_state))
  67                 return ERR_CAST(priv_state);
  68
  69         return to_vc4_ctm_state(priv_state);
  70 }
  71
  72 static struct drm_private_state *
  73 vc4_ctm_duplicate_state(struct drm_private_obj *obj)
  74 {
  75         struct vc4_ctm_state *state;
  76
  77         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
  78         if (!state)
  79                 return NULL;
  80
  81         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
  82
  83         return &state->base;
  84 }
  85
  86 static void vc4_ctm_destroy_state(struct drm_private_obj *obj,
  87                                   struct drm_private_state *state)
  88 {
  89         struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(state);
  90
  91         kfree(ctm_state);
  92 }
  93
  94 static const struct drm_private_state_funcs vc4_ctm_state_funcs = {
  95         .atomic_duplicate_state = vc4_ctm_duplicate_state,
  96         .atomic_destroy_state = vc4_ctm_destroy_state,
  97 };
  98
  99 /* Converts a DRM S31.32 value to the HW S0.9 format. */
 100 static u16 vc4_ctm_s31_32_to_s0_9(u64 in)
 101 {
 102         u16 r;
 103
 104         /* Sign bit. */
 105         r = in & BIT_ULL(63) ? BIT(9) : 0;
 106
 107         if ((in & GENMASK_ULL(62, 32)) > 0) {
 108                 /* We have zero integer bits so we can only saturate here. */
 109                 r |= GENMASK(8, 0);
 110         } else {
 111                 /* Otherwise take the 9 most important fractional bits. */
 112                 r |= (in >> 23) & GENMASK(8, 0);
 113         }
 114
 115         return r;
 116 }
 117
 118 static void
 119 vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state)
 120 {
 121         struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state);
 122         struct drm_color_ctm *ctm = ctm_state->ctm;
 123
 124         if (vc4->firmware_kms)
 125                 return;
 126
 127         if (ctm_state->fifo) {
 128                 HVS_WRITE(SCALER_OLEDCOEF2,
 129                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]),
 130                                         SCALER_OLEDCOEF2_R_TO_R) |
 131                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]),
 132                                         SCALER_OLEDCOEF2_R_TO_G) |
 133                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]),
 134                                         SCALER_OLEDCOEF2_R_TO_B));
 135                 HVS_WRITE(SCALER_OLEDCOEF1,
 136                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]),
 137                                         SCALER_OLEDCOEF1_G_TO_R) |
 138                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]),
 139                                         SCALER_OLEDCOEF1_G_TO_G) |
 140                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]),
 141                                         SCALER_OLEDCOEF1_G_TO_B));
 142                 HVS_WRITE(SCALER_OLEDCOEF0,
 143                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]),
 144                                         SCALER_OLEDCOEF0_B_TO_R) |
 145                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]),
 146                                         SCALER_OLEDCOEF0_B_TO_G) |
 147                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]),
 148                                         SCALER_OLEDCOEF0_B_TO_B));
 149         }
 150
 151         HVS_WRITE(SCALER_OLEDOFFS,
 152                   VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO));
 153 }
 154
 155 static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4,
 156                                      struct drm_atomic_state *state)
 157 {
 158         struct drm_crtc_state *crtc_state;
 159         struct drm_crtc *crtc;
 160         unsigned char dsp2_mux = 0;
 161         unsigned char dsp3_mux = 3;
 162         unsigned char dsp4_mux = 3;
 163         unsigned char dsp5_mux = 3;
 164         unsigned int i;
 165         u32 reg;
 166
 167         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 168                 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 169                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 170
 171                 if (!crtc_state->active)
 172                         continue;
 173
 174                 switch (vc4_crtc->data->hvs_output) {
 175                 case 2:
 176                         dsp2_mux = (vc4_state->assigned_channel == 2) ? 1 : 0;
 177                         break;
 178
 179                 case 3:
 180                         dsp3_mux = vc4_state->assigned_channel;
 181                         break;
 182
 183                 case 4:
 184                         dsp4_mux = vc4_state->assigned_channel;
 185                         break;
 186
 187                 case 5:
 188                         dsp5_mux = vc4_state->assigned_channel;
 189                         break;
 190
 191                 default:
 192                         break;
 193                 }
 194         }
 195
 196         reg = HVS_READ(SCALER_DISPECTRL);
 197         if (FIELD_GET(SCALER_DISPECTRL_DSP2_MUX_MASK, reg) != dsp2_mux)
 198                 HVS_WRITE(SCALER_DISPECTRL,
 199                           (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) |
 200                           VC4_SET_FIELD(dsp2_mux, SCALER_DISPECTRL_DSP2_MUX));
 201
 202         reg = HVS_READ(SCALER_DISPCTRL);
 203         if (FIELD_GET(SCALER_DISPCTRL_DSP3_MUX_MASK, reg) != dsp3_mux)
 204                 HVS_WRITE(SCALER_DISPCTRL,
 205                           (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) |
 206                           VC4_SET_FIELD(dsp3_mux, SCALER_DISPCTRL_DSP3_MUX));
 207
 208         reg = HVS_READ(SCALER_DISPEOLN);
 209         if (FIELD_GET(SCALER_DISPEOLN_DSP4_MUX_MASK, reg) != dsp4_mux)
 210                 HVS_WRITE(SCALER_DISPEOLN,
 211                           (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) |
 212                           VC4_SET_FIELD(dsp4_mux, SCALER_DISPEOLN_DSP4_MUX));
 213
 214         reg = HVS_READ(SCALER_DISPDITHER);
 215         if (FIELD_GET(SCALER_DISPDITHER_DSP5_MUX_MASK, reg) != dsp5_mux)
 216                 HVS_WRITE(SCALER_DISPDITHER,
 217                           (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) |
 218                           VC4_SET_FIELD(dsp5_mux, SCALER_DISPDITHER_DSP5_MUX));
 219 }
 220
 221 static void
 222 vc4_atomic_complete_commit(struct drm_atomic_state *state)
 223 {
 224         struct drm_device *dev = state->dev;
 225         struct vc4_dev *vc4 = to_vc4_dev(dev);
 226         struct vc4_hvs *hvs = vc4->hvs;
 227         struct vc4_crtc *vc4_crtc;
 228         int i;
 229
 230         for (i = 0; vc4->hvs && i < dev->mode_config.num_crtc; i++) {
 231                 struct __drm_crtcs_state *_state = &state->crtcs[i];
 232                 struct vc4_crtc_state *vc4_crtc_state;
 233
 234                 if (!_state->ptr || !_state->commit)
 235                         continue;
 236
 237                 vc4_crtc = to_vc4_crtc(_state->ptr);
 238                 vc4_crtc_state = to_vc4_crtc_state(_state->state);
 239                 vc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel);
 240         }
 241
 242         if (vc4->hvs->hvs5)
 243                 clk_set_min_rate(hvs->core_clk, 500000000);
 244
 245         drm_atomic_helper_wait_for_fences(dev, state, false);
 246
 247         drm_atomic_helper_wait_for_dependencies(state);
 248
 249         drm_atomic_helper_commit_modeset_disables(dev, state);
 250
 251         if (!vc4->firmware_kms) {
 252                 vc4_ctm_commit(vc4, state);
 253                 vc4_hvs_pv_muxing_commit(vc4, state);
 254         }
 255
 256         drm_atomic_helper_commit_planes(dev, state, 0);
 257
 258         drm_atomic_helper_commit_modeset_enables(dev, state);
 259
 260         drm_atomic_helper_fake_vblank(state);
 261
 262         drm_atomic_helper_commit_hw_done(state);
 263
 264         drm_atomic_helper_wait_for_flip_done(dev, state);
 265
 266         drm_atomic_helper_cleanup_planes(dev, state);
 267
 268         drm_atomic_helper_commit_cleanup_done(state);
 269
 270         drm_atomic_state_put(state);
 271
 272         up(&vc4->async_modeset);
 273 }
 274
 275 static void commit_work(struct work_struct *work)
 276 {
 277         struct drm_atomic_state *state = container_of(work,
 278                                                       struct drm_atomic_state,
 279                                                       commit_work);
 280         vc4_atomic_complete_commit(state);
 281 }
 282
 283 /**
 284  * vc4_atomic_commit - commit validated state object
 285  * @dev: DRM device
 286  * @state: the driver state object
 287  * @nonblock: nonblocking commit
 288  *
 289  * This function commits a with drm_atomic_helper_check() pre-validated state
 290  * object. This can still fail when e.g. the framebuffer reservation fails. For
 291  * now this doesn't implement asynchronous commits.
 292  *
 293  * RETURNS
 294  * Zero for success or -errno.
 295  */
 296 static int vc4_atomic_commit(struct drm_device *dev,
 297                              struct drm_atomic_state *state,
 298                              bool nonblock)
 299 {
 300         struct vc4_dev *vc4 = to_vc4_dev(dev);
 301         int ret;
 302
 303         if (state->async_update) {
 304                 ret = down_interruptible(&vc4->async_modeset);
 305                 if (ret)
 306                         return ret;
 307
 308                 ret = drm_atomic_helper_prepare_planes(dev, state);
 309                 if (ret) {
 310                         up(&vc4->async_modeset);
 311                         return ret;
 312                 }
 313
 314                 drm_atomic_helper_async_commit(dev, state);
 315
 316                 drm_atomic_helper_cleanup_planes(dev, state);
 317
 318                 up(&vc4->async_modeset);
 319
 320                 return 0;
 321         }
 322
 323         /* We know for sure we don't want an async update here. Set
 324          * state->legacy_cursor_update to false to prevent
 325          * drm_atomic_helper_setup_commit() from auto-completing
 326          * commit->flip_done.
 327          */
 328         if (!vc4->firmware_kms)
 329                 state->legacy_cursor_update = false;
 330         ret = drm_atomic_helper_setup_commit(state, nonblock);
 331         if (ret)
 332                 return ret;
 333
 334         INIT_WORK(&state->commit_work, commit_work);
 335
 336         ret = down_interruptible(&vc4->async_modeset);
 337         if (ret)
 338                 return ret;
 339
 340         ret = drm_atomic_helper_prepare_planes(dev, state);
 341         if (ret) {
 342                 up(&vc4->async_modeset);
 343                 return ret;
 344         }
 345
 346         if (!nonblock) {
 347                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
 348                 if (ret) {
 349                         drm_atomic_helper_cleanup_planes(dev, state);
 350                         up(&vc4->async_modeset);
 351                         return ret;
 352                 }
 353         }
 354
 355         /*
 356          * This is the point of no return - everything below never fails except
 357          * when the hw goes bonghits. Which means we can commit the new state on
 358          * the software side now.
 359          */
 360
 361         BUG_ON(drm_atomic_helper_swap_state(state, false) < 0);
 362
 363         /*
 364          * Everything below can be run asynchronously without the need to grab
 365          * any modeset locks at all under one condition: It must be guaranteed
 366          * that the asynchronous work has either been cancelled (if the driver
 367          * supports it, which at least requires that the framebuffers get
 368          * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
 369          * before the new state gets committed on the software side with
 370          * drm_atomic_helper_swap_state().
 371          *
 372          * This scheme allows new atomic state updates to be prepared and
 373          * checked in parallel to the asynchronous completion of the previous
 374          * update. Which is important since compositors need to figure out the
 375          * composition of the next frame right after having submitted the
 376          * current layout.
 377          */
 378
 379         drm_atomic_state_get(state);
 380         if (nonblock)
 381                 queue_work(system_unbound_wq, &state->commit_work);
 382         else
 383                 vc4_atomic_complete_commit(state);
 384
 385         return 0;
 386 }
 387
 388 static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev,
 389                                              struct drm_file *file_priv,
 390                                              const struct drm_mode_fb_cmd2 *mode_cmd)
 391 {
 392         struct drm_mode_fb_cmd2 mode_cmd_local;
 393
 394         /* If the user didn't specify a modifier, use the
 395          * vc4_set_tiling_ioctl() state for the BO.
 396          */
 397         if (!(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) {
 398                 struct drm_gem_object *gem_obj;
 399                 struct vc4_bo *bo;
 400
 401                 gem_obj = drm_gem_object_lookup(file_priv,
 402                                                 mode_cmd->handles[0]);
 403                 if (!gem_obj) {
 404                         DRM_DEBUG("Failed to look up GEM BO %d\n",
 405                                   mode_cmd->handles[0]);
 406                         return ERR_PTR(-ENOENT);
 407                 }
 408                 bo = to_vc4_bo(gem_obj);
 409
 410                 mode_cmd_local = *mode_cmd;
 411
 412                 if (bo->t_format) {
 413                         mode_cmd_local.modifier[0] =
 414                                 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED;
 415                 } else {
 416                         mode_cmd_local.modifier[0] = DRM_FORMAT_MOD_NONE;
 417                 }
 418
 419                 drm_gem_object_put_unlocked(gem_obj);
 420
 421                 mode_cmd = &mode_cmd_local;
 422         }
 423
 424         return drm_gem_fb_create(dev, file_priv, mode_cmd);
 425 }
 426
 427 /* Our CTM has some peculiar limitations: we can only enable it for one CRTC
 428  * at a time and the HW only supports S0.9 scalars. To account for the latter,
 429  * we don't allow userland to set a CTM that we have no hope of approximating.
 430  */
 431 static int
 432 vc4_ctm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
 433 {
 434         struct vc4_dev *vc4 = to_vc4_dev(dev);
 435         struct vc4_ctm_state *ctm_state = NULL;
 436         struct drm_crtc *crtc;
 437         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 438         struct drm_color_ctm *ctm;
 439         int i;
 440
 441         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 442                 /* CTM is being disabled. */
 443                 if (!new_crtc_state->ctm && old_crtc_state->ctm) {
 444                         ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
 445                         if (IS_ERR(ctm_state))
 446                                 return PTR_ERR(ctm_state);
 447                         ctm_state->fifo = 0;
 448                 }
 449         }
 450
 451         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 452                 if (new_crtc_state->ctm == old_crtc_state->ctm)
 453                         continue;
 454
 455                 if (!ctm_state) {
 456                         ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
 457                         if (IS_ERR(ctm_state))
 458                                 return PTR_ERR(ctm_state);
 459                 }
 460
 461                 /* CTM is being enabled or the matrix changed. */
 462                 if (new_crtc_state->ctm) {
 463                         struct vc4_crtc_state *vc4_crtc_state =
 464                                 to_vc4_crtc_state(new_crtc_state);
 465
 466                         /* fifo is 1-based since 0 disables CTM. */
 467                         int fifo = vc4_crtc_state->assigned_channel + 1;
 468
 469                         /* Check userland isn't trying to turn on CTM for more
 470                          * than one CRTC at a time.
 471                          */
 472                         if (ctm_state->fifo && ctm_state->fifo != fifo) {
 473                                 DRM_DEBUG_DRIVER("Too many CTM configured\n");
 474                                 return -EINVAL;
 475                         }
 476
 477                         /* Check we can approximate the specified CTM.
 478                          * We disallow scalars |c| > 1.0 since the HW has
 479                          * no integer bits.
 480                          */
 481                         ctm = new_crtc_state->ctm->data;
 482                         for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) {
 483                                 u64 val = ctm->matrix[i];
 484
 485                                 val &= ~BIT_ULL(63);
 486                                 if (val > BIT_ULL(32))
 487                                         return -EINVAL;
 488                         }
 489
 490                         ctm_state->fifo = fifo;
 491                         ctm_state->ctm = ctm;
 492                 }
 493         }
 494
 495         return 0;
 496 }
 497
 498 static int vc4_load_tracker_atomic_check(struct drm_atomic_state *state)
 499 {
 500         struct drm_plane_state *old_plane_state, *new_plane_state;
 501         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 502         struct vc4_load_tracker_state *load_state;
 503         struct drm_private_state *priv_state;
 504         struct drm_plane *plane;
 505         int i;
 506
 507         if (!vc4->load_tracker_available)
 508                 return 0;
 509
 510         priv_state = drm_atomic_get_private_obj_state(state,
 511                                                       &vc4->load_tracker);
 512         if (IS_ERR(priv_state))
 513                 return PTR_ERR(priv_state);
 514
 515         load_state = to_vc4_load_tracker_state(priv_state);
 516         for_each_oldnew_plane_in_state(state, plane, old_plane_state,
 517                                        new_plane_state, i) {
 518                 struct vc4_plane_state *vc4_plane_state;
 519
 520                 if (old_plane_state->fb && old_plane_state->crtc) {
 521                         vc4_plane_state = to_vc4_plane_state(old_plane_state);
 522                         load_state->membus_load -= vc4_plane_state->membus_load;
 523                         load_state->hvs_load -= vc4_plane_state->hvs_load;
 524                 }
 525
 526                 if (new_plane_state->fb && new_plane_state->crtc) {
 527                         vc4_plane_state = to_vc4_plane_state(new_plane_state);
 528                         load_state->membus_load += vc4_plane_state->membus_load;
 529                         load_state->hvs_load += vc4_plane_state->hvs_load;
 530                 }
 531         }
 532
 533         /* Don't check the load when the tracker is disabled. */
 534         if (!vc4->load_tracker_enabled)
 535                 return 0;
 536
 537         /* The absolute limit is 2Gbyte/sec, but let's take a margin to let
 538          * the system work when other blocks are accessing the memory.
 539          */
 540         if (load_state->membus_load > SZ_1G + SZ_512M)
 541                 return -ENOSPC;
 542
 543         /* HVS clock is supposed to run @ 250Mhz, let's take a margin and
 544          * consider the maximum number of cycles is 240M.
 545          */
 546         if (load_state->hvs_load > 240000000ULL)
 547                 return -ENOSPC;
 548
 549         return 0;
 550 }
 551
 552 static struct drm_private_state *
 553 vc4_load_tracker_duplicate_state(struct drm_private_obj *obj)
 554 {
 555         struct vc4_load_tracker_state *state;
 556
 557         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
 558         if (!state)
 559                 return NULL;
 560
 561         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 562
 563         return &state->base;
 564 }
 565
 566 static void vc4_load_tracker_destroy_state(struct drm_private_obj *obj,
 567                                            struct drm_private_state *state)
 568 {
 569         struct vc4_load_tracker_state *load_state;
 570
 571         load_state = to_vc4_load_tracker_state(state);
 572         kfree(load_state);
 573 }
 574
 575 static const struct drm_private_state_funcs vc4_load_tracker_state_funcs = {
 576         .atomic_duplicate_state = vc4_load_tracker_duplicate_state,
 577         .atomic_destroy_state = vc4_load_tracker_destroy_state,
 578 };
 579
 580 #define NUM_OUTPUTS  6
 581 #define NUM_CHANNELS 3
 582
 583 static int
 584 vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
 585 {
 586         unsigned long unassigned_channels = GENMASK(NUM_CHANNELS - 1, 0);
 587         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 588         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 589         struct drm_crtc *crtc;
 590         int i, ret;
 591
 592         /*
 593          * Since the HVS FIFOs are shared across all the pixelvalves and
 594          * the TXP (and thus all the CRTCs), we need to pull the current
 595          * state of all the enabled CRTCs so that an update to a single
 596          * CRTC still keeps the previous FIFOs enabled and assigned to
 597          * the same CRTCs, instead of evaluating only the CRTC being
 598          * modified.
 599          */
 600         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 601                 struct drm_crtc_state *crtc_state;
 602                 if (!crtc->state->enable)
 603                         continue;
 604
 605                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 606                 if (IS_ERR(crtc_state))
 607                         return PTR_ERR(crtc_state);
 608         }
 609
 610         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 611                 struct vc4_crtc_state *new_vc4_crtc_state =
 612                         to_vc4_crtc_state(new_crtc_state);
 613                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 614                 bool is_assigned = false;
 615                 unsigned int channel;
 616
 617                 if (old_crtc_state->enable && !new_crtc_state->enable)
 618                         new_vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
 619
 620                 if (!new_crtc_state->enable)
 621                         continue;
 622
 623                 if (new_vc4_crtc_state->assigned_channel != VC4_HVS_CHANNEL_DISABLED) {
 624                         unassigned_channels &= ~BIT(new_vc4_crtc_state->assigned_channel);
 625                         continue;
 626                 }
 627
 628                 /*
 629                  * The problem we have to solve here is that we have
 630                  * up to 7 encoders, connected to up to 6 CRTCs.
 631                  *
 632                  * Those CRTCs, depending on the instance, can be
 633                  * routed to 1, 2 or 3 HVS FIFOs, and we need to set
 634                  * the change the muxing between FIFOs and outputs in
 635                  * the HVS accordingly.
 636                  *
 637                  * It would be pretty hard to come up with an
 638                  * algorithm that would generically solve
 639                  * this. However, the current routing trees we support
 640                  * allow us to simplify a bit the problem.
 641                  *
 642                  * Indeed, with the current supported layouts, if we
 643                  * try to assign in the ascending crtc index order the
 644                  * FIFOs, we can't fall into the situation where an
 645                  * earlier CRTC that had multiple routes is assigned
 646                  * one that was the only option for a later CRTC.
 647                  *
 648                  * If the layout changes and doesn't give us that in
 649                  * the future, we will need to have something smarter,
 650                  * but it works so far.
 651                  */
 652                 for_each_set_bit(channel, &unassigned_channels,
 653                                  sizeof(unassigned_channels)) {
 654
 655                         if (!(BIT(channel) & vc4_crtc->data->hvs_available_channels))
 656                                 continue;
 657
 658                         new_vc4_crtc_state->assigned_channel = channel;
 659                         unassigned_channels &= ~BIT(channel);
 660                         is_assigned = true;
 661                         break;
 662                 }
 663
 664                 if (!is_assigned)
 665                         return -EINVAL;
 666         }
 667
 668         ret = vc4_ctm_atomic_check(dev, state);
 669         if (ret < 0)
 670                 return ret;
 671
 672         ret = drm_atomic_helper_check(dev, state);
 673         if (ret)
 674                 return ret;
 675
 676         return vc4_load_tracker_atomic_check(state);
 677 }
 678
 679 static const struct drm_mode_config_funcs vc4_mode_funcs = {
 680         .atomic_check = vc4_atomic_check,
 681         .atomic_commit = vc4_atomic_commit,
 682         .fb_create = vc4_fb_create,
 683 };
 684
 685 int vc4_kms_load(struct drm_device *dev)
 686 {
 687         struct vc4_dev *vc4 = to_vc4_dev(dev);
 688         struct vc4_ctm_state *ctm_state;
 689         struct vc4_load_tracker_state *load_state;
 690         int ret;
 691
 692         if (!of_device_is_compatible(dev->dev->of_node, "brcm,bcm2711-vc5")) {
 693                 vc4->load_tracker_available = true;
 694
 695                 /* Start with the load tracker enabled. Can be
 696                  * disabled through the debugfs load_tracker file.
 697                  */
 698                 vc4->load_tracker_enabled = true;
 699         }
 700
 701         sema_init(&vc4->async_modeset, 1);
 702
 703         /* Set support for vblank irq fast disable, before drm_vblank_init() */
 704         dev->vblank_disable_immediate = true;
 705
 706         dev->irq_enabled = true;
 707         ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
 708         if (ret < 0) {
 709                 dev_err(dev->dev, "failed to initialize vblank\n");
 710                 return ret;
 711         }
 712
 713         if (!drm_core_check_feature(dev, DRIVER_RENDER)) {
 714                 /* No V3D as part of vc4. Assume this is Pi4. */
 715                 dev->mode_config.max_width = 7680;
 716                 dev->mode_config.max_height = 7680;
 717         } else {
 718                 dev->mode_config.max_width = 2048;
 719                 dev->mode_config.max_height = 2048;
 720         }
 721         dev->mode_config.funcs = &vc4_mode_funcs;
 722         dev->mode_config.preferred_depth = 24;
 723         dev->mode_config.async_page_flip = true;
 724         dev->mode_config.allow_fb_modifiers = true;
 725         dev->mode_config.normalize_zpos = true;
 726
 727         drm_modeset_lock_init(&vc4->ctm_state_lock);
 728
 729         ctm_state = kzalloc(sizeof(*ctm_state), GFP_KERNEL);
 730         if (!ctm_state)
 731                 return -ENOMEM;
 732
 733         drm_atomic_private_obj_init(dev, &vc4->ctm_manager, &ctm_state->base,
 734                                     &vc4_ctm_state_funcs);
 735
 736         if (vc4->load_tracker_available) {
 737                 load_state = kzalloc(sizeof(*load_state), GFP_KERNEL);
 738                 if (!load_state) {
 739                         drm_atomic_private_obj_fini(&vc4->ctm_manager);
 740                         return -ENOMEM;
 741                 }
 742
 743                 drm_atomic_private_obj_init(dev, &vc4->load_tracker,
 744                                             &load_state->base,
 745                                             &vc4_load_tracker_state_funcs);
 746         }
 747
 748         drm_mode_config_reset(dev);
 749
 750         drm_kms_helper_poll_init(dev);
 751
 752         return 0;
 753 }