drivers/gpu/drm/vc4/vc4_kms.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 KMS
   8  *
   9  * This is the general code for implementing KMS mode setting that
  10  * doesn't clearly associate with any of the other objects (plane,
  11  * crtc, HDMI encoder).
  12  */
  13
  14 #include <linux/clk.h>
  15
  16 #include <drm/drm_atomic.h>
  17 #include <drm/drm_atomic_helper.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_gem_framebuffer_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21 #include <drm/drm_probe_helper.h>
  22 #include <drm/drm_vblank.h>
  23
  24 #include "vc4_drv.h"
  25 #include "vc4_regs.h"
  26
  27 #define HVS_NUM_CHANNELS 3
  28
  29 struct vc4_ctm_state {
  30         struct drm_private_state base;
  31         struct drm_color_ctm *ctm;
  32         int fifo;
  33 };
  34
  35 static struct vc4_ctm_state *to_vc4_ctm_state(struct drm_private_state *priv)
  36 {
  37         return container_of(priv, struct vc4_ctm_state, base);
  38 }
  39
  40 struct vc4_hvs_state {
  41         struct drm_private_state base;
  42
  43         struct {
  44                 unsigned in_use: 1;
  45                 struct drm_crtc_commit *pending_commit;
  46         } fifo_state[HVS_NUM_CHANNELS];
  47 };
  48
  49 static struct vc4_hvs_state *
  50 to_vc4_hvs_state(struct drm_private_state *priv)
  51 {
  52         return container_of(priv, struct vc4_hvs_state, base);
  53 }
  54
  55 struct vc4_load_tracker_state {
  56         struct drm_private_state base;
  57         u64 hvs_load;
  58         u64 membus_load;
  59 };
  60
  61 static struct vc4_load_tracker_state *
  62 to_vc4_load_tracker_state(struct drm_private_state *priv)
  63 {
  64         return container_of(priv, struct vc4_load_tracker_state, base);
  65 }
  66
  67 static struct vc4_ctm_state *vc4_get_ctm_state(struct drm_atomic_state *state,
  68                                                struct drm_private_obj *manager)
  69 {
  70         struct drm_device *dev = state->dev;
  71         struct vc4_dev *vc4 = to_vc4_dev(dev);
  72         struct drm_private_state *priv_state;
  73         int ret;
  74
  75         ret = drm_modeset_lock(&vc4->ctm_state_lock, state->acquire_ctx);
  76         if (ret)
  77                 return ERR_PTR(ret);
  78
  79         priv_state = drm_atomic_get_private_obj_state(state, manager);
  80         if (IS_ERR(priv_state))
  81                 return ERR_CAST(priv_state);
  82
  83         return to_vc4_ctm_state(priv_state);
  84 }
  85
  86 static struct drm_private_state *
  87 vc4_ctm_duplicate_state(struct drm_private_obj *obj)
  88 {
  89         struct vc4_ctm_state *state;
  90
  91         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
  92         if (!state)
  93                 return NULL;
  94
  95         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
  96
  97         return &state->base;
  98 }
  99
 100 static void vc4_ctm_destroy_state(struct drm_private_obj *obj,
 101                                   struct drm_private_state *state)
 102 {
 103         struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(state);
 104
 105         kfree(ctm_state);
 106 }
 107
 108 static const struct drm_private_state_funcs vc4_ctm_state_funcs = {
 109         .atomic_duplicate_state = vc4_ctm_duplicate_state,
 110         .atomic_destroy_state = vc4_ctm_destroy_state,
 111 };
 112
 113 static void vc4_ctm_obj_fini(struct drm_device *dev, void *unused)
 114 {
 115         struct vc4_dev *vc4 = to_vc4_dev(dev);
 116
 117         drm_atomic_private_obj_fini(&vc4->ctm_manager);
 118 }
 119
 120 static int vc4_ctm_obj_init(struct vc4_dev *vc4)
 121 {
 122         struct vc4_ctm_state *ctm_state;
 123
 124         drm_modeset_lock_init(&vc4->ctm_state_lock);
 125
 126         ctm_state = kzalloc(sizeof(*ctm_state), GFP_KERNEL);
 127         if (!ctm_state)
 128                 return -ENOMEM;
 129
 130         drm_atomic_private_obj_init(&vc4->base, &vc4->ctm_manager, &ctm_state->base,
 131                                     &vc4_ctm_state_funcs);
 132
 133         return drmm_add_action_or_reset(&vc4->base, vc4_ctm_obj_fini, NULL);
 134 }
 135
 136 /* Converts a DRM S31.32 value to the HW S0.9 format. */
 137 static u16 vc4_ctm_s31_32_to_s0_9(u64 in)
 138 {
 139         u16 r;
 140
 141         /* Sign bit. */
 142         r = in & BIT_ULL(63) ? BIT(9) : 0;
 143
 144         if ((in & GENMASK_ULL(62, 32)) > 0) {
 145                 /* We have zero integer bits so we can only saturate here. */
 146                 r |= GENMASK(8, 0);
 147         } else {
 148                 /* Otherwise take the 9 most important fractional bits. */
 149                 r |= (in >> 23) & GENMASK(8, 0);
 150         }
 151
 152         return r;
 153 }
 154
 155 static void
 156 vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state)
 157 {
 158         struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state);
 159         struct drm_color_ctm *ctm = ctm_state->ctm;
 160
 161         if (ctm_state->fifo) {
 162                 HVS_WRITE(SCALER_OLEDCOEF2,
 163                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]),
 164                                         SCALER_OLEDCOEF2_R_TO_R) |
 165                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]),
 166                                         SCALER_OLEDCOEF2_R_TO_G) |
 167                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]),
 168                                         SCALER_OLEDCOEF2_R_TO_B));
 169                 HVS_WRITE(SCALER_OLEDCOEF1,
 170                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]),
 171                                         SCALER_OLEDCOEF1_G_TO_R) |
 172                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]),
 173                                         SCALER_OLEDCOEF1_G_TO_G) |
 174                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]),
 175                                         SCALER_OLEDCOEF1_G_TO_B));
 176                 HVS_WRITE(SCALER_OLEDCOEF0,
 177                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]),
 178                                         SCALER_OLEDCOEF0_B_TO_R) |
 179                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]),
 180                                         SCALER_OLEDCOEF0_B_TO_G) |
 181                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]),
 182                                         SCALER_OLEDCOEF0_B_TO_B));
 183         }
 184
 185         HVS_WRITE(SCALER_OLEDOFFS,
 186                   VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO));
 187 }
 188
 189 static struct vc4_hvs_state *
 190 vc4_hvs_get_new_global_state(struct drm_atomic_state *state)
 191 {
 192         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 193         struct drm_private_state *priv_state;
 194
 195         priv_state = drm_atomic_get_new_private_obj_state(state, &vc4->hvs_channels);
 196         if (IS_ERR(priv_state))
 197                 return ERR_CAST(priv_state);
 198
 199         return to_vc4_hvs_state(priv_state);
 200 }
 201
 202 static struct vc4_hvs_state *
 203 vc4_hvs_get_old_global_state(struct drm_atomic_state *state)
 204 {
 205         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 206         struct drm_private_state *priv_state;
 207
 208         priv_state = drm_atomic_get_old_private_obj_state(state, &vc4->hvs_channels);
 209         if (IS_ERR(priv_state))
 210                 return ERR_CAST(priv_state);
 211
 212         return to_vc4_hvs_state(priv_state);
 213 }
 214
 215 static struct vc4_hvs_state *
 216 vc4_hvs_get_global_state(struct drm_atomic_state *state)
 217 {
 218         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 219         struct drm_private_state *priv_state;
 220
 221         priv_state = drm_atomic_get_private_obj_state(state, &vc4->hvs_channels);
 222         if (IS_ERR(priv_state))
 223                 return ERR_CAST(priv_state);
 224
 225         return to_vc4_hvs_state(priv_state);
 226 }
 227
 228 static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4,
 229                                      struct drm_atomic_state *state)
 230 {
 231         struct drm_crtc_state *crtc_state;
 232         struct drm_crtc *crtc;
 233         unsigned int i;
 234
 235         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 236                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 237                 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 238                 u32 dispctrl;
 239                 u32 dsp3_mux;
 240
 241                 if (!crtc_state->active)
 242                         continue;
 243
 244                 if (vc4_state->assigned_channel != 2)
 245                         continue;
 246
 247                 /*
 248                  * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
 249                  * FIFO X'.
 250                  * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
 251                  *
 252                  * DSP3 is connected to FIFO2 unless the transposer is
 253                  * enabled. In this case, FIFO 2 is directly accessed by the
 254                  * TXP IP, and we need to disable the FIFO2 -> pixelvalve1
 255                  * route.
 256                  */
 257                 if (vc4_crtc->feeds_txp)
 258                         dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
 259                 else
 260                         dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
 261
 262                 dispctrl = HVS_READ(SCALER_DISPCTRL) &
 263                            ~SCALER_DISPCTRL_DSP3_MUX_MASK;
 264                 HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
 265         }
 266 }
 267
 268 static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4,
 269                                      struct drm_atomic_state *state)
 270 {
 271         struct drm_crtc_state *crtc_state;
 272         struct drm_crtc *crtc;
 273         unsigned char mux;
 274         unsigned int i;
 275         u32 reg;
 276
 277         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 278                 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 279                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 280
 281                 if (!vc4_state->update_muxing)
 282                         continue;
 283
 284                 switch (vc4_crtc->data->hvs_output) {
 285                 case 2:
 286                         mux = (vc4_state->assigned_channel == 2) ? 0 : 1;
 287                         reg = HVS_READ(SCALER_DISPECTRL);
 288                         HVS_WRITE(SCALER_DISPECTRL,
 289                                   (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) |
 290                                   VC4_SET_FIELD(mux, SCALER_DISPECTRL_DSP2_MUX));
 291                         break;
 292
 293                 case 3:
 294                         if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED)
 295                                 mux = 3;
 296                         else
 297                                 mux = vc4_state->assigned_channel;
 298
 299                         reg = HVS_READ(SCALER_DISPCTRL);
 300                         HVS_WRITE(SCALER_DISPCTRL,
 301                                   (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) |
 302                                   VC4_SET_FIELD(mux, SCALER_DISPCTRL_DSP3_MUX));
 303                         break;
 304
 305                 case 4:
 306                         if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED)
 307                                 mux = 3;
 308                         else
 309                                 mux = vc4_state->assigned_channel;
 310
 311                         reg = HVS_READ(SCALER_DISPEOLN);
 312                         HVS_WRITE(SCALER_DISPEOLN,
 313                                   (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) |
 314                                   VC4_SET_FIELD(mux, SCALER_DISPEOLN_DSP4_MUX));
 315
 316                         break;
 317
 318                 case 5:
 319                         if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED)
 320                                 mux = 3;
 321                         else
 322                                 mux = vc4_state->assigned_channel;
 323
 324                         reg = HVS_READ(SCALER_DISPDITHER);
 325                         HVS_WRITE(SCALER_DISPDITHER,
 326                                   (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) |
 327                                   VC4_SET_FIELD(mux, SCALER_DISPDITHER_DSP5_MUX));
 328                         break;
 329
 330                 default:
 331                         break;
 332                 }
 333         }
 334 }
 335
 336 static void vc4_atomic_commit_tail(struct drm_atomic_state *state)
 337 {
 338         struct drm_device *dev = state->dev;
 339         struct vc4_dev *vc4 = to_vc4_dev(dev);
 340         struct vc4_hvs *hvs = vc4->hvs;
 341         struct drm_crtc_state *new_crtc_state;
 342         struct drm_crtc *crtc;
 343         struct vc4_hvs_state *old_hvs_state;
 344         unsigned int channel;
 345         int i;
 346
 347         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
 348                 struct vc4_crtc_state *vc4_crtc_state;
 349
 350                 if (!new_crtc_state->commit)
 351                         continue;
 352
 353                 vc4_crtc_state = to_vc4_crtc_state(new_crtc_state);
 354                 vc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel);
 355         }
 356
 357         old_hvs_state = vc4_hvs_get_old_global_state(state);
 358         if (IS_ERR(old_hvs_state))
 359                 return;
 360
 361         for (channel = 0; channel < HVS_NUM_CHANNELS; channel++) {
 362                 struct drm_crtc_commit *commit;
 363                 int ret;
 364
 365                 if (!old_hvs_state->fifo_state[channel].in_use)
 366                         continue;
 367
 368                 commit = old_hvs_state->fifo_state[channel].pending_commit;
 369                 if (!commit)
 370                         continue;
 371
 372                 ret = drm_crtc_commit_wait(commit);
 373                 if (ret)
 374                         drm_err(dev, "Timed out waiting for commit\n");
 375
 376                 drm_crtc_commit_put(commit);
 377                 old_hvs_state->fifo_state[channel].pending_commit = NULL;
 378         }
 379
 380         if (vc4->hvs->hvs5)
 381                 clk_set_min_rate(hvs->core_clk, 500000000);
 382
 383         drm_atomic_helper_commit_modeset_disables(dev, state);
 384
 385         vc4_ctm_commit(vc4, state);
 386
 387         if (vc4->hvs->hvs5)
 388                 vc5_hvs_pv_muxing_commit(vc4, state);
 389         else
 390                 vc4_hvs_pv_muxing_commit(vc4, state);
 391
 392         drm_atomic_helper_commit_planes(dev, state, 0);
 393
 394         drm_atomic_helper_commit_modeset_enables(dev, state);
 395
 396         drm_atomic_helper_fake_vblank(state);
 397
 398         drm_atomic_helper_commit_hw_done(state);
 399
 400         drm_atomic_helper_wait_for_flip_done(dev, state);
 401
 402         drm_atomic_helper_cleanup_planes(dev, state);
 403
 404         if (vc4->hvs->hvs5)
 405                 clk_set_min_rate(hvs->core_clk, 0);
 406 }
 407
 408 static int vc4_atomic_commit_setup(struct drm_atomic_state *state)
 409 {
 410         struct drm_crtc_state *crtc_state;
 411         struct vc4_hvs_state *hvs_state;
 412         struct drm_crtc *crtc;
 413         unsigned int i;
 414
 415         hvs_state = vc4_hvs_get_new_global_state(state);
 416         if (WARN_ON(IS_ERR(hvs_state)))
 417                 return PTR_ERR(hvs_state);
 418
 419         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 420                 struct vc4_crtc_state *vc4_crtc_state =
 421                         to_vc4_crtc_state(crtc_state);
 422                 unsigned int channel =
 423                         vc4_crtc_state->assigned_channel;
 424
 425                 if (channel == VC4_HVS_CHANNEL_DISABLED)
 426                         continue;
 427
 428                 if (!hvs_state->fifo_state[channel].in_use)
 429                         continue;
 430
 431                 hvs_state->fifo_state[channel].pending_commit =
 432                         drm_crtc_commit_get(crtc_state->commit);
 433         }
 434
 435         return 0;
 436 }
 437
 438 static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev,
 439                                              struct drm_file *file_priv,
 440                                              const struct drm_mode_fb_cmd2 *mode_cmd)
 441 {
 442         struct drm_mode_fb_cmd2 mode_cmd_local;
 443
 444         /* If the user didn't specify a modifier, use the
 445          * vc4_set_tiling_ioctl() state for the BO.
 446          */
 447         if (!(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) {
 448                 struct drm_gem_object *gem_obj;
 449                 struct vc4_bo *bo;
 450
 451                 gem_obj = drm_gem_object_lookup(file_priv,
 452                                                 mode_cmd->handles[0]);
 453                 if (!gem_obj) {
 454                         DRM_DEBUG("Failed to look up GEM BO %d\n",
 455                                   mode_cmd->handles[0]);
 456                         return ERR_PTR(-ENOENT);
 457                 }
 458                 bo = to_vc4_bo(gem_obj);
 459
 460                 mode_cmd_local = *mode_cmd;
 461
 462                 if (bo->t_format) {
 463                         mode_cmd_local.modifier[0] =
 464                                 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED;
 465                 } else {
 466                         mode_cmd_local.modifier[0] = DRM_FORMAT_MOD_NONE;
 467                 }
 468
 469                 drm_gem_object_put(gem_obj);
 470
 471                 mode_cmd = &mode_cmd_local;
 472         }
 473
 474         return drm_gem_fb_create(dev, file_priv, mode_cmd);
 475 }
 476
 477 /* Our CTM has some peculiar limitations: we can only enable it for one CRTC
 478  * at a time and the HW only supports S0.9 scalars. To account for the latter,
 479  * we don't allow userland to set a CTM that we have no hope of approximating.
 480  */
 481 static int
 482 vc4_ctm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
 483 {
 484         struct vc4_dev *vc4 = to_vc4_dev(dev);
 485         struct vc4_ctm_state *ctm_state = NULL;
 486         struct drm_crtc *crtc;
 487         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 488         struct drm_color_ctm *ctm;
 489         int i;
 490
 491         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 492                 /* CTM is being disabled. */
 493                 if (!new_crtc_state->ctm && old_crtc_state->ctm) {
 494                         ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
 495                         if (IS_ERR(ctm_state))
 496                                 return PTR_ERR(ctm_state);
 497                         ctm_state->fifo = 0;
 498                 }
 499         }
 500
 501         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 502                 if (new_crtc_state->ctm == old_crtc_state->ctm)
 503                         continue;
 504
 505                 if (!ctm_state) {
 506                         ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
 507                         if (IS_ERR(ctm_state))
 508                                 return PTR_ERR(ctm_state);
 509                 }
 510
 511                 /* CTM is being enabled or the matrix changed. */
 512                 if (new_crtc_state->ctm) {
 513                         struct vc4_crtc_state *vc4_crtc_state =
 514                                 to_vc4_crtc_state(new_crtc_state);
 515
 516                         /* fifo is 1-based since 0 disables CTM. */
 517                         int fifo = vc4_crtc_state->assigned_channel + 1;
 518
 519                         /* Check userland isn't trying to turn on CTM for more
 520                          * than one CRTC at a time.
 521                          */
 522                         if (ctm_state->fifo && ctm_state->fifo != fifo) {
 523                                 DRM_DEBUG_DRIVER("Too many CTM configured\n");
 524                                 return -EINVAL;
 525                         }
 526
 527                         /* Check we can approximate the specified CTM.
 528                          * We disallow scalars |c| > 1.0 since the HW has
 529                          * no integer bits.
 530                          */
 531                         ctm = new_crtc_state->ctm->data;
 532                         for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) {
 533                                 u64 val = ctm->matrix[i];
 534
 535                                 val &= ~BIT_ULL(63);
 536                                 if (val > BIT_ULL(32))
 537                                         return -EINVAL;
 538                         }
 539
 540                         ctm_state->fifo = fifo;
 541                         ctm_state->ctm = ctm;
 542                 }
 543         }
 544
 545         return 0;
 546 }
 547
 548 static int vc4_load_tracker_atomic_check(struct drm_atomic_state *state)
 549 {
 550         struct drm_plane_state *old_plane_state, *new_plane_state;
 551         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 552         struct vc4_load_tracker_state *load_state;
 553         struct drm_private_state *priv_state;
 554         struct drm_plane *plane;
 555         int i;
 556
 557         if (!vc4->load_tracker_available)
 558                 return 0;
 559
 560         priv_state = drm_atomic_get_private_obj_state(state,
 561                                                       &vc4->load_tracker);
 562         if (IS_ERR(priv_state))
 563                 return PTR_ERR(priv_state);
 564
 565         load_state = to_vc4_load_tracker_state(priv_state);
 566         for_each_oldnew_plane_in_state(state, plane, old_plane_state,
 567                                        new_plane_state, i) {
 568                 struct vc4_plane_state *vc4_plane_state;
 569
 570                 if (old_plane_state->fb && old_plane_state->crtc) {
 571                         vc4_plane_state = to_vc4_plane_state(old_plane_state);
 572                         load_state->membus_load -= vc4_plane_state->membus_load;
 573                         load_state->hvs_load -= vc4_plane_state->hvs_load;
 574                 }
 575
 576                 if (new_plane_state->fb && new_plane_state->crtc) {
 577                         vc4_plane_state = to_vc4_plane_state(new_plane_state);
 578                         load_state->membus_load += vc4_plane_state->membus_load;
 579                         load_state->hvs_load += vc4_plane_state->hvs_load;
 580                 }
 581         }
 582
 583         /* Don't check the load when the tracker is disabled. */
 584         if (!vc4->load_tracker_enabled)
 585                 return 0;
 586
 587         /* The absolute limit is 2Gbyte/sec, but let's take a margin to let
 588          * the system work when other blocks are accessing the memory.
 589          */
 590         if (load_state->membus_load > SZ_1G + SZ_512M)
 591                 return -ENOSPC;
 592
 593         /* HVS clock is supposed to run @ 250Mhz, let's take a margin and
 594          * consider the maximum number of cycles is 240M.
 595          */
 596         if (load_state->hvs_load > 240000000ULL)
 597                 return -ENOSPC;
 598
 599         return 0;
 600 }
 601
 602 static struct drm_private_state *
 603 vc4_load_tracker_duplicate_state(struct drm_private_obj *obj)
 604 {
 605         struct vc4_load_tracker_state *state;
 606
 607         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
 608         if (!state)
 609                 return NULL;
 610
 611         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 612
 613         return &state->base;
 614 }
 615
 616 static void vc4_load_tracker_destroy_state(struct drm_private_obj *obj,
 617                                            struct drm_private_state *state)
 618 {
 619         struct vc4_load_tracker_state *load_state;
 620
 621         load_state = to_vc4_load_tracker_state(state);
 622         kfree(load_state);
 623 }
 624
 625 static const struct drm_private_state_funcs vc4_load_tracker_state_funcs = {
 626         .atomic_duplicate_state = vc4_load_tracker_duplicate_state,
 627         .atomic_destroy_state = vc4_load_tracker_destroy_state,
 628 };
 629
 630 static void vc4_load_tracker_obj_fini(struct drm_device *dev, void *unused)
 631 {
 632         struct vc4_dev *vc4 = to_vc4_dev(dev);
 633
 634         if (!vc4->load_tracker_available)
 635                 return;
 636
 637         drm_atomic_private_obj_fini(&vc4->load_tracker);
 638 }
 639
 640 static int vc4_load_tracker_obj_init(struct vc4_dev *vc4)
 641 {
 642         struct vc4_load_tracker_state *load_state;
 643
 644         if (!vc4->load_tracker_available)
 645                 return 0;
 646
 647         load_state = kzalloc(sizeof(*load_state), GFP_KERNEL);
 648         if (!load_state)
 649                 return -ENOMEM;
 650
 651         drm_atomic_private_obj_init(&vc4->base, &vc4->load_tracker,
 652                                     &load_state->base,
 653                                     &vc4_load_tracker_state_funcs);
 654
 655         return drmm_add_action_or_reset(&vc4->base, vc4_load_tracker_obj_fini, NULL);
 656 }
 657
 658 static struct drm_private_state *
 659 vc4_hvs_channels_duplicate_state(struct drm_private_obj *obj)
 660 {
 661         struct vc4_hvs_state *old_state = to_vc4_hvs_state(obj->state);
 662         struct vc4_hvs_state *state;
 663         unsigned int i;
 664
 665         state = kzalloc(sizeof(*state), GFP_KERNEL);
 666         if (!state)
 667                 return NULL;
 668
 669         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 670
 671
 672         for (i = 0; i < HVS_NUM_CHANNELS; i++) {
 673                 state->fifo_state[i].in_use = old_state->fifo_state[i].in_use;
 674         }
 675
 676         return &state->base;
 677 }
 678
 679 static void vc4_hvs_channels_destroy_state(struct drm_private_obj *obj,
 680                                            struct drm_private_state *state)
 681 {
 682         struct vc4_hvs_state *hvs_state = to_vc4_hvs_state(state);
 683         unsigned int i;
 684
 685         for (i = 0; i < HVS_NUM_CHANNELS; i++) {
 686                 if (!hvs_state->fifo_state[i].pending_commit)
 687                         continue;
 688
 689                 drm_crtc_commit_put(hvs_state->fifo_state[i].pending_commit);
 690         }
 691
 692         kfree(hvs_state);
 693 }
 694
 695 static const struct drm_private_state_funcs vc4_hvs_state_funcs = {
 696         .atomic_duplicate_state = vc4_hvs_channels_duplicate_state,
 697         .atomic_destroy_state = vc4_hvs_channels_destroy_state,
 698 };
 699
 700 static void vc4_hvs_channels_obj_fini(struct drm_device *dev, void *unused)
 701 {
 702         struct vc4_dev *vc4 = to_vc4_dev(dev);
 703
 704         drm_atomic_private_obj_fini(&vc4->hvs_channels);
 705 }
 706
 707 static int vc4_hvs_channels_obj_init(struct vc4_dev *vc4)
 708 {
 709         struct vc4_hvs_state *state;
 710
 711         state = kzalloc(sizeof(*state), GFP_KERNEL);
 712         if (!state)
 713                 return -ENOMEM;
 714
 715         drm_atomic_private_obj_init(&vc4->base, &vc4->hvs_channels,
 716                                     &state->base,
 717                                     &vc4_hvs_state_funcs);
 718
 719         return drmm_add_action_or_reset(&vc4->base, vc4_hvs_channels_obj_fini, NULL);
 720 }
 721
 722 /*
 723  * The BCM2711 HVS has up to 7 outputs connected to the pixelvalves and
 724  * the TXP (and therefore all the CRTCs found on that platform).
 725  *
 726  * The naive (and our initial) implementation would just iterate over
 727  * all the active CRTCs, try to find a suitable FIFO, and then remove it
 728  * from the pool of available FIFOs. However, there are a few corner
 729  * cases that need to be considered:
 730  *
 731  * - When running in a dual-display setup (so with two CRTCs involved),
 732  *   we can update the state of a single CRTC (for example by changing
 733  *   its mode using xrandr under X11) without affecting the other. In
 734  *   this case, the other CRTC wouldn't be in the state at all, so we
 735  *   need to consider all the running CRTCs in the DRM device to assign
 736  *   a FIFO, not just the one in the state.
 737  *
 738  * - To fix the above, we can't use drm_atomic_get_crtc_state on all
 739  *   enabled CRTCs to pull their CRTC state into the global state, since
 740  *   a page flip would start considering their vblank to complete. Since
 741  *   we don't have a guarantee that they are actually active, that
 742  *   vblank might never happen, and shouldn't even be considered if we
 743  *   want to do a page flip on a single CRTC. That can be tested by
 744  *   doing a modetest -v first on HDMI1 and then on HDMI0.
 745  *
 746  * - Since we need the pixelvalve to be disabled and enabled back when
 747  *   the FIFO is changed, we should keep the FIFO assigned for as long
 748  *   as the CRTC is enabled, only considering it free again once that
 749  *   CRTC has been disabled. This can be tested by booting X11 on a
 750  *   single display, and changing the resolution down and then back up.
 751  */
 752 static int vc4_pv_muxing_atomic_check(struct drm_device *dev,
 753                                       struct drm_atomic_state *state)
 754 {
 755         struct vc4_hvs_state *hvs_new_state;
 756         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 757         struct drm_crtc *crtc;
 758         unsigned int unassigned_channels = 0;
 759         unsigned int i;
 760
 761         hvs_new_state = vc4_hvs_get_global_state(state);
 762         if (IS_ERR(hvs_new_state))
 763                 return PTR_ERR(hvs_new_state);
 764
 765         for (i = 0; i < ARRAY_SIZE(hvs_new_state->fifo_state); i++)
 766                 if (!hvs_new_state->fifo_state[i].in_use)
 767                         unassigned_channels |= BIT(i);
 768
 769         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 770                 struct vc4_crtc_state *old_vc4_crtc_state =
 771                         to_vc4_crtc_state(old_crtc_state);
 772                 struct vc4_crtc_state *new_vc4_crtc_state =
 773                         to_vc4_crtc_state(new_crtc_state);
 774                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 775                 unsigned int matching_channels;
 776                 unsigned int channel;
 777
 778                 /* Nothing to do here, let's skip it */
 779                 if (old_crtc_state->enable == new_crtc_state->enable)
 780                         continue;
 781
 782                 /* Muxing will need to be modified, mark it as such */
 783                 new_vc4_crtc_state->update_muxing = true;
 784
 785                 /* If we're disabling our CRTC, we put back our channel */
 786                 if (!new_crtc_state->enable) {
 787                         channel = old_vc4_crtc_state->assigned_channel;
 788                         hvs_new_state->fifo_state[channel].in_use = false;
 789                         new_vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
 790                         continue;
 791                 }
 792
 793                 /*
 794                  * The problem we have to solve here is that we have
 795                  * up to 7 encoders, connected to up to 6 CRTCs.
 796                  *
 797                  * Those CRTCs, depending on the instance, can be
 798                  * routed to 1, 2 or 3 HVS FIFOs, and we need to set
 799                  * the change the muxing between FIFOs and outputs in
 800                  * the HVS accordingly.
 801                  *
 802                  * It would be pretty hard to come up with an
 803                  * algorithm that would generically solve
 804                  * this. However, the current routing trees we support
 805                  * allow us to simplify a bit the problem.
 806                  *
 807                  * Indeed, with the current supported layouts, if we
 808                  * try to assign in the ascending crtc index order the
 809                  * FIFOs, we can't fall into the situation where an
 810                  * earlier CRTC that had multiple routes is assigned
 811                  * one that was the only option for a later CRTC.
 812                  *
 813                  * If the layout changes and doesn't give us that in
 814                  * the future, we will need to have something smarter,
 815                  * but it works so far.
 816                  */
 817                 matching_channels = unassigned_channels & vc4_crtc->data->hvs_available_channels;
 818                 if (!matching_channels)
 819                         return -EINVAL;
 820
 821                 channel = ffs(matching_channels) - 1;
 822                 new_vc4_crtc_state->assigned_channel = channel;
 823                 unassigned_channels &= ~BIT(channel);
 824                 hvs_new_state->fifo_state[channel].in_use = true;
 825         }
 826
 827         return 0;
 828 }
 829
 830 static int
 831 vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
 832 {
 833         int ret;
 834
 835         ret = vc4_pv_muxing_atomic_check(dev, state);
 836         if (ret)
 837                 return ret;
 838
 839         ret = vc4_ctm_atomic_check(dev, state);
 840         if (ret < 0)
 841                 return ret;
 842
 843         ret = drm_atomic_helper_check(dev, state);
 844         if (ret)
 845                 return ret;
 846
 847         return vc4_load_tracker_atomic_check(state);
 848 }
 849
 850 static struct drm_mode_config_helper_funcs vc4_mode_config_helpers = {
 851         .atomic_commit_setup    = vc4_atomic_commit_setup,
 852         .atomic_commit_tail     = vc4_atomic_commit_tail,
 853 };
 854
 855 static const struct drm_mode_config_funcs vc4_mode_funcs = {
 856         .atomic_check = vc4_atomic_check,
 857         .atomic_commit = drm_atomic_helper_commit,
 858         .fb_create = vc4_fb_create,
 859 };
 860
 861 int vc4_kms_load(struct drm_device *dev)
 862 {
 863         struct vc4_dev *vc4 = to_vc4_dev(dev);
 864         bool is_vc5 = of_device_is_compatible(dev->dev->of_node,
 865                                               "brcm,bcm2711-vc5");
 866         int ret;
 867
 868         if (!is_vc5) {
 869                 vc4->load_tracker_available = true;
 870
 871                 /* Start with the load tracker enabled. Can be
 872                  * disabled through the debugfs load_tracker file.
 873                  */
 874                 vc4->load_tracker_enabled = true;
 875         }
 876
 877         /* Set support for vblank irq fast disable, before drm_vblank_init() */
 878         dev->vblank_disable_immediate = true;
 879
 880         ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
 881         if (ret < 0) {
 882                 dev_err(dev->dev, "failed to initialize vblank\n");
 883                 return ret;
 884         }
 885
 886         if (is_vc5) {
 887                 dev->mode_config.max_width = 7680;
 888                 dev->mode_config.max_height = 7680;
 889         } else {
 890                 dev->mode_config.max_width = 2048;
 891                 dev->mode_config.max_height = 2048;
 892         }
 893
 894         dev->mode_config.funcs = &vc4_mode_funcs;
 895         dev->mode_config.helper_private = &vc4_mode_config_helpers;
 896         dev->mode_config.preferred_depth = 24;
 897         dev->mode_config.async_page_flip = true;
 898
 899         ret = vc4_ctm_obj_init(vc4);
 900         if (ret)
 901                 return ret;
 902
 903         ret = vc4_load_tracker_obj_init(vc4);
 904         if (ret)
 905                 return ret;
 906
 907         ret = vc4_hvs_channels_obj_init(vc4);
 908         if (ret)
 909                 return ret;
 910
 911         drm_mode_config_reset(dev);
 912
 913         drm_kms_helper_poll_init(dev);
 914
 915         return 0;
 916 }