drivers/gpu/drm/vc4/vc4_kms.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 KMS
   8  *
   9  * This is the general code for implementing KMS mode setting that
  10  * doesn't clearly associate with any of the other objects (plane,
  11  * crtc, HDMI encoder).
  12  */
  13
  14 #include <linux/clk.h>
  15
  16 #include <drm/drm_atomic.h>
  17 #include <drm/drm_atomic_helper.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_gem_framebuffer_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21 #include <drm/drm_probe_helper.h>
  22 #include <drm/drm_vblank.h>
  23
  24 #include "vc4_drv.h"
  25 #include "vc4_regs.h"
  26
  27 #define HVS_NUM_CHANNELS 3
  28
  29 struct vc4_ctm_state {
  30         struct drm_private_state base;
  31         struct drm_color_ctm *ctm;
  32         int fifo;
  33 };
  34
  35 static struct vc4_ctm_state *to_vc4_ctm_state(struct drm_private_state *priv)
  36 {
  37         return container_of(priv, struct vc4_ctm_state, base);
  38 }
  39
  40 struct vc4_hvs_state {
  41         struct drm_private_state base;
  42         unsigned long core_clock_rate;
  43
  44         struct {
  45                 unsigned in_use: 1;
  46                 unsigned long fifo_load;
  47                 struct drm_crtc_commit *pending_commit;
  48         } fifo_state[HVS_NUM_CHANNELS];
  49 };
  50
  51 static struct vc4_hvs_state *
  52 to_vc4_hvs_state(struct drm_private_state *priv)
  53 {
  54         return container_of(priv, struct vc4_hvs_state, base);
  55 }
  56
  57 struct vc4_load_tracker_state {
  58         struct drm_private_state base;
  59         u64 hvs_load;
  60         u64 membus_load;
  61 };
  62
  63 static struct vc4_load_tracker_state *
  64 to_vc4_load_tracker_state(struct drm_private_state *priv)
  65 {
  66         return container_of(priv, struct vc4_load_tracker_state, base);
  67 }
  68
  69 static struct vc4_ctm_state *vc4_get_ctm_state(struct drm_atomic_state *state,
  70                                                struct drm_private_obj *manager)
  71 {
  72         struct drm_device *dev = state->dev;
  73         struct vc4_dev *vc4 = to_vc4_dev(dev);
  74         struct drm_private_state *priv_state;
  75         int ret;
  76
  77         ret = drm_modeset_lock(&vc4->ctm_state_lock, state->acquire_ctx);
  78         if (ret)
  79                 return ERR_PTR(ret);
  80
  81         priv_state = drm_atomic_get_private_obj_state(state, manager);
  82         if (IS_ERR(priv_state))
  83                 return ERR_CAST(priv_state);
  84
  85         return to_vc4_ctm_state(priv_state);
  86 }
  87
  88 static struct drm_private_state *
  89 vc4_ctm_duplicate_state(struct drm_private_obj *obj)
  90 {
  91         struct vc4_ctm_state *state;
  92
  93         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
  94         if (!state)
  95                 return NULL;
  96
  97         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
  98
  99         return &state->base;
 100 }
 101
 102 static void vc4_ctm_destroy_state(struct drm_private_obj *obj,
 103                                   struct drm_private_state *state)
 104 {
 105         struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(state);
 106
 107         kfree(ctm_state);
 108 }
 109
 110 static const struct drm_private_state_funcs vc4_ctm_state_funcs = {
 111         .atomic_duplicate_state = vc4_ctm_duplicate_state,
 112         .atomic_destroy_state = vc4_ctm_destroy_state,
 113 };
 114
 115 static void vc4_ctm_obj_fini(struct drm_device *dev, void *unused)
 116 {
 117         struct vc4_dev *vc4 = to_vc4_dev(dev);
 118
 119         drm_atomic_private_obj_fini(&vc4->ctm_manager);
 120 }
 121
 122 static int vc4_ctm_obj_init(struct vc4_dev *vc4)
 123 {
 124         struct vc4_ctm_state *ctm_state;
 125
 126         drm_modeset_lock_init(&vc4->ctm_state_lock);
 127
 128         ctm_state = kzalloc(sizeof(*ctm_state), GFP_KERNEL);
 129         if (!ctm_state)
 130                 return -ENOMEM;
 131
 132         drm_atomic_private_obj_init(&vc4->base, &vc4->ctm_manager, &ctm_state->base,
 133                                     &vc4_ctm_state_funcs);
 134
 135         return drmm_add_action_or_reset(&vc4->base, vc4_ctm_obj_fini, NULL);
 136 }
 137
 138 /* Converts a DRM S31.32 value to the HW S0.9 format. */
 139 static u16 vc4_ctm_s31_32_to_s0_9(u64 in)
 140 {
 141         u16 r;
 142
 143         /* Sign bit. */
 144         r = in & BIT_ULL(63) ? BIT(9) : 0;
 145
 146         if ((in & GENMASK_ULL(62, 32)) > 0) {
 147                 /* We have zero integer bits so we can only saturate here. */
 148                 r |= GENMASK(8, 0);
 149         } else {
 150                 /* Otherwise take the 9 most important fractional bits. */
 151                 r |= (in >> 23) & GENMASK(8, 0);
 152         }
 153
 154         return r;
 155 }
 156
 157 static void
 158 vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state)
 159 {
 160         struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state);
 161         struct drm_color_ctm *ctm = ctm_state->ctm;
 162
 163         if (vc4->firmware_kms)
 164                 return;
 165
 166         if (ctm_state->fifo) {
 167                 HVS_WRITE(SCALER_OLEDCOEF2,
 168                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]),
 169                                         SCALER_OLEDCOEF2_R_TO_R) |
 170                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]),
 171                                         SCALER_OLEDCOEF2_R_TO_G) |
 172                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]),
 173                                         SCALER_OLEDCOEF2_R_TO_B));
 174                 HVS_WRITE(SCALER_OLEDCOEF1,
 175                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]),
 176                                         SCALER_OLEDCOEF1_G_TO_R) |
 177                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]),
 178                                         SCALER_OLEDCOEF1_G_TO_G) |
 179                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]),
 180                                         SCALER_OLEDCOEF1_G_TO_B));
 181                 HVS_WRITE(SCALER_OLEDCOEF0,
 182                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]),
 183                                         SCALER_OLEDCOEF0_B_TO_R) |
 184                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]),
 185                                         SCALER_OLEDCOEF0_B_TO_G) |
 186                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]),
 187                                         SCALER_OLEDCOEF0_B_TO_B));
 188         }
 189
 190         HVS_WRITE(SCALER_OLEDOFFS,
 191                   VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO));
 192 }
 193
 194 static struct vc4_hvs_state *
 195 vc4_hvs_get_new_global_state(struct drm_atomic_state *state)
 196 {
 197         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 198         struct drm_private_state *priv_state;
 199
 200         priv_state = drm_atomic_get_new_private_obj_state(state, &vc4->hvs_channels);
 201         if (IS_ERR(priv_state))
 202                 return ERR_CAST(priv_state);
 203
 204         return to_vc4_hvs_state(priv_state);
 205 }
 206
 207 static struct vc4_hvs_state *
 208 vc4_hvs_get_old_global_state(struct drm_atomic_state *state)
 209 {
 210         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 211         struct drm_private_state *priv_state;
 212
 213         priv_state = drm_atomic_get_old_private_obj_state(state, &vc4->hvs_channels);
 214         if (IS_ERR(priv_state))
 215                 return ERR_CAST(priv_state);
 216
 217         return to_vc4_hvs_state(priv_state);
 218 }
 219
 220 static struct vc4_hvs_state *
 221 vc4_hvs_get_global_state(struct drm_atomic_state *state)
 222 {
 223         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 224         struct drm_private_state *priv_state;
 225
 226         priv_state = drm_atomic_get_private_obj_state(state, &vc4->hvs_channels);
 227         if (IS_ERR(priv_state))
 228                 return ERR_CAST(priv_state);
 229
 230         return to_vc4_hvs_state(priv_state);
 231 }
 232
 233 static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4,
 234                                      struct drm_atomic_state *state)
 235 {
 236         struct drm_crtc_state *crtc_state;
 237         struct drm_crtc *crtc;
 238         unsigned int i;
 239
 240         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 241                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 242                 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 243                 u32 dispctrl;
 244                 u32 dsp3_mux;
 245
 246                 if (!crtc_state->active)
 247                         continue;
 248
 249                 if (vc4_state->assigned_channel != 2)
 250                         continue;
 251
 252                 /*
 253                  * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
 254                  * FIFO X'.
 255                  * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
 256                  *
 257                  * DSP3 is connected to FIFO2 unless the transposer is
 258                  * enabled. In this case, FIFO 2 is directly accessed by the
 259                  * TXP IP, and we need to disable the FIFO2 -> pixelvalve1
 260                  * route.
 261                  */
 262                 if (vc4_crtc->feeds_txp)
 263                         dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
 264                 else
 265                         dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
 266
 267                 dispctrl = HVS_READ(SCALER_DISPCTRL) &
 268                            ~SCALER_DISPCTRL_DSP3_MUX_MASK;
 269                 HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
 270         }
 271 }
 272
 273 static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4,
 274                                      struct drm_atomic_state *state)
 275 {
 276         struct drm_crtc_state *crtc_state;
 277         struct drm_crtc *crtc;
 278         unsigned char mux;
 279         unsigned int i;
 280         u32 reg;
 281
 282         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 283                 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 284                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 285
 286                 if (!vc4_state->update_muxing)
 287                         continue;
 288
 289                 switch (vc4_crtc->data->hvs_output) {
 290                 case 2:
 291                         mux = (vc4_state->assigned_channel == 2) ? 0 : 1;
 292                         reg = HVS_READ(SCALER_DISPECTRL);
 293                         HVS_WRITE(SCALER_DISPECTRL,
 294                                   (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) |
 295                                   VC4_SET_FIELD(mux, SCALER_DISPECTRL_DSP2_MUX));
 296                         break;
 297
 298                 case 3:
 299                         if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED)
 300                                 mux = 3;
 301                         else
 302                                 mux = vc4_state->assigned_channel;
 303
 304                         reg = HVS_READ(SCALER_DISPCTRL);
 305                         HVS_WRITE(SCALER_DISPCTRL,
 306                                   (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) |
 307                                   VC4_SET_FIELD(mux, SCALER_DISPCTRL_DSP3_MUX));
 308                         break;
 309
 310                 case 4:
 311                         if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED)
 312                                 mux = 3;
 313                         else
 314                                 mux = vc4_state->assigned_channel;
 315
 316                         reg = HVS_READ(SCALER_DISPEOLN);
 317                         HVS_WRITE(SCALER_DISPEOLN,
 318                                   (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) |
 319                                   VC4_SET_FIELD(mux, SCALER_DISPEOLN_DSP4_MUX));
 320
 321                         break;
 322
 323                 case 5:
 324                         if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED)
 325                                 mux = 3;
 326                         else
 327                                 mux = vc4_state->assigned_channel;
 328
 329                         reg = HVS_READ(SCALER_DISPDITHER);
 330                         HVS_WRITE(SCALER_DISPDITHER,
 331                                   (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) |
 332                                   VC4_SET_FIELD(mux, SCALER_DISPDITHER_DSP5_MUX));
 333                         break;
 334
 335                 default:
 336                         break;
 337                 }
 338         }
 339 }
 340
 341 static void vc4_atomic_commit_tail(struct drm_atomic_state *state)
 342 {
 343         struct drm_device *dev = state->dev;
 344         struct vc4_dev *vc4 = to_vc4_dev(dev);
 345         struct vc4_hvs *hvs = vc4->hvs;
 346         struct drm_crtc_state *new_crtc_state;
 347         struct vc4_hvs_state *new_hvs_state;
 348         struct drm_crtc *crtc;
 349         struct vc4_hvs_state *old_hvs_state;
 350         unsigned int channel;
 351         struct clk_request *core_req;
 352         int i;
 353
 354         old_hvs_state = vc4_hvs_get_old_global_state(state);
 355         if (WARN_ON(!old_hvs_state))
 356                 return;
 357
 358         new_hvs_state = vc4_hvs_get_new_global_state(state);
 359         if (WARN_ON(!new_hvs_state))
 360                 return;
 361
 362         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
 363                 struct vc4_crtc_state *vc4_crtc_state;
 364
 365                 if (!new_crtc_state->commit || vc4->firmware_kms)
 366                         continue;
 367
 368                 vc4_crtc_state = to_vc4_crtc_state(new_crtc_state);
 369                 vc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel);
 370         }
 371
 372         for (channel = 0; channel < HVS_NUM_CHANNELS; channel++) {
 373                 struct drm_crtc_commit *commit;
 374                 int ret;
 375
 376                 if (!old_hvs_state->fifo_state[channel].in_use)
 377                         continue;
 378
 379                 commit = old_hvs_state->fifo_state[channel].pending_commit;
 380                 if (!commit)
 381                         continue;
 382
 383                 ret = drm_crtc_commit_wait(commit);
 384                 if (ret)
 385                         drm_err(dev, "Timed out waiting for commit\n");
 386
 387                 drm_crtc_commit_put(commit);
 388                 old_hvs_state->fifo_state[channel].pending_commit = NULL;
 389         }
 390
 391         if (vc4->hvs && vc4->hvs->hvs5) {
 392                 unsigned long core_rate = max_t(unsigned long,
 393                                                 500000000,
 394                                                 new_hvs_state->core_clock_rate);
 395
 396                 core_req = clk_request_start(hvs->core_clk, core_rate);
 397                 /*
 398                  * And remove the previous one based on the HVS
 399                  * requirements if any.
 400                  */
 401                clk_request_done(hvs->core_req);
 402         }
 403
 404         drm_atomic_helper_commit_modeset_disables(dev, state);
 405
 406         vc4_ctm_commit(vc4, state);
 407
 408         if (!vc4->firmware_kms) {
 409                 if (vc4->hvs && vc4->hvs->hvs5)
 410                         vc5_hvs_pv_muxing_commit(vc4, state);
 411                 else
 412                         vc4_hvs_pv_muxing_commit(vc4, state);
 413         }
 414
 415         drm_atomic_helper_commit_planes(dev, state, 0);
 416
 417         drm_atomic_helper_commit_modeset_enables(dev, state);
 418
 419         drm_atomic_helper_fake_vblank(state);
 420
 421         drm_atomic_helper_commit_hw_done(state);
 422
 423         drm_atomic_helper_wait_for_flip_done(dev, state);
 424
 425         drm_atomic_helper_cleanup_planes(dev, state);
 426
 427         if (vc4->hvs && vc4->hvs->hvs5) {
 428                 drm_dbg(dev, "Running the core clock at %lu Hz\n",
 429                         new_hvs_state->core_clock_rate);
 430
 431                 /*
 432                  * Request a clock rate based on the current HVS
 433                  * requirements.
 434                  */
 435                 hvs->core_req = clk_request_start(hvs->core_clk,
 436                                                   new_hvs_state->core_clock_rate);
 437
 438                 /* And drop the temporary request */
 439                 clk_request_done(core_req);
 440         }
 441 }
 442
 443 static int vc4_atomic_commit_setup(struct drm_atomic_state *state)
 444 {
 445         struct drm_device *dev = state->dev;
 446         struct vc4_dev *vc4 = to_vc4_dev(dev);
 447         struct drm_crtc_state *crtc_state;
 448         struct vc4_hvs_state *hvs_state;
 449         struct drm_crtc *crtc;
 450         unsigned int i;
 451
 452         /* We know for sure we don't want an async update here. Set
 453          * state->legacy_cursor_update to false to prevent
 454          * drm_atomic_helper_setup_commit() from auto-completing
 455          * commit->flip_done.
 456          */
 457         if (!vc4->firmware_kms)
 458                 state->legacy_cursor_update = false;
 459
 460         hvs_state = vc4_hvs_get_new_global_state(state);
 461         if (WARN_ON(IS_ERR(hvs_state)))
 462                 return PTR_ERR(hvs_state);
 463
 464         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 465                 struct vc4_crtc_state *vc4_crtc_state =
 466                         to_vc4_crtc_state(crtc_state);
 467                 unsigned int channel =
 468                         vc4_crtc_state->assigned_channel;
 469
 470                 if (channel == VC4_HVS_CHANNEL_DISABLED)
 471                         continue;
 472
 473                 if (!hvs_state->fifo_state[channel].in_use)
 474                         continue;
 475
 476                 hvs_state->fifo_state[channel].pending_commit =
 477                         drm_crtc_commit_get(crtc_state->commit);
 478         }
 479
 480         return 0;
 481 }
 482
 483 static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev,
 484                                              struct drm_file *file_priv,
 485                                              const struct drm_mode_fb_cmd2 *mode_cmd)
 486 {
 487         struct drm_mode_fb_cmd2 mode_cmd_local;
 488
 489         /* If the user didn't specify a modifier, use the
 490          * vc4_set_tiling_ioctl() state for the BO.
 491          */
 492         if (!(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) {
 493                 struct drm_gem_object *gem_obj;
 494                 struct vc4_bo *bo;
 495
 496                 gem_obj = drm_gem_object_lookup(file_priv,
 497                                                 mode_cmd->handles[0]);
 498                 if (!gem_obj) {
 499                         DRM_DEBUG("Failed to look up GEM BO %d\n",
 500                                   mode_cmd->handles[0]);
 501                         return ERR_PTR(-ENOENT);
 502                 }
 503                 bo = to_vc4_bo(gem_obj);
 504
 505                 mode_cmd_local = *mode_cmd;
 506
 507                 if (bo->t_format) {
 508                         mode_cmd_local.modifier[0] =
 509                                 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED;
 510                 } else {
 511                         mode_cmd_local.modifier[0] = DRM_FORMAT_MOD_NONE;
 512                 }
 513
 514                 drm_gem_object_put(gem_obj);
 515
 516                 mode_cmd = &mode_cmd_local;
 517         }
 518
 519         return drm_gem_fb_create(dev, file_priv, mode_cmd);
 520 }
 521
 522 /* Our CTM has some peculiar limitations: we can only enable it for one CRTC
 523  * at a time and the HW only supports S0.9 scalars. To account for the latter,
 524  * we don't allow userland to set a CTM that we have no hope of approximating.
 525  */
 526 static int
 527 vc4_ctm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
 528 {
 529         struct vc4_dev *vc4 = to_vc4_dev(dev);
 530         struct vc4_ctm_state *ctm_state = NULL;
 531         struct drm_crtc *crtc;
 532         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 533         struct drm_color_ctm *ctm;
 534         int i;
 535
 536         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 537                 /* CTM is being disabled. */
 538                 if (!new_crtc_state->ctm && old_crtc_state->ctm) {
 539                         ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
 540                         if (IS_ERR(ctm_state))
 541                                 return PTR_ERR(ctm_state);
 542                         ctm_state->fifo = 0;
 543                 }
 544         }
 545
 546         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 547                 if (new_crtc_state->ctm == old_crtc_state->ctm)
 548                         continue;
 549
 550                 if (!ctm_state) {
 551                         ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
 552                         if (IS_ERR(ctm_state))
 553                                 return PTR_ERR(ctm_state);
 554                 }
 555
 556                 /* CTM is being enabled or the matrix changed. */
 557                 if (new_crtc_state->ctm) {
 558                         struct vc4_crtc_state *vc4_crtc_state =
 559                                 to_vc4_crtc_state(new_crtc_state);
 560
 561                         /* fifo is 1-based since 0 disables CTM. */
 562                         int fifo = vc4_crtc_state->assigned_channel + 1;
 563
 564                         /* Check userland isn't trying to turn on CTM for more
 565                          * than one CRTC at a time.
 566                          */
 567                         if (ctm_state->fifo && ctm_state->fifo != fifo) {
 568                                 DRM_DEBUG_DRIVER("Too many CTM configured\n");
 569                                 return -EINVAL;
 570                         }
 571
 572                         /* Check we can approximate the specified CTM.
 573                          * We disallow scalars |c| > 1.0 since the HW has
 574                          * no integer bits.
 575                          */
 576                         ctm = new_crtc_state->ctm->data;
 577                         for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) {
 578                                 u64 val = ctm->matrix[i];
 579
 580                                 val &= ~BIT_ULL(63);
 581                                 if (val > BIT_ULL(32))
 582                                         return -EINVAL;
 583                         }
 584
 585                         ctm_state->fifo = fifo;
 586                         ctm_state->ctm = ctm;
 587                 }
 588         }
 589
 590         return 0;
 591 }
 592
 593 static int vc4_load_tracker_atomic_check(struct drm_atomic_state *state)
 594 {
 595         struct drm_plane_state *old_plane_state, *new_plane_state;
 596         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 597         struct vc4_load_tracker_state *load_state;
 598         struct drm_private_state *priv_state;
 599         struct drm_plane *plane;
 600         int i;
 601
 602         priv_state = drm_atomic_get_private_obj_state(state,
 603                                                       &vc4->load_tracker);
 604         if (IS_ERR(priv_state))
 605                 return PTR_ERR(priv_state);
 606
 607         load_state = to_vc4_load_tracker_state(priv_state);
 608         for_each_oldnew_plane_in_state(state, plane, old_plane_state,
 609                                        new_plane_state, i) {
 610                 struct vc4_plane_state *vc4_plane_state;
 611
 612                 if (old_plane_state->fb && old_plane_state->crtc) {
 613                         vc4_plane_state = to_vc4_plane_state(old_plane_state);
 614                         load_state->membus_load -= vc4_plane_state->membus_load;
 615                         load_state->hvs_load -= vc4_plane_state->hvs_load;
 616                 }
 617
 618                 if (new_plane_state->fb && new_plane_state->crtc) {
 619                         vc4_plane_state = to_vc4_plane_state(new_plane_state);
 620                         load_state->membus_load += vc4_plane_state->membus_load;
 621                         load_state->hvs_load += vc4_plane_state->hvs_load;
 622                 }
 623         }
 624
 625         /* Don't check the load when the tracker is disabled. */
 626         if (!vc4->load_tracker_enabled)
 627                 return 0;
 628
 629         /* The absolute limit is 2Gbyte/sec, but let's take a margin to let
 630          * the system work when other blocks are accessing the memory.
 631          */
 632         if (load_state->membus_load > SZ_1G + SZ_512M)
 633                 return -ENOSPC;
 634
 635         /* HVS clock is supposed to run @ 250Mhz, let's take a margin and
 636          * consider the maximum number of cycles is 240M.
 637          */
 638         if (load_state->hvs_load > 240000000ULL)
 639                 return -ENOSPC;
 640
 641         return 0;
 642 }
 643
 644 static struct drm_private_state *
 645 vc4_load_tracker_duplicate_state(struct drm_private_obj *obj)
 646 {
 647         struct vc4_load_tracker_state *state;
 648
 649         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
 650         if (!state)
 651                 return NULL;
 652
 653         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 654
 655         return &state->base;
 656 }
 657
 658 static void vc4_load_tracker_destroy_state(struct drm_private_obj *obj,
 659                                            struct drm_private_state *state)
 660 {
 661         struct vc4_load_tracker_state *load_state;
 662
 663         load_state = to_vc4_load_tracker_state(state);
 664         kfree(load_state);
 665 }
 666
 667 static const struct drm_private_state_funcs vc4_load_tracker_state_funcs = {
 668         .atomic_duplicate_state = vc4_load_tracker_duplicate_state,
 669         .atomic_destroy_state = vc4_load_tracker_destroy_state,
 670 };
 671
 672 static void vc4_load_tracker_obj_fini(struct drm_device *dev, void *unused)
 673 {
 674         struct vc4_dev *vc4 = to_vc4_dev(dev);
 675
 676         drm_atomic_private_obj_fini(&vc4->load_tracker);
 677 }
 678
 679 static int vc4_load_tracker_obj_init(struct vc4_dev *vc4)
 680 {
 681         struct vc4_load_tracker_state *load_state;
 682
 683         load_state = kzalloc(sizeof(*load_state), GFP_KERNEL);
 684         if (!load_state)
 685                 return -ENOMEM;
 686
 687         drm_atomic_private_obj_init(&vc4->base, &vc4->load_tracker,
 688                                     &load_state->base,
 689                                     &vc4_load_tracker_state_funcs);
 690
 691         return drmm_add_action_or_reset(&vc4->base, vc4_load_tracker_obj_fini, NULL);
 692 }
 693
 694 static struct drm_private_state *
 695 vc4_hvs_channels_duplicate_state(struct drm_private_obj *obj)
 696 {
 697         struct vc4_hvs_state *old_state = to_vc4_hvs_state(obj->state);
 698         struct vc4_hvs_state *state;
 699         unsigned int i;
 700
 701         state = kzalloc(sizeof(*state), GFP_KERNEL);
 702         if (!state)
 703                 return NULL;
 704
 705         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 706
 707         for (i = 0; i < HVS_NUM_CHANNELS; i++) {
 708                 state->fifo_state[i].in_use = old_state->fifo_state[i].in_use;
 709                 state->fifo_state[i].fifo_load = old_state->fifo_state[i].fifo_load;
 710         }
 711
 712         state->core_clock_rate = old_state->core_clock_rate;
 713
 714         return &state->base;
 715 }
 716
 717 static void vc4_hvs_channels_destroy_state(struct drm_private_obj *obj,
 718                                            struct drm_private_state *state)
 719 {
 720         struct vc4_hvs_state *hvs_state = to_vc4_hvs_state(state);
 721         unsigned int i;
 722
 723         for (i = 0; i < HVS_NUM_CHANNELS; i++) {
 724                 if (!hvs_state->fifo_state[i].pending_commit)
 725                         continue;
 726
 727                 drm_crtc_commit_put(hvs_state->fifo_state[i].pending_commit);
 728         }
 729
 730         kfree(hvs_state);
 731 }
 732
 733 static const struct drm_private_state_funcs vc4_hvs_state_funcs = {
 734         .atomic_duplicate_state = vc4_hvs_channels_duplicate_state,
 735         .atomic_destroy_state = vc4_hvs_channels_destroy_state,
 736 };
 737
 738 static void vc4_hvs_channels_obj_fini(struct drm_device *dev, void *unused)
 739 {
 740         struct vc4_dev *vc4 = to_vc4_dev(dev);
 741
 742         drm_atomic_private_obj_fini(&vc4->hvs_channels);
 743 }
 744
 745 static int vc4_hvs_channels_obj_init(struct vc4_dev *vc4)
 746 {
 747         struct vc4_hvs_state *state;
 748
 749         state = kzalloc(sizeof(*state), GFP_KERNEL);
 750         if (!state)
 751                 return -ENOMEM;
 752
 753         drm_atomic_private_obj_init(&vc4->base, &vc4->hvs_channels,
 754                                     &state->base,
 755                                     &vc4_hvs_state_funcs);
 756
 757         return drmm_add_action_or_reset(&vc4->base, vc4_hvs_channels_obj_fini, NULL);
 758 }
 759
 760 /*
 761  * The BCM2711 HVS has up to 7 outputs connected to the pixelvalves and
 762  * the TXP (and therefore all the CRTCs found on that platform).
 763  *
 764  * The naive (and our initial) implementation would just iterate over
 765  * all the active CRTCs, try to find a suitable FIFO, and then remove it
 766  * from the pool of available FIFOs. However, there are a few corner
 767  * cases that need to be considered:
 768  *
 769  * - When running in a dual-display setup (so with two CRTCs involved),
 770  *   we can update the state of a single CRTC (for example by changing
 771  *   its mode using xrandr under X11) without affecting the other. In
 772  *   this case, the other CRTC wouldn't be in the state at all, so we
 773  *   need to consider all the running CRTCs in the DRM device to assign
 774  *   a FIFO, not just the one in the state.
 775  *
 776  * - To fix the above, we can't use drm_atomic_get_crtc_state on all
 777  *   enabled CRTCs to pull their CRTC state into the global state, since
 778  *   a page flip would start considering their vblank to complete. Since
 779  *   we don't have a guarantee that they are actually active, that
 780  *   vblank might never happen, and shouldn't even be considered if we
 781  *   want to do a page flip on a single CRTC. That can be tested by
 782  *   doing a modetest -v first on HDMI1 and then on HDMI0.
 783  *
 784  * - Since we need the pixelvalve to be disabled and enabled back when
 785  *   the FIFO is changed, we should keep the FIFO assigned for as long
 786  *   as the CRTC is enabled, only considering it free again once that
 787  *   CRTC has been disabled. This can be tested by booting X11 on a
 788  *   single display, and changing the resolution down and then back up.
 789  */
 790 static int vc4_pv_muxing_atomic_check(struct drm_device *dev,
 791                                       struct drm_atomic_state *state)
 792 {
 793         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 794         struct vc4_hvs_state *hvs_new_state;
 795         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 796         struct drm_crtc *crtc;
 797         unsigned int unassigned_channels = 0;
 798         unsigned int i;
 799
 800         hvs_new_state = vc4_hvs_get_global_state(state);
 801         if (IS_ERR(hvs_new_state))
 802                 return PTR_ERR(hvs_new_state);
 803
 804         for (i = 0; i < ARRAY_SIZE(hvs_new_state->fifo_state); i++)
 805                 if (!hvs_new_state->fifo_state[i].in_use)
 806                         unassigned_channels |= BIT(i);
 807
 808         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 809                 struct vc4_crtc_state *old_vc4_crtc_state =
 810                         to_vc4_crtc_state(old_crtc_state);
 811                 struct vc4_crtc_state *new_vc4_crtc_state =
 812                         to_vc4_crtc_state(new_crtc_state);
 813                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 814                 unsigned int matching_channels;
 815                 unsigned int channel;
 816
 817                 if (vc4->firmware_kms)
 818                         continue;
 819
 820                 /* Nothing to do here, let's skip it */
 821                 if (old_crtc_state->enable == new_crtc_state->enable)
 822                         continue;
 823
 824                 /* Muxing will need to be modified, mark it as such */
 825                 new_vc4_crtc_state->update_muxing = true;
 826
 827                 /* If we're disabling our CRTC, we put back our channel */
 828                 if (!new_crtc_state->enable) {
 829                         channel = old_vc4_crtc_state->assigned_channel;
 830                         hvs_new_state->fifo_state[channel].in_use = false;
 831                         new_vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
 832                         continue;
 833                 }
 834
 835                 /*
 836                  * The problem we have to solve here is that we have
 837                  * up to 7 encoders, connected to up to 6 CRTCs.
 838                  *
 839                  * Those CRTCs, depending on the instance, can be
 840                  * routed to 1, 2 or 3 HVS FIFOs, and we need to set
 841                  * the change the muxing between FIFOs and outputs in
 842                  * the HVS accordingly.
 843                  *
 844                  * It would be pretty hard to come up with an
 845                  * algorithm that would generically solve
 846                  * this. However, the current routing trees we support
 847                  * allow us to simplify a bit the problem.
 848                  *
 849                  * Indeed, with the current supported layouts, if we
 850                  * try to assign in the ascending crtc index order the
 851                  * FIFOs, we can't fall into the situation where an
 852                  * earlier CRTC that had multiple routes is assigned
 853                  * one that was the only option for a later CRTC.
 854                  *
 855                  * If the layout changes and doesn't give us that in
 856                  * the future, we will need to have something smarter,
 857                  * but it works so far.
 858                  */
 859                 matching_channels = unassigned_channels & vc4_crtc->data->hvs_available_channels;
 860                 if (!matching_channels)
 861                         return -EINVAL;
 862
 863                 channel = ffs(matching_channels) - 1;
 864                 new_vc4_crtc_state->assigned_channel = channel;
 865                 unassigned_channels &= ~BIT(channel);
 866                 hvs_new_state->fifo_state[channel].in_use = true;
 867         }
 868
 869         return 0;
 870 }
 871
 872 static int
 873 vc4_core_clock_atomic_check(struct drm_atomic_state *state)
 874 {
 875         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 876         struct drm_private_state *priv_state;
 877         struct vc4_hvs_state *hvs_new_state;
 878         struct vc4_load_tracker_state *load_state;
 879         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 880         struct drm_crtc *crtc;
 881         unsigned int num_outputs;
 882         unsigned long pixel_rate;
 883         unsigned long cob_rate;
 884         unsigned int i;
 885
 886         priv_state = drm_atomic_get_private_obj_state(state,
 887                                                       &vc4->load_tracker);
 888         if (IS_ERR(priv_state))
 889                 return PTR_ERR(priv_state);
 890
 891         load_state = to_vc4_load_tracker_state(priv_state);
 892
 893         hvs_new_state = vc4_hvs_get_global_state(state);
 894         if (!hvs_new_state)
 895                 return -EINVAL;
 896
 897         for_each_oldnew_crtc_in_state(state, crtc,
 898                                       old_crtc_state,
 899                                       new_crtc_state,
 900                                       i) {
 901                 if (old_crtc_state->active) {
 902                         struct vc4_crtc_state *old_vc4_state =
 903                                 to_vc4_crtc_state(old_crtc_state);
 904                         unsigned int channel = old_vc4_state->assigned_channel;
 905
 906                         hvs_new_state->fifo_state[channel].fifo_load = 0;
 907                 }
 908
 909                 if (new_crtc_state->active) {
 910                         struct vc4_crtc_state *new_vc4_state =
 911                                 to_vc4_crtc_state(new_crtc_state);
 912                         unsigned int channel = new_vc4_state->assigned_channel;
 913
 914                         hvs_new_state->fifo_state[channel].fifo_load =
 915                                 new_vc4_state->hvs_load;
 916                 }
 917         }
 918
 919         cob_rate = 0;
 920         num_outputs = 0;
 921         for (i = 0; i < HVS_NUM_CHANNELS; i++) {
 922                 if (!hvs_new_state->fifo_state[i].in_use)
 923                         continue;
 924
 925                 num_outputs++;
 926                 cob_rate += hvs_new_state->fifo_state[i].fifo_load;
 927         }
 928
 929         pixel_rate = load_state->hvs_load;
 930         if (num_outputs > 1) {
 931                 pixel_rate = (pixel_rate * 40) / 100;
 932         } else {
 933                 pixel_rate = (pixel_rate * 60) / 100;
 934         }
 935
 936         hvs_new_state->core_clock_rate = max(cob_rate, pixel_rate);
 937
 938         return 0;
 939 }
 940
 941
 942 static int
 943 vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
 944 {
 945         int ret;
 946
 947         ret = vc4_pv_muxing_atomic_check(dev, state);
 948         if (ret)
 949                 return ret;
 950
 951         ret = vc4_ctm_atomic_check(dev, state);
 952         if (ret < 0)
 953                 return ret;
 954
 955         ret = drm_atomic_helper_check(dev, state);
 956         if (ret)
 957                 return ret;
 958
 959         ret = vc4_load_tracker_atomic_check(state);
 960         if (ret)
 961                 return ret;
 962
 963         return vc4_core_clock_atomic_check(state);
 964 }
 965
 966 static struct drm_mode_config_helper_funcs vc4_mode_config_helpers = {
 967         .atomic_commit_setup    = vc4_atomic_commit_setup,
 968         .atomic_commit_tail     = vc4_atomic_commit_tail,
 969 };
 970
 971 static const struct drm_mode_config_funcs vc4_mode_funcs = {
 972         .atomic_check = vc4_atomic_check,
 973         .atomic_commit = drm_atomic_helper_commit,
 974         .fb_create = vc4_fb_create,
 975 };
 976
 977 int vc4_kms_load(struct drm_device *dev)
 978 {
 979         struct vc4_dev *vc4 = to_vc4_dev(dev);
 980         bool is_vc5 = of_device_is_compatible(dev->dev->of_node,
 981                                               "brcm,bcm2711-vc5");
 982         int ret;
 983
 984         /*
 985          * The limits enforced by the load tracker aren't relevant for
 986          * the BCM2711, but the load tracker computations are used for
 987          * the core clock rate calculation.
 988          */
 989         if (!is_vc5) {
 990                 /* Start with the load tracker enabled. Can be
 991                  * disabled through the debugfs load_tracker file.
 992                  */
 993                 vc4->load_tracker_enabled = true;
 994         }
 995
 996         /* Set support for vblank irq fast disable, before drm_vblank_init() */
 997         dev->vblank_disable_immediate = true;
 998
 999         ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
1000         if (ret < 0) {
1001                 dev_err(dev->dev, "failed to initialize vblank\n");
1002                 return ret;
1003         }
1004
1005         if (is_vc5) {
1006                 dev->mode_config.max_width = 7680;
1007                 dev->mode_config.max_height = 7680;
1008         } else {
1009                 dev->mode_config.max_width = 2048;
1010                 dev->mode_config.max_height = 2048;
1011         }
1012
1013         dev->mode_config.funcs = &vc4_mode_funcs;
1014         dev->mode_config.helper_private = &vc4_mode_config_helpers;
1015         dev->mode_config.preferred_depth = 24;
1016         dev->mode_config.async_page_flip = true;
1017         if (vc4->firmware_kms)
1018                 dev->mode_config.normalize_zpos = true;
1019
1020         ret = vc4_ctm_obj_init(vc4);
1021         if (ret)
1022                 return ret;
1023
1024         ret = vc4_load_tracker_obj_init(vc4);
1025         if (ret)
1026                 return ret;
1027
1028         ret = vc4_hvs_channels_obj_init(vc4);
1029         if (ret)
1030                 return ret;
1031
1032         drm_mode_config_reset(dev);
1033
1034         drm_kms_helper_poll_init(dev);
1035
1036         return 0;
1037 }