drivers/gpu/drm/vc4/vc4_kms.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 KMS
   8  *
   9  * This is the general code for implementing KMS mode setting that
  10  * doesn't clearly associate with any of the other objects (plane,
  11  * crtc, HDMI encoder).
  12  */
  13
  14 #include <linux/bitfield.h>
  15 #include <linux/bitops.h>
  16 #include <linux/clk.h>
  17
  18 #include <drm/drm_atomic.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_crtc.h>
  21 #include <drm/drm_gem_framebuffer_helper.h>
  22 #include <drm/drm_plane_helper.h>
  23 #include <drm/drm_probe_helper.h>
  24 #include <drm/drm_vblank.h>
  25 #include <drm/drm_drv.h>
  26
  27 #include "vc4_drv.h"
  28 #include "vc4_regs.h"
  29
  30 struct vc4_ctm_state {
  31         struct drm_private_state base;
  32         struct drm_color_ctm *ctm;
  33         int fifo;
  34 };
  35
  36 static struct vc4_ctm_state *to_vc4_ctm_state(struct drm_private_state *priv)
  37 {
  38         return container_of(priv, struct vc4_ctm_state, base);
  39 }
  40
  41 struct vc4_load_tracker_state {
  42         struct drm_private_state base;
  43         u64 hvs_load;
  44         u64 membus_load;
  45 };
  46
  47 static struct vc4_load_tracker_state *
  48 to_vc4_load_tracker_state(struct drm_private_state *priv)
  49 {
  50         return container_of(priv, struct vc4_load_tracker_state, base);
  51 }
  52
  53 static struct vc4_ctm_state *vc4_get_ctm_state(struct drm_atomic_state *state,
  54                                                struct drm_private_obj *manager)
  55 {
  56         struct drm_device *dev = state->dev;
  57         struct vc4_dev *vc4 = dev->dev_private;
  58         struct drm_private_state *priv_state;
  59         int ret;
  60
  61         ret = drm_modeset_lock(&vc4->ctm_state_lock, state->acquire_ctx);
  62         if (ret)
  63                 return ERR_PTR(ret);
  64
  65         priv_state = drm_atomic_get_private_obj_state(state, manager);
  66         if (IS_ERR(priv_state))
  67                 return ERR_CAST(priv_state);
  68
  69         return to_vc4_ctm_state(priv_state);
  70 }
  71
  72 static struct drm_private_state *
  73 vc4_ctm_duplicate_state(struct drm_private_obj *obj)
  74 {
  75         struct vc4_ctm_state *state;
  76
  77         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
  78         if (!state)
  79                 return NULL;
  80
  81         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
  82
  83         return &state->base;
  84 }
  85
  86 static void vc4_ctm_destroy_state(struct drm_private_obj *obj,
  87                                   struct drm_private_state *state)
  88 {
  89         struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(state);
  90
  91         kfree(ctm_state);
  92 }
  93
  94 static const struct drm_private_state_funcs vc4_ctm_state_funcs = {
  95         .atomic_duplicate_state = vc4_ctm_duplicate_state,
  96         .atomic_destroy_state = vc4_ctm_destroy_state,
  97 };
  98
  99 /* Converts a DRM S31.32 value to the HW S0.9 format. */
 100 static u16 vc4_ctm_s31_32_to_s0_9(u64 in)
 101 {
 102         u16 r;
 103
 104         /* Sign bit. */
 105         r = in & BIT_ULL(63) ? BIT(9) : 0;
 106
 107         if ((in & GENMASK_ULL(62, 32)) > 0) {
 108                 /* We have zero integer bits so we can only saturate here. */
 109                 r |= GENMASK(8, 0);
 110         } else {
 111                 /* Otherwise take the 9 most important fractional bits. */
 112                 r |= (in >> 23) & GENMASK(8, 0);
 113         }
 114
 115         return r;
 116 }
 117
 118 static void
 119 vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state)
 120 {
 121         struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state);
 122         struct drm_color_ctm *ctm = ctm_state->ctm;
 123
 124         if (vc4->firmware_kms)
 125                 return;
 126
 127         if (ctm_state->fifo) {
 128                 HVS_WRITE(SCALER_OLEDCOEF2,
 129                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]),
 130                                         SCALER_OLEDCOEF2_R_TO_R) |
 131                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]),
 132                                         SCALER_OLEDCOEF2_R_TO_G) |
 133                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]),
 134                                         SCALER_OLEDCOEF2_R_TO_B));
 135                 HVS_WRITE(SCALER_OLEDCOEF1,
 136                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]),
 137                                         SCALER_OLEDCOEF1_G_TO_R) |
 138                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]),
 139                                         SCALER_OLEDCOEF1_G_TO_G) |
 140                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]),
 141                                         SCALER_OLEDCOEF1_G_TO_B));
 142                 HVS_WRITE(SCALER_OLEDCOEF0,
 143                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]),
 144                                         SCALER_OLEDCOEF0_B_TO_R) |
 145                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]),
 146                                         SCALER_OLEDCOEF0_B_TO_G) |
 147                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]),
 148                                         SCALER_OLEDCOEF0_B_TO_B));
 149         }
 150
 151         HVS_WRITE(SCALER_OLEDOFFS,
 152                   VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO));
 153 }
 154
 155 static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4,
 156                                      struct drm_atomic_state *state)
 157 {
 158         struct drm_crtc_state *crtc_state;
 159         struct drm_crtc *crtc;
 160         unsigned int i;
 161
 162         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 163                 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 164                 u32 dispctrl;
 165                 u32 dsp3_mux;
 166
 167                 if (!crtc_state->active)
 168                         continue;
 169
 170                 if (vc4_state->assigned_channel != 2)
 171                         continue;
 172
 173                 /*
 174                  * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
 175                  * FIFO X'.
 176                  * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
 177                  *
 178                  * DSP3 is connected to FIFO2 unless the transposer is
 179                  * enabled. In this case, FIFO 2 is directly accessed by the
 180                  * TXP IP, and we need to disable the FIFO2 -> pixelvalve1
 181                  * route.
 182                  */
 183                 if (vc4_state->feed_txp)
 184                         dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
 185                 else
 186                         dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
 187
 188                 dispctrl = HVS_READ(SCALER_DISPCTRL) &
 189                            ~SCALER_DISPCTRL_DSP3_MUX_MASK;
 190                 HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
 191         }
 192 }
 193
 194 static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4,
 195                                      struct drm_atomic_state *state)
 196 {
 197         struct drm_crtc_state *crtc_state;
 198         struct drm_crtc *crtc;
 199         unsigned char dsp2_mux = 0;
 200         unsigned char dsp3_mux = 3;
 201         unsigned char dsp4_mux = 3;
 202         unsigned char dsp5_mux = 3;
 203         unsigned int i;
 204         u32 reg;
 205
 206         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 207                 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 208                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 209
 210                 if (!crtc_state->active)
 211                         continue;
 212
 213                 switch (vc4_crtc->data->hvs_output) {
 214                 case 2:
 215                         dsp2_mux = (vc4_state->assigned_channel == 2) ? 0 : 1;
 216                         break;
 217
 218                 case 3:
 219                         dsp3_mux = vc4_state->assigned_channel;
 220                         break;
 221
 222                 case 4:
 223                         dsp4_mux = vc4_state->assigned_channel;
 224                         break;
 225
 226                 case 5:
 227                         dsp5_mux = vc4_state->assigned_channel;
 228                         break;
 229
 230                 default:
 231                         break;
 232                 }
 233         }
 234
 235         reg = HVS_READ(SCALER_DISPECTRL);
 236         HVS_WRITE(SCALER_DISPECTRL,
 237                   (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) |
 238                   VC4_SET_FIELD(dsp2_mux, SCALER_DISPECTRL_DSP2_MUX));
 239
 240         reg = HVS_READ(SCALER_DISPCTRL);
 241         HVS_WRITE(SCALER_DISPCTRL,
 242                   (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) |
 243                   VC4_SET_FIELD(dsp3_mux, SCALER_DISPCTRL_DSP3_MUX));
 244
 245         reg = HVS_READ(SCALER_DISPEOLN);
 246         HVS_WRITE(SCALER_DISPEOLN,
 247                   (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) |
 248                   VC4_SET_FIELD(dsp4_mux, SCALER_DISPEOLN_DSP4_MUX));
 249
 250         reg = HVS_READ(SCALER_DISPDITHER);
 251         HVS_WRITE(SCALER_DISPDITHER,
 252                   (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) |
 253                   VC4_SET_FIELD(dsp5_mux, SCALER_DISPDITHER_DSP5_MUX));
 254 }
 255
 256
 257 static void
 258 vc4_atomic_complete_commit(struct drm_atomic_state *state)
 259 {
 260         struct drm_device *dev = state->dev;
 261         struct vc4_dev *vc4 = to_vc4_dev(dev);
 262         struct vc4_hvs *hvs = vc4->hvs;
 263         struct vc4_crtc *vc4_crtc;
 264         int i;
 265
 266         for (i = 0; vc4->hvs && i < dev->mode_config.num_crtc; i++) {
 267                 struct __drm_crtcs_state *_state = &state->crtcs[i];
 268                 struct vc4_crtc_state *vc4_crtc_state;
 269
 270                 if (!_state->ptr || !_state->commit)
 271                         continue;
 272
 273                 vc4_crtc = to_vc4_crtc(_state->ptr);
 274                 vc4_crtc_state = to_vc4_crtc_state(_state->state);
 275                 vc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel);
 276         }
 277
 278         if (vc4->hvs->hvs5)
 279                 clk_set_min_rate(hvs->core_clk, 500000000);
 280
 281         drm_atomic_helper_wait_for_fences(dev, state, false);
 282
 283         drm_atomic_helper_wait_for_dependencies(state);
 284
 285         drm_atomic_helper_commit_modeset_disables(dev, state);
 286
 287         vc4_ctm_commit(vc4, state);
 288
 289         if (vc4->hvs->hvs5)
 290                 vc5_hvs_pv_muxing_commit(vc4, state);
 291         else
 292                 vc4_hvs_pv_muxing_commit(vc4, state);
 293
 294         drm_atomic_helper_commit_planes(dev, state, 0);
 295
 296         drm_atomic_helper_commit_modeset_enables(dev, state);
 297
 298         drm_atomic_helper_fake_vblank(state);
 299
 300         drm_atomic_helper_commit_hw_done(state);
 301
 302         drm_atomic_helper_wait_for_flip_done(dev, state);
 303
 304         drm_atomic_helper_cleanup_planes(dev, state);
 305
 306         drm_atomic_helper_commit_cleanup_done(state);
 307
 308         drm_atomic_state_put(state);
 309
 310         up(&vc4->async_modeset);
 311 }
 312
 313 static void commit_work(struct work_struct *work)
 314 {
 315         struct drm_atomic_state *state = container_of(work,
 316                                                       struct drm_atomic_state,
 317                                                       commit_work);
 318         vc4_atomic_complete_commit(state);
 319 }
 320
 321 /**
 322  * vc4_atomic_commit - commit validated state object
 323  * @dev: DRM device
 324  * @state: the driver state object
 325  * @nonblock: nonblocking commit
 326  *
 327  * This function commits a with drm_atomic_helper_check() pre-validated state
 328  * object. This can still fail when e.g. the framebuffer reservation fails. For
 329  * now this doesn't implement asynchronous commits.
 330  *
 331  * RETURNS
 332  * Zero for success or -errno.
 333  */
 334 static int vc4_atomic_commit(struct drm_device *dev,
 335                              struct drm_atomic_state *state,
 336                              bool nonblock)
 337 {
 338         struct vc4_dev *vc4 = to_vc4_dev(dev);
 339         int ret;
 340
 341         if (state->async_update) {
 342                 ret = down_interruptible(&vc4->async_modeset);
 343                 if (ret)
 344                         return ret;
 345
 346                 ret = drm_atomic_helper_prepare_planes(dev, state);
 347                 if (ret) {
 348                         up(&vc4->async_modeset);
 349                         return ret;
 350                 }
 351
 352                 drm_atomic_helper_async_commit(dev, state);
 353
 354                 drm_atomic_helper_cleanup_planes(dev, state);
 355
 356                 up(&vc4->async_modeset);
 357
 358                 return 0;
 359         }
 360
 361         /* We know for sure we don't want an async update here. Set
 362          * state->legacy_cursor_update to false to prevent
 363          * drm_atomic_helper_setup_commit() from auto-completing
 364          * commit->flip_done.
 365          */
 366         if (!vc4->firmware_kms)
 367                 state->legacy_cursor_update = false;
 368         ret = drm_atomic_helper_setup_commit(state, nonblock);
 369         if (ret)
 370                 return ret;
 371
 372         INIT_WORK(&state->commit_work, commit_work);
 373
 374         ret = down_interruptible(&vc4->async_modeset);
 375         if (ret)
 376                 return ret;
 377
 378         ret = drm_atomic_helper_prepare_planes(dev, state);
 379         if (ret) {
 380                 up(&vc4->async_modeset);
 381                 return ret;
 382         }
 383
 384         if (!nonblock) {
 385                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
 386                 if (ret) {
 387                         drm_atomic_helper_cleanup_planes(dev, state);
 388                         up(&vc4->async_modeset);
 389                         return ret;
 390                 }
 391         }
 392
 393         /*
 394          * This is the point of no return - everything below never fails except
 395          * when the hw goes bonghits. Which means we can commit the new state on
 396          * the software side now.
 397          */
 398
 399         BUG_ON(drm_atomic_helper_swap_state(state, false) < 0);
 400
 401         /*
 402          * Everything below can be run asynchronously without the need to grab
 403          * any modeset locks at all under one condition: It must be guaranteed
 404          * that the asynchronous work has either been cancelled (if the driver
 405          * supports it, which at least requires that the framebuffers get
 406          * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
 407          * before the new state gets committed on the software side with
 408          * drm_atomic_helper_swap_state().
 409          *
 410          * This scheme allows new atomic state updates to be prepared and
 411          * checked in parallel to the asynchronous completion of the previous
 412          * update. Which is important since compositors need to figure out the
 413          * composition of the next frame right after having submitted the
 414          * current layout.
 415          */
 416
 417         drm_atomic_state_get(state);
 418         if (nonblock)
 419                 queue_work(system_unbound_wq, &state->commit_work);
 420         else
 421                 vc4_atomic_complete_commit(state);
 422
 423         return 0;
 424 }
 425
 426 static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev,
 427                                              struct drm_file *file_priv,
 428                                              const struct drm_mode_fb_cmd2 *mode_cmd)
 429 {
 430         struct drm_mode_fb_cmd2 mode_cmd_local;
 431
 432         /* If the user didn't specify a modifier, use the
 433          * vc4_set_tiling_ioctl() state for the BO.
 434          */
 435         if (!(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) {
 436                 struct drm_gem_object *gem_obj;
 437                 struct vc4_bo *bo;
 438
 439                 gem_obj = drm_gem_object_lookup(file_priv,
 440                                                 mode_cmd->handles[0]);
 441                 if (!gem_obj) {
 442                         DRM_DEBUG("Failed to look up GEM BO %d\n",
 443                                   mode_cmd->handles[0]);
 444                         return ERR_PTR(-ENOENT);
 445                 }
 446                 bo = to_vc4_bo(gem_obj);
 447
 448                 mode_cmd_local = *mode_cmd;
 449
 450                 if (bo->t_format) {
 451                         mode_cmd_local.modifier[0] =
 452                                 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED;
 453                 } else {
 454                         mode_cmd_local.modifier[0] = DRM_FORMAT_MOD_NONE;
 455                 }
 456
 457                 drm_gem_object_put_unlocked(gem_obj);
 458
 459                 mode_cmd = &mode_cmd_local;
 460         }
 461
 462         return drm_gem_fb_create(dev, file_priv, mode_cmd);
 463 }
 464
 465 /* Our CTM has some peculiar limitations: we can only enable it for one CRTC
 466  * at a time and the HW only supports S0.9 scalars. To account for the latter,
 467  * we don't allow userland to set a CTM that we have no hope of approximating.
 468  */
 469 static int
 470 vc4_ctm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
 471 {
 472         struct vc4_dev *vc4 = to_vc4_dev(dev);
 473         struct vc4_ctm_state *ctm_state = NULL;
 474         struct drm_crtc *crtc;
 475         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 476         struct drm_color_ctm *ctm;
 477         int i;
 478
 479         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 480                 /* CTM is being disabled. */
 481                 if (!new_crtc_state->ctm && old_crtc_state->ctm) {
 482                         ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
 483                         if (IS_ERR(ctm_state))
 484                                 return PTR_ERR(ctm_state);
 485                         ctm_state->fifo = 0;
 486                 }
 487         }
 488
 489         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 490                 if (new_crtc_state->ctm == old_crtc_state->ctm)
 491                         continue;
 492
 493                 if (!ctm_state) {
 494                         ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
 495                         if (IS_ERR(ctm_state))
 496                                 return PTR_ERR(ctm_state);
 497                 }
 498
 499                 /* CTM is being enabled or the matrix changed. */
 500                 if (new_crtc_state->ctm) {
 501                         struct vc4_crtc_state *vc4_crtc_state =
 502                                 to_vc4_crtc_state(new_crtc_state);
 503
 504                         /* fifo is 1-based since 0 disables CTM. */
 505                         int fifo = vc4_crtc_state->assigned_channel + 1;
 506
 507                         /* Check userland isn't trying to turn on CTM for more
 508                          * than one CRTC at a time.
 509                          */
 510                         if (ctm_state->fifo && ctm_state->fifo != fifo) {
 511                                 DRM_DEBUG_DRIVER("Too many CTM configured\n");
 512                                 return -EINVAL;
 513                         }
 514
 515                         /* Check we can approximate the specified CTM.
 516                          * We disallow scalars |c| > 1.0 since the HW has
 517                          * no integer bits.
 518                          */
 519                         ctm = new_crtc_state->ctm->data;
 520                         for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) {
 521                                 u64 val = ctm->matrix[i];
 522
 523                                 val &= ~BIT_ULL(63);
 524                                 if (val > BIT_ULL(32))
 525                                         return -EINVAL;
 526                         }
 527
 528                         ctm_state->fifo = fifo;
 529                         ctm_state->ctm = ctm;
 530                 }
 531         }
 532
 533         return 0;
 534 }
 535
 536 static int vc4_load_tracker_atomic_check(struct drm_atomic_state *state)
 537 {
 538         struct drm_plane_state *old_plane_state, *new_plane_state;
 539         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 540         struct vc4_load_tracker_state *load_state;
 541         struct drm_private_state *priv_state;
 542         struct drm_plane *plane;
 543         int i;
 544
 545         if (!vc4->load_tracker_available)
 546                 return 0;
 547
 548         priv_state = drm_atomic_get_private_obj_state(state,
 549                                                       &vc4->load_tracker);
 550         if (IS_ERR(priv_state))
 551                 return PTR_ERR(priv_state);
 552
 553         load_state = to_vc4_load_tracker_state(priv_state);
 554         for_each_oldnew_plane_in_state(state, plane, old_plane_state,
 555                                        new_plane_state, i) {
 556                 struct vc4_plane_state *vc4_plane_state;
 557
 558                 if (old_plane_state->fb && old_plane_state->crtc) {
 559                         vc4_plane_state = to_vc4_plane_state(old_plane_state);
 560                         load_state->membus_load -= vc4_plane_state->membus_load;
 561                         load_state->hvs_load -= vc4_plane_state->hvs_load;
 562                 }
 563
 564                 if (new_plane_state->fb && new_plane_state->crtc) {
 565                         vc4_plane_state = to_vc4_plane_state(new_plane_state);
 566                         load_state->membus_load += vc4_plane_state->membus_load;
 567                         load_state->hvs_load += vc4_plane_state->hvs_load;
 568                 }
 569         }
 570
 571         /* Don't check the load when the tracker is disabled. */
 572         if (!vc4->load_tracker_enabled)
 573                 return 0;
 574
 575         /* The absolute limit is 2Gbyte/sec, but let's take a margin to let
 576          * the system work when other blocks are accessing the memory.
 577          */
 578         if (load_state->membus_load > SZ_1G + SZ_512M)
 579                 return -ENOSPC;
 580
 581         /* HVS clock is supposed to run @ 250Mhz, let's take a margin and
 582          * consider the maximum number of cycles is 240M.
 583          */
 584         if (load_state->hvs_load > 240000000ULL)
 585                 return -ENOSPC;
 586
 587         return 0;
 588 }
 589
 590 static struct drm_private_state *
 591 vc4_load_tracker_duplicate_state(struct drm_private_obj *obj)
 592 {
 593         struct vc4_load_tracker_state *state;
 594
 595         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
 596         if (!state)
 597                 return NULL;
 598
 599         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 600
 601         return &state->base;
 602 }
 603
 604 static void vc4_load_tracker_destroy_state(struct drm_private_obj *obj,
 605                                            struct drm_private_state *state)
 606 {
 607         struct vc4_load_tracker_state *load_state;
 608
 609         load_state = to_vc4_load_tracker_state(state);
 610         kfree(load_state);
 611 }
 612
 613 static const struct drm_private_state_funcs vc4_load_tracker_state_funcs = {
 614         .atomic_duplicate_state = vc4_load_tracker_duplicate_state,
 615         .atomic_destroy_state = vc4_load_tracker_destroy_state,
 616 };
 617
 618 #define NUM_CHANNELS 3
 619
 620 /*
 621  * The BCM2711 HVS has up to 7 output connected to the pixelvalves and
 622  * the TXP (and therefore all the CRTCs found on that platform).
 623  *
 624  * The naive (and our initial) implementation would just iterate over
 625  * all the active CRTCs, try to find a suitable FIFO, and then remove it
 626  * from the available FIFOs pool. However, there's a few corner cases
 627  * that need to be considered:
 628  *
 629  * - When running in a dual-display setup (so with two CRTCs involved),
 630  *   we can update the state of a single CRTC (for example by changing
 631  *   its mode using xrandr under X11) without affecting the other. In
 632  *   this case, the other CRTC wouldn't be in the state at all, so we
 633  *   need to consider all the running CRTCs in the DRM device to assign
 634  *   a FIFO, not just the one in the state.
 635  *
 636  * - Since we need the pixelvalve to be disabled and enabled back when
 637  *   the FIFO is changed, we should keep the FIFO assigned for as long
 638  *   as the CRTC is enabled, only considering it free again once that
 639  *   CRTC has been disabled. This can be tested by booting X11 on a
 640  *   single display, and changing the resolution down and then back up.
 641  */
 642 static int vc4_pv_muxing_atomic_check(struct drm_device *dev,
 643                                       struct drm_atomic_state *state)
 644 {
 645         unsigned long unassigned_channels = GENMASK(NUM_CHANNELS - 1, 0);
 646         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 647         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 648         struct drm_crtc *crtc;
 649         unsigned int i;
 650
 651         /*
 652          * Since the HVS FIFOs are shared across all the pixelvalves and
 653          * the TXP (and thus all the CRTCs), we need to pull the current
 654          * state of all the enabled CRTCs so that an update to a single
 655          * CRTC still keeps the previous FIFOs enabled and assigned to
 656          * the same CRTCs, instead of evaluating only the CRTC being
 657          * modified.
 658          */
 659         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 660                 struct drm_crtc_state *crtc_state;
 661                 if (!crtc->state->enable)
 662                         continue;
 663
 664                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 665                 if (IS_ERR(crtc_state))
 666                         return PTR_ERR(crtc_state);
 667         }
 668
 669         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 670                 struct vc4_crtc_state *new_vc4_crtc_state =
 671                         to_vc4_crtc_state(new_crtc_state);
 672                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 673                 bool is_assigned = false;
 674                 unsigned int channel;
 675
 676                 if (old_crtc_state->enable && !new_crtc_state->enable)
 677                         new_vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
 678
 679                 if (!new_crtc_state->enable)
 680                         continue;
 681
 682                 if (new_vc4_crtc_state->assigned_channel != VC4_HVS_CHANNEL_DISABLED) {
 683                         unassigned_channels &= ~BIT(new_vc4_crtc_state->assigned_channel);
 684                         continue;
 685                 }
 686
 687                 /*
 688                  * The problem we have to solve here is that we have
 689                  * up to 7 encoders, connected to up to 6 CRTCs.
 690                  *
 691                  * Those CRTCs, depending on the instance, can be
 692                  * routed to 1, 2 or 3 HVS FIFOs, and we need to set
 693                  * the change the muxing between FIFOs and outputs in
 694                  * the HVS accordingly.
 695                  *
 696                  * It would be pretty hard to come up with an
 697                  * algorithm that would generically solve
 698                  * this. However, the current routing trees we support
 699                  * allow us to simplify a bit the problem.
 700                  *
 701                  * Indeed, with the current supported layouts, if we
 702                  * try to assign in the ascending crtc index order the
 703                  * FIFOs, we can't fall into the situation where an
 704                  * earlier CRTC that had multiple routes is assigned
 705                  * one that was the only option for a later CRTC.
 706                  *
 707                  * If the layout changes and doesn't give us that in
 708                  * the future, we will need to have something smarter,
 709                  * but it works so far.
 710                  */
 711                 for_each_set_bit(channel, &unassigned_channels,
 712                                  sizeof(unassigned_channels)) {
 713
 714                         if (!(BIT(channel) & vc4_crtc->data->hvs_available_channels))
 715                                 continue;
 716
 717                         new_vc4_crtc_state->assigned_channel = channel;
 718                         unassigned_channels &= ~BIT(channel);
 719                         is_assigned = true;
 720                         break;
 721                 }
 722
 723                 if (!is_assigned)
 724                         return -EINVAL;
 725         }
 726
 727         return 0;
 728 }
 729
 730 static int
 731 vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
 732 {
 733         int ret;
 734
 735         ret = vc4_pv_muxing_atomic_check(dev, state);
 736         if (ret)
 737                 return ret;
 738
 739         ret = vc4_ctm_atomic_check(dev, state);
 740         if (ret < 0)
 741                 return ret;
 742
 743         ret = drm_atomic_helper_check(dev, state);
 744         if (ret)
 745                 return ret;
 746
 747         return vc4_load_tracker_atomic_check(state);
 748 }
 749
 750 static const struct drm_mode_config_funcs vc4_mode_funcs = {
 751         .atomic_check = vc4_atomic_check,
 752         .atomic_commit = vc4_atomic_commit,
 753         .fb_create = vc4_fb_create,
 754 };
 755
 756 int vc4_kms_load(struct drm_device *dev)
 757 {
 758         struct vc4_dev *vc4 = to_vc4_dev(dev);
 759         struct vc4_ctm_state *ctm_state;
 760         struct vc4_load_tracker_state *load_state;
 761         int ret;
 762
 763         if (!of_device_is_compatible(dev->dev->of_node, "brcm,bcm2711-vc5")) {
 764                 vc4->load_tracker_available = true;
 765
 766                 /* Start with the load tracker enabled. Can be
 767                  * disabled through the debugfs load_tracker file.
 768                  */
 769                 vc4->load_tracker_enabled = true;
 770         }
 771
 772         sema_init(&vc4->async_modeset, 1);
 773
 774         /* Set support for vblank irq fast disable, before drm_vblank_init() */
 775         dev->vblank_disable_immediate = true;
 776
 777         dev->irq_enabled = true;
 778         ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
 779         if (ret < 0) {
 780                 dev_err(dev->dev, "failed to initialize vblank\n");
 781                 return ret;
 782         }
 783
 784         if (!drm_core_check_feature(dev, DRIVER_RENDER)) {
 785                 /* No V3D as part of vc4. Assume this is Pi4. */
 786                 dev->mode_config.max_width = 7680;
 787                 dev->mode_config.max_height = 7680;
 788         } else {
 789                 dev->mode_config.max_width = 2048;
 790                 dev->mode_config.max_height = 2048;
 791         }
 792         dev->mode_config.funcs = &vc4_mode_funcs;
 793         dev->mode_config.preferred_depth = 24;
 794         dev->mode_config.async_page_flip = true;
 795         dev->mode_config.allow_fb_modifiers = true;
 796         dev->mode_config.normalize_zpos = true;
 797
 798         drm_modeset_lock_init(&vc4->ctm_state_lock);
 799
 800         ctm_state = kzalloc(sizeof(*ctm_state), GFP_KERNEL);
 801         if (!ctm_state)
 802                 return -ENOMEM;
 803
 804         drm_atomic_private_obj_init(dev, &vc4->ctm_manager, &ctm_state->base,
 805                                     &vc4_ctm_state_funcs);
 806
 807         if (vc4->load_tracker_available) {
 808                 load_state = kzalloc(sizeof(*load_state), GFP_KERNEL);
 809                 if (!load_state) {
 810                         drm_atomic_private_obj_fini(&vc4->ctm_manager);
 811                         return -ENOMEM;
 812                 }
 813
 814                 drm_atomic_private_obj_init(dev, &vc4->load_tracker,
 815                                             &load_state->base,
 816                                             &vc4_load_tracker_state_funcs);
 817         }
 818
 819         drm_mode_config_reset(dev);
 820
 821         drm_kms_helper_poll_init(dev);
 822
 823         return 0;
 824 }