drivers/gpu/drm/vc4/vc4_hdmi_regs.h

   1 #ifndef _VC4_HDMI_REGS_H_
   2 #define _VC4_HDMI_REGS_H_
   3
   4 #include <linux/pm_runtime.h>
   5
   6 #include "vc4_hdmi.h"
   7
   8 #define VC4_HDMI_PACKET_STRIDE                  0x24
   9
  10 enum vc4_hdmi_regs {
  11         VC4_INVALID = 0,
  12         VC4_HDMI,
  13         VC4_HD,
  14         VC5_CEC,
  15         VC5_CSC,
  16         VC5_DVP,
  17         VC5_PHY,
  18         VC5_RAM,
  19         VC5_RM,
  20 };
  21
  22 enum vc4_hdmi_field {
  23         HDMI_AUDIO_PACKET_CONFIG,
  24         HDMI_CEC_CNTRL_1,
  25         HDMI_CEC_CNTRL_2,
  26         HDMI_CEC_CNTRL_3,
  27         HDMI_CEC_CNTRL_4,
  28         HDMI_CEC_CNTRL_5,
  29         HDMI_CEC_CPU_CLEAR,
  30         HDMI_CEC_CPU_MASK_CLEAR,
  31         HDMI_CEC_CPU_MASK_SET,
  32         HDMI_CEC_CPU_MASK_STATUS,
  33         HDMI_CEC_CPU_STATUS,
  34         HDMI_CEC_CPU_SET,
  35
  36         /*
  37          * Transmit data, first byte is low byte of the 32-bit reg.
  38          * MSB of each byte transmitted first.
  39          */
  40         HDMI_CEC_RX_DATA_1,
  41         HDMI_CEC_RX_DATA_2,
  42         HDMI_CEC_RX_DATA_3,
  43         HDMI_CEC_RX_DATA_4,
  44         HDMI_CEC_TX_DATA_1,
  45         HDMI_CEC_TX_DATA_2,
  46         HDMI_CEC_TX_DATA_3,
  47         HDMI_CEC_TX_DATA_4,
  48         HDMI_CLOCK_STOP,
  49         HDMI_CORE_REV,
  50         HDMI_CRP_CFG,
  51         HDMI_CSC_12_11,
  52         HDMI_CSC_14_13,
  53         HDMI_CSC_22_21,
  54         HDMI_CSC_24_23,
  55         HDMI_CSC_32_31,
  56         HDMI_CSC_34_33,
  57         HDMI_CSC_CHANNEL_CTL,
  58         HDMI_CSC_CTL,
  59
  60         /*
  61          * 20-bit fields containing CTS values to be transmitted if
  62          * !EXTERNAL_CTS_EN
  63          */
  64         HDMI_CTS_0,
  65         HDMI_CTS_1,
  66         HDMI_DEEP_COLOR_CONFIG_1,
  67         HDMI_DVP_CTL,
  68         HDMI_FIFO_CTL,
  69         HDMI_FRAME_COUNT,
  70         HDMI_GCP_CONFIG,
  71         HDMI_GCP_WORD_1,
  72         HDMI_HORZA,
  73         HDMI_HORZB,
  74         HDMI_HOTPLUG,
  75         HDMI_HOTPLUG_INT,
  76
  77         /*
  78          * 3 bits per field, where each field maps from that
  79          * corresponding MAI bus channel to the given HDMI channel.
  80          */
  81         HDMI_MAI_CHANNEL_MAP,
  82         HDMI_MAI_CONFIG,
  83         HDMI_MAI_CTL,
  84
  85         /*
  86          * Register for DMAing in audio data to be transported over
  87          * the MAI bus to the Falcon core.
  88          */
  89         HDMI_MAI_DATA,
  90
  91         /* Format header to be placed on the MAI data. Unused. */
  92         HDMI_MAI_FMT,
  93
  94         /* Last received format word on the MAI bus. */
  95         HDMI_MAI_FORMAT,
  96         HDMI_MAI_SMP,
  97         HDMI_MAI_THR,
  98         HDMI_M_CTL,
  99         HDMI_RAM_PACKET_CONFIG,
 100         HDMI_RAM_PACKET_START,
 101         HDMI_RAM_PACKET_STATUS,
 102         HDMI_RM_CONTROL,
 103         HDMI_RM_FORMAT,
 104         HDMI_RM_OFFSET,
 105         HDMI_SCHEDULER_CONTROL,
 106         HDMI_SCRAMBLER_CTL,
 107         HDMI_SW_RESET_CONTROL,
 108         HDMI_TX_PHY_CHANNEL_SWAP,
 109         HDMI_TX_PHY_CLK_DIV,
 110         HDMI_TX_PHY_CTL_0,
 111         HDMI_TX_PHY_CTL_1,
 112         HDMI_TX_PHY_CTL_2,
 113         HDMI_TX_PHY_CTL_3,
 114         HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1,
 115         HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2,
 116         HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4,
 117         HDMI_TX_PHY_PLL_CFG,
 118         HDMI_TX_PHY_PLL_CTL_0,
 119         HDMI_TX_PHY_PLL_CTL_1,
 120         HDMI_TX_PHY_POWERDOWN_CTL,
 121         HDMI_TX_PHY_RESET_CTL,
 122         HDMI_TX_PHY_TMDS_CLK_WORD_SEL,
 123         HDMI_VEC_INTERFACE_CFG,
 124         HDMI_VEC_INTERFACE_XBAR,
 125         HDMI_VERTA0,
 126         HDMI_VERTA1,
 127         HDMI_VERTB0,
 128         HDMI_VERTB1,
 129         HDMI_VID_CTL,
 130         HDMI_MISC_CONTROL,
 131 };
 132
 133 struct vc4_hdmi_register {
 134         char *name;
 135         enum vc4_hdmi_regs reg;
 136         unsigned int offset;
 137 };
 138
 139 #define _VC4_REG(_base, _reg, _offset)  \
 140         [_reg] = {                              \
 141                 .name = #_reg,                  \
 142                 .reg = _base,                   \
 143                 .offset = _offset,              \
 144         }
 145
 146 #define VC4_HD_REG(reg, offset)         _VC4_REG(VC4_HD, reg, offset)
 147 #define VC4_HDMI_REG(reg, offset)       _VC4_REG(VC4_HDMI, reg, offset)
 148 #define VC5_CEC_REG(reg, offset)        _VC4_REG(VC5_CEC, reg, offset)
 149 #define VC5_CSC_REG(reg, offset)        _VC4_REG(VC5_CSC, reg, offset)
 150 #define VC5_DVP_REG(reg, offset)        _VC4_REG(VC5_DVP, reg, offset)
 151 #define VC5_PHY_REG(reg, offset)        _VC4_REG(VC5_PHY, reg, offset)
 152 #define VC5_RAM_REG(reg, offset)        _VC4_REG(VC5_RAM, reg, offset)
 153 #define VC5_RM_REG(reg, offset)         _VC4_REG(VC5_RM, reg, offset)
 154
 155 static const struct vc4_hdmi_register __maybe_unused vc4_hdmi_fields[] = {
 156         VC4_HD_REG(HDMI_M_CTL, 0x000c),
 157         VC4_HD_REG(HDMI_MAI_CTL, 0x0014),
 158         VC4_HD_REG(HDMI_MAI_THR, 0x0018),
 159         VC4_HD_REG(HDMI_MAI_FMT, 0x001c),
 160         VC4_HD_REG(HDMI_MAI_DATA, 0x0020),
 161         VC4_HD_REG(HDMI_MAI_SMP, 0x002c),
 162         VC4_HD_REG(HDMI_VID_CTL, 0x0038),
 163         VC4_HD_REG(HDMI_CSC_CTL, 0x0040),
 164         VC4_HD_REG(HDMI_CSC_12_11, 0x0044),
 165         VC4_HD_REG(HDMI_CSC_14_13, 0x0048),
 166         VC4_HD_REG(HDMI_CSC_22_21, 0x004c),
 167         VC4_HD_REG(HDMI_CSC_24_23, 0x0050),
 168         VC4_HD_REG(HDMI_CSC_32_31, 0x0054),
 169         VC4_HD_REG(HDMI_CSC_34_33, 0x0058),
 170         VC4_HD_REG(HDMI_FRAME_COUNT, 0x0068),
 171
 172         VC4_HDMI_REG(HDMI_CORE_REV, 0x0000),
 173         VC4_HDMI_REG(HDMI_SW_RESET_CONTROL, 0x0004),
 174         VC4_HDMI_REG(HDMI_HOTPLUG_INT, 0x0008),
 175         VC4_HDMI_REG(HDMI_HOTPLUG, 0x000c),
 176         VC4_HDMI_REG(HDMI_FIFO_CTL, 0x005c),
 177         VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0090),
 178         VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0094),
 179         VC4_HDMI_REG(HDMI_MAI_FORMAT, 0x0098),
 180         VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x009c),
 181         VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x00a0),
 182         VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x00a4),
 183         VC4_HDMI_REG(HDMI_CRP_CFG, 0x00a8),
 184         VC4_HDMI_REG(HDMI_CTS_0, 0x00ac),
 185         VC4_HDMI_REG(HDMI_CTS_1, 0x00b0),
 186         VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x00c0),
 187         VC4_HDMI_REG(HDMI_HORZA, 0x00c4),
 188         VC4_HDMI_REG(HDMI_HORZB, 0x00c8),
 189         VC4_HDMI_REG(HDMI_VERTA0, 0x00cc),
 190         VC4_HDMI_REG(HDMI_VERTB0, 0x00d0),
 191         VC4_HDMI_REG(HDMI_VERTA1, 0x00d4),
 192         VC4_HDMI_REG(HDMI_VERTB1, 0x00d8),
 193         VC4_HDMI_REG(HDMI_CEC_CNTRL_1, 0x00e8),
 194         VC4_HDMI_REG(HDMI_CEC_CNTRL_2, 0x00ec),
 195         VC4_HDMI_REG(HDMI_CEC_CNTRL_3, 0x00f0),
 196         VC4_HDMI_REG(HDMI_CEC_CNTRL_4, 0x00f4),
 197         VC4_HDMI_REG(HDMI_CEC_CNTRL_5, 0x00f8),
 198         VC4_HDMI_REG(HDMI_CEC_TX_DATA_1, 0x00fc),
 199         VC4_HDMI_REG(HDMI_CEC_TX_DATA_2, 0x0100),
 200         VC4_HDMI_REG(HDMI_CEC_TX_DATA_3, 0x0104),
 201         VC4_HDMI_REG(HDMI_CEC_TX_DATA_4, 0x0108),
 202         VC4_HDMI_REG(HDMI_CEC_RX_DATA_1, 0x010c),
 203         VC4_HDMI_REG(HDMI_CEC_RX_DATA_2, 0x0110),
 204         VC4_HDMI_REG(HDMI_CEC_RX_DATA_3, 0x0114),
 205         VC4_HDMI_REG(HDMI_CEC_RX_DATA_4, 0x0118),
 206         VC4_HDMI_REG(HDMI_TX_PHY_RESET_CTL, 0x02c0),
 207         VC4_HDMI_REG(HDMI_TX_PHY_CTL_0, 0x02c4),
 208         VC4_HDMI_REG(HDMI_CEC_CPU_STATUS, 0x0340),
 209         VC4_HDMI_REG(HDMI_CEC_CPU_SET, 0x0344),
 210         VC4_HDMI_REG(HDMI_CEC_CPU_CLEAR, 0x0348),
 211         VC4_HDMI_REG(HDMI_CEC_CPU_MASK_STATUS, 0x034c),
 212         VC4_HDMI_REG(HDMI_CEC_CPU_MASK_SET, 0x0350),
 213         VC4_HDMI_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0354),
 214         VC4_HDMI_REG(HDMI_RAM_PACKET_START, 0x0400),
 215 };
 216
 217 static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi0_fields[] = {
 218         VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
 219         VC4_HD_REG(HDMI_MAI_CTL, 0x0010),
 220         VC4_HD_REG(HDMI_MAI_THR, 0x0014),
 221         VC4_HD_REG(HDMI_MAI_FMT, 0x0018),
 222         VC4_HD_REG(HDMI_MAI_DATA, 0x001c),
 223         VC4_HD_REG(HDMI_MAI_SMP, 0x0020),
 224         VC4_HD_REG(HDMI_VID_CTL, 0x0044),
 225         VC4_HD_REG(HDMI_FRAME_COUNT, 0x0060),
 226
 227         VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074),
 228         VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8),
 229         VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc),
 230         VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4),
 231         VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8),
 232         VC4_HDMI_REG(HDMI_CTS_0, 0x0cc),
 233         VC4_HDMI_REG(HDMI_CTS_1, 0x0d0),
 234         VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0),
 235         VC4_HDMI_REG(HDMI_HORZA, 0x0e4),
 236         VC4_HDMI_REG(HDMI_HORZB, 0x0e8),
 237         VC4_HDMI_REG(HDMI_VERTA0, 0x0ec),
 238         VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
 239         VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
 240         VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
 241         VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x100),
 242         VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
 243         VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
 244         VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),
 245         VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),
 246         VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),
 247         VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
 248         VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),
 249
 250         VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
 251         VC5_DVP_REG(HDMI_VEC_INTERFACE_CFG, 0x0ec),
 252         VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
 253
 254         VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
 255         VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
 256         VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
 257         VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
 258         VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
 259         VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
 260         VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
 261         VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
 262         VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
 263         VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
 264         VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
 265         VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
 266         VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
 267         VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
 268         VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
 269
 270         VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
 271         VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
 272         VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
 273
 274         VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
 275
 276         VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
 277         VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
 278         VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
 279         VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
 280         VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
 281         VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
 282         VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
 283         VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
 284         VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
 285         VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
 286         VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
 287         VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
 288         VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
 289
 290         VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
 291         VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
 292         VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
 293         VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
 294         VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
 295         VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
 296         VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
 297         VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),
 298 };
 299
 300 static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi1_fields[] = {
 301         VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
 302         VC4_HD_REG(HDMI_MAI_CTL, 0x0030),
 303         VC4_HD_REG(HDMI_MAI_THR, 0x0034),
 304         VC4_HD_REG(HDMI_MAI_FMT, 0x0038),
 305         VC4_HD_REG(HDMI_MAI_DATA, 0x003c),
 306         VC4_HD_REG(HDMI_MAI_SMP, 0x0040),
 307         VC4_HD_REG(HDMI_VID_CTL, 0x0048),
 308         VC4_HD_REG(HDMI_FRAME_COUNT, 0x0064),
 309
 310         VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074),
 311         VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8),
 312         VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc),
 313         VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4),
 314         VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8),
 315         VC4_HDMI_REG(HDMI_CTS_0, 0x0cc),
 316         VC4_HDMI_REG(HDMI_CTS_1, 0x0d0),
 317         VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0),
 318         VC4_HDMI_REG(HDMI_HORZA, 0x0e4),
 319         VC4_HDMI_REG(HDMI_HORZB, 0x0e8),
 320         VC4_HDMI_REG(HDMI_VERTA0, 0x0ec),
 321         VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
 322         VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
 323         VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
 324         VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x100),
 325         VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
 326         VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
 327         VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),
 328         VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),
 329         VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),
 330         VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
 331         VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),
 332
 333         VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
 334         VC5_DVP_REG(HDMI_VEC_INTERFACE_CFG, 0x0ec),
 335         VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
 336
 337         VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
 338         VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
 339         VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
 340         VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
 341         VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
 342         VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
 343         VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
 344         VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
 345         VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
 346         VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
 347         VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
 348         VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
 349         VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
 350         VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
 351         VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
 352
 353         VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
 354         VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
 355         VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
 356
 357         VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
 358
 359         VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
 360         VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
 361         VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
 362         VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
 363         VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
 364         VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
 365         VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
 366         VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
 367         VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
 368         VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
 369         VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
 370         VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
 371         VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
 372
 373         VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
 374         VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
 375         VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
 376         VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
 377         VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
 378         VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
 379         VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
 380         VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),
 381 };
 382
 383 static inline
 384 void __iomem *__vc4_hdmi_get_field_base(struct vc4_hdmi *hdmi,
 385                                         enum vc4_hdmi_regs reg)
 386 {
 387         switch (reg) {
 388         case VC4_HD:
 389                 return hdmi->hd_regs;
 390
 391         case VC4_HDMI:
 392                 return hdmi->hdmicore_regs;
 393
 394         case VC5_CSC:
 395                 return hdmi->csc_regs;
 396
 397         case VC5_CEC:
 398                 return hdmi->cec_regs;
 399
 400         case VC5_DVP:
 401                 return hdmi->dvp_regs;
 402
 403         case VC5_PHY:
 404                 return hdmi->phy_regs;
 405
 406         case VC5_RAM:
 407                 return hdmi->ram_regs;
 408
 409         case VC5_RM:
 410                 return hdmi->rm_regs;
 411
 412         default:
 413                 return NULL;
 414         }
 415
 416         return NULL;
 417 }
 418
 419 static inline u32 vc4_hdmi_read(struct vc4_hdmi *hdmi,
 420                                 enum vc4_hdmi_field reg)
 421 {
 422         const struct vc4_hdmi_register *field;
 423         const struct vc4_hdmi_variant *variant = hdmi->variant;
 424         void __iomem *base;
 425
 426         WARN_ON(pm_runtime_status_suspended(&hdmi->pdev->dev));
 427
 428         if (reg >= variant->num_registers) {
 429                 dev_warn(&hdmi->pdev->dev,
 430                          "Invalid register ID %u\n", reg);
 431                 return 0;
 432         }
 433
 434         field = &variant->registers[reg];
 435         base = __vc4_hdmi_get_field_base(hdmi, field->reg);
 436         if (!base) {
 437                 dev_warn(&hdmi->pdev->dev,
 438                          "Unknown register ID %u\n", reg);
 439                 return 0;
 440         }
 441
 442         return readl(base + field->offset);
 443 }
 444 #define HDMI_READ(reg)          vc4_hdmi_read(vc4_hdmi, reg)
 445
 446 static inline void vc4_hdmi_write(struct vc4_hdmi *hdmi,
 447                                   enum vc4_hdmi_field reg,
 448                                   u32 value)
 449 {
 450         const struct vc4_hdmi_register *field;
 451         const struct vc4_hdmi_variant *variant = hdmi->variant;
 452         void __iomem *base;
 453
 454         lockdep_assert_held(&hdmi->hw_lock);
 455
 456         WARN_ON(pm_runtime_status_suspended(&hdmi->pdev->dev));
 457
 458         if (reg >= variant->num_registers) {
 459                 dev_warn(&hdmi->pdev->dev,
 460                          "Invalid register ID %u\n", reg);
 461                 return;
 462         }
 463
 464         field = &variant->registers[reg];
 465         base = __vc4_hdmi_get_field_base(hdmi, field->reg);
 466         if (!base)
 467                 return;
 468
 469         writel(value, base + field->offset);
 470 }
 471 #define HDMI_WRITE(reg, val)    vc4_hdmi_write(vc4_hdmi, reg, val)
 472
 473 #endif /* _VC4_HDMI_REGS_H_ */