drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <drm/drm_simple_kms_helper.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include <linux/clk.h>
  40 #include <linux/component.h>
  41 #include <linux/i2c.h>
  42 #include <linux/of_address.h>
  43 #include <linux/of_gpio.h>
  44 #include <linux/of_platform.h>
  45 #include <linux/pm_runtime.h>
  46 #include <linux/rational.h>
  47 #include <linux/reset.h>
  48 #include <sound/dmaengine_pcm.h>
  49 #include <sound/hdmi-codec.h>
  50 #include <sound/pcm_drm_eld.h>
  51 #include <sound/pcm_params.h>
  52 #include <sound/soc.h>
  53 #include "media/cec.h"
  54 #include "vc4_drv.h"
  55 #include "vc4_hdmi.h"
  56 #include "vc4_hdmi_regs.h"
  57 #include "vc4_regs.h"
  58
  59 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  60 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  61 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  62 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  63 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  64 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  65
  66 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  67 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  68 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  69 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  70
  71 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  72 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  73 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  74 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  75 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  76 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  77
  78 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  79 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  80
  81 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  82 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  83
  84 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  85
  86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  88
  89 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  90 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  91
  92 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  93
  94 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
  95 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
  96
  97 # define VC4_HD_M_SW_RST                        BIT(2)
  98 # define VC4_HD_M_ENABLE                        BIT(0)
  99
 100 #define HSM_MIN_CLOCK_FREQ      120000000
 101 #define CEC_CLOCK_FREQ 40000
 102
 103 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 104
 105 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode)
 106 {
 107         return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK;
 108 }
 109
 110 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi,
 111                                        const struct drm_display_mode *mode)
 112 {
 113         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 114
 115         return !vc4_encoder->hdmi_monitor ||
 116                 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
 117 }
 118
 119 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 120 {
 121         struct drm_info_node *node = (struct drm_info_node *)m->private;
 122         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
 123         struct drm_printer p = drm_seq_file_printer(m);
 124
 125         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 126         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 127         drm_print_regset32(&p, &vc4_hdmi->cec_regset);
 128         drm_print_regset32(&p, &vc4_hdmi->csc_regset);
 129         drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
 130         drm_print_regset32(&p, &vc4_hdmi->phy_regset);
 131         drm_print_regset32(&p, &vc4_hdmi->ram_regset);
 132         drm_print_regset32(&p, &vc4_hdmi->rm_regset);
 133
 134         return 0;
 135 }
 136
 137 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 138 {
 139         unsigned long flags;
 140
 141         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 142
 143         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 144         udelay(1);
 145         HDMI_WRITE(HDMI_M_CTL, 0);
 146
 147         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 148
 149         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 150                    VC4_HDMI_SW_RESET_HDMI |
 151                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 152
 153         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 154
 155         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 156 }
 157
 158 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 159 {
 160         unsigned long flags;
 161
 162         reset_control_reset(vc4_hdmi->reset);
 163
 164         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 165
 166         HDMI_WRITE(HDMI_DVP_CTL, 0);
 167
 168         HDMI_WRITE(HDMI_CLOCK_STOP,
 169                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 170
 171         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 172 }
 173
 174 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 175 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 176 {
 177         unsigned long cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
 178         unsigned long flags;
 179         u16 clk_cnt;
 180         u32 value;
 181
 182         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 183
 184         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 185         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 186
 187         /*
 188          * Set the clock divider: the hsm_clock rate and this divider
 189          * setting will give a 40 kHz CEC clock.
 190          */
 191         clk_cnt = cec_rate / CEC_CLOCK_FREQ;
 192         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 193         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 194
 195         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 196 }
 197 #else
 198 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 199 #endif
 200
 201 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder);
 202
 203 static enum drm_connector_status
 204 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 205 {
 206         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 207         bool connected = false;
 208
 209         mutex_lock(&vc4_hdmi->mutex);
 210
 211         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 212
 213         if (vc4_hdmi->hpd_gpio) {
 214                 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
 215                         connected = true;
 216         } else {
 217                 if (vc4_hdmi->variant->hp_detect &&
 218                     vc4_hdmi->variant->hp_detect(vc4_hdmi))
 219                         connected = true;
 220         }
 221
 222         vc4_hdmi->encoder.hdmi_monitor = false;
 223         if (connected) {
 224                 if (connector->status != connector_status_connected) {
 225                         struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
 226
 227                         if (edid) {
 228                                 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 229                                 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
 230                                 kfree(edid);
 231                         }
 232                 }
 233
 234                 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base);
 235                 pm_runtime_put(&vc4_hdmi->pdev->dev);
 236                 mutex_unlock(&vc4_hdmi->mutex);
 237                 return connector_status_connected;
 238         }
 239
 240         cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 241         pm_runtime_put(&vc4_hdmi->pdev->dev);
 242         mutex_unlock(&vc4_hdmi->mutex);
 243         return connector_status_disconnected;
 244 }
 245
 246 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 247 {
 248         drm_connector_unregister(connector);
 249         drm_connector_cleanup(connector);
 250 }
 251
 252 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 253 {
 254         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 255         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 256         int ret = 0;
 257         struct edid *edid;
 258
 259         mutex_lock(&vc4_hdmi->mutex);
 260
 261         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 262         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 263         if (!edid) {
 264                 ret = -ENODEV;
 265                 goto out;
 266         }
 267
 268         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 269
 270         drm_connector_update_edid_property(connector, edid);
 271         ret = drm_add_edid_modes(connector, edid);
 272         kfree(edid);
 273
 274         if (vc4_hdmi->disable_4kp60) {
 275                 struct drm_device *drm = connector->dev;
 276                 struct drm_display_mode *mode;
 277
 278                 list_for_each_entry(mode, &connector->probed_modes, head) {
 279                         if (vc4_hdmi_mode_needs_scrambling(mode)) {
 280                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 281                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 282                         }
 283                 }
 284         }
 285
 286 out:
 287         mutex_unlock(&vc4_hdmi->mutex);
 288
 289         return ret;
 290 }
 291
 292 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 293                                            struct drm_atomic_state *state)
 294 {
 295         struct drm_connector_state *old_state =
 296                 drm_atomic_get_old_connector_state(state, connector);
 297         struct drm_connector_state *new_state =
 298                 drm_atomic_get_new_connector_state(state, connector);
 299         struct drm_crtc *crtc = new_state->crtc;
 300
 301         if (!crtc)
 302                 return 0;
 303
 304         if (old_state->colorspace != new_state->colorspace ||
 305             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 306                 struct drm_crtc_state *crtc_state;
 307
 308                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 309                 if (IS_ERR(crtc_state))
 310                         return PTR_ERR(crtc_state);
 311
 312                 crtc_state->mode_changed = true;
 313         }
 314
 315         return 0;
 316 }
 317
 318 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 319 {
 320         struct vc4_hdmi_connector_state *old_state =
 321                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 322         struct vc4_hdmi_connector_state *new_state =
 323                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 324
 325         if (connector->state)
 326                 __drm_atomic_helper_connector_destroy_state(connector->state);
 327
 328         kfree(old_state);
 329         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 330
 331         if (!new_state)
 332                 return;
 333
 334         new_state->base.max_bpc = 8;
 335         new_state->base.max_requested_bpc = 8;
 336         drm_atomic_helper_connector_tv_reset(connector);
 337 }
 338
 339 static struct drm_connector_state *
 340 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 341 {
 342         struct drm_connector_state *conn_state = connector->state;
 343         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 344         struct vc4_hdmi_connector_state *new_state;
 345
 346         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 347         if (!new_state)
 348                 return NULL;
 349
 350         new_state->pixel_rate = vc4_state->pixel_rate;
 351         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 352
 353         return &new_state->base;
 354 }
 355
 356 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 357         .detect = vc4_hdmi_connector_detect,
 358         .fill_modes = drm_helper_probe_single_connector_modes,
 359         .destroy = vc4_hdmi_connector_destroy,
 360         .reset = vc4_hdmi_connector_reset,
 361         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 362         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 363 };
 364
 365 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 366         .get_modes = vc4_hdmi_connector_get_modes,
 367         .atomic_check = vc4_hdmi_connector_atomic_check,
 368 };
 369
 370 static int vc4_hdmi_connector_init(struct drm_device *dev,
 371                                    struct vc4_hdmi *vc4_hdmi)
 372 {
 373         struct drm_connector *connector = &vc4_hdmi->connector;
 374         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 375         int ret;
 376
 377         drm_connector_init_with_ddc(dev, connector,
 378                                     &vc4_hdmi_connector_funcs,
 379                                     DRM_MODE_CONNECTOR_HDMIA,
 380                                     vc4_hdmi->ddc);
 381         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 382
 383         /*
 384          * Some of the properties below require access to state, like bpc.
 385          * Allocate some default initial connector state with our reset helper.
 386          */
 387         if (connector->funcs->reset)
 388                 connector->funcs->reset(connector);
 389
 390         /* Create and attach TV margin props to this connector. */
 391         ret = drm_mode_create_tv_margin_properties(dev);
 392         if (ret)
 393                 return ret;
 394
 395         ret = drm_mode_create_hdmi_colorspace_property(connector);
 396         if (ret)
 397                 return ret;
 398
 399         drm_connector_attach_colorspace_property(connector);
 400         drm_connector_attach_tv_margin_properties(connector);
 401         drm_connector_attach_max_bpc_property(connector, 8, 12);
 402
 403         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 404                              DRM_CONNECTOR_POLL_DISCONNECT);
 405
 406         connector->interlace_allowed = 1;
 407         connector->doublescan_allowed = 0;
 408         connector->stereo_allowed = 1;
 409
 410         if (vc4_hdmi->variant->supports_hdr)
 411                 drm_connector_attach_hdr_output_metadata_property(connector);
 412
 413         drm_connector_attach_encoder(connector, encoder);
 414
 415         return 0;
 416 }
 417
 418 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 419                                 enum hdmi_infoframe_type type,
 420                                 bool poll)
 421 {
 422         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 423         u32 packet_id = type - 0x80;
 424         unsigned long flags;
 425
 426         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 427         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 428                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 429         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 430
 431         if (!poll)
 432                 return 0;
 433
 434         return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 435                           BIT(packet_id)), 100);
 436 }
 437
 438 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 439                                      union hdmi_infoframe *frame)
 440 {
 441         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 442         u32 packet_id = frame->any.type - 0x80;
 443         const struct vc4_hdmi_register *ram_packet_start =
 444                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 445         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 446         u32 packet_reg_next = ram_packet_start->offset +
 447                 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
 448         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 449                                                        ram_packet_start->reg);
 450         uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
 451         unsigned long flags;
 452         ssize_t len, i;
 453         int ret;
 454
 455         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 456                     VC4_HDMI_RAM_PACKET_ENABLE),
 457                   "Packet RAM has to be on to store the packet.");
 458
 459         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 460         if (len < 0)
 461                 return;
 462
 463         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 464         if (ret) {
 465                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 466                 return;
 467         }
 468
 469         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 470
 471         for (i = 0; i < len; i += 7) {
 472                 writel(buffer[i + 0] << 0 |
 473                        buffer[i + 1] << 8 |
 474                        buffer[i + 2] << 16,
 475                        base + packet_reg);
 476                 packet_reg += 4;
 477
 478                 writel(buffer[i + 3] << 0 |
 479                        buffer[i + 4] << 8 |
 480                        buffer[i + 5] << 16 |
 481                        buffer[i + 6] << 24,
 482                        base + packet_reg);
 483                 packet_reg += 4;
 484         }
 485
 486         /*
 487          * clear remainder of packet ram as it's included in the
 488          * infoframe and triggers a checksum error on hdmi analyser
 489          */
 490         for (; packet_reg < packet_reg_next; packet_reg += 4)
 491                 writel(0, base + packet_reg);
 492
 493         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 494                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 495
 496         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 497
 498         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 499                         BIT(packet_id)), 100);
 500         if (ret)
 501                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 502 }
 503
 504 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 505 {
 506         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 507         struct drm_connector *connector = &vc4_hdmi->connector;
 508         struct drm_connector_state *cstate = connector->state;
 509         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 510         union hdmi_infoframe frame;
 511         int ret;
 512
 513         lockdep_assert_held(&vc4_hdmi->mutex);
 514
 515         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 516                                                        connector, mode);
 517         if (ret < 0) {
 518                 DRM_ERROR("couldn't fill AVI infoframe\n");
 519                 return;
 520         }
 521
 522         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 523                                            connector, mode,
 524                                            vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ?
 525                                            HDMI_QUANTIZATION_RANGE_FULL :
 526                                            HDMI_QUANTIZATION_RANGE_LIMITED);
 527         drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
 528         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 529
 530         vc4_hdmi_write_infoframe(encoder, &frame);
 531 }
 532
 533 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 534 {
 535         union hdmi_infoframe frame;
 536         int ret;
 537
 538         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 539         if (ret < 0) {
 540                 DRM_ERROR("couldn't fill SPD infoframe\n");
 541                 return;
 542         }
 543
 544         frame.spd.sdi = HDMI_SPD_SDI_PC;
 545
 546         vc4_hdmi_write_infoframe(encoder, &frame);
 547 }
 548
 549 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 550 {
 551         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 552         struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
 553         union hdmi_infoframe frame;
 554
 555         memcpy(&frame.audio, audio, sizeof(*audio));
 556         vc4_hdmi_write_infoframe(encoder, &frame);
 557 }
 558
 559 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 560 {
 561         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 562         struct drm_connector *connector = &vc4_hdmi->connector;
 563         struct drm_connector_state *conn_state = connector->state;
 564         union hdmi_infoframe frame;
 565
 566         lockdep_assert_held(&vc4_hdmi->mutex);
 567
 568         if (!vc4_hdmi->variant->supports_hdr)
 569                 return;
 570
 571         if (!conn_state->hdr_output_metadata)
 572                 return;
 573
 574         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 575                 return;
 576
 577         vc4_hdmi_write_infoframe(encoder, &frame);
 578 }
 579
 580 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 581 {
 582         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 583
 584         lockdep_assert_held(&vc4_hdmi->mutex);
 585
 586         vc4_hdmi_set_avi_infoframe(encoder);
 587         vc4_hdmi_set_spd_infoframe(encoder);
 588         /*
 589          * If audio was streaming, then we need to reenabled the audio
 590          * infoframe here during encoder_enable.
 591          */
 592         if (vc4_hdmi->audio.streaming)
 593                 vc4_hdmi_set_audio_infoframe(encoder);
 594
 595         vc4_hdmi_set_hdr_infoframe(encoder);
 596 }
 597
 598 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
 599                                          struct drm_display_mode *mode)
 600 {
 601         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 602         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 603         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 604
 605         lockdep_assert_held(&vc4_hdmi->mutex);
 606
 607         if (!vc4_encoder->hdmi_monitor)
 608                 return false;
 609
 610         if (!display->hdmi.scdc.supported ||
 611             !display->hdmi.scdc.scrambling.supported)
 612                 return false;
 613
 614         return true;
 615 }
 616
 617 #define SCRAMBLING_POLLING_DELAY_MS     1000
 618
 619 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 620 {
 621         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 622         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 623         unsigned long flags;
 624
 625         lockdep_assert_held(&vc4_hdmi->mutex);
 626
 627         if (!vc4_hdmi_supports_scrambling(encoder, mode))
 628                 return;
 629
 630         if (!vc4_hdmi_mode_needs_scrambling(mode))
 631                 return;
 632
 633         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 634         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 635
 636         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 637         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
 638                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 639         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 640
 641         vc4_hdmi->scdc_enabled = true;
 642
 643         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 644                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 645 }
 646
 647 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
 648 {
 649         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 650         unsigned long flags;
 651
 652         lockdep_assert_held(&vc4_hdmi->mutex);
 653
 654         if (!vc4_hdmi->scdc_enabled)
 655                 return;
 656
 657         vc4_hdmi->scdc_enabled = false;
 658
 659         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
 660                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
 661
 662         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 663         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
 664                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 665         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 666
 667         drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
 668         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
 669 }
 670
 671 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
 672 {
 673         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
 674                                                  struct vc4_hdmi,
 675                                                  scrambling_work);
 676
 677         if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
 678                 return;
 679
 680         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 681         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 682
 683         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 684                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 685 }
 686
 687 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 688                                                struct drm_atomic_state *state)
 689 {
 690         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 691         unsigned long flags;
 692
 693         mutex_lock(&vc4_hdmi->mutex);
 694
 695         vc4_hdmi->output_enabled = false;
 696         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 697
 698         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 699
 700         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
 701
 702         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 703
 704         mdelay(1);
 705
 706         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 707         HDMI_WRITE(HDMI_VID_CTL,
 708                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 709         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 710
 711         vc4_hdmi_disable_scrambling(encoder);
 712
 713         mutex_unlock(&vc4_hdmi->mutex);
 714 }
 715
 716 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
 717                                                  struct drm_atomic_state *state)
 718 {
 719         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 720         unsigned long flags;
 721         int ret;
 722
 723         mutex_lock(&vc4_hdmi->mutex);
 724
 725         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 726         HDMI_WRITE(HDMI_VID_CTL,
 727                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 728         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 729
 730         if (vc4_hdmi->variant->phy_disable)
 731                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 732
 733         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 734         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 735
 736         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 737         if (ret < 0)
 738                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 739
 740         mutex_unlock(&vc4_hdmi->mutex);
 741 }
 742
 743 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
 744                                const struct drm_display_mode *mode)
 745 {
 746         unsigned long flags;
 747         u32 csc_ctl;
 748
 749         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 750
 751         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 752                                 VC4_HD_CSC_CTL_ORDER);
 753
 754         if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) {
 755                 /* CEA VICs other than #1 requre limited range RGB
 756                  * output unless overridden by an AVI infoframe.
 757                  * Apply a colorspace conversion to squash 0-255 down
 758                  * to 16-235.  The matrix here is:
 759                  *
 760                  * [ 0      0      0.8594 16]
 761                  * [ 0      0.8594 0      16]
 762                  * [ 0.8594 0      0      16]
 763                  * [ 0      0      0       1]
 764                  */
 765                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 766                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 767                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 768                                          VC4_HD_CSC_CTL_MODE);
 769
 770                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 771                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 772                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 773                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 774                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 775                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 776         }
 777
 778         /* The RGB order applies even when CSC is disabled. */
 779         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 780
 781         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 782 }
 783
 784
 785 /*
 786  * If we need to output Full Range RGB, then use the unity matrix
 787  *
 788  * [ 1      0      0      0]
 789  * [ 0      1      0      0]
 790  * [ 0      0      1      0]
 791  *
 792  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 793  */
 794 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = {
 795         { 0x2000, 0x0000, 0x0000, 0x0000 },
 796         { 0x0000, 0x2000, 0x0000, 0x0000 },
 797         { 0x0000, 0x0000, 0x2000, 0x0000 },
 798 };
 799
 800 /*
 801  * CEA VICs other than #1 require limited range RGB output unless
 802  * overridden by an AVI infoframe. Apply a colorspace conversion to
 803  * squash 0-255 down to 16-235. The matrix here is:
 804  *
 805  * [ 0.8594 0      0      16]
 806  * [ 0      0.8594 0      16]
 807  * [ 0      0      0.8594 16]
 808  *
 809  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 810  */
 811 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = {
 812         { 0x1b80, 0x0000, 0x0000, 0x0400 },
 813         { 0x0000, 0x1b80, 0x0000, 0x0400 },
 814         { 0x0000, 0x0000, 0x1b80, 0x0400 },
 815 };
 816
 817 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
 818                                     const u16 coeffs[3][4])
 819 {
 820         lockdep_assert_held(&vc4_hdmi->hw_lock);
 821
 822         HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
 823         HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
 824         HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
 825         HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
 826         HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
 827         HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
 828 }
 829
 830 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
 831                                const struct drm_display_mode *mode)
 832 {
 833         unsigned long flags;
 834         u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 835                                                                VC5_MT_CP_CSC_CTL_MODE);
 836
 837         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 838
 839         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
 840
 841         if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode))
 842                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb);
 843         else
 844                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity);
 845
 846         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 847
 848         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 849 }
 850
 851 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 852                                  struct drm_connector_state *state,
 853                                  struct drm_display_mode *mode)
 854 {
 855         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 856         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 857         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 858         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 859         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 860                                    VC4_HDMI_VERTA_VSP) |
 861                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 862                                    VC4_HDMI_VERTA_VFP) |
 863                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 864         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 865                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
 866                                    interlaced,
 867                                    VC4_HDMI_VERTB_VBP));
 868         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 869                           VC4_SET_FIELD(mode->crtc_vtotal -
 870                                         mode->crtc_vsync_end,
 871                                         VC4_HDMI_VERTB_VBP));
 872         unsigned long flags;
 873
 874         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 875
 876         HDMI_WRITE(HDMI_HORZA,
 877                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 878                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 879                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 880                                  VC4_HDMI_HORZA_HAP));
 881
 882         HDMI_WRITE(HDMI_HORZB,
 883                    VC4_SET_FIELD((mode->htotal -
 884                                   mode->hsync_end) * pixel_rep,
 885                                  VC4_HDMI_HORZB_HBP) |
 886                    VC4_SET_FIELD((mode->hsync_end -
 887                                   mode->hsync_start) * pixel_rep,
 888                                  VC4_HDMI_HORZB_HSP) |
 889                    VC4_SET_FIELD((mode->hsync_start -
 890                                   mode->hdisplay) * pixel_rep,
 891                                  VC4_HDMI_HORZB_HFP));
 892
 893         HDMI_WRITE(HDMI_VERTA0, verta);
 894         HDMI_WRITE(HDMI_VERTA1, verta);
 895
 896         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 897         HDMI_WRITE(HDMI_VERTB1, vertb);
 898
 899         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 900 }
 901
 902 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 903                                  struct drm_connector_state *state,
 904                                  struct drm_display_mode *mode)
 905 {
 906         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 907         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 908         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 909         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 910         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 911                                    VC5_HDMI_VERTA_VSP) |
 912                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 913                                    VC5_HDMI_VERTA_VFP) |
 914                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
 915         u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 916                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
 917                                    interlaced,
 918                                    VC4_HDMI_VERTB_VBP));
 919         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 920                           VC4_SET_FIELD(mode->crtc_vtotal -
 921                                         mode->crtc_vsync_end,
 922                                         VC4_HDMI_VERTB_VBP));
 923         unsigned long flags;
 924         unsigned char gcp;
 925         bool gcp_en;
 926         u32 reg;
 927
 928         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 929
 930         HDMI_WRITE(HDMI_HORZA,
 931                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
 932                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
 933                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 934                                  VC5_HDMI_HORZA_HAP) |
 935                    VC4_SET_FIELD((mode->hsync_start -
 936                                   mode->hdisplay) * pixel_rep,
 937                                  VC5_HDMI_HORZA_HFP));
 938
 939         HDMI_WRITE(HDMI_HORZB,
 940                    VC4_SET_FIELD((mode->htotal -
 941                                   mode->hsync_end) * pixel_rep,
 942                                  VC5_HDMI_HORZB_HBP) |
 943                    VC4_SET_FIELD((mode->hsync_end -
 944                                   mode->hsync_start) * pixel_rep,
 945                                  VC5_HDMI_HORZB_HSP));
 946
 947         HDMI_WRITE(HDMI_VERTA0, verta);
 948         HDMI_WRITE(HDMI_VERTA1, verta);
 949
 950         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 951         HDMI_WRITE(HDMI_VERTB1, vertb);
 952
 953         switch (state->max_bpc) {
 954         case 12:
 955                 gcp = 6;
 956                 gcp_en = true;
 957                 break;
 958         case 10:
 959                 gcp = 5;
 960                 gcp_en = true;
 961                 break;
 962         case 8:
 963         default:
 964                 gcp = 4;
 965                 gcp_en = false;
 966                 break;
 967         }
 968
 969         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
 970         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
 971                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
 972         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
 973                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
 974         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
 975
 976         reg = HDMI_READ(HDMI_GCP_WORD_1);
 977         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
 978         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
 979         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
 980
 981         reg = HDMI_READ(HDMI_GCP_CONFIG);
 982         reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
 983         reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
 984         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
 985
 986         reg = HDMI_READ(HDMI_MISC_CONTROL);
 987         reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
 988         reg |= VC4_SET_FIELD(0, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
 989         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
 990
 991         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
 992
 993         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 994 }
 995
 996 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
 997 {
 998         unsigned long flags;
 999         u32 drift;
1000         int ret;
1001
1002         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1003
1004         drift = HDMI_READ(HDMI_FIFO_CTL);
1005         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1006
1007         HDMI_WRITE(HDMI_FIFO_CTL,
1008                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1009         HDMI_WRITE(HDMI_FIFO_CTL,
1010                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1011
1012         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1013
1014         usleep_range(1000, 1100);
1015
1016         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1017
1018         HDMI_WRITE(HDMI_FIFO_CTL,
1019                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1020         HDMI_WRITE(HDMI_FIFO_CTL,
1021                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1022
1023         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1024
1025         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1026                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1027         WARN_ONCE(ret, "Timeout waiting for "
1028                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1029 }
1030
1031 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1032                                                 struct drm_atomic_state *state)
1033 {
1034         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1035         struct drm_connector *connector = &vc4_hdmi->connector;
1036         struct drm_connector_state *conn_state =
1037                 drm_atomic_get_new_connector_state(state, connector);
1038         struct vc4_hdmi_connector_state *vc4_conn_state =
1039                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1040         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1041         unsigned long pixel_rate = vc4_conn_state->pixel_rate;
1042         unsigned long bvb_rate, hsm_rate;
1043         unsigned long flags;
1044         int ret;
1045
1046         mutex_lock(&vc4_hdmi->mutex);
1047
1048         /*
1049          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1050          * be faster than pixel clock, infinitesimally faster, tested in
1051          * simulation. Otherwise, exact value is unimportant for HDMI
1052          * operation." This conflicts with bcm2835's vc4 documentation, which
1053          * states HSM's clock has to be at least 108% of the pixel clock.
1054          *
1055          * Real life tests reveal that vc4's firmware statement holds up, and
1056          * users are able to use pixel clocks closer to HSM's, namely for
1057          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1058          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1059          * 162MHz.
1060          *
1061          * Additionally, the AXI clock needs to be at least 25% of
1062          * pixel clock, but HSM ends up being the limiting factor.
1063          */
1064         hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
1065         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1066         if (ret) {
1067                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1068                 goto out;
1069         }
1070
1071         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1072         if (ret < 0) {
1073                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1074                 goto out;
1075         }
1076
1077         ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
1078         if (ret) {
1079                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1080                 goto err_put_runtime_pm;
1081         }
1082
1083         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1084         if (ret) {
1085                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1086                 goto err_put_runtime_pm;
1087         }
1088
1089
1090         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1091
1092         if (pixel_rate > 297000000)
1093                 bvb_rate = 300000000;
1094         else if (pixel_rate > 148500000)
1095                 bvb_rate = 150000000;
1096         else
1097                 bvb_rate = 75000000;
1098
1099         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1100         if (ret) {
1101                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1102                 goto err_disable_pixel_clock;
1103         }
1104
1105         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1106         if (ret) {
1107                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1108                 goto err_disable_pixel_clock;
1109         }
1110
1111         if (vc4_hdmi->variant->phy_init)
1112                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1113
1114         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1115
1116         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1117                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1118                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1119                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1120
1121         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1122
1123         if (vc4_hdmi->variant->set_timings)
1124                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1125
1126         mutex_unlock(&vc4_hdmi->mutex);
1127
1128         return;
1129
1130 err_disable_pixel_clock:
1131         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1132 err_put_runtime_pm:
1133         pm_runtime_put(&vc4_hdmi->pdev->dev);
1134 out:
1135         mutex_unlock(&vc4_hdmi->mutex);
1136         return;
1137 }
1138
1139 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1140                                              struct drm_atomic_state *state)
1141 {
1142         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1143         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1144         unsigned long flags;
1145
1146         mutex_lock(&vc4_hdmi->mutex);
1147
1148         if (vc4_hdmi->variant->csc_setup)
1149                 vc4_hdmi->variant->csc_setup(vc4_hdmi, mode);
1150
1151         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1152         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1153         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1154
1155         mutex_unlock(&vc4_hdmi->mutex);
1156 }
1157
1158 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1159                                               struct drm_atomic_state *state)
1160 {
1161         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1162         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1163         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1164         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1165         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1166         unsigned long flags;
1167         int ret;
1168
1169         mutex_lock(&vc4_hdmi->mutex);
1170
1171         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1172
1173         HDMI_WRITE(HDMI_VID_CTL,
1174                    VC4_HD_VID_CTL_ENABLE |
1175                    VC4_HD_VID_CTL_CLRRGB |
1176                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1177                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1178                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1179                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1180
1181         HDMI_WRITE(HDMI_VID_CTL,
1182                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1183
1184         if (vc4_encoder->hdmi_monitor) {
1185                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1186                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1187                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1188
1189                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1190
1191                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1192                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1193                 WARN_ONCE(ret, "Timeout waiting for "
1194                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1195         } else {
1196                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1197                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1198                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1199                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1200                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1201                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1202
1203                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1204
1205                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1206                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1207                 WARN_ONCE(ret, "Timeout waiting for "
1208                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1209         }
1210
1211         if (vc4_encoder->hdmi_monitor) {
1212                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1213
1214                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1215                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1216                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1217                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1218                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
1219
1220                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1221                            VC4_HDMI_RAM_PACKET_ENABLE);
1222
1223                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1224                 vc4_hdmi->output_enabled = true;
1225
1226                 vc4_hdmi_set_infoframes(encoder);
1227         }
1228
1229         vc4_hdmi_recenter_fifo(vc4_hdmi);
1230         vc4_hdmi_enable_scrambling(encoder);
1231
1232         mutex_unlock(&vc4_hdmi->mutex);
1233 }
1234
1235 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1236                                              struct drm_crtc_state *crtc_state,
1237                                              struct drm_connector_state *conn_state)
1238 {
1239         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1240
1241         mutex_lock(&vc4_hdmi->mutex);
1242         memcpy(&vc4_hdmi->saved_adjusted_mode,
1243                &crtc_state->adjusted_mode,
1244                sizeof(vc4_hdmi->saved_adjusted_mode));
1245         mutex_unlock(&vc4_hdmi->mutex);
1246 }
1247
1248 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
1249 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
1250
1251 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1252                                          struct drm_crtc_state *crtc_state,
1253                                          struct drm_connector_state *conn_state)
1254 {
1255         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1256         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1257         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1258         unsigned long long pixel_rate = mode->clock * 1000;
1259         unsigned long long tmds_rate;
1260
1261         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1262             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1263             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1264              (mode->hsync_end % 2) || (mode->htotal % 2)))
1265                 return -EINVAL;
1266
1267         /*
1268          * The 1440p@60 pixel rate is in the same range than the first
1269          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1270          * bandwidth). Slightly lower the frequency to bring it out of
1271          * the WiFi range.
1272          */
1273         tmds_rate = pixel_rate * 10;
1274         if (vc4_hdmi->disable_wifi_frequencies &&
1275             (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1276              tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1277                 mode->clock = 238560;
1278                 pixel_rate = mode->clock * 1000;
1279         }
1280
1281         if (conn_state->max_bpc == 12) {
1282                 pixel_rate = pixel_rate * 150;
1283                 do_div(pixel_rate, 100);
1284         } else if (conn_state->max_bpc == 10) {
1285                 pixel_rate = pixel_rate * 125;
1286                 do_div(pixel_rate, 100);
1287         }
1288
1289         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1290                 pixel_rate = pixel_rate * 2;
1291
1292         if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
1293                 return -EINVAL;
1294
1295         if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK))
1296                 return -EINVAL;
1297
1298         vc4_state->pixel_rate = pixel_rate;
1299
1300         return 0;
1301 }
1302
1303 static enum drm_mode_status
1304 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1305                             const struct drm_display_mode *mode)
1306 {
1307         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1308
1309         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1310             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1311             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1312              (mode->hsync_end % 2) || (mode->htotal % 2)))
1313                 return MODE_H_ILLEGAL;
1314
1315         if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
1316                 return MODE_CLOCK_HIGH;
1317
1318         if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode))
1319                 return MODE_CLOCK_HIGH;
1320
1321         return MODE_OK;
1322 }
1323
1324 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1325         .atomic_check = vc4_hdmi_encoder_atomic_check,
1326         .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1327         .mode_valid = vc4_hdmi_encoder_mode_valid,
1328 };
1329
1330 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1331 {
1332         int i;
1333         u32 channel_map = 0;
1334
1335         for (i = 0; i < 8; i++) {
1336                 if (channel_mask & BIT(i))
1337                         channel_map |= i << (3 * i);
1338         }
1339         return channel_map;
1340 }
1341
1342 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1343 {
1344         int i;
1345         u32 channel_map = 0;
1346
1347         for (i = 0; i < 8; i++) {
1348                 if (channel_mask & BIT(i))
1349                         channel_map |= i << (4 * i);
1350         }
1351         return channel_map;
1352 }
1353
1354 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
1355 {
1356         unsigned long flags;
1357         u32 hotplug;
1358
1359         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1360         hotplug = HDMI_READ(HDMI_HOTPLUG);
1361         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1362
1363         return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
1364 }
1365
1366 /* HDMI audio codec callbacks */
1367 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1368                                          unsigned int samplerate)
1369 {
1370         u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1371         unsigned long flags;
1372         unsigned long n, m;
1373
1374         rational_best_approximation(hsm_clock, samplerate,
1375                                     VC4_HD_MAI_SMP_N_MASK >>
1376                                     VC4_HD_MAI_SMP_N_SHIFT,
1377                                     (VC4_HD_MAI_SMP_M_MASK >>
1378                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
1379                                     &n, &m);
1380
1381         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1382         HDMI_WRITE(HDMI_MAI_SMP,
1383                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1384                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1385         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1386 }
1387
1388 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1389 {
1390         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1391         u32 n, cts;
1392         u64 tmp;
1393
1394         lockdep_assert_held(&vc4_hdmi->mutex);
1395         lockdep_assert_held(&vc4_hdmi->hw_lock);
1396
1397         n = 128 * samplerate / 1000;
1398         tmp = (u64)(mode->clock * 1000) * n;
1399         do_div(tmp, 128 * samplerate);
1400         cts = tmp;
1401
1402         HDMI_WRITE(HDMI_CRP_CFG,
1403                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1404                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1405
1406         /*
1407          * We could get slightly more accurate clocks in some cases by
1408          * providing a CTS_1 value.  The two CTS values are alternated
1409          * between based on the period fields
1410          */
1411         HDMI_WRITE(HDMI_CTS_0, cts);
1412         HDMI_WRITE(HDMI_CTS_1, cts);
1413 }
1414
1415 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1416 {
1417         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1418
1419         return snd_soc_card_get_drvdata(card);
1420 }
1421
1422 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
1423 {
1424         lockdep_assert_held(&vc4_hdmi->mutex);
1425
1426         /*
1427          * If the encoder is currently in DVI mode, treat the codec DAI
1428          * as missing.
1429          */
1430         if (!vc4_hdmi->encoder.hdmi_monitor)
1431                 return false;
1432
1433         return true;
1434 }
1435
1436 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1437 {
1438         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1439         unsigned long flags;
1440
1441         mutex_lock(&vc4_hdmi->mutex);
1442
1443         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1444                 mutex_unlock(&vc4_hdmi->mutex);
1445                 return -ENODEV;
1446         }
1447
1448         vc4_hdmi->audio.streaming = true;
1449
1450         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1451         HDMI_WRITE(HDMI_MAI_CTL,
1452                    VC4_HD_MAI_CTL_RESET |
1453                    VC4_HD_MAI_CTL_FLUSH |
1454                    VC4_HD_MAI_CTL_DLATE |
1455                    VC4_HD_MAI_CTL_ERRORE |
1456                    VC4_HD_MAI_CTL_ERRORF);
1457         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1458
1459         if (vc4_hdmi->variant->phy_rng_enable)
1460                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1461
1462         mutex_unlock(&vc4_hdmi->mutex);
1463
1464         return 0;
1465 }
1466
1467 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1468 {
1469         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1470         struct device *dev = &vc4_hdmi->pdev->dev;
1471         unsigned long flags;
1472         int ret;
1473
1474         lockdep_assert_held(&vc4_hdmi->mutex);
1475
1476         vc4_hdmi->audio.streaming = false;
1477         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1478         if (ret)
1479                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1480
1481         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1482
1483         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1484         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1485         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1486
1487         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1488 }
1489
1490 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1491 {
1492         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1493         unsigned long flags;
1494
1495         mutex_lock(&vc4_hdmi->mutex);
1496
1497         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1498
1499         HDMI_WRITE(HDMI_MAI_CTL,
1500                    VC4_HD_MAI_CTL_DLATE |
1501                    VC4_HD_MAI_CTL_ERRORE |
1502                    VC4_HD_MAI_CTL_ERRORF);
1503
1504         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1505
1506         if (vc4_hdmi->variant->phy_rng_disable)
1507                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1508
1509         vc4_hdmi->audio.streaming = false;
1510         vc4_hdmi_audio_reset(vc4_hdmi);
1511
1512         mutex_unlock(&vc4_hdmi->mutex);
1513 }
1514
1515 static int sample_rate_to_mai_fmt(int samplerate)
1516 {
1517         switch (samplerate) {
1518         case 8000:
1519                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1520         case 11025:
1521                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1522         case 12000:
1523                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1524         case 16000:
1525                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1526         case 22050:
1527                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1528         case 24000:
1529                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1530         case 32000:
1531                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1532         case 44100:
1533                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1534         case 48000:
1535                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1536         case 64000:
1537                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
1538         case 88200:
1539                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
1540         case 96000:
1541                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
1542         case 128000:
1543                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
1544         case 176400:
1545                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
1546         case 192000:
1547                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
1548         default:
1549                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
1550         }
1551 }
1552
1553 /* HDMI audio codec callbacks */
1554 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
1555                                   struct hdmi_codec_daifmt *daifmt,
1556                                   struct hdmi_codec_params *params)
1557 {
1558         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1559         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1560         unsigned int sample_rate = params->sample_rate;
1561         unsigned int channels = params->channels;
1562         unsigned long flags;
1563         u32 audio_packet_config, channel_mask;
1564         u32 channel_map;
1565         u32 mai_audio_format;
1566         u32 mai_sample_rate;
1567
1568         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1569                 sample_rate, params->sample_width, channels);
1570
1571         mutex_lock(&vc4_hdmi->mutex);
1572
1573         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1574                 mutex_unlock(&vc4_hdmi->mutex);
1575                 return -EINVAL;
1576         }
1577
1578         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
1579
1580         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1581         HDMI_WRITE(HDMI_MAI_CTL,
1582                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
1583                    VC4_HD_MAI_CTL_WHOLSMP |
1584                    VC4_HD_MAI_CTL_CHALIGN |
1585                    VC4_HD_MAI_CTL_ENABLE);
1586
1587         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
1588         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
1589             params->channels == 8)
1590                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
1591         else
1592                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
1593         HDMI_WRITE(HDMI_MAI_FMT,
1594                    VC4_SET_FIELD(mai_sample_rate,
1595                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
1596                    VC4_SET_FIELD(mai_audio_format,
1597                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
1598
1599         /* The B frame identifier should match the value used by alsa-lib (8) */
1600         audio_packet_config =
1601                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1602                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1603                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1604
1605         channel_mask = GENMASK(channels - 1, 0);
1606         audio_packet_config |= VC4_SET_FIELD(channel_mask,
1607                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1608
1609         /* Set the MAI threshold */
1610         HDMI_WRITE(HDMI_MAI_THR,
1611                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
1612                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
1613                    VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
1614                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
1615
1616         HDMI_WRITE(HDMI_MAI_CONFIG,
1617                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1618                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
1619                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1620
1621         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1622         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1623         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1624
1625         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
1626
1627         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1628
1629         memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
1630         if (vc4_hdmi->output_enabled)
1631                 vc4_hdmi_set_audio_infoframe(encoder);
1632
1633         mutex_unlock(&vc4_hdmi->mutex);
1634
1635         return 0;
1636 }
1637
1638 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1639         .name = "vc4-hdmi-cpu-dai-component",
1640 };
1641
1642 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1643 {
1644         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1645
1646         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1647
1648         return 0;
1649 }
1650
1651 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1652         .name = "vc4-hdmi-cpu-dai",
1653         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1654         .playback = {
1655                 .stream_name = "Playback",
1656                 .channels_min = 1,
1657                 .channels_max = 8,
1658                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1659                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1660                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1661                          SNDRV_PCM_RATE_192000,
1662                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1663         },
1664 };
1665
1666 static const struct snd_dmaengine_pcm_config pcm_conf = {
1667         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1668         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1669 };
1670
1671 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
1672                                   uint8_t *buf, size_t len)
1673 {
1674         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1675         struct drm_connector *connector = &vc4_hdmi->connector;
1676
1677         mutex_lock(&vc4_hdmi->mutex);
1678         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1679         mutex_unlock(&vc4_hdmi->mutex);
1680
1681         return 0;
1682 }
1683
1684 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
1685         .get_eld = vc4_hdmi_audio_get_eld,
1686         .prepare = vc4_hdmi_audio_prepare,
1687         .audio_shutdown = vc4_hdmi_audio_shutdown,
1688         .audio_startup = vc4_hdmi_audio_startup,
1689 };
1690
1691 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
1692         .ops = &vc4_hdmi_codec_ops,
1693         .max_i2s_channels = 8,
1694         .i2s = 1,
1695 };
1696
1697 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1698 {
1699         const struct vc4_hdmi_register *mai_data =
1700                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1701         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1702         struct snd_soc_card *card = &vc4_hdmi->audio.card;
1703         struct device *dev = &vc4_hdmi->pdev->dev;
1704         struct platform_device *codec_pdev;
1705         const __be32 *addr;
1706         int index;
1707         int ret;
1708         int len;
1709
1710         if (!of_find_property(dev->of_node, "dmas", &len) ||
1711             len == 0) {
1712                 dev_warn(dev,
1713                          "'dmas' DT property is missing or empty, no HDMI audio\n");
1714                 return 0;
1715         }
1716
1717         if (mai_data->reg != VC4_HD) {
1718                 WARN_ONCE(true, "MAI isn't in the HD block\n");
1719                 return -EINVAL;
1720         }
1721
1722         /*
1723          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1724          * the bus address specified in the DT, because the physical address
1725          * (the one returned by platform_get_resource()) is not appropriate
1726          * for DMA transfers.
1727          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1728          */
1729         index = of_property_match_string(dev->of_node, "reg-names", "hd");
1730         /* Before BCM2711, we don't have a named register range */
1731         if (index < 0)
1732                 index = 1;
1733
1734         addr = of_get_address(dev->of_node, index, NULL, NULL);
1735
1736         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1737         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1738         vc4_hdmi->audio.dma_data.maxburst = 2;
1739
1740         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1741         if (ret) {
1742                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1743                 return ret;
1744         }
1745
1746         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1747                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1748         if (ret) {
1749                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1750                 return ret;
1751         }
1752
1753         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1754                                                    PLATFORM_DEVID_AUTO,
1755                                                    &vc4_hdmi_codec_pdata,
1756                                                    sizeof(vc4_hdmi_codec_pdata));
1757         if (IS_ERR(codec_pdev)) {
1758                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
1759                 return PTR_ERR(codec_pdev);
1760         }
1761         vc4_hdmi->audio.codec_pdev = codec_pdev;
1762
1763         dai_link->cpus          = &vc4_hdmi->audio.cpu;
1764         dai_link->codecs        = &vc4_hdmi->audio.codec;
1765         dai_link->platforms     = &vc4_hdmi->audio.platform;
1766
1767         dai_link->num_cpus      = 1;
1768         dai_link->num_codecs    = 1;
1769         dai_link->num_platforms = 1;
1770
1771         dai_link->name = "MAI";
1772         dai_link->stream_name = "MAI PCM";
1773         dai_link->codecs->dai_name = "i2s-hifi";
1774         dai_link->cpus->dai_name = dev_name(dev);
1775         dai_link->codecs->name = dev_name(&codec_pdev->dev);
1776         dai_link->platforms->name = dev_name(dev);
1777
1778         card->dai_link = dai_link;
1779         card->num_links = 1;
1780         card->name = vc4_hdmi->variant->card_name;
1781         card->driver_name = "vc4-hdmi";
1782         card->dev = dev;
1783         card->owner = THIS_MODULE;
1784
1785         /*
1786          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1787          * stores a pointer to the snd card object in dev->driver_data. This
1788          * means we cannot use it for something else. The hdmi back-pointer is
1789          * now stored in card->drvdata and should be retrieved with
1790          * snd_soc_card_get_drvdata() if needed.
1791          */
1792         snd_soc_card_set_drvdata(card, vc4_hdmi);
1793         ret = devm_snd_soc_register_card(dev, card);
1794         if (ret)
1795                 dev_err_probe(dev, ret, "Could not register sound card\n");
1796
1797         return ret;
1798
1799 }
1800
1801 static void vc4_hdmi_audio_exit(struct vc4_hdmi *vc4_hdmi)
1802 {
1803         platform_device_unregister(vc4_hdmi->audio.codec_pdev);
1804         vc4_hdmi->audio.codec_pdev = NULL;
1805 }
1806
1807 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
1808 {
1809         struct vc4_hdmi *vc4_hdmi = priv;
1810         struct drm_connector *connector = &vc4_hdmi->connector;
1811         struct drm_device *dev = connector->dev;
1812
1813         if (dev && dev->registered)
1814                 drm_connector_helper_hpd_irq_event(connector);
1815
1816         return IRQ_HANDLED;
1817 }
1818
1819 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
1820 {
1821         struct drm_connector *connector = &vc4_hdmi->connector;
1822         struct platform_device *pdev = vc4_hdmi->pdev;
1823         int ret;
1824
1825         if (vc4_hdmi->variant->external_irq_controller) {
1826                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
1827                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
1828
1829                 ret = request_threaded_irq(hpd_con,
1830                                            NULL,
1831                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1832                                            "vc4 hdmi hpd connected", vc4_hdmi);
1833                 if (ret)
1834                         return ret;
1835
1836                 ret = request_threaded_irq(hpd_rm,
1837                                            NULL,
1838                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1839                                            "vc4 hdmi hpd disconnected", vc4_hdmi);
1840                 if (ret) {
1841                         free_irq(hpd_con, vc4_hdmi);
1842                         return ret;
1843                 }
1844
1845                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1846         }
1847
1848         return 0;
1849 }
1850
1851 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi)
1852 {
1853         struct platform_device *pdev = vc4_hdmi->pdev;
1854
1855         if (vc4_hdmi->variant->external_irq_controller) {
1856                 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi);
1857                 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi);
1858         }
1859 }
1860
1861 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1862 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1863 {
1864         struct vc4_hdmi *vc4_hdmi = priv;
1865
1866         if (vc4_hdmi->cec_rx_msg.len)
1867                 cec_received_msg(vc4_hdmi->cec_adap,
1868                                  &vc4_hdmi->cec_rx_msg);
1869
1870         return IRQ_HANDLED;
1871 }
1872
1873 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1874 {
1875         struct vc4_hdmi *vc4_hdmi = priv;
1876
1877         if (vc4_hdmi->cec_tx_ok) {
1878                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1879                                   0, 0, 0, 0);
1880         } else {
1881                 /*
1882                  * This CEC implementation makes 1 retry, so if we
1883                  * get a NACK, then that means it made 2 attempts.
1884                  */
1885                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1886                                   0, 2, 0, 0);
1887         }
1888         return IRQ_HANDLED;
1889 }
1890
1891 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1892 {
1893         struct vc4_hdmi *vc4_hdmi = priv;
1894         irqreturn_t ret;
1895
1896         if (vc4_hdmi->cec_irq_was_rx)
1897                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1898         else
1899                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1900
1901         return ret;
1902 }
1903
1904 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1905 {
1906         struct drm_device *dev = vc4_hdmi->connector.dev;
1907         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1908         unsigned int i;
1909
1910         lockdep_assert_held(&vc4_hdmi->hw_lock);
1911
1912         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1913                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1914
1915         if (msg->len > 16) {
1916                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1917                 return;
1918         }
1919
1920         for (i = 0; i < msg->len; i += 4) {
1921                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1922
1923                 msg->msg[i] = val & 0xff;
1924                 msg->msg[i + 1] = (val >> 8) & 0xff;
1925                 msg->msg[i + 2] = (val >> 16) & 0xff;
1926                 msg->msg[i + 3] = (val >> 24) & 0xff;
1927         }
1928 }
1929
1930 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
1931 {
1932         u32 cntrl1;
1933
1934         lockdep_assert_held(&vc4_hdmi->hw_lock);
1935
1936         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1937         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1938         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1939         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1940
1941         return IRQ_WAKE_THREAD;
1942 }
1943
1944 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1945 {
1946         struct vc4_hdmi *vc4_hdmi = priv;
1947         irqreturn_t ret;
1948
1949         spin_lock(&vc4_hdmi->hw_lock);
1950         ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
1951         spin_unlock(&vc4_hdmi->hw_lock);
1952
1953         return ret;
1954 }
1955
1956 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
1957 {
1958         u32 cntrl1;
1959
1960         lockdep_assert_held(&vc4_hdmi->hw_lock);
1961
1962         vc4_hdmi->cec_rx_msg.len = 0;
1963         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1964         vc4_cec_read_msg(vc4_hdmi, cntrl1);
1965         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1966         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1967         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1968
1969         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1970
1971         return IRQ_WAKE_THREAD;
1972 }
1973
1974 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1975 {
1976         struct vc4_hdmi *vc4_hdmi = priv;
1977         irqreturn_t ret;
1978
1979         spin_lock(&vc4_hdmi->hw_lock);
1980         ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
1981         spin_unlock(&vc4_hdmi->hw_lock);
1982
1983         return ret;
1984 }
1985
1986 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1987 {
1988         struct vc4_hdmi *vc4_hdmi = priv;
1989         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1990         irqreturn_t ret;
1991         u32 cntrl5;
1992
1993         if (!(stat & VC4_HDMI_CPU_CEC))
1994                 return IRQ_NONE;
1995
1996         spin_lock(&vc4_hdmi->hw_lock);
1997         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1998         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1999         if (vc4_hdmi->cec_irq_was_rx)
2000                 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2001         else
2002                 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2003
2004         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2005         spin_unlock(&vc4_hdmi->hw_lock);
2006
2007         return ret;
2008 }
2009
2010 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2011 {
2012         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2013         /* clock period in microseconds */
2014         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2015         unsigned long flags;
2016         u32 val;
2017         int ret;
2018
2019         /*
2020          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2021          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2022          * .detect or .get_modes might call .adap_enable, which leads to this
2023          * function being called with that mutex held.
2024          *
2025          * Concurrency is not an issue for the moment since we don't share any
2026          * state with KMS, so we can ignore the lock for now, but we need to
2027          * keep it in mind if we were to change that assumption.
2028          */
2029
2030         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2031         if (ret)
2032                 return ret;
2033
2034         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2035
2036         val = HDMI_READ(HDMI_CEC_CNTRL_5);
2037         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2038                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2039                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2040         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2041                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2042
2043         HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2044                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2045         HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2046         HDMI_WRITE(HDMI_CEC_CNTRL_2,
2047                    ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2048                    ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2049                    ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2050                    ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2051                    ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2052         HDMI_WRITE(HDMI_CEC_CNTRL_3,
2053                    ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2054                    ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2055                    ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2056                    ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2057         HDMI_WRITE(HDMI_CEC_CNTRL_4,
2058                    ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2059                    ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2060                    ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2061                    ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2062
2063         if (!vc4_hdmi->variant->external_irq_controller)
2064                 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2065
2066         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2067
2068         return 0;
2069 }
2070
2071 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2072 {
2073         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2074         unsigned long flags;
2075
2076         /*
2077          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2078          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2079          * .detect or .get_modes might call .adap_enable, which leads to this
2080          * function being called with that mutex held.
2081          *
2082          * Concurrency is not an issue for the moment since we don't share any
2083          * state with KMS, so we can ignore the lock for now, but we need to
2084          * keep it in mind if we were to change that assumption.
2085          */
2086
2087         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2088
2089         if (!vc4_hdmi->variant->external_irq_controller)
2090                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2091
2092         HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2093                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2094
2095         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2096
2097         pm_runtime_put(&vc4_hdmi->pdev->dev);
2098
2099         return 0;
2100 }
2101
2102 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2103 {
2104         if (enable)
2105                 return vc4_hdmi_cec_enable(adap);
2106         else
2107                 return vc4_hdmi_cec_disable(adap);
2108 }
2109
2110 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2111 {
2112         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2113         unsigned long flags;
2114
2115         /*
2116          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2117          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2118          * .detect or .get_modes might call .adap_enable, which leads to this
2119          * function being called with that mutex held.
2120          *
2121          * Concurrency is not an issue for the moment since we don't share any
2122          * state with KMS, so we can ignore the lock for now, but we need to
2123          * keep it in mind if we were to change that assumption.
2124          */
2125
2126         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2127         HDMI_WRITE(HDMI_CEC_CNTRL_1,
2128                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2129                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2130         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2131
2132         return 0;
2133 }
2134
2135 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2136                                       u32 signal_free_time, struct cec_msg *msg)
2137 {
2138         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2139         struct drm_device *dev = vc4_hdmi->connector.dev;
2140         unsigned long flags;
2141         u32 val;
2142         unsigned int i;
2143
2144         /*
2145          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2146          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2147          * .detect or .get_modes might call .adap_enable, which leads to this
2148          * function being called with that mutex held.
2149          *
2150          * Concurrency is not an issue for the moment since we don't share any
2151          * state with KMS, so we can ignore the lock for now, but we need to
2152          * keep it in mind if we were to change that assumption.
2153          */
2154
2155         if (msg->len > 16) {
2156                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2157                 return -ENOMEM;
2158         }
2159
2160         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2161
2162         for (i = 0; i < msg->len; i += 4)
2163                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2164                            (msg->msg[i]) |
2165                            (msg->msg[i + 1] << 8) |
2166                            (msg->msg[i + 2] << 16) |
2167                            (msg->msg[i + 3] << 24));
2168
2169         val = HDMI_READ(HDMI_CEC_CNTRL_1);
2170         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2171         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2172         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2173         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2174         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2175
2176         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2177
2178         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2179
2180         return 0;
2181 }
2182
2183 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2184         .adap_enable = vc4_hdmi_cec_adap_enable,
2185         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2186         .adap_transmit = vc4_hdmi_cec_adap_transmit,
2187 };
2188
2189 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2190 {
2191         struct cec_connector_info conn_info;
2192         struct platform_device *pdev = vc4_hdmi->pdev;
2193         struct device *dev = &pdev->dev;
2194         unsigned long flags;
2195         int ret;
2196
2197         if (!of_find_property(dev->of_node, "interrupts", NULL)) {
2198                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
2199                 return 0;
2200         }
2201
2202         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
2203                                                   vc4_hdmi, "vc4",
2204                                                   CEC_CAP_DEFAULTS |
2205                                                   CEC_CAP_CONNECTOR_INFO, 1);
2206         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
2207         if (ret < 0)
2208                 return ret;
2209
2210         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
2211         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
2212
2213         if (vc4_hdmi->variant->external_irq_controller) {
2214                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"),
2215                                            vc4_cec_irq_handler_rx_bare,
2216                                            vc4_cec_irq_handler_rx_thread, 0,
2217                                            "vc4 hdmi cec rx", vc4_hdmi);
2218                 if (ret)
2219                         goto err_delete_cec_adap;
2220
2221                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"),
2222                                            vc4_cec_irq_handler_tx_bare,
2223                                            vc4_cec_irq_handler_tx_thread, 0,
2224                                            "vc4 hdmi cec tx", vc4_hdmi);
2225                 if (ret)
2226                         goto err_remove_cec_rx_handler;
2227         } else {
2228                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2229                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
2230                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2231
2232                 ret = request_threaded_irq(platform_get_irq(pdev, 0),
2233                                            vc4_cec_irq_handler,
2234                                            vc4_cec_irq_handler_thread, 0,
2235                                            "vc4 hdmi cec", vc4_hdmi);
2236                 if (ret)
2237                         goto err_delete_cec_adap;
2238         }
2239
2240         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
2241         if (ret < 0)
2242                 goto err_remove_handlers;
2243
2244         return 0;
2245
2246 err_remove_handlers:
2247         if (vc4_hdmi->variant->external_irq_controller)
2248                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
2249         else
2250                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
2251
2252 err_remove_cec_rx_handler:
2253         if (vc4_hdmi->variant->external_irq_controller)
2254                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
2255
2256 err_delete_cec_adap:
2257         cec_delete_adapter(vc4_hdmi->cec_adap);
2258
2259         return ret;
2260 }
2261
2262 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
2263 {
2264         struct platform_device *pdev = vc4_hdmi->pdev;
2265
2266         if (vc4_hdmi->variant->external_irq_controller) {
2267                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
2268                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
2269         } else {
2270                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
2271         }
2272
2273         cec_unregister_adapter(vc4_hdmi->cec_adap);
2274 }
2275
2276 static int vc4_hdmi_cec_resume(struct vc4_hdmi *vc4_hdmi)
2277 {
2278         unsigned long flags;
2279         u32 value;
2280
2281         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2282         value = HDMI_READ(HDMI_CEC_CNTRL_1);
2283         /* Set the logical address to Unregistered */
2284         value |= VC4_HDMI_CEC_ADDR_MASK;
2285         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
2286         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2287
2288         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
2289
2290         if (!vc4_hdmi->variant->external_irq_controller) {
2291                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2292                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
2293                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2294         }
2295
2296         return 0;
2297 }
2298 #else
2299 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2300 {
2301         return 0;
2302 }
2303
2304 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
2305
2306 static int vc4_hdmi_cec_resume(struct vc4_hdmi *vc4_hdmi)
2307 {
2308         return 0;
2309 }
2310 #endif
2311
2312 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
2313                                  struct debugfs_regset32 *regset,
2314                                  enum vc4_hdmi_regs reg)
2315 {
2316         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2317         struct debugfs_reg32 *regs, *new_regs;
2318         unsigned int count = 0;
2319         unsigned int i;
2320
2321         regs = kcalloc(variant->num_registers, sizeof(*regs),
2322                        GFP_KERNEL);
2323         if (!regs)
2324                 return -ENOMEM;
2325
2326         for (i = 0; i < variant->num_registers; i++) {
2327                 const struct vc4_hdmi_register *field = &variant->registers[i];
2328
2329                 if (field->reg != reg)
2330                         continue;
2331
2332                 regs[count].name = field->name;
2333                 regs[count].offset = field->offset;
2334                 count++;
2335         }
2336
2337         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
2338         if (!new_regs)
2339                 return -ENOMEM;
2340
2341         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
2342         regset->regs = new_regs;
2343         regset->nregs = count;
2344
2345         return 0;
2346 }
2347
2348 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2349 {
2350         struct platform_device *pdev = vc4_hdmi->pdev;
2351         struct device *dev = &pdev->dev;
2352         int ret;
2353
2354         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
2355         if (IS_ERR(vc4_hdmi->hdmicore_regs))
2356                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
2357
2358         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
2359         if (IS_ERR(vc4_hdmi->hd_regs))
2360                 return PTR_ERR(vc4_hdmi->hd_regs);
2361
2362         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2363         if (ret)
2364                 return ret;
2365
2366         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2367         if (ret)
2368                 return ret;
2369
2370         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
2371         if (IS_ERR(vc4_hdmi->pixel_clock)) {
2372                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
2373                 if (ret != -EPROBE_DEFER)
2374                         DRM_ERROR("Failed to get pixel clock\n");
2375                 return ret;
2376         }
2377
2378         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2379         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2380                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2381                 return PTR_ERR(vc4_hdmi->hsm_clock);
2382         }
2383         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2384         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2385
2386         return 0;
2387 }
2388
2389 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2390 {
2391         struct platform_device *pdev = vc4_hdmi->pdev;
2392         struct device *dev = &pdev->dev;
2393         struct resource *res;
2394         int ret;
2395
2396         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2397         if (!res)
2398                 return -ENODEV;
2399
2400         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2401                                                resource_size(res));
2402         if (!vc4_hdmi->hdmicore_regs)
2403                 return -ENOMEM;
2404
2405         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2406         if (!res)
2407                 return -ENODEV;
2408
2409         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2410         if (!vc4_hdmi->hd_regs)
2411                 return -ENOMEM;
2412
2413         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2414         if (!res)
2415                 return -ENODEV;
2416
2417         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2418         if (!vc4_hdmi->cec_regs)
2419                 return -ENOMEM;
2420
2421         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2422         if (!res)
2423                 return -ENODEV;
2424
2425         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2426         if (!vc4_hdmi->csc_regs)
2427                 return -ENOMEM;
2428
2429         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2430         if (!res)
2431                 return -ENODEV;
2432
2433         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2434         if (!vc4_hdmi->dvp_regs)
2435                 return -ENOMEM;
2436
2437         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2438         if (!res)
2439                 return -ENODEV;
2440
2441         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2442         if (!vc4_hdmi->phy_regs)
2443                 return -ENOMEM;
2444
2445         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2446         if (!res)
2447                 return -ENODEV;
2448
2449         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2450         if (!vc4_hdmi->ram_regs)
2451                 return -ENOMEM;
2452
2453         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2454         if (!res)
2455                 return -ENODEV;
2456
2457         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2458         if (!vc4_hdmi->rm_regs)
2459                 return -ENOMEM;
2460
2461         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2462         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2463                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2464                 return PTR_ERR(vc4_hdmi->hsm_clock);
2465         }
2466
2467         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2468         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2469                 DRM_ERROR("Failed to get pixel bvb clock\n");
2470                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2471         }
2472
2473         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2474         if (IS_ERR(vc4_hdmi->audio_clock)) {
2475                 DRM_ERROR("Failed to get audio clock\n");
2476                 return PTR_ERR(vc4_hdmi->audio_clock);
2477         }
2478
2479         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2480         if (IS_ERR(vc4_hdmi->cec_clock)) {
2481                 DRM_ERROR("Failed to get CEC clock\n");
2482                 return PTR_ERR(vc4_hdmi->cec_clock);
2483         }
2484
2485         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2486         if (IS_ERR(vc4_hdmi->reset)) {
2487                 DRM_ERROR("Failed to get HDMI reset line\n");
2488                 return PTR_ERR(vc4_hdmi->reset);
2489         }
2490
2491         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2492         if (ret)
2493                 return ret;
2494
2495         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2496         if (ret)
2497                 return ret;
2498
2499         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
2500         if (ret)
2501                 return ret;
2502
2503         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
2504         if (ret)
2505                 return ret;
2506
2507         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
2508         if (ret)
2509                 return ret;
2510
2511         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
2512         if (ret)
2513                 return ret;
2514
2515         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
2516         if (ret)
2517                 return ret;
2518
2519         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
2520         if (ret)
2521                 return ret;
2522
2523         return 0;
2524 }
2525
2526 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev)
2527 {
2528         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2529
2530         clk_disable_unprepare(vc4_hdmi->hsm_clock);
2531
2532         return 0;
2533 }
2534
2535 static int vc4_hdmi_runtime_resume(struct device *dev)
2536 {
2537         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2538         int ret;
2539
2540         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
2541         if (ret)
2542                 return ret;
2543
2544         if (vc4_hdmi->variant->reset)
2545                 vc4_hdmi->variant->reset(vc4_hdmi);
2546
2547         ret = vc4_hdmi_cec_resume(vc4_hdmi);
2548         if (ret) {
2549                 clk_disable_unprepare(vc4_hdmi->hsm_clock);
2550                 return ret;
2551         }
2552
2553         return 0;
2554 }
2555
2556 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2557 {
2558         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2559         struct platform_device *pdev = to_platform_device(dev);
2560         struct drm_device *drm = dev_get_drvdata(master);
2561         struct vc4_hdmi *vc4_hdmi;
2562         struct drm_encoder *encoder;
2563         struct device_node *ddc_node;
2564         int ret;
2565
2566         vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2567         if (!vc4_hdmi)
2568                 return -ENOMEM;
2569         mutex_init(&vc4_hdmi->mutex);
2570         spin_lock_init(&vc4_hdmi->hw_lock);
2571         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2572
2573         dev_set_drvdata(dev, vc4_hdmi);
2574         encoder = &vc4_hdmi->encoder.base.base;
2575         vc4_hdmi->encoder.base.type = variant->encoder_type;
2576         vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2577         vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2578         vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2579         vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2580         vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2581         vc4_hdmi->pdev = pdev;
2582         vc4_hdmi->variant = variant;
2583
2584         /*
2585          * Since we don't know the state of the controller and its
2586          * display (if any), let's assume it's always enabled.
2587          * vc4_hdmi_disable_scrambling() will thus run at boot, make
2588          * sure it's disabled, and avoid any inconsistency.
2589          */
2590         if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
2591                 vc4_hdmi->scdc_enabled = true;
2592
2593         ret = variant->init_resources(vc4_hdmi);
2594         if (ret)
2595                 return ret;
2596
2597         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2598         if (!ddc_node) {
2599                 DRM_ERROR("Failed to find ddc node in device tree\n");
2600                 return -ENODEV;
2601         }
2602
2603         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2604         of_node_put(ddc_node);
2605         if (!vc4_hdmi->ddc) {
2606                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2607                 return -EPROBE_DEFER;
2608         }
2609
2610         /* Only use the GPIO HPD pin if present in the DT, otherwise
2611          * we'll use the HDMI core's register.
2612          */
2613         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2614         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
2615                 ret = PTR_ERR(vc4_hdmi->hpd_gpio);
2616                 goto err_put_ddc;
2617         }
2618
2619         vc4_hdmi->disable_wifi_frequencies =
2620                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2621
2622         if (variant->max_pixel_clock == 600000000) {
2623                 struct vc4_dev *vc4 = to_vc4_dev(drm);
2624                 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
2625
2626                 if (max_rate < 550000000)
2627                         vc4_hdmi->disable_4kp60 = true;
2628         }
2629
2630         /*
2631          * If we boot without any cable connected to the HDMI connector,
2632          * the firmware will skip the HSM initialization and leave it
2633          * with a rate of 0, resulting in a bus lockup when we're
2634          * accessing the registers even if it's enabled.
2635          *
2636          * Let's put a sensible default at runtime_resume so that we
2637          * don't end up in this situation.
2638          */
2639         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
2640         if (ret)
2641                 goto err_put_ddc;
2642
2643         pm_runtime_enable(dev);
2644
2645         ret = pm_runtime_resume_and_get(dev);
2646         if (ret)
2647                 goto err_put_ddc;
2648
2649         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
2650              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
2651             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
2652                 clk_prepare_enable(vc4_hdmi->pixel_clock);
2653                 clk_prepare_enable(vc4_hdmi->hsm_clock);
2654                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
2655         }
2656
2657         drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2658         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2659
2660         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2661         if (ret)
2662                 goto err_destroy_encoder;
2663
2664         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
2665         if (ret)
2666                 goto err_destroy_conn;
2667
2668         ret = vc4_hdmi_cec_init(vc4_hdmi);
2669         if (ret)
2670                 goto err_free_hotplug;
2671
2672         ret = vc4_hdmi_audio_init(vc4_hdmi);
2673         if (ret)
2674                 goto err_free_cec;
2675
2676         vc4_debugfs_add_file(drm, variant->debugfs_name,
2677                              vc4_hdmi_debugfs_regs,
2678                              vc4_hdmi);
2679
2680         pm_runtime_put_sync(dev);
2681
2682         return 0;
2683
2684 err_free_cec:
2685         vc4_hdmi_cec_exit(vc4_hdmi);
2686 err_free_hotplug:
2687         vc4_hdmi_hotplug_exit(vc4_hdmi);
2688 err_destroy_conn:
2689         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2690 err_destroy_encoder:
2691         drm_encoder_cleanup(encoder);
2692         pm_runtime_put_sync(dev);
2693         pm_runtime_disable(dev);
2694 err_put_ddc:
2695         put_device(&vc4_hdmi->ddc->dev);
2696
2697         return ret;
2698 }
2699
2700 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2701                             void *data)
2702 {
2703         struct vc4_hdmi *vc4_hdmi;
2704
2705         /*
2706          * ASoC makes it a bit hard to retrieve a pointer to the
2707          * vc4_hdmi structure. Registering the card will overwrite our
2708          * device drvdata with a pointer to the snd_soc_card structure,
2709          * which can then be used to retrieve whatever drvdata we want
2710          * to associate.
2711          *
2712          * However, that doesn't fly in the case where we wouldn't
2713          * register an ASoC card (because of an old DT that is missing
2714          * the dmas properties for example), then the card isn't
2715          * registered and the device drvdata wouldn't be set.
2716          *
2717          * We can deal with both cases by making sure a snd_soc_card
2718          * pointer and a vc4_hdmi structure are pointing to the same
2719          * memory address, so we can treat them indistinctly without any
2720          * issue.
2721          */
2722         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2723         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2724         vc4_hdmi = dev_get_drvdata(dev);
2725
2726         kfree(vc4_hdmi->hdmi_regset.regs);
2727         kfree(vc4_hdmi->hd_regset.regs);
2728
2729         vc4_hdmi_audio_exit(vc4_hdmi);
2730         vc4_hdmi_cec_exit(vc4_hdmi);
2731         vc4_hdmi_hotplug_exit(vc4_hdmi);
2732         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2733         drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2734
2735         pm_runtime_disable(dev);
2736
2737         put_device(&vc4_hdmi->ddc->dev);
2738 }
2739
2740 static const struct component_ops vc4_hdmi_ops = {
2741         .bind   = vc4_hdmi_bind,
2742         .unbind = vc4_hdmi_unbind,
2743 };
2744
2745 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2746 {
2747         return component_add(&pdev->dev, &vc4_hdmi_ops);
2748 }
2749
2750 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2751 {
2752         component_del(&pdev->dev, &vc4_hdmi_ops);
2753         return 0;
2754 }
2755
2756 static const struct vc4_hdmi_variant bcm2835_variant = {
2757         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2758         .debugfs_name           = "hdmi_regs",
2759         .card_name              = "vc4-hdmi",
2760         .max_pixel_clock        = 162000000,
2761         .registers              = vc4_hdmi_fields,
2762         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
2763
2764         .init_resources         = vc4_hdmi_init_resources,
2765         .csc_setup              = vc4_hdmi_csc_setup,
2766         .reset                  = vc4_hdmi_reset,
2767         .set_timings            = vc4_hdmi_set_timings,
2768         .phy_init               = vc4_hdmi_phy_init,
2769         .phy_disable            = vc4_hdmi_phy_disable,
2770         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
2771         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
2772         .channel_map            = vc4_hdmi_channel_map,
2773         .supports_hdr           = false,
2774 };
2775
2776 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2777         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2778         .debugfs_name           = "hdmi0_regs",
2779         .card_name              = "vc4-hdmi-0",
2780         .max_pixel_clock        = 600000000,
2781         .registers              = vc5_hdmi_hdmi0_fields,
2782         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2783         .phy_lane_mapping       = {
2784                 PHY_LANE_0,
2785                 PHY_LANE_1,
2786                 PHY_LANE_2,
2787                 PHY_LANE_CK,
2788         },
2789         .unsupported_odd_h_timings      = true,
2790         .external_irq_controller        = true,
2791
2792         .init_resources         = vc5_hdmi_init_resources,
2793         .csc_setup              = vc5_hdmi_csc_setup,
2794         .reset                  = vc5_hdmi_reset,
2795         .set_timings            = vc5_hdmi_set_timings,
2796         .phy_init               = vc5_hdmi_phy_init,
2797         .phy_disable            = vc5_hdmi_phy_disable,
2798         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2799         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2800         .channel_map            = vc5_hdmi_channel_map,
2801         .supports_hdr           = true,
2802         .hp_detect              = vc5_hdmi_hp_detect,
2803 };
2804
2805 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2806         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
2807         .debugfs_name           = "hdmi1_regs",
2808         .card_name              = "vc4-hdmi-1",
2809         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2810         .registers              = vc5_hdmi_hdmi1_fields,
2811         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2812         .phy_lane_mapping       = {
2813                 PHY_LANE_1,
2814                 PHY_LANE_0,
2815                 PHY_LANE_CK,
2816                 PHY_LANE_2,
2817         },
2818         .unsupported_odd_h_timings      = true,
2819         .external_irq_controller        = true,
2820
2821         .init_resources         = vc5_hdmi_init_resources,
2822         .csc_setup              = vc5_hdmi_csc_setup,
2823         .reset                  = vc5_hdmi_reset,
2824         .set_timings            = vc5_hdmi_set_timings,
2825         .phy_init               = vc5_hdmi_phy_init,
2826         .phy_disable            = vc5_hdmi_phy_disable,
2827         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2828         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2829         .channel_map            = vc5_hdmi_channel_map,
2830         .supports_hdr           = true,
2831         .hp_detect              = vc5_hdmi_hp_detect,
2832 };
2833
2834 static const struct of_device_id vc4_hdmi_dt_match[] = {
2835         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2836         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2837         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2838         {}
2839 };
2840
2841 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
2842         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
2843                            vc4_hdmi_runtime_resume,
2844                            NULL)
2845 };
2846
2847 struct platform_driver vc4_hdmi_driver = {
2848         .probe = vc4_hdmi_dev_probe,
2849         .remove = vc4_hdmi_dev_remove,
2850         .driver = {
2851                 .name = "vc4_hdmi",
2852                 .of_match_table = vc4_hdmi_dt_match,
2853                 .pm = &vc4_hdmi_pm_ops,
2854         },
2855 };