drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <drm/drm_simple_kms_helper.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include <linux/clk.h>
  40 #include <linux/component.h>
  41 #include <linux/i2c.h>
  42 #include <linux/of_address.h>
  43 #include <linux/of_gpio.h>
  44 #include <linux/of_platform.h>
  45 #include <linux/pm_runtime.h>
  46 #include <linux/rational.h>
  47 #include <linux/reset.h>
  48 #include <sound/dmaengine_pcm.h>
  49 #include <sound/hdmi-codec.h>
  50 #include <sound/pcm_drm_eld.h>
  51 #include <sound/pcm_params.h>
  52 #include <sound/soc.h>
  53 #include "media/cec.h"
  54 #include "vc4_drv.h"
  55 #include "vc4_hdmi.h"
  56 #include "vc4_hdmi_regs.h"
  57 #include "vc4_regs.h"
  58
  59 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  60 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  61 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  62 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  63 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  64 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  65
  66 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  67 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  68 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  69 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  70
  71 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  72 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  73 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  74 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  75 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  76 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  77
  78 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  79 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  80
  81 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  82
  83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  85
  86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  88
  89 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  90
  91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
  92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
  93
  94 # define VC4_HD_M_SW_RST                        BIT(2)
  95 # define VC4_HD_M_ENABLE                        BIT(0)
  96
  97 #define HSM_MIN_CLOCK_FREQ      120000000
  98 #define CEC_CLOCK_FREQ 40000
  99
 100 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 101
 102 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode)
 103 {
 104         return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK;
 105 }
 106
 107 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 108 {
 109         struct drm_info_node *node = (struct drm_info_node *)m->private;
 110         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
 111         struct drm_printer p = drm_seq_file_printer(m);
 112
 113         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 114         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 115
 116         return 0;
 117 }
 118
 119 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 120 {
 121         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 122         udelay(1);
 123         HDMI_WRITE(HDMI_M_CTL, 0);
 124
 125         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 126
 127         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 128                    VC4_HDMI_SW_RESET_HDMI |
 129                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 130
 131         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 132 }
 133
 134 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 135 {
 136         reset_control_reset(vc4_hdmi->reset);
 137
 138         HDMI_WRITE(HDMI_DVP_CTL, 0);
 139
 140         HDMI_WRITE(HDMI_CLOCK_STOP,
 141                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 142 }
 143
 144 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 145 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 146 {
 147         u16 clk_cnt;
 148         u32 value;
 149
 150         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 151         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 152
 153         /*
 154          * Set the clock divider: the hsm_clock rate and this divider
 155          * setting will give a 40 kHz CEC clock.
 156          */
 157         clk_cnt = clk_get_rate(vc4_hdmi->cec_clock) / CEC_CLOCK_FREQ;
 158         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 159         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 160 }
 161 #else
 162 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 163 #endif
 164
 165 static enum drm_connector_status
 166 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 167 {
 168         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 169         bool connected = false;
 170
 171         if (vc4_hdmi->hpd_gpio &&
 172             gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) {
 173                 connected = true;
 174         } else if (drm_probe_ddc(vc4_hdmi->ddc)) {
 175                 connected = true;
 176         } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) {
 177                 connected = true;
 178         }
 179
 180         if (connected) {
 181                 if (connector->status != connector_status_connected) {
 182                         struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
 183
 184                         if (edid) {
 185                                 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 186                                 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
 187                                 kfree(edid);
 188                         }
 189                 }
 190
 191                 return connector_status_connected;
 192         }
 193
 194         cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 195         return connector_status_disconnected;
 196 }
 197
 198 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 199 {
 200         drm_connector_unregister(connector);
 201         drm_connector_cleanup(connector);
 202 }
 203
 204 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 205 {
 206         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 207         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 208         int ret = 0;
 209         struct edid *edid;
 210
 211         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 212         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 213         if (!edid)
 214                 return -ENODEV;
 215
 216         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 217
 218         drm_connector_update_edid_property(connector, edid);
 219         ret = drm_add_edid_modes(connector, edid);
 220         kfree(edid);
 221
 222         if (vc4_hdmi->disable_4kp60) {
 223                 struct drm_device *drm = connector->dev;
 224                 struct drm_display_mode *mode;
 225
 226                 list_for_each_entry(mode, &connector->probed_modes, head) {
 227                         if (vc4_hdmi_mode_needs_scrambling(mode)) {
 228                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 229                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 230                         }
 231                 }
 232         }
 233
 234         return ret;
 235 }
 236
 237 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 238                                            struct drm_atomic_state *state)
 239 {
 240         struct drm_connector_state *old_state =
 241                 drm_atomic_get_old_connector_state(state, connector);
 242         struct drm_connector_state *new_state =
 243                 drm_atomic_get_new_connector_state(state, connector);
 244         struct drm_crtc *crtc = new_state->crtc;
 245
 246         if (!crtc)
 247                 return 0;
 248
 249         if (old_state->colorspace != new_state->colorspace ||
 250             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 251                 struct drm_crtc_state *crtc_state;
 252
 253                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 254                 if (IS_ERR(crtc_state))
 255                         return PTR_ERR(crtc_state);
 256
 257                 crtc_state->mode_changed = true;
 258         }
 259
 260         return 0;
 261 }
 262
 263 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 264 {
 265         struct vc4_hdmi_connector_state *old_state =
 266                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 267         struct vc4_hdmi_connector_state *new_state =
 268                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 269
 270         if (connector->state)
 271                 __drm_atomic_helper_connector_destroy_state(connector->state);
 272
 273         kfree(old_state);
 274         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 275
 276         if (!new_state)
 277                 return;
 278
 279         new_state->base.max_bpc = 8;
 280         new_state->base.max_requested_bpc = 8;
 281         drm_atomic_helper_connector_tv_reset(connector);
 282 }
 283
 284 static struct drm_connector_state *
 285 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 286 {
 287         struct drm_connector_state *conn_state = connector->state;
 288         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 289         struct vc4_hdmi_connector_state *new_state;
 290
 291         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 292         if (!new_state)
 293                 return NULL;
 294
 295         new_state->pixel_rate = vc4_state->pixel_rate;
 296         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 297
 298         return &new_state->base;
 299 }
 300
 301 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 302         .detect = vc4_hdmi_connector_detect,
 303         .fill_modes = drm_helper_probe_single_connector_modes,
 304         .destroy = vc4_hdmi_connector_destroy,
 305         .reset = vc4_hdmi_connector_reset,
 306         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 307         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 308 };
 309
 310 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 311         .get_modes = vc4_hdmi_connector_get_modes,
 312         .atomic_check = vc4_hdmi_connector_atomic_check,
 313 };
 314
 315 static int vc4_hdmi_connector_init(struct drm_device *dev,
 316                                    struct vc4_hdmi *vc4_hdmi)
 317 {
 318         struct drm_connector *connector = &vc4_hdmi->connector;
 319         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 320         int ret;
 321
 322         drm_connector_init_with_ddc(dev, connector,
 323                                     &vc4_hdmi_connector_funcs,
 324                                     DRM_MODE_CONNECTOR_HDMIA,
 325                                     vc4_hdmi->ddc);
 326         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 327
 328         /*
 329          * Some of the properties below require access to state, like bpc.
 330          * Allocate some default initial connector state with our reset helper.
 331          */
 332         if (connector->funcs->reset)
 333                 connector->funcs->reset(connector);
 334
 335         /* Create and attach TV margin props to this connector. */
 336         ret = drm_mode_create_tv_margin_properties(dev);
 337         if (ret)
 338                 return ret;
 339
 340         ret = drm_mode_create_hdmi_colorspace_property(connector);
 341         if (ret)
 342                 return ret;
 343
 344         drm_connector_attach_colorspace_property(connector);
 345         drm_connector_attach_tv_margin_properties(connector);
 346         drm_connector_attach_max_bpc_property(connector, 8, 12);
 347
 348         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 349                              DRM_CONNECTOR_POLL_DISCONNECT);
 350
 351         connector->interlace_allowed = 1;
 352         connector->doublescan_allowed = 0;
 353
 354         if (vc4_hdmi->variant->supports_hdr)
 355                 drm_connector_attach_hdr_output_metadata_property(connector);
 356
 357         drm_connector_attach_encoder(connector, encoder);
 358
 359         return 0;
 360 }
 361
 362 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 363                                 enum hdmi_infoframe_type type,
 364                                 bool poll)
 365 {
 366         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 367         u32 packet_id = type - 0x80;
 368
 369         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 370                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 371
 372         if (!poll)
 373                 return 0;
 374
 375         return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 376                           BIT(packet_id)), 100);
 377 }
 378
 379 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 380                                      union hdmi_infoframe *frame)
 381 {
 382         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 383         u32 packet_id = frame->any.type - 0x80;
 384         const struct vc4_hdmi_register *ram_packet_start =
 385                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 386         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 387         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 388                                                        ram_packet_start->reg);
 389         uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
 390         ssize_t len, i;
 391         int ret;
 392
 393         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 394                     VC4_HDMI_RAM_PACKET_ENABLE),
 395                   "Packet RAM has to be on to store the packet.");
 396
 397         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 398         if (len < 0)
 399                 return;
 400
 401         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 402         if (ret) {
 403                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 404                 return;
 405         }
 406
 407         for (i = 0; i < len; i += 7) {
 408                 writel(buffer[i + 0] << 0 |
 409                        buffer[i + 1] << 8 |
 410                        buffer[i + 2] << 16,
 411                        base + packet_reg);
 412                 packet_reg += 4;
 413
 414                 writel(buffer[i + 3] << 0 |
 415                        buffer[i + 4] << 8 |
 416                        buffer[i + 5] << 16 |
 417                        buffer[i + 6] << 24,
 418                        base + packet_reg);
 419                 packet_reg += 4;
 420         }
 421
 422         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 423                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 424         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 425                         BIT(packet_id)), 100);
 426         if (ret)
 427                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 428 }
 429
 430 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 431 {
 432         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 433         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 434         struct drm_connector *connector = &vc4_hdmi->connector;
 435         struct drm_connector_state *cstate = connector->state;
 436         struct drm_crtc *crtc = encoder->crtc;
 437         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 438         union hdmi_infoframe frame;
 439         int ret;
 440
 441         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 442                                                        connector, mode);
 443         if (ret < 0) {
 444                 DRM_ERROR("couldn't fill AVI infoframe\n");
 445                 return;
 446         }
 447
 448         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 449                                            connector, mode,
 450                                            vc4_encoder->limited_rgb_range ?
 451                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 452                                            HDMI_QUANTIZATION_RANGE_FULL);
 453         drm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate);
 454         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 455
 456         vc4_hdmi_write_infoframe(encoder, &frame);
 457 }
 458
 459 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 460 {
 461         union hdmi_infoframe frame;
 462         int ret;
 463
 464         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 465         if (ret < 0) {
 466                 DRM_ERROR("couldn't fill SPD infoframe\n");
 467                 return;
 468         }
 469
 470         frame.spd.sdi = HDMI_SPD_SDI_PC;
 471
 472         vc4_hdmi_write_infoframe(encoder, &frame);
 473 }
 474
 475 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 476 {
 477         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 478         struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
 479         union hdmi_infoframe frame;
 480
 481         memcpy(&frame.audio, audio, sizeof(*audio));
 482         vc4_hdmi_write_infoframe(encoder, &frame);
 483 }
 484
 485 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 486 {
 487         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 488         struct drm_connector *connector = &vc4_hdmi->connector;
 489         struct drm_connector_state *conn_state = connector->state;
 490         union hdmi_infoframe frame;
 491
 492         if (!vc4_hdmi->variant->supports_hdr)
 493                 return;
 494
 495         if (!conn_state->hdr_output_metadata)
 496                 return;
 497
 498         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 499                 return;
 500
 501         vc4_hdmi_write_infoframe(encoder, &frame);
 502 }
 503
 504 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 505 {
 506         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 507
 508         vc4_hdmi_set_avi_infoframe(encoder);
 509         vc4_hdmi_set_spd_infoframe(encoder);
 510         /*
 511          * If audio was streaming, then we need to reenabled the audio
 512          * infoframe here during encoder_enable.
 513          */
 514         if (vc4_hdmi->audio.streaming)
 515                 vc4_hdmi_set_audio_infoframe(encoder);
 516
 517         vc4_hdmi_set_hdr_infoframe(encoder);
 518 }
 519
 520 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
 521                                          struct drm_display_mode *mode)
 522 {
 523         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 524         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 525         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 526
 527         if (!vc4_encoder->hdmi_monitor)
 528                 return false;
 529
 530         if (!display->hdmi.scdc.supported ||
 531             !display->hdmi.scdc.scrambling.supported)
 532                 return false;
 533
 534         return true;
 535 }
 536
 537 #define SCRAMBLING_POLLING_DELAY_MS     1000
 538
 539 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 540 {
 541         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 542         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 543
 544         if (!vc4_hdmi_supports_scrambling(encoder, mode))
 545                 return;
 546
 547         if (!vc4_hdmi_mode_needs_scrambling(mode))
 548                 return;
 549
 550         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 551         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 552
 553         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
 554                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 555
 556         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 557                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 558 }
 559
 560 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
 561 {
 562         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 563         struct drm_crtc *crtc = encoder->crtc;
 564
 565         /*
 566          * At boot, encoder->crtc will be NULL. Since we don't know the
 567          * state of the scrambler and in order to avoid any
 568          * inconsistency, let's disable it all the time.
 569          */
 570         if (crtc && !vc4_hdmi_supports_scrambling(encoder, &crtc->mode))
 571                 return;
 572
 573         if (crtc && !vc4_hdmi_mode_needs_scrambling(&crtc->mode))
 574                 return;
 575
 576         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
 577                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
 578
 579         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
 580                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 581
 582         drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
 583         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
 584 }
 585
 586 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
 587 {
 588         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
 589                                                  struct vc4_hdmi,
 590                                                  scrambling_work);
 591
 592         if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
 593                 return;
 594
 595         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 596         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 597
 598         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 599                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 600 }
 601
 602 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 603                                                struct drm_atomic_state *state)
 604 {
 605         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 606
 607         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 608
 609         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
 610
 611         mdelay(1);
 612
 613         HDMI_WRITE(HDMI_VID_CTL,
 614                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 615         vc4_hdmi_disable_scrambling(encoder);
 616 }
 617
 618 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
 619                                                  struct drm_atomic_state *state)
 620 {
 621         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 622         int ret;
 623
 624         HDMI_WRITE(HDMI_VID_CTL,
 625                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 626
 627         if (vc4_hdmi->variant->phy_disable)
 628                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 629
 630         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 631         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 632
 633         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 634         if (ret < 0)
 635                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 636 }
 637
 638 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 639 {
 640 }
 641
 642 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 643 {
 644         u32 csc_ctl;
 645
 646         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 647                                 VC4_HD_CSC_CTL_ORDER);
 648
 649         if (enable) {
 650                 /* CEA VICs other than #1 requre limited range RGB
 651                  * output unless overridden by an AVI infoframe.
 652                  * Apply a colorspace conversion to squash 0-255 down
 653                  * to 16-235.  The matrix here is:
 654                  *
 655                  * [ 0      0      0.8594 16]
 656                  * [ 0      0.8594 0      16]
 657                  * [ 0.8594 0      0      16]
 658                  * [ 0      0      0       1]
 659                  */
 660                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 661                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 662                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 663                                          VC4_HD_CSC_CTL_MODE);
 664
 665                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 666                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 667                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 668                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 669                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 670                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 671         }
 672
 673         /* The RGB order applies even when CSC is disabled. */
 674         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 675 }
 676
 677 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 678 {
 679         u32 csc_ctl;
 680
 681         csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
 682
 683         if (enable) {
 684                 /* CEA VICs other than #1 requre limited range RGB
 685                  * output unless overridden by an AVI infoframe.
 686                  * Apply a colorspace conversion to squash 0-255 down
 687                  * to 16-235.  The matrix here is:
 688                  *
 689                  * [ 0.8594 0      0      16]
 690                  * [ 0      0.8594 0      16]
 691                  * [ 0      0      0.8594 16]
 692                  * [ 0      0      0       1]
 693                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 694                  */
 695                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
 696                 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
 697                 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
 698                 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
 699                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 700                 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
 701         } else {
 702                 /* Still use the matrix for full range, but make it unity.
 703                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 704                  */
 705                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
 706                 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
 707                 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
 708                 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
 709                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 710                 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
 711         }
 712
 713         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 714 }
 715
 716 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 717                                  struct drm_connector_state *state,
 718                                  struct drm_display_mode *mode)
 719 {
 720         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 721         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 722         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 723         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 724         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 725                                    VC4_HDMI_VERTA_VSP) |
 726                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 727                                    VC4_HDMI_VERTA_VFP) |
 728                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 729         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 730                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 731                                    VC4_HDMI_VERTB_VBP));
 732         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 733                           VC4_SET_FIELD(mode->crtc_vtotal -
 734                                         mode->crtc_vsync_end -
 735                                         interlaced,
 736                                         VC4_HDMI_VERTB_VBP));
 737
 738         HDMI_WRITE(HDMI_HORZA,
 739                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 740                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 741                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 742                                  VC4_HDMI_HORZA_HAP));
 743
 744         HDMI_WRITE(HDMI_HORZB,
 745                    VC4_SET_FIELD((mode->htotal -
 746                                   mode->hsync_end) * pixel_rep,
 747                                  VC4_HDMI_HORZB_HBP) |
 748                    VC4_SET_FIELD((mode->hsync_end -
 749                                   mode->hsync_start) * pixel_rep,
 750                                  VC4_HDMI_HORZB_HSP) |
 751                    VC4_SET_FIELD((mode->hsync_start -
 752                                   mode->hdisplay) * pixel_rep,
 753                                  VC4_HDMI_HORZB_HFP));
 754
 755         HDMI_WRITE(HDMI_VERTA0, verta);
 756         HDMI_WRITE(HDMI_VERTA1, verta);
 757
 758         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 759         HDMI_WRITE(HDMI_VERTB1, vertb);
 760 }
 761
 762 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 763                                  struct drm_connector_state *state,
 764                                  struct drm_display_mode *mode)
 765 {
 766         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 767         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 768         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 769         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 770         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 771                                    VC5_HDMI_VERTA_VSP) |
 772                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 773                                    VC5_HDMI_VERTA_VFP) |
 774                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
 775         u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 776                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 777                                    VC4_HDMI_VERTB_VBP));
 778         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 779                           VC4_SET_FIELD(mode->crtc_vtotal -
 780                                         mode->crtc_vsync_end -
 781                                         interlaced,
 782                                         VC4_HDMI_VERTB_VBP));
 783         unsigned char gcp;
 784         bool gcp_en;
 785         u32 reg;
 786
 787         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
 788         HDMI_WRITE(HDMI_HORZA,
 789                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
 790                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
 791                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 792                                  VC5_HDMI_HORZA_HAP) |
 793                    VC4_SET_FIELD((mode->hsync_start -
 794                                   mode->hdisplay) * pixel_rep,
 795                                  VC5_HDMI_HORZA_HFP));
 796
 797         HDMI_WRITE(HDMI_HORZB,
 798                    VC4_SET_FIELD((mode->htotal -
 799                                   mode->hsync_end) * pixel_rep,
 800                                  VC5_HDMI_HORZB_HBP) |
 801                    VC4_SET_FIELD((mode->hsync_end -
 802                                   mode->hsync_start) * pixel_rep,
 803                                  VC5_HDMI_HORZB_HSP));
 804
 805         HDMI_WRITE(HDMI_VERTA0, verta);
 806         HDMI_WRITE(HDMI_VERTA1, verta);
 807
 808         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 809         HDMI_WRITE(HDMI_VERTB1, vertb);
 810
 811         switch (state->max_bpc) {
 812         case 12:
 813                 gcp = 6;
 814                 gcp_en = true;
 815                 break;
 816         case 10:
 817                 gcp = 5;
 818                 gcp_en = true;
 819                 break;
 820         case 8:
 821         default:
 822                 gcp = 4;
 823                 gcp_en = false;
 824                 break;
 825         }
 826
 827         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
 828         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
 829                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
 830         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
 831                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
 832         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
 833
 834         reg = HDMI_READ(HDMI_GCP_WORD_1);
 835         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
 836         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
 837         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
 838
 839         reg = HDMI_READ(HDMI_GCP_CONFIG);
 840         reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
 841         reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
 842         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
 843
 844         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
 845 }
 846
 847 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
 848 {
 849         u32 drift;
 850         int ret;
 851
 852         drift = HDMI_READ(HDMI_FIFO_CTL);
 853         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 854
 855         HDMI_WRITE(HDMI_FIFO_CTL,
 856                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 857         HDMI_WRITE(HDMI_FIFO_CTL,
 858                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 859         usleep_range(1000, 1100);
 860         HDMI_WRITE(HDMI_FIFO_CTL,
 861                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 862         HDMI_WRITE(HDMI_FIFO_CTL,
 863                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 864
 865         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
 866                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
 867         WARN_ONCE(ret, "Timeout waiting for "
 868                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
 869 }
 870
 871 static struct drm_connector_state *
 872 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder,
 873                                      struct drm_atomic_state *state)
 874 {
 875         struct drm_connector_state *conn_state;
 876         struct drm_connector *connector;
 877         unsigned int i;
 878
 879         for_each_new_connector_in_state(state, connector, conn_state, i) {
 880                 if (conn_state->best_encoder == encoder)
 881                         return conn_state;
 882         }
 883
 884         return NULL;
 885 }
 886
 887 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
 888                                                 struct drm_atomic_state *state)
 889 {
 890         struct drm_connector_state *conn_state =
 891                 vc4_hdmi_encoder_get_connector_state(encoder, state);
 892         struct vc4_hdmi_connector_state *vc4_conn_state =
 893                 conn_state_to_vc4_hdmi_conn_state(conn_state);
 894         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 895         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 896         unsigned long pixel_rate = vc4_conn_state->pixel_rate;
 897         unsigned long bvb_rate, hsm_rate;
 898         int ret;
 899
 900         /*
 901          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
 902          * be faster than pixel clock, infinitesimally faster, tested in
 903          * simulation. Otherwise, exact value is unimportant for HDMI
 904          * operation." This conflicts with bcm2835's vc4 documentation, which
 905          * states HSM's clock has to be at least 108% of the pixel clock.
 906          *
 907          * Real life tests reveal that vc4's firmware statement holds up, and
 908          * users are able to use pixel clocks closer to HSM's, namely for
 909          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
 910          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
 911          * 162MHz.
 912          *
 913          * Additionally, the AXI clock needs to be at least 25% of
 914          * pixel clock, but HSM ends up being the limiting factor.
 915          */
 916         hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
 917         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
 918         if (ret) {
 919                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
 920                 return;
 921         }
 922
 923         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
 924         if (ret < 0) {
 925                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
 926                 return;
 927         }
 928
 929         ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
 930         if (ret) {
 931                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
 932                 return;
 933         }
 934
 935         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
 936         if (ret) {
 937                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
 938                 return;
 939         }
 940
 941         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
 942
 943         if (pixel_rate > 297000000)
 944                 bvb_rate = 300000000;
 945         else if (pixel_rate > 148500000)
 946                 bvb_rate = 150000000;
 947         else
 948                 bvb_rate = 75000000;
 949
 950         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
 951         if (ret) {
 952                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
 953                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
 954                 return;
 955         }
 956
 957         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
 958         if (ret) {
 959                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
 960                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
 961                 return;
 962         }
 963
 964         if (vc4_hdmi->variant->phy_init)
 965                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
 966
 967         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 968                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
 969                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
 970                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
 971
 972         if (vc4_hdmi->variant->set_timings)
 973                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
 974 }
 975
 976 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
 977                                              struct drm_atomic_state *state)
 978 {
 979         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 980         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 981         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 982
 983         if (vc4_encoder->hdmi_monitor &&
 984             drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
 985                 if (vc4_hdmi->variant->csc_setup)
 986                         vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
 987
 988                 vc4_encoder->limited_rgb_range = true;
 989         } else {
 990                 if (vc4_hdmi->variant->csc_setup)
 991                         vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
 992
 993                 vc4_encoder->limited_rgb_range = false;
 994         }
 995
 996         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
 997 }
 998
 999 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1000                                               struct drm_atomic_state *state)
1001 {
1002         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1003         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1004         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1005         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1006         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1007         int ret;
1008
1009         HDMI_WRITE(HDMI_VID_CTL,
1010                    VC4_HD_VID_CTL_ENABLE |
1011                    VC4_HD_VID_CTL_CLRRGB |
1012                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1013                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1014                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1015                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1016
1017         HDMI_WRITE(HDMI_VID_CTL,
1018                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1019
1020         if (vc4_encoder->hdmi_monitor) {
1021                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1022                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1023                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1024
1025                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1026                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1027                 WARN_ONCE(ret, "Timeout waiting for "
1028                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1029         } else {
1030                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1031                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1032                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1033                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1034                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1035                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1036
1037                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1038                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1039                 WARN_ONCE(ret, "Timeout waiting for "
1040                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1041         }
1042
1043         if (vc4_encoder->hdmi_monitor) {
1044                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1045                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1046                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1047                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1048                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
1049
1050                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1051                            VC4_HDMI_RAM_PACKET_ENABLE);
1052
1053                 vc4_hdmi_set_infoframes(encoder);
1054         }
1055
1056         vc4_hdmi_recenter_fifo(vc4_hdmi);
1057         vc4_hdmi_enable_scrambling(encoder);
1058 }
1059
1060 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
1061 {
1062 }
1063
1064 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
1065 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
1066
1067 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1068                                          struct drm_crtc_state *crtc_state,
1069                                          struct drm_connector_state *conn_state)
1070 {
1071         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1072         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1073         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1074         unsigned long long pixel_rate = mode->clock * 1000;
1075         unsigned long long tmds_rate;
1076
1077         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1078             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1079              (mode->hsync_end % 2) || (mode->htotal % 2)))
1080                 return -EINVAL;
1081
1082         /*
1083          * The 1440p@60 pixel rate is in the same range than the first
1084          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1085          * bandwidth). Slightly lower the frequency to bring it out of
1086          * the WiFi range.
1087          */
1088         tmds_rate = pixel_rate * 10;
1089         if (vc4_hdmi->disable_wifi_frequencies &&
1090             (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1091              tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1092                 mode->clock = 238560;
1093                 pixel_rate = mode->clock * 1000;
1094         }
1095
1096         if (conn_state->max_bpc == 12) {
1097                 pixel_rate = pixel_rate * 150;
1098                 do_div(pixel_rate, 100);
1099         } else if (conn_state->max_bpc == 10) {
1100                 pixel_rate = pixel_rate * 125;
1101                 do_div(pixel_rate, 100);
1102         }
1103
1104         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1105                 pixel_rate = pixel_rate * 2;
1106
1107         if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
1108                 return -EINVAL;
1109
1110         if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK))
1111                 return -EINVAL;
1112
1113         vc4_state->pixel_rate = pixel_rate;
1114
1115         return 0;
1116 }
1117
1118 static enum drm_mode_status
1119 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1120                             const struct drm_display_mode *mode)
1121 {
1122         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1123
1124         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1125             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1126              (mode->hsync_end % 2) || (mode->htotal % 2)))
1127                 return MODE_H_ILLEGAL;
1128
1129         if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
1130                 return MODE_CLOCK_HIGH;
1131
1132         if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode))
1133                 return MODE_CLOCK_HIGH;
1134
1135         return MODE_OK;
1136 }
1137
1138 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1139         .atomic_check = vc4_hdmi_encoder_atomic_check,
1140         .mode_valid = vc4_hdmi_encoder_mode_valid,
1141         .disable = vc4_hdmi_encoder_disable,
1142         .enable = vc4_hdmi_encoder_enable,
1143 };
1144
1145 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1146 {
1147         int i;
1148         u32 channel_map = 0;
1149
1150         for (i = 0; i < 8; i++) {
1151                 if (channel_mask & BIT(i))
1152                         channel_map |= i << (3 * i);
1153         }
1154         return channel_map;
1155 }
1156
1157 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1158 {
1159         int i;
1160         u32 channel_map = 0;
1161
1162         for (i = 0; i < 8; i++) {
1163                 if (channel_mask & BIT(i))
1164                         channel_map |= i << (4 * i);
1165         }
1166         return channel_map;
1167 }
1168
1169 /* HDMI audio codec callbacks */
1170 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1171                                          unsigned int samplerate)
1172 {
1173         u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1174         unsigned long n, m;
1175
1176         rational_best_approximation(hsm_clock, samplerate,
1177                                     VC4_HD_MAI_SMP_N_MASK >>
1178                                     VC4_HD_MAI_SMP_N_SHIFT,
1179                                     (VC4_HD_MAI_SMP_M_MASK >>
1180                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
1181                                     &n, &m);
1182
1183         HDMI_WRITE(HDMI_MAI_SMP,
1184                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1185                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1186 }
1187
1188 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1189 {
1190         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1191         struct drm_crtc *crtc = encoder->crtc;
1192         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1193         u32 n, cts;
1194         u64 tmp;
1195
1196         n = 128 * samplerate / 1000;
1197         tmp = (u64)(mode->clock * 1000) * n;
1198         do_div(tmp, 128 * samplerate);
1199         cts = tmp;
1200
1201         HDMI_WRITE(HDMI_CRP_CFG,
1202                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1203                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1204
1205         /*
1206          * We could get slightly more accurate clocks in some cases by
1207          * providing a CTS_1 value.  The two CTS values are alternated
1208          * between based on the period fields
1209          */
1210         HDMI_WRITE(HDMI_CTS_0, cts);
1211         HDMI_WRITE(HDMI_CTS_1, cts);
1212 }
1213
1214 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1215 {
1216         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1217
1218         return snd_soc_card_get_drvdata(card);
1219 }
1220
1221 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1222 {
1223         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1224         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1225
1226         /*
1227          * If the HDMI encoder hasn't probed, or the encoder is
1228          * currently in DVI mode, treat the codec dai as missing.
1229          */
1230         if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1231                                 VC4_HDMI_RAM_PACKET_ENABLE))
1232                 return -ENODEV;
1233
1234         vc4_hdmi->audio.streaming = true;
1235
1236         HDMI_WRITE(HDMI_MAI_CTL,
1237                    VC4_HD_MAI_CTL_RESET |
1238                    VC4_HD_MAI_CTL_FLUSH |
1239                    VC4_HD_MAI_CTL_DLATE |
1240                    VC4_HD_MAI_CTL_ERRORE |
1241                    VC4_HD_MAI_CTL_ERRORF);
1242
1243         if (vc4_hdmi->variant->phy_rng_enable)
1244                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1245
1246         return 0;
1247 }
1248
1249 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1250 {
1251         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1252         struct device *dev = &vc4_hdmi->pdev->dev;
1253         int ret;
1254
1255         vc4_hdmi->audio.streaming = false;
1256         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1257         if (ret)
1258                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1259
1260         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1261         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1262         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1263 }
1264
1265 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1266 {
1267         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1268
1269         HDMI_WRITE(HDMI_MAI_CTL,
1270                    VC4_HD_MAI_CTL_DLATE |
1271                    VC4_HD_MAI_CTL_ERRORE |
1272                    VC4_HD_MAI_CTL_ERRORF);
1273
1274         if (vc4_hdmi->variant->phy_rng_disable)
1275                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1276
1277         vc4_hdmi->audio.streaming = false;
1278         vc4_hdmi_audio_reset(vc4_hdmi);
1279 }
1280
1281 static int sample_rate_to_mai_fmt(int samplerate)
1282 {
1283         switch (samplerate) {
1284         case 8000:
1285                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1286         case 11025:
1287                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1288         case 12000:
1289                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1290         case 16000:
1291                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1292         case 22050:
1293                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1294         case 24000:
1295                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1296         case 32000:
1297                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1298         case 44100:
1299                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1300         case 48000:
1301                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1302         case 64000:
1303                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
1304         case 88200:
1305                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
1306         case 96000:
1307                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
1308         case 128000:
1309                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
1310         case 176400:
1311                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
1312         case 192000:
1313                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
1314         default:
1315                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
1316         }
1317 }
1318
1319 /* HDMI audio codec callbacks */
1320 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
1321                                   struct hdmi_codec_daifmt *daifmt,
1322                                   struct hdmi_codec_params *params)
1323 {
1324         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1325         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1326         unsigned int sample_rate = params->sample_rate;
1327         unsigned int channels = params->channels;
1328         u32 audio_packet_config, channel_mask;
1329         u32 channel_map;
1330         u32 mai_audio_format;
1331         u32 mai_sample_rate;
1332
1333         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1334                 sample_rate, params->sample_width, channels);
1335
1336         HDMI_WRITE(HDMI_MAI_CTL,
1337                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
1338                    VC4_HD_MAI_CTL_WHOLSMP |
1339                    VC4_HD_MAI_CTL_CHALIGN |
1340                    VC4_HD_MAI_CTL_ENABLE);
1341
1342         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
1343
1344         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
1345         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
1346             params->channels == 8)
1347                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
1348         else
1349                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
1350         HDMI_WRITE(HDMI_MAI_FMT,
1351                    VC4_SET_FIELD(mai_sample_rate,
1352                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
1353                    VC4_SET_FIELD(mai_audio_format,
1354                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
1355
1356         /* The B frame identifier should match the value used by alsa-lib (8) */
1357         audio_packet_config =
1358                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1359                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1360                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1361
1362         channel_mask = GENMASK(channels - 1, 0);
1363         audio_packet_config |= VC4_SET_FIELD(channel_mask,
1364                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1365
1366         /* Set the MAI threshold */
1367         HDMI_WRITE(HDMI_MAI_THR,
1368                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1369                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1370                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1371                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1372
1373         HDMI_WRITE(HDMI_MAI_CONFIG,
1374                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1375                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
1376                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1377
1378         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1379         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1380         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1381         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
1382
1383         memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
1384         vc4_hdmi_set_audio_infoframe(encoder);
1385
1386         return 0;
1387 }
1388
1389 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1390         .name = "vc4-hdmi-cpu-dai-component",
1391 };
1392
1393 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1394 {
1395         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1396
1397         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1398
1399         return 0;
1400 }
1401
1402 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1403         .name = "vc4-hdmi-cpu-dai",
1404         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1405         .playback = {
1406                 .stream_name = "Playback",
1407                 .channels_min = 1,
1408                 .channels_max = 8,
1409                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1410                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1411                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1412                          SNDRV_PCM_RATE_192000,
1413                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1414         },
1415 };
1416
1417 static const struct snd_dmaengine_pcm_config pcm_conf = {
1418         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1419         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1420 };
1421
1422 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
1423                                   uint8_t *buf, size_t len)
1424 {
1425         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1426         struct drm_connector *connector = &vc4_hdmi->connector;
1427
1428         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1429
1430         return 0;
1431 }
1432
1433 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
1434         .get_eld = vc4_hdmi_audio_get_eld,
1435         .prepare = vc4_hdmi_audio_prepare,
1436         .audio_shutdown = vc4_hdmi_audio_shutdown,
1437         .audio_startup = vc4_hdmi_audio_startup,
1438 };
1439
1440 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
1441         .ops = &vc4_hdmi_codec_ops,
1442         .max_i2s_channels = 8,
1443         .i2s = 1,
1444 };
1445
1446 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1447 {
1448         const struct vc4_hdmi_register *mai_data =
1449                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1450         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1451         struct snd_soc_card *card = &vc4_hdmi->audio.card;
1452         struct device *dev = &vc4_hdmi->pdev->dev;
1453         struct platform_device *codec_pdev;
1454         const __be32 *addr;
1455         int index;
1456         int ret;
1457
1458         if (!of_find_property(dev->of_node, "dmas", NULL)) {
1459                 dev_warn(dev,
1460                          "'dmas' DT property is missing, no HDMI audio\n");
1461                 return 0;
1462         }
1463
1464         if (mai_data->reg != VC4_HD) {
1465                 WARN_ONCE(true, "MAI isn't in the HD block\n");
1466                 return -EINVAL;
1467         }
1468
1469         /*
1470          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1471          * the bus address specified in the DT, because the physical address
1472          * (the one returned by platform_get_resource()) is not appropriate
1473          * for DMA transfers.
1474          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1475          */
1476         index = of_property_match_string(dev->of_node, "reg-names", "hd");
1477         /* Before BCM2711, we don't have a named register range */
1478         if (index < 0)
1479                 index = 1;
1480
1481         addr = of_get_address(dev->of_node, index, NULL, NULL);
1482
1483         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1484         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1485         vc4_hdmi->audio.dma_data.maxburst = 2;
1486
1487         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1488         if (ret) {
1489                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1490                 return ret;
1491         }
1492
1493         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1494                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1495         if (ret) {
1496                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1497                 return ret;
1498         }
1499
1500         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1501                                                    PLATFORM_DEVID_AUTO,
1502                                                    &vc4_hdmi_codec_pdata,
1503                                                    sizeof(vc4_hdmi_codec_pdata));
1504         if (IS_ERR(codec_pdev)) {
1505                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
1506                 return PTR_ERR(codec_pdev);
1507         }
1508
1509         dai_link->cpus          = &vc4_hdmi->audio.cpu;
1510         dai_link->codecs        = &vc4_hdmi->audio.codec;
1511         dai_link->platforms     = &vc4_hdmi->audio.platform;
1512
1513         dai_link->num_cpus      = 1;
1514         dai_link->num_codecs    = 1;
1515         dai_link->num_platforms = 1;
1516
1517         dai_link->name = "MAI";
1518         dai_link->stream_name = "MAI PCM";
1519         dai_link->codecs->dai_name = "i2s-hifi";
1520         dai_link->cpus->dai_name = dev_name(dev);
1521         dai_link->codecs->name = dev_name(&codec_pdev->dev);
1522         dai_link->platforms->name = dev_name(dev);
1523
1524         card->dai_link = dai_link;
1525         card->num_links = 1;
1526         card->name = vc4_hdmi->variant->card_name;
1527         card->driver_name = "vc4-hdmi";
1528         card->dev = dev;
1529         card->owner = THIS_MODULE;
1530
1531         /*
1532          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1533          * stores a pointer to the snd card object in dev->driver_data. This
1534          * means we cannot use it for something else. The hdmi back-pointer is
1535          * now stored in card->drvdata and should be retrieved with
1536          * snd_soc_card_get_drvdata() if needed.
1537          */
1538         snd_soc_card_set_drvdata(card, vc4_hdmi);
1539         ret = devm_snd_soc_register_card(dev, card);
1540         if (ret)
1541                 dev_err_probe(dev, ret, "Could not register sound card\n");
1542
1543         return ret;
1544
1545 }
1546
1547 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
1548 {
1549         struct vc4_hdmi *vc4_hdmi = priv;
1550         struct drm_device *dev = vc4_hdmi->connector.dev;
1551
1552         if (dev && dev->registered)
1553                 drm_kms_helper_hotplug_event(dev);
1554
1555         return IRQ_HANDLED;
1556 }
1557
1558 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
1559 {
1560         struct drm_connector *connector = &vc4_hdmi->connector;
1561         struct platform_device *pdev = vc4_hdmi->pdev;
1562         int ret;
1563
1564         if (vc4_hdmi->variant->external_irq_controller) {
1565                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
1566                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
1567
1568                 ret = request_threaded_irq(hpd_con,
1569                                            NULL,
1570                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1571                                            "vc4 hdmi hpd connected", vc4_hdmi);
1572                 if (ret)
1573                         return ret;
1574
1575                 ret = request_threaded_irq(hpd_rm,
1576                                            NULL,
1577                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1578                                            "vc4 hdmi hpd disconnected", vc4_hdmi);
1579                 if (ret) {
1580                         free_irq(hpd_con, vc4_hdmi);
1581                         return ret;
1582                 }
1583
1584                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1585         }
1586
1587         return 0;
1588 }
1589
1590 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi)
1591 {
1592         struct platform_device *pdev = vc4_hdmi->pdev;
1593
1594         if (vc4_hdmi->variant->external_irq_controller) {
1595                 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi);
1596                 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi);
1597         }
1598 }
1599
1600 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1601 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1602 {
1603         struct vc4_hdmi *vc4_hdmi = priv;
1604
1605         if (vc4_hdmi->cec_rx_msg.len)
1606                 cec_received_msg(vc4_hdmi->cec_adap,
1607                                  &vc4_hdmi->cec_rx_msg);
1608
1609         return IRQ_HANDLED;
1610 }
1611
1612 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1613 {
1614         struct vc4_hdmi *vc4_hdmi = priv;
1615
1616         if (vc4_hdmi->cec_tx_ok) {
1617                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1618                                   0, 0, 0, 0);
1619         } else {
1620                 /*
1621                  * This CEC implementation makes 1 retry, so if we
1622                  * get a NACK, then that means it made 2 attempts.
1623                  */
1624                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1625                                   0, 2, 0, 0);
1626         }
1627         return IRQ_HANDLED;
1628 }
1629
1630 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1631 {
1632         struct vc4_hdmi *vc4_hdmi = priv;
1633         irqreturn_t ret;
1634
1635         if (vc4_hdmi->cec_irq_was_rx)
1636                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1637         else
1638                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1639
1640         return ret;
1641 }
1642
1643 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1644 {
1645         struct drm_device *dev = vc4_hdmi->connector.dev;
1646         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1647         unsigned int i;
1648
1649         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1650                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1651
1652         if (msg->len > 16) {
1653                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1654                 return;
1655         }
1656
1657         for (i = 0; i < msg->len; i += 4) {
1658                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1659
1660                 msg->msg[i] = val & 0xff;
1661                 msg->msg[i + 1] = (val >> 8) & 0xff;
1662                 msg->msg[i + 2] = (val >> 16) & 0xff;
1663                 msg->msg[i + 3] = (val >> 24) & 0xff;
1664         }
1665 }
1666
1667 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1668 {
1669         struct vc4_hdmi *vc4_hdmi = priv;
1670         u32 cntrl1;
1671
1672         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1673         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1674         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1675         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1676
1677         return IRQ_WAKE_THREAD;
1678 }
1679
1680 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1681 {
1682         struct vc4_hdmi *vc4_hdmi = priv;
1683         u32 cntrl1;
1684
1685         vc4_hdmi->cec_rx_msg.len = 0;
1686         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1687         vc4_cec_read_msg(vc4_hdmi, cntrl1);
1688         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1689         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1690         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1691
1692         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1693
1694         return IRQ_WAKE_THREAD;
1695 }
1696
1697 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1698 {
1699         struct vc4_hdmi *vc4_hdmi = priv;
1700         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1701         irqreturn_t ret;
1702         u32 cntrl5;
1703
1704         if (!(stat & VC4_HDMI_CPU_CEC))
1705                 return IRQ_NONE;
1706
1707         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1708         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1709         if (vc4_hdmi->cec_irq_was_rx)
1710                 ret = vc4_cec_irq_handler_rx_bare(irq, priv);
1711         else
1712                 ret = vc4_cec_irq_handler_tx_bare(irq, priv);
1713
1714         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1715         return ret;
1716 }
1717
1718 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1719 {
1720         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1721         /* clock period in microseconds */
1722         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1723         u32 val = HDMI_READ(HDMI_CEC_CNTRL_5);
1724
1725         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1726                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1727                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1728         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1729                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1730
1731         if (enable) {
1732                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1733                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1734                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1735                 HDMI_WRITE(HDMI_CEC_CNTRL_2,
1736                            ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1737                            ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1738                            ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1739                            ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1740                            ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1741                 HDMI_WRITE(HDMI_CEC_CNTRL_3,
1742                            ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1743                            ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1744                            ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1745                            ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1746                 HDMI_WRITE(HDMI_CEC_CNTRL_4,
1747                            ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1748                            ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1749                            ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1750                            ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1751
1752                 if (!vc4_hdmi->variant->external_irq_controller)
1753                         HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1754         } else {
1755                 if (!vc4_hdmi->variant->external_irq_controller)
1756                         HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1757                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1758                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1759         }
1760         return 0;
1761 }
1762
1763 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1764 {
1765         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1766
1767         HDMI_WRITE(HDMI_CEC_CNTRL_1,
1768                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1769                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1770         return 0;
1771 }
1772
1773 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1774                                       u32 signal_free_time, struct cec_msg *msg)
1775 {
1776         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1777         struct drm_device *dev = vc4_hdmi->connector.dev;
1778         u32 val;
1779         unsigned int i;
1780
1781         if (msg->len > 16) {
1782                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
1783                 return -ENOMEM;
1784         }
1785
1786         for (i = 0; i < msg->len; i += 4)
1787                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
1788                            (msg->msg[i]) |
1789                            (msg->msg[i + 1] << 8) |
1790                            (msg->msg[i + 2] << 16) |
1791                            (msg->msg[i + 3] << 24));
1792
1793         val = HDMI_READ(HDMI_CEC_CNTRL_1);
1794         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1795         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1796         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1797         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1798         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1799
1800         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1801         return 0;
1802 }
1803
1804 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1805         .adap_enable = vc4_hdmi_cec_adap_enable,
1806         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1807         .adap_transmit = vc4_hdmi_cec_adap_transmit,
1808 };
1809
1810 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1811 {
1812         struct cec_connector_info conn_info;
1813         struct platform_device *pdev = vc4_hdmi->pdev;
1814         struct device *dev = &pdev->dev;
1815         u32 value;
1816         int ret;
1817
1818         if (!of_find_property(dev->of_node, "interrupts", NULL)) {
1819                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
1820                 return 0;
1821         }
1822
1823         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1824                                                   vc4_hdmi, "vc4",
1825                                                   CEC_CAP_DEFAULTS |
1826                                                   CEC_CAP_CONNECTOR_INFO, 1);
1827         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
1828         if (ret < 0)
1829                 return ret;
1830
1831         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
1832         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
1833
1834         value = HDMI_READ(HDMI_CEC_CNTRL_1);
1835         /* Set the logical address to Unregistered */
1836         value |= VC4_HDMI_CEC_ADDR_MASK;
1837         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
1838
1839         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1840
1841         if (vc4_hdmi->variant->external_irq_controller) {
1842                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"),
1843                                            vc4_cec_irq_handler_rx_bare,
1844                                            vc4_cec_irq_handler_rx_thread, 0,
1845                                            "vc4 hdmi cec rx", vc4_hdmi);
1846                 if (ret)
1847                         goto err_delete_cec_adap;
1848
1849                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"),
1850                                            vc4_cec_irq_handler_tx_bare,
1851                                            vc4_cec_irq_handler_tx_thread, 0,
1852                                            "vc4 hdmi cec tx", vc4_hdmi);
1853                 if (ret)
1854                         goto err_remove_cec_rx_handler;
1855         } else {
1856                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
1857
1858                 ret = request_threaded_irq(platform_get_irq(pdev, 0),
1859                                            vc4_cec_irq_handler,
1860                                            vc4_cec_irq_handler_thread, 0,
1861                                            "vc4 hdmi cec", vc4_hdmi);
1862                 if (ret)
1863                         goto err_delete_cec_adap;
1864         }
1865
1866         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
1867         if (ret < 0)
1868                 goto err_remove_handlers;
1869
1870         return 0;
1871
1872 err_remove_handlers:
1873         if (vc4_hdmi->variant->external_irq_controller)
1874                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
1875         else
1876                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
1877
1878 err_remove_cec_rx_handler:
1879         if (vc4_hdmi->variant->external_irq_controller)
1880                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
1881
1882 err_delete_cec_adap:
1883         cec_delete_adapter(vc4_hdmi->cec_adap);
1884
1885         return ret;
1886 }
1887
1888 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
1889 {
1890         struct platform_device *pdev = vc4_hdmi->pdev;
1891
1892         if (vc4_hdmi->variant->external_irq_controller) {
1893                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
1894                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
1895         } else {
1896                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
1897         }
1898
1899         cec_unregister_adapter(vc4_hdmi->cec_adap);
1900 }
1901 #else
1902 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1903 {
1904         return 0;
1905 }
1906
1907 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
1908
1909 #endif
1910
1911 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
1912                                  struct debugfs_regset32 *regset,
1913                                  enum vc4_hdmi_regs reg)
1914 {
1915         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1916         struct debugfs_reg32 *regs, *new_regs;
1917         unsigned int count = 0;
1918         unsigned int i;
1919
1920         regs = kcalloc(variant->num_registers, sizeof(*regs),
1921                        GFP_KERNEL);
1922         if (!regs)
1923                 return -ENOMEM;
1924
1925         for (i = 0; i < variant->num_registers; i++) {
1926                 const struct vc4_hdmi_register *field = &variant->registers[i];
1927
1928                 if (field->reg != reg)
1929                         continue;
1930
1931                 regs[count].name = field->name;
1932                 regs[count].offset = field->offset;
1933                 count++;
1934         }
1935
1936         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
1937         if (!new_regs)
1938                 return -ENOMEM;
1939
1940         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
1941         regset->regs = new_regs;
1942         regset->nregs = count;
1943
1944         return 0;
1945 }
1946
1947 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1948 {
1949         struct platform_device *pdev = vc4_hdmi->pdev;
1950         struct device *dev = &pdev->dev;
1951         int ret;
1952
1953         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1954         if (IS_ERR(vc4_hdmi->hdmicore_regs))
1955                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1956
1957         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1958         if (IS_ERR(vc4_hdmi->hd_regs))
1959                 return PTR_ERR(vc4_hdmi->hd_regs);
1960
1961         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
1962         if (ret)
1963                 return ret;
1964
1965         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
1966         if (ret)
1967                 return ret;
1968
1969         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1970         if (IS_ERR(vc4_hdmi->pixel_clock)) {
1971                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
1972                 if (ret != -EPROBE_DEFER)
1973                         DRM_ERROR("Failed to get pixel clock\n");
1974                 return ret;
1975         }
1976
1977         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1978         if (IS_ERR(vc4_hdmi->hsm_clock)) {
1979                 DRM_ERROR("Failed to get HDMI state machine clock\n");
1980                 return PTR_ERR(vc4_hdmi->hsm_clock);
1981         }
1982         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
1983         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
1984
1985         return 0;
1986 }
1987
1988 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1989 {
1990         struct platform_device *pdev = vc4_hdmi->pdev;
1991         struct device *dev = &pdev->dev;
1992         struct resource *res;
1993
1994         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
1995         if (!res)
1996                 return -ENODEV;
1997
1998         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
1999                                                resource_size(res));
2000         if (!vc4_hdmi->hdmicore_regs)
2001                 return -ENOMEM;
2002
2003         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2004         if (!res)
2005                 return -ENODEV;
2006
2007         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2008         if (!vc4_hdmi->hd_regs)
2009                 return -ENOMEM;
2010
2011         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2012         if (!res)
2013                 return -ENODEV;
2014
2015         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2016         if (!vc4_hdmi->cec_regs)
2017                 return -ENOMEM;
2018
2019         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2020         if (!res)
2021                 return -ENODEV;
2022
2023         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2024         if (!vc4_hdmi->csc_regs)
2025                 return -ENOMEM;
2026
2027         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2028         if (!res)
2029                 return -ENODEV;
2030
2031         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2032         if (!vc4_hdmi->dvp_regs)
2033                 return -ENOMEM;
2034
2035         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2036         if (!res)
2037                 return -ENODEV;
2038
2039         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2040         if (!vc4_hdmi->phy_regs)
2041                 return -ENOMEM;
2042
2043         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2044         if (!res)
2045                 return -ENODEV;
2046
2047         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2048         if (!vc4_hdmi->ram_regs)
2049                 return -ENOMEM;
2050
2051         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2052         if (!res)
2053                 return -ENODEV;
2054
2055         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2056         if (!vc4_hdmi->rm_regs)
2057                 return -ENOMEM;
2058
2059         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2060         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2061                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2062                 return PTR_ERR(vc4_hdmi->hsm_clock);
2063         }
2064
2065         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2066         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2067                 DRM_ERROR("Failed to get pixel bvb clock\n");
2068                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2069         }
2070
2071         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2072         if (IS_ERR(vc4_hdmi->audio_clock)) {
2073                 DRM_ERROR("Failed to get audio clock\n");
2074                 return PTR_ERR(vc4_hdmi->audio_clock);
2075         }
2076
2077         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2078         if (IS_ERR(vc4_hdmi->cec_clock)) {
2079                 DRM_ERROR("Failed to get CEC clock\n");
2080                 return PTR_ERR(vc4_hdmi->cec_clock);
2081         }
2082
2083         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2084         if (IS_ERR(vc4_hdmi->reset)) {
2085                 DRM_ERROR("Failed to get HDMI reset line\n");
2086                 return PTR_ERR(vc4_hdmi->reset);
2087         }
2088
2089         return 0;
2090 }
2091
2092 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev)
2093 {
2094         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2095
2096         clk_disable_unprepare(vc4_hdmi->hsm_clock);
2097
2098         return 0;
2099 }
2100
2101 static int vc4_hdmi_runtime_resume(struct device *dev)
2102 {
2103         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2104         int ret;
2105
2106         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
2107         if (ret)
2108                 return ret;
2109
2110         return 0;
2111 }
2112
2113 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2114 {
2115         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2116         struct platform_device *pdev = to_platform_device(dev);
2117         struct drm_device *drm = dev_get_drvdata(master);
2118         struct vc4_hdmi *vc4_hdmi;
2119         struct drm_encoder *encoder;
2120         struct device_node *ddc_node;
2121         int ret;
2122
2123         vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2124         if (!vc4_hdmi)
2125                 return -ENOMEM;
2126         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2127
2128         dev_set_drvdata(dev, vc4_hdmi);
2129         encoder = &vc4_hdmi->encoder.base.base;
2130         vc4_hdmi->encoder.base.type = variant->encoder_type;
2131         vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2132         vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2133         vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2134         vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2135         vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2136         vc4_hdmi->pdev = pdev;
2137         vc4_hdmi->variant = variant;
2138
2139         ret = variant->init_resources(vc4_hdmi);
2140         if (ret)
2141                 return ret;
2142
2143         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2144         if (!ddc_node) {
2145                 DRM_ERROR("Failed to find ddc node in device tree\n");
2146                 return -ENODEV;
2147         }
2148
2149         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2150         of_node_put(ddc_node);
2151         if (!vc4_hdmi->ddc) {
2152                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2153                 return -EPROBE_DEFER;
2154         }
2155
2156         /* Only use the GPIO HPD pin if present in the DT, otherwise
2157          * we'll use the HDMI core's register.
2158          */
2159         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2160         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
2161                 ret = PTR_ERR(vc4_hdmi->hpd_gpio);
2162                 goto err_put_ddc;
2163         }
2164
2165         vc4_hdmi->disable_wifi_frequencies =
2166                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2167
2168         if (variant->max_pixel_clock == 600000000) {
2169                 struct vc4_dev *vc4 = to_vc4_dev(drm);
2170                 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
2171
2172                 if (max_rate < 550000000)
2173                         vc4_hdmi->disable_4kp60 = true;
2174         }
2175
2176         /*
2177          * If we boot without any cable connected to the HDMI connector,
2178          * the firmware will skip the HSM initialization and leave it
2179          * with a rate of 0, resulting in a bus lockup when we're
2180          * accessing the registers even if it's enabled.
2181          *
2182          * Let's put a sensible default at runtime_resume so that we
2183          * don't end up in this situation.
2184          */
2185         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
2186         if (ret)
2187                 goto err_put_ddc;
2188
2189         if (vc4_hdmi->variant->reset)
2190                 vc4_hdmi->variant->reset(vc4_hdmi);
2191
2192         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
2193              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
2194             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
2195                 clk_prepare_enable(vc4_hdmi->pixel_clock);
2196                 clk_prepare_enable(vc4_hdmi->hsm_clock);
2197                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
2198         }
2199
2200         pm_runtime_enable(dev);
2201
2202         drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2203         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2204
2205         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2206         if (ret)
2207                 goto err_destroy_encoder;
2208
2209         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
2210         if (ret)
2211                 goto err_destroy_conn;
2212
2213         ret = vc4_hdmi_cec_init(vc4_hdmi);
2214         if (ret)
2215                 goto err_free_hotplug;
2216
2217         ret = vc4_hdmi_audio_init(vc4_hdmi);
2218         if (ret)
2219                 goto err_free_cec;
2220
2221         vc4_debugfs_add_file(drm, variant->debugfs_name,
2222                              vc4_hdmi_debugfs_regs,
2223                              vc4_hdmi);
2224
2225         return 0;
2226
2227 err_free_cec:
2228         vc4_hdmi_cec_exit(vc4_hdmi);
2229 err_free_hotplug:
2230         vc4_hdmi_hotplug_exit(vc4_hdmi);
2231 err_destroy_conn:
2232         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2233 err_destroy_encoder:
2234         drm_encoder_cleanup(encoder);
2235         pm_runtime_disable(dev);
2236 err_put_ddc:
2237         put_device(&vc4_hdmi->ddc->dev);
2238
2239         return ret;
2240 }
2241
2242 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2243                             void *data)
2244 {
2245         struct vc4_hdmi *vc4_hdmi;
2246
2247         /*
2248          * ASoC makes it a bit hard to retrieve a pointer to the
2249          * vc4_hdmi structure. Registering the card will overwrite our
2250          * device drvdata with a pointer to the snd_soc_card structure,
2251          * which can then be used to retrieve whatever drvdata we want
2252          * to associate.
2253          *
2254          * However, that doesn't fly in the case where we wouldn't
2255          * register an ASoC card (because of an old DT that is missing
2256          * the dmas properties for example), then the card isn't
2257          * registered and the device drvdata wouldn't be set.
2258          *
2259          * We can deal with both cases by making sure a snd_soc_card
2260          * pointer and a vc4_hdmi structure are pointing to the same
2261          * memory address, so we can treat them indistinctly without any
2262          * issue.
2263          */
2264         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2265         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2266         vc4_hdmi = dev_get_drvdata(dev);
2267
2268         kfree(vc4_hdmi->hdmi_regset.regs);
2269         kfree(vc4_hdmi->hd_regset.regs);
2270
2271         vc4_hdmi_cec_exit(vc4_hdmi);
2272         vc4_hdmi_hotplug_exit(vc4_hdmi);
2273         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2274         drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2275
2276         pm_runtime_disable(dev);
2277
2278         put_device(&vc4_hdmi->ddc->dev);
2279 }
2280
2281 static const struct component_ops vc4_hdmi_ops = {
2282         .bind   = vc4_hdmi_bind,
2283         .unbind = vc4_hdmi_unbind,
2284 };
2285
2286 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2287 {
2288         return component_add(&pdev->dev, &vc4_hdmi_ops);
2289 }
2290
2291 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2292 {
2293         component_del(&pdev->dev, &vc4_hdmi_ops);
2294         return 0;
2295 }
2296
2297 static const struct vc4_hdmi_variant bcm2835_variant = {
2298         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2299         .debugfs_name           = "hdmi_regs",
2300         .card_name              = "vc4-hdmi",
2301         .max_pixel_clock        = 162000000,
2302         .registers              = vc4_hdmi_fields,
2303         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
2304
2305         .init_resources         = vc4_hdmi_init_resources,
2306         .csc_setup              = vc4_hdmi_csc_setup,
2307         .reset                  = vc4_hdmi_reset,
2308         .set_timings            = vc4_hdmi_set_timings,
2309         .phy_init               = vc4_hdmi_phy_init,
2310         .phy_disable            = vc4_hdmi_phy_disable,
2311         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
2312         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
2313         .channel_map            = vc4_hdmi_channel_map,
2314         .supports_hdr           = false,
2315 };
2316
2317 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2318         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2319         .debugfs_name           = "hdmi0_regs",
2320         .card_name              = "vc4-hdmi-0",
2321         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2322         .registers              = vc5_hdmi_hdmi0_fields,
2323         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2324         .phy_lane_mapping       = {
2325                 PHY_LANE_0,
2326                 PHY_LANE_1,
2327                 PHY_LANE_2,
2328                 PHY_LANE_CK,
2329         },
2330         .unsupported_odd_h_timings      = true,
2331         .external_irq_controller        = true,
2332
2333         .init_resources         = vc5_hdmi_init_resources,
2334         .csc_setup              = vc5_hdmi_csc_setup,
2335         .reset                  = vc5_hdmi_reset,
2336         .set_timings            = vc5_hdmi_set_timings,
2337         .phy_init               = vc5_hdmi_phy_init,
2338         .phy_disable            = vc5_hdmi_phy_disable,
2339         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2340         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2341         .channel_map            = vc5_hdmi_channel_map,
2342         .supports_hdr           = true,
2343 };
2344
2345 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2346         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
2347         .debugfs_name           = "hdmi1_regs",
2348         .card_name              = "vc4-hdmi-1",
2349         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2350         .registers              = vc5_hdmi_hdmi1_fields,
2351         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2352         .phy_lane_mapping       = {
2353                 PHY_LANE_1,
2354                 PHY_LANE_0,
2355                 PHY_LANE_CK,
2356                 PHY_LANE_2,
2357         },
2358         .unsupported_odd_h_timings      = true,
2359         .external_irq_controller        = true,
2360
2361         .init_resources         = vc5_hdmi_init_resources,
2362         .csc_setup              = vc5_hdmi_csc_setup,
2363         .reset                  = vc5_hdmi_reset,
2364         .set_timings            = vc5_hdmi_set_timings,
2365         .phy_init               = vc5_hdmi_phy_init,
2366         .phy_disable            = vc5_hdmi_phy_disable,
2367         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2368         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2369         .channel_map            = vc5_hdmi_channel_map,
2370         .supports_hdr           = true,
2371 };
2372
2373 static const struct of_device_id vc4_hdmi_dt_match[] = {
2374         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2375         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2376         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2377         {}
2378 };
2379
2380 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
2381         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
2382                            vc4_hdmi_runtime_resume,
2383                            NULL)
2384 };
2385
2386 struct platform_driver vc4_hdmi_driver = {
2387         .probe = vc4_hdmi_dev_probe,
2388         .remove = vc4_hdmi_dev_remove,
2389         .driver = {
2390                 .name = "vc4_hdmi",
2391                 .of_match_table = vc4_hdmi_dt_match,
2392                 .pm = &vc4_hdmi_pm_ops,
2393         },
2394 };