drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_drv.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_probe_helper.h>
  38 #include <drm/drm_simple_kms_helper.h>
  39 #include <drm/drm_scdc_helper.h>
  40 #include <linux/clk.h>
  41 #include <linux/component.h>
  42 #include <linux/gpio/consumer.h>
  43 #include <linux/i2c.h>
  44 #include <linux/module.h>
  45 #include <linux/moduleparam.h>
  46 #include <linux/of_address.h>
  47 #include <linux/of_gpio.h>
  48 #include <linux/of_platform.h>
  49 #include <linux/pm_runtime.h>
  50 #include <linux/rational.h>
  51 #include <linux/reset.h>
  52 #include <sound/dmaengine_pcm.h>
  53 #include <sound/hdmi-codec.h>
  54 #include <sound/pcm_drm_eld.h>
  55 #include <sound/pcm_params.h>
  56 #include <sound/soc.h>
  57 #include "media/cec.h"
  58 #include "vc4_drv.h"
  59 #include "vc4_hdmi.h"
  60 #include "vc4_hdmi_regs.h"
  61 #include "vc4_regs.h"
  62
  63 /*
  64  * "Broadcast RGB" property.
  65  * Allows overriding of HDMI full or limited range RGB
  66  */
  67 #define VC4_BROADCAST_RGB_AUTO 0
  68 #define VC4_BROADCAST_RGB_FULL 1
  69 #define VC4_BROADCAST_RGB_LIMITED 2
  70
  71 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  72 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  73 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  74 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  75 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  76 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  77
  78 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  79 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  80 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  81 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  82
  83 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  84 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  85 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  86 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  87 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  88 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  89
  90 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  91 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  92
  93 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  94 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  95 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  96 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  97
  98 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  99
 100 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
 101 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
 102
 103 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
 104 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
 105
 106 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
 107
 108 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
 109 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
 110
 111 # define VC4_HD_M_SW_RST                        BIT(2)
 112 # define VC4_HD_M_ENABLE                        BIT(0)
 113
 114 #define HSM_MIN_CLOCK_FREQ      120000000
 115 #define CEC_CLOCK_FREQ 40000
 116
 117 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 118
 119 /* bit field to force hotplug detection. bit0 = HDMI0 */
 120 static int force_hotplug = 0;
 121 module_param(force_hotplug, int, 0644);
 122
 123 static const char * const output_format_str[] = {
 124         [VC4_HDMI_OUTPUT_RGB]           = "RGB",
 125         [VC4_HDMI_OUTPUT_YUV420]        = "YUV 4:2:0",
 126         [VC4_HDMI_OUTPUT_YUV422]        = "YUV 4:2:2",
 127         [VC4_HDMI_OUTPUT_YUV444]        = "YUV 4:4:4",
 128 };
 129
 130 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt)
 131 {
 132         if (fmt >= ARRAY_SIZE(output_format_str))
 133                 return "invalid";
 134
 135         return output_format_str[fmt];
 136 }
 137
 138 static unsigned long long
 139 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
 140                                     unsigned int bpc, enum vc4_hdmi_output_format fmt);
 141
 142 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
 143                                            unsigned int bpc,
 144                                            enum vc4_hdmi_output_format fmt)
 145 {
 146         unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
 147
 148         return clock > HDMI_14_MAX_TMDS_CLK;
 149 }
 150
 151 static bool vc4_hdmi_is_full_range(struct vc4_hdmi *vc4_hdmi,
 152                                    const struct drm_display_mode *mode)
 153 {
 154         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 155
 156         if (vc4_hdmi->broadcast_rgb == VC4_BROADCAST_RGB_LIMITED)
 157                 return false;
 158         else if (vc4_hdmi->broadcast_rgb == VC4_BROADCAST_RGB_FULL)
 159                 return true;
 160         return !vc4_encoder->hdmi_monitor ||
 161                 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
 162 }
 163
 164 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 165 {
 166         struct drm_info_node *node = (struct drm_info_node *)m->private;
 167         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
 168         struct drm_device *drm = vc4_hdmi->connector.dev;
 169         struct drm_printer p = drm_seq_file_printer(m);
 170         int idx;
 171
 172         if (!drm_dev_enter(drm, &idx))
 173                 return -ENODEV;
 174
 175         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 176         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 177         drm_print_regset32(&p, &vc4_hdmi->cec_regset);
 178         drm_print_regset32(&p, &vc4_hdmi->csc_regset);
 179         drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
 180         drm_print_regset32(&p, &vc4_hdmi->phy_regset);
 181         drm_print_regset32(&p, &vc4_hdmi->ram_regset);
 182         drm_print_regset32(&p, &vc4_hdmi->rm_regset);
 183
 184         drm_dev_exit(idx);
 185
 186         return 0;
 187 }
 188
 189 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 190 {
 191         struct drm_device *drm = vc4_hdmi->connector.dev;
 192         unsigned long flags;
 193         int idx;
 194
 195         /*
 196          * We can be called by our bind callback, when the
 197          * connector->dev pointer might not be initialised yet.
 198          */
 199         if (drm && !drm_dev_enter(drm, &idx))
 200                 return;
 201
 202         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 203
 204         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 205         udelay(1);
 206         HDMI_WRITE(HDMI_M_CTL, 0);
 207
 208         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 209
 210         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 211                    VC4_HDMI_SW_RESET_HDMI |
 212                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 213
 214         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 215
 216         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 217
 218         if (drm)
 219                 drm_dev_exit(idx);
 220 }
 221
 222 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 223 {
 224         struct drm_device *drm = vc4_hdmi->connector.dev;
 225         unsigned long flags;
 226         int idx;
 227
 228         /*
 229          * We can be called by our bind callback, when the
 230          * connector->dev pointer might not be initialised yet.
 231          */
 232         if (drm && !drm_dev_enter(drm, &idx))
 233                 return;
 234
 235         reset_control_reset(vc4_hdmi->reset);
 236
 237         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 238
 239         HDMI_WRITE(HDMI_DVP_CTL, 0);
 240
 241         HDMI_WRITE(HDMI_CLOCK_STOP,
 242                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 243
 244         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 245
 246         if (drm)
 247                 drm_dev_exit(idx);
 248 }
 249
 250 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 251 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 252 {
 253         struct drm_device *drm = vc4_hdmi->connector.dev;
 254         unsigned long cec_rate;
 255         unsigned long flags;
 256         u16 clk_cnt;
 257         u32 value;
 258         int idx;
 259
 260         /*
 261          * This function is called by our runtime_resume implementation
 262          * and thus at bind time, when we haven't registered our
 263          * connector yet and thus don't have a pointer to the DRM
 264          * device.
 265          */
 266         if (drm && !drm_dev_enter(drm, &idx))
 267                 return;
 268
 269         cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
 270
 271         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 272
 273         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 274         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 275
 276         /*
 277          * Set the clock divider: the hsm_clock rate and this divider
 278          * setting will give a 40 kHz CEC clock.
 279          */
 280         clk_cnt = cec_rate / CEC_CLOCK_FREQ;
 281         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 282         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 283
 284         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 285
 286         if (drm)
 287                 drm_dev_exit(idx);
 288 }
 289 #else
 290 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 291 #endif
 292
 293 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder);
 294
 295 static enum drm_connector_status
 296 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 297 {
 298         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 299         bool connected = false;
 300
 301         mutex_lock(&vc4_hdmi->mutex);
 302
 303         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 304
 305         if (force_hotplug & BIT(vc4_hdmi->encoder.base.type - VC4_ENCODER_TYPE_HDMI0))
 306                 connected = true;
 307         else if (vc4_hdmi->hpd_gpio) {
 308                 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
 309                         connected = true;
 310         } else {
 311                 if (vc4_hdmi->variant->hp_detect &&
 312                     vc4_hdmi->variant->hp_detect(vc4_hdmi))
 313                         connected = true;
 314         }
 315
 316         if (connected) {
 317                 if (connector->status != connector_status_connected) {
 318                         struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
 319
 320                         if (edid) {
 321                                 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 322                                 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
 323                                 kfree(edid);
 324                         } else {
 325                                 vc4_hdmi->encoder.hdmi_monitor = false;
 326                         }
 327                 }
 328
 329                 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base);
 330                 pm_runtime_put(&vc4_hdmi->pdev->dev);
 331                 mutex_unlock(&vc4_hdmi->mutex);
 332                 return connector_status_connected;
 333         }
 334
 335         vc4_hdmi->encoder.hdmi_monitor = false;
 336
 337         cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 338         pm_runtime_put(&vc4_hdmi->pdev->dev);
 339         mutex_unlock(&vc4_hdmi->mutex);
 340         return connector_status_disconnected;
 341 }
 342
 343 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 344 {
 345         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 346         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 347         struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
 348         int ret = 0;
 349         struct edid *edid;
 350
 351         mutex_lock(&vc4_hdmi->mutex);
 352
 353         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 354         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 355         if (!edid) {
 356                 ret = -ENODEV;
 357                 goto out;
 358         }
 359
 360         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 361
 362         drm_connector_update_edid_property(connector, edid);
 363         ret = drm_add_edid_modes(connector, edid);
 364         kfree(edid);
 365
 366         if (!vc4->hvs->vc5_hdmi_enable_scrambling) {
 367                 struct drm_device *drm = connector->dev;
 368                 struct drm_display_mode *mode;
 369
 370                 list_for_each_entry(mode, &connector->probed_modes, head) {
 371                         if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) {
 372                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 373                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 374                         }
 375                 }
 376         }
 377
 378 out:
 379         mutex_unlock(&vc4_hdmi->mutex);
 380
 381         return ret;
 382 }
 383
 384 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 385                                            struct drm_atomic_state *state)
 386 {
 387         struct drm_connector_state *old_state =
 388                 drm_atomic_get_old_connector_state(state, connector);
 389         struct vc4_hdmi_connector_state *old_vc4_state = conn_state_to_vc4_hdmi_conn_state(old_state);
 390         struct drm_connector_state *new_state =
 391                 drm_atomic_get_new_connector_state(state, connector);
 392         struct vc4_hdmi_connector_state *new_vc4_state = conn_state_to_vc4_hdmi_conn_state(new_state);
 393         struct drm_crtc *crtc = new_state->crtc;
 394
 395         if (!crtc)
 396                 return 0;
 397
 398         if (old_state->colorspace != new_state->colorspace ||
 399             old_vc4_state->broadcast_rgb != new_vc4_state->broadcast_rgb ||
 400             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 401                 struct drm_crtc_state *crtc_state;
 402
 403                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 404                 if (IS_ERR(crtc_state))
 405                         return PTR_ERR(crtc_state);
 406
 407                 crtc_state->mode_changed = true;
 408         }
 409
 410         return 0;
 411 }
 412
 413 /**
 414  * vc4_hdmi_connector_atomic_get_property - hook for
 415  *                                              connector->atomic_get_property.
 416  * @connector: Connector to get the property for.
 417  * @state: Connector state to retrieve the property from.
 418  * @property: Property to retrieve.
 419  * @val: Return value for the property.
 420  *
 421  * Returns the atomic property value for a digital connector.
 422  */
 423 int vc4_hdmi_connector_get_property(struct drm_connector *connector,
 424                                     const struct drm_connector_state *state,
 425                                     struct drm_property *property,
 426                                     uint64_t *val)
 427 {
 428         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 429         const struct vc4_hdmi_connector_state *vc4_conn_state =
 430                                 const_conn_state_to_vc4_hdmi_conn_state(state);
 431
 432         if (property == vc4_hdmi->broadcast_rgb_property) {
 433                 *val = vc4_conn_state->broadcast_rgb;
 434         } else {
 435                 DRM_DEBUG_ATOMIC("Unknown property [PROP:%d:%s]\n",
 436                                  property->base.id, property->name);
 437                 return -EINVAL;
 438         }
 439
 440         return 0;
 441 }
 442
 443 /**
 444  * vc4_hdmi_connector_atomic_set_property - hook for
 445  *                                              connector->atomic_set_property.
 446  * @connector: Connector to set the property for.
 447  * @state: Connector state to set the property on.
 448  * @property: Property to set.
 449  * @val: New value for the property.
 450  *
 451  * Sets the atomic property value for a digital connector.
 452  */
 453 int vc4_hdmi_connector_set_property(struct drm_connector *connector,
 454                                     struct drm_connector_state *state,
 455                                     struct drm_property *property,
 456                                     uint64_t val)
 457 {
 458         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 459         struct vc4_hdmi_connector_state *vc4_conn_state =
 460                                 conn_state_to_vc4_hdmi_conn_state(state);
 461
 462         if (property == vc4_hdmi->broadcast_rgb_property) {
 463                 vc4_conn_state->broadcast_rgb = val;
 464                 return 0;
 465         }
 466
 467         DRM_DEBUG_ATOMIC("Unknown property [PROP:%d:%s]\n",
 468                          property->base.id, property->name);
 469         return -EINVAL;
 470 }
 471
 472 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 473 {
 474         struct vc4_hdmi_connector_state *old_state =
 475                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 476         struct vc4_hdmi_connector_state *new_state =
 477                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 478
 479         if (connector->state)
 480                 __drm_atomic_helper_connector_destroy_state(connector->state);
 481
 482         kfree(old_state);
 483         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 484
 485         if (!new_state)
 486                 return;
 487
 488         new_state->base.max_bpc = 8;
 489         new_state->base.max_requested_bpc = 8;
 490         new_state->output_format = VC4_HDMI_OUTPUT_RGB;
 491         drm_atomic_helper_connector_tv_reset(connector);
 492 }
 493
 494 static struct drm_connector_state *
 495 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 496 {
 497         struct drm_connector_state *conn_state = connector->state;
 498         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 499         struct vc4_hdmi_connector_state *new_state;
 500
 501         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 502         if (!new_state)
 503                 return NULL;
 504
 505         new_state->pixel_rate = vc4_state->pixel_rate;
 506         new_state->output_bpc = vc4_state->output_bpc;
 507         new_state->output_format = vc4_state->output_format;
 508         new_state->broadcast_rgb = vc4_state->broadcast_rgb;
 509         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 510
 511         return &new_state->base;
 512 }
 513
 514 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 515         .detect = vc4_hdmi_connector_detect,
 516         .fill_modes = drm_helper_probe_single_connector_modes,
 517         .reset = vc4_hdmi_connector_reset,
 518         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 519         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 520         .atomic_get_property = vc4_hdmi_connector_get_property,
 521         .atomic_set_property = vc4_hdmi_connector_set_property,
 522 };
 523
 524 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 525         .get_modes = vc4_hdmi_connector_get_modes,
 526         .atomic_check = vc4_hdmi_connector_atomic_check,
 527 };
 528
 529 static const struct drm_prop_enum_list broadcast_rgb_names[] = {
 530         { VC4_BROADCAST_RGB_AUTO, "Automatic" },
 531         { VC4_BROADCAST_RGB_FULL, "Full" },
 532         { VC4_BROADCAST_RGB_LIMITED, "Limited 16:235" },
 533 };
 534
 535 static void
 536 vc4_hdmi_attach_broadcast_rgb_property(struct drm_device *dev,
 537                                        struct vc4_hdmi *vc4_hdmi)
 538 {
 539         struct drm_property *prop = vc4_hdmi->broadcast_rgb_property;
 540
 541         if (!prop) {
 542                 prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
 543                                                 "Broadcast RGB",
 544                                                 broadcast_rgb_names,
 545                                                 ARRAY_SIZE(broadcast_rgb_names));
 546                 if (!prop)
 547                         return;
 548
 549                 vc4_hdmi->broadcast_rgb_property = prop;
 550         }
 551
 552         drm_object_attach_property(&vc4_hdmi->connector.base, prop, 0);
 553 }
 554
 555 static int vc4_hdmi_connector_init(struct drm_device *dev,
 556                                    struct vc4_hdmi *vc4_hdmi)
 557 {
 558         struct drm_connector *connector = &vc4_hdmi->connector;
 559         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 560         int ret;
 561
 562         ret = drmm_connector_init(dev, connector,
 563                                   &vc4_hdmi_connector_funcs,
 564                                   DRM_MODE_CONNECTOR_HDMIA,
 565                                   vc4_hdmi->ddc);
 566         if (ret)
 567                 return ret;
 568
 569         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 570
 571         /*
 572          * Some of the properties below require access to state, like bpc.
 573          * Allocate some default initial connector state with our reset helper.
 574          */
 575         if (connector->funcs->reset)
 576                 connector->funcs->reset(connector);
 577
 578         /* Create and attach TV margin props to this connector. */
 579         ret = drm_mode_create_tv_margin_properties(dev);
 580         if (ret)
 581                 return ret;
 582
 583         ret = drm_mode_create_hdmi_colorspace_property(connector);
 584         if (ret)
 585                 return ret;
 586
 587         drm_connector_attach_colorspace_property(connector);
 588         drm_connector_attach_tv_margin_properties(connector);
 589         drm_connector_attach_max_bpc_property(connector, 8, 12);
 590
 591         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 592                              DRM_CONNECTOR_POLL_DISCONNECT);
 593
 594         connector->interlace_allowed = 1;
 595         connector->doublescan_allowed = 0;
 596         connector->stereo_allowed = 1;
 597
 598         if (vc4_hdmi->variant->supports_hdr)
 599                 drm_connector_attach_hdr_output_metadata_property(connector);
 600
 601         vc4_hdmi_attach_broadcast_rgb_property(dev, vc4_hdmi);
 602
 603         drm_connector_attach_encoder(connector, encoder);
 604
 605         return 0;
 606 }
 607
 608 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 609                                 enum hdmi_infoframe_type type,
 610                                 bool poll)
 611 {
 612         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 613         struct drm_device *drm = vc4_hdmi->connector.dev;
 614         u32 packet_id = type - 0x80;
 615         unsigned long flags;
 616         int ret = 0;
 617         int idx;
 618
 619         if (!drm_dev_enter(drm, &idx))
 620                 return -ENODEV;
 621
 622         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 623         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 624                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 625         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 626
 627         if (poll) {
 628                 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 629                                  BIT(packet_id)), 100);
 630         }
 631
 632         drm_dev_exit(idx);
 633         return ret;
 634 }
 635
 636 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 637                                      union hdmi_infoframe *frame)
 638 {
 639         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 640         struct drm_device *drm = vc4_hdmi->connector.dev;
 641         u32 packet_id = frame->any.type - 0x80;
 642         const struct vc4_hdmi_register *ram_packet_start =
 643                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 644         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 645         u32 packet_reg_next = ram_packet_start->offset +
 646                 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
 647         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 648                                                        ram_packet_start->reg);
 649         uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
 650         unsigned long flags;
 651         ssize_t len, i;
 652         int ret;
 653         int idx;
 654
 655         if (!drm_dev_enter(drm, &idx))
 656                 return;
 657
 658         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 659                     VC4_HDMI_RAM_PACKET_ENABLE),
 660                   "Packet RAM has to be on to store the packet.");
 661
 662         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 663         if (len < 0)
 664                 goto out;
 665
 666         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 667         if (ret) {
 668                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 669                 goto out;
 670         }
 671
 672         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 673
 674         for (i = 0; i < len; i += 7) {
 675                 writel(buffer[i + 0] << 0 |
 676                        buffer[i + 1] << 8 |
 677                        buffer[i + 2] << 16,
 678                        base + packet_reg);
 679                 packet_reg += 4;
 680
 681                 writel(buffer[i + 3] << 0 |
 682                        buffer[i + 4] << 8 |
 683                        buffer[i + 5] << 16 |
 684                        buffer[i + 6] << 24,
 685                        base + packet_reg);
 686                 packet_reg += 4;
 687         }
 688
 689         /*
 690          * clear remainder of packet ram as it's included in the
 691          * infoframe and triggers a checksum error on hdmi analyser
 692          */
 693         for (; packet_reg < packet_reg_next; packet_reg += 4)
 694                 writel(0, base + packet_reg);
 695
 696         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 697                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 698
 699         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 700
 701         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 702                         BIT(packet_id)), 100);
 703         if (ret)
 704                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 705
 706 out:
 707         drm_dev_exit(idx);
 708 }
 709
 710 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
 711                                               enum vc4_hdmi_output_format fmt)
 712 {
 713         switch (fmt) {
 714         case VC4_HDMI_OUTPUT_RGB:
 715                 frame->colorspace = HDMI_COLORSPACE_RGB;
 716                 break;
 717
 718         case VC4_HDMI_OUTPUT_YUV420:
 719                 frame->colorspace = HDMI_COLORSPACE_YUV420;
 720                 break;
 721
 722         case VC4_HDMI_OUTPUT_YUV422:
 723                 frame->colorspace = HDMI_COLORSPACE_YUV422;
 724                 break;
 725
 726         case VC4_HDMI_OUTPUT_YUV444:
 727                 frame->colorspace = HDMI_COLORSPACE_YUV444;
 728                 break;
 729
 730         default:
 731                 break;
 732         }
 733 }
 734
 735 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 736 {
 737         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 738         struct drm_connector *connector = &vc4_hdmi->connector;
 739         struct drm_connector_state *cstate = connector->state;
 740         struct vc4_hdmi_connector_state *vc4_state =
 741                 conn_state_to_vc4_hdmi_conn_state(cstate);
 742         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 743         union hdmi_infoframe frame;
 744         int ret;
 745
 746         lockdep_assert_held(&vc4_hdmi->mutex);
 747
 748         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 749                                                        connector, mode);
 750         if (ret < 0) {
 751                 DRM_ERROR("couldn't fill AVI infoframe\n");
 752                 return;
 753         }
 754
 755         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 756                                            connector, mode,
 757                                            vc4_hdmi_is_full_range(vc4_hdmi, mode) ?
 758                                            HDMI_QUANTIZATION_RANGE_FULL :
 759                                            HDMI_QUANTIZATION_RANGE_LIMITED);
 760         drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
 761         vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format);
 762         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 763
 764         vc4_hdmi_write_infoframe(encoder, &frame);
 765 }
 766
 767 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 768 {
 769         union hdmi_infoframe frame;
 770         int ret;
 771
 772         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 773         if (ret < 0) {
 774                 DRM_ERROR("couldn't fill SPD infoframe\n");
 775                 return;
 776         }
 777
 778         frame.spd.sdi = HDMI_SPD_SDI_PC;
 779
 780         vc4_hdmi_write_infoframe(encoder, &frame);
 781 }
 782
 783 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 784 {
 785         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 786         struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
 787         union hdmi_infoframe frame;
 788
 789         memcpy(&frame.audio, audio, sizeof(*audio));
 790         vc4_hdmi_write_infoframe(encoder, &frame);
 791 }
 792
 793 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 794 {
 795         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 796         struct drm_connector *connector = &vc4_hdmi->connector;
 797         struct drm_connector_state *conn_state = connector->state;
 798         union hdmi_infoframe frame;
 799
 800         lockdep_assert_held(&vc4_hdmi->mutex);
 801
 802         if (!vc4_hdmi->variant->supports_hdr)
 803                 return;
 804
 805         if (!conn_state->hdr_output_metadata)
 806                 return;
 807
 808         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 809                 return;
 810
 811         vc4_hdmi_write_infoframe(encoder, &frame);
 812 }
 813
 814 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 815 {
 816         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 817
 818         lockdep_assert_held(&vc4_hdmi->mutex);
 819
 820         vc4_hdmi_set_avi_infoframe(encoder);
 821         vc4_hdmi_set_spd_infoframe(encoder);
 822         /*
 823          * If audio was streaming, then we need to reenabled the audio
 824          * infoframe here during encoder_enable.
 825          */
 826         if (vc4_hdmi->audio.streaming)
 827                 vc4_hdmi_set_audio_infoframe(encoder);
 828
 829         vc4_hdmi_set_hdr_infoframe(encoder);
 830 }
 831
 832 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
 833                                          struct drm_display_mode *mode)
 834 {
 835         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 836         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 837         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 838
 839         lockdep_assert_held(&vc4_hdmi->mutex);
 840
 841         if (!vc4_encoder->hdmi_monitor)
 842                 return false;
 843
 844         if (!display->hdmi.scdc.supported ||
 845             !display->hdmi.scdc.scrambling.supported)
 846                 return false;
 847
 848         return true;
 849 }
 850
 851 #define SCRAMBLING_POLLING_DELAY_MS     1000
 852
 853 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 854 {
 855         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 856         struct drm_device *drm = vc4_hdmi->connector.dev;
 857         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 858         unsigned long flags;
 859         int idx;
 860
 861         lockdep_assert_held(&vc4_hdmi->mutex);
 862
 863         if (!vc4_hdmi_supports_scrambling(encoder, mode))
 864                 return;
 865
 866         if (!vc4_hdmi_mode_needs_scrambling(mode,
 867                                             vc4_hdmi->output_bpc,
 868                                             vc4_hdmi->output_format))
 869                 return;
 870
 871         if (!drm_dev_enter(drm, &idx))
 872                 return;
 873
 874         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 875         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 876
 877         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 878         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
 879                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 880         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 881
 882         drm_dev_exit(idx);
 883
 884         vc4_hdmi->scdc_enabled = true;
 885
 886         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 887                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 888 }
 889
 890 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
 891 {
 892         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 893         struct drm_device *drm = vc4_hdmi->connector.dev;
 894         unsigned long flags;
 895         int idx;
 896
 897         lockdep_assert_held(&vc4_hdmi->mutex);
 898
 899         if (!vc4_hdmi->scdc_enabled)
 900                 return;
 901
 902         vc4_hdmi->scdc_enabled = false;
 903
 904         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
 905                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
 906
 907         if (!drm_dev_enter(drm, &idx))
 908                 return;
 909
 910         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 911         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
 912                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 913         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 914
 915         drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
 916         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
 917
 918         drm_dev_exit(idx);
 919 }
 920
 921 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
 922 {
 923         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
 924                                                  struct vc4_hdmi,
 925                                                  scrambling_work);
 926
 927         if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
 928                 return;
 929
 930         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 931         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 932
 933         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 934                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 935 }
 936
 937 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 938                                                struct drm_atomic_state *state)
 939 {
 940         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 941         struct drm_device *drm = vc4_hdmi->connector.dev;
 942         unsigned long flags;
 943         int idx;
 944
 945         mutex_lock(&vc4_hdmi->mutex);
 946
 947         vc4_hdmi->output_enabled = false;
 948
 949         if (!drm_dev_enter(drm, &idx))
 950                 goto out;
 951
 952         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 953
 954         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 955
 956         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
 957
 958         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 959
 960         mdelay(1);
 961
 962         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 963         HDMI_WRITE(HDMI_VID_CTL,
 964                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 965         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 966
 967         vc4_hdmi_disable_scrambling(encoder);
 968
 969         drm_dev_exit(idx);
 970
 971 out:
 972         mutex_unlock(&vc4_hdmi->mutex);
 973 }
 974
 975 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
 976                                                  struct drm_atomic_state *state)
 977 {
 978         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 979         struct drm_device *drm = vc4_hdmi->connector.dev;
 980         unsigned long flags;
 981         int ret;
 982         int idx;
 983
 984         mutex_lock(&vc4_hdmi->mutex);
 985
 986         if (!drm_dev_enter(drm, &idx))
 987                 goto out;
 988
 989         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 990         HDMI_WRITE(HDMI_VID_CTL,
 991                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 992         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 993
 994         if (vc4_hdmi->variant->phy_disable)
 995                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 996
 997         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 998         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 999
1000         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
1001         if (ret < 0)
1002                 DRM_ERROR("Failed to release power domain: %d\n", ret);
1003
1004         drm_dev_exit(idx);
1005
1006 out:
1007         mutex_unlock(&vc4_hdmi->mutex);
1008 }
1009
1010 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1011                                struct drm_connector_state *state,
1012                                const struct drm_display_mode *mode)
1013 {
1014         struct drm_device *drm = vc4_hdmi->connector.dev;
1015         unsigned long flags;
1016         u32 csc_ctl;
1017         int idx;
1018
1019         if (!drm_dev_enter(drm, &idx))
1020                 return;
1021
1022         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1023
1024         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
1025                                 VC4_HD_CSC_CTL_ORDER);
1026
1027         if (!vc4_hdmi_is_full_range(vc4_hdmi, mode)) {
1028                 /* CEA VICs other than #1 requre limited range RGB
1029                  * output unless overridden by an AVI infoframe.
1030                  * Apply a colorspace conversion to squash 0-255 down
1031                  * to 16-235.  The matrix here is:
1032                  *
1033                  * [ 0      0      0.8594 16]
1034                  * [ 0      0.8594 0      16]
1035                  * [ 0.8594 0      0      16]
1036                  * [ 0      0      0       1]
1037                  */
1038                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
1039                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
1040                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1041                                          VC4_HD_CSC_CTL_MODE);
1042
1043                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
1044                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
1045                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
1046                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
1047                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
1048                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
1049         }
1050
1051         /* The RGB order applies even when CSC is disabled. */
1052         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1053
1054         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1055
1056         drm_dev_exit(idx);
1057 }
1058
1059 /*
1060  * If we need to output Full Range RGB, then use the unity matrix
1061  *
1062  * [ 1      0      0      0]
1063  * [ 0      1      0      0]
1064  * [ 0      0      1      0]
1065  *
1066  * CEA VICs other than #1 require limited range RGB output unless
1067  * overridden by an AVI infoframe. Apply a colorspace conversion to
1068  * squash 0-255 down to 16-235. The matrix here is:
1069  *
1070  * [ 0.8594 0      0      16]
1071  * [ 0      0.8594 0      16]
1072  * [ 0      0      0.8594 16]
1073  *
1074  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1075  */
1076 static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = {
1077         {
1078                 /* Full range - unity */
1079                 { 0x2000, 0x0000, 0x0000, 0x0000 },
1080                 { 0x0000, 0x2000, 0x0000, 0x0000 },
1081                 { 0x0000, 0x0000, 0x2000, 0x0000 },
1082         }, {
1083                 /* Limited range */
1084                 { 0x1b80, 0x0000, 0x0000, 0x0400 },
1085                 { 0x0000, 0x1b80, 0x0000, 0x0400 },
1086                 { 0x0000, 0x0000, 0x1b80, 0x0400 },
1087         }
1088 };
1089
1090 /*
1091  * Conversion between Full Range RGB and YUV using the BT.601 Colorspace
1092  *
1093  * Full range
1094  * [    0.299000   0.587000   0.114000   0.000000 ]
1095  * [   -0.168736  -0.331264   0.500000 128.000000 ]
1096  * [    0.500000  -0.418688  -0.081312 128.000000 ]
1097  *
1098  * Limited range
1099  * [    0.255785   0.502160   0.097523  16.000000 ]
1100  * [   -0.147644  -0.289856   0.437500 128.000000 ]
1101  * [    0.437500  -0.366352  -0.071148 128.000000 ]
1102  *
1103  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1104  */
1105 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = {
1106         {
1107                 /* Full range */
1108                 { 0x0991, 0x12c9, 0x03a6, 0x0000 },
1109                 { 0xfa9b, 0xf567, 0x1000, 0x2000 },
1110                 { 0x1000, 0xf29b, 0xfd67, 0x2000 },
1111         }, {
1112                 /* Limited range */
1113                 { 0x082f, 0x1012, 0x031f, 0x0400 },
1114                 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1115                 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1116         }
1117 };
1118
1119 /*
1120  * Conversion between Full Range RGB and YUV using the BT.709 Colorspace
1121  *
1122  * Full range
1123  * [    0.212600   0.715200   0.072200   0.000000 ]
1124  * [   -0.114572  -0.385428   0.500000 128.000000 ]
1125  * [    0.500000  -0.454153  -0.045847 128.000000 ]
1126  *
1127  * Limited range
1128  * [    0.181873   0.611831   0.061765  16.000000 ]
1129  * [   -0.100251  -0.337249   0.437500 128.000000 ]
1130  * [    0.437500  -0.397384  -0.040116 128.000000 ]
1131  *
1132  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1133  */
1134 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = {
1135         {
1136                 /* Full range */
1137                 { 0x06ce, 0x16e3, 0x024f, 0x0000 },
1138                 { 0xfc56, 0xf3ac, 0x1000, 0x2000 },
1139                 { 0x1000, 0xf179, 0xfe89, 0x2000 },
1140         }, {
1141                 /* Limited range        */
1142                 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1143                 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1144                 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1145         }
1146 };
1147
1148 /*
1149  * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace
1150  *
1151  * Full range
1152  * [    0.262700   0.678000   0.059300   0.000000 ]
1153  * [   -0.139630  -0.360370   0.500000 128.000000 ]
1154  * [    0.500000  -0.459786  -0.040214 128.000000 ]
1155  *
1156  * Limited range
1157  * [    0.224732   0.580008   0.050729  16.000000 ]
1158  * [   -0.122176  -0.315324   0.437500 128.000000 ]
1159  * [    0.437500  -0.402312  -0.035188 128.000000 ]
1160  *
1161  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1162  */
1163 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = {
1164         {
1165                 /* Full range */
1166                 { 0x0868, 0x15b2, 0x01e6, 0x0000 },
1167                 { 0xfb89, 0xf479, 0x1000, 0x2000 },
1168                 { 0x1000, 0xf14a, 0xfeb8, 0x2000 },
1169         }, {
1170                 /* Limited range */
1171                 { 0x0731, 0x128f, 0x01a0, 0x0400 },
1172                 { 0xfc18, 0xf5ea, 0x0e00, 0x2000 },
1173                 { 0x0e00, 0xf321, 0xfee1, 0x2000 },
1174         }
1175 };
1176
1177 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1178                                     const u16 coeffs[3][4])
1179 {
1180         lockdep_assert_held(&vc4_hdmi->hw_lock);
1181
1182         HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1183         HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1184         HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1185         HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1186         HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1187         HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1188 }
1189
1190 static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi,
1191                                          const u16 coeffs[3][4])
1192 {
1193         lockdep_assert_held(&vc4_hdmi->hw_lock);
1194
1195         /* YUV444 needs the CSC matrices using the channels in a different order */
1196         HDMI_WRITE(HDMI_CSC_12_11, (coeffs[2][1] << 16) | coeffs[2][0]);
1197         HDMI_WRITE(HDMI_CSC_14_13, (coeffs[2][3] << 16) | coeffs[2][2]);
1198         HDMI_WRITE(HDMI_CSC_22_21, (coeffs[0][1] << 16) | coeffs[0][0]);
1199         HDMI_WRITE(HDMI_CSC_24_23, (coeffs[0][3] << 16) | coeffs[0][2]);
1200         HDMI_WRITE(HDMI_CSC_32_31, (coeffs[1][1] << 16) | coeffs[1][0]);
1201         HDMI_WRITE(HDMI_CSC_34_33, (coeffs[1][3] << 16) | coeffs[1][2]);
1202 }
1203
1204 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1205                                struct drm_connector_state *state,
1206                                const struct drm_display_mode *mode)
1207 {
1208         struct drm_device *drm = vc4_hdmi->connector.dev;
1209         struct vc4_hdmi_connector_state *vc4_state =
1210                 conn_state_to_vc4_hdmi_conn_state(state);
1211         unsigned int lim_range = vc4_hdmi_is_full_range(vc4_hdmi, mode) ? 0 : 1;
1212         const u16 (*csc)[4];
1213         unsigned long flags;
1214         u32 if_cfg = 0;
1215         u32 if_xbar = 0x543210;
1216         u32 csc_chan_ctl = 0;
1217         u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1218                                                                VC5_MT_CP_CSC_CTL_MODE);
1219         int idx;
1220
1221         if (!drm_dev_enter(drm, &idx))
1222                 return;
1223
1224         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1225
1226         switch (vc4_state->output_format) {
1227         case VC4_HDMI_OUTPUT_YUV444:
1228         case VC4_HDMI_OUTPUT_YUV422:
1229                 switch (state->colorspace) {
1230                 default:
1231                 case DRM_MODE_COLORIMETRY_NO_DATA:
1232                 case DRM_MODE_COLORIMETRY_BT709_YCC:
1233                 case DRM_MODE_COLORIMETRY_XVYCC_709:
1234                 case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED:
1235                 case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT:
1236                         csc = vc5_hdmi_csc_full_rgb_to_yuv_bt709[lim_range];
1237                         break;
1238                 case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC:
1239                 case DRM_MODE_COLORIMETRY_XVYCC_601:
1240                 case DRM_MODE_COLORIMETRY_SYCC_601:
1241                 case DRM_MODE_COLORIMETRY_OPYCC_601:
1242                 case DRM_MODE_COLORIMETRY_BT601_YCC:
1243                         csc = vc5_hdmi_csc_full_rgb_to_yuv_bt601[lim_range];
1244                         break;
1245                 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1246                 case DRM_MODE_COLORIMETRY_BT2020_YCC:
1247                 case DRM_MODE_COLORIMETRY_BT2020_RGB:
1248                 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1249                 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1250                         csc = vc5_hdmi_csc_full_rgb_to_yuv_bt2020[lim_range];
1251                         break;
1252                 }
1253
1254                 if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {
1255                         csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1256                                                  VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1257                                 VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1258                                 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1259
1260                         csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1261                                                       VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1262
1263                         if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1264                                                 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1265
1266                         vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc);
1267                 } else {
1268                         vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc);
1269                 }
1270
1271                 break;
1272
1273         case VC4_HDMI_OUTPUT_RGB:
1274                 if_xbar = 0x354021;
1275
1276                 vc5_hdmi_set_csc_coeffs(vc4_hdmi,
1277                                         vc5_hdmi_csc_full_rgb_to_rgb[lim_range]);
1278                 break;
1279
1280         default:
1281                 break;
1282         }
1283
1284         HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1285         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1286         HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1287         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1288
1289         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1290
1291         drm_dev_exit(idx);
1292 }
1293
1294 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1295                                  struct drm_connector_state *state,
1296                                  struct drm_display_mode *mode)
1297 {
1298         struct drm_device *drm = vc4_hdmi->connector.dev;
1299         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1300         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1301         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1302         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1303         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1304                                    VC4_HDMI_VERTA_VSP) |
1305                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1306                                    VC4_HDMI_VERTA_VFP) |
1307                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1308         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1309                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1310                                    interlaced,
1311                                    VC4_HDMI_VERTB_VBP));
1312         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1313                           VC4_SET_FIELD(mode->crtc_vtotal -
1314                                         mode->crtc_vsync_end,
1315                                         VC4_HDMI_VERTB_VBP));
1316         unsigned long flags;
1317         u32 reg;
1318         int idx;
1319
1320         if (!drm_dev_enter(drm, &idx))
1321                 return;
1322
1323         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1324
1325         HDMI_WRITE(HDMI_HORZA,
1326                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1327                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1328                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1329                                  VC4_HDMI_HORZA_HAP));
1330
1331         HDMI_WRITE(HDMI_HORZB,
1332                    VC4_SET_FIELD((mode->htotal -
1333                                   mode->hsync_end) * pixel_rep,
1334                                  VC4_HDMI_HORZB_HBP) |
1335                    VC4_SET_FIELD((mode->hsync_end -
1336                                   mode->hsync_start) * pixel_rep,
1337                                  VC4_HDMI_HORZB_HSP) |
1338                    VC4_SET_FIELD((mode->hsync_start -
1339                                   mode->hdisplay) * pixel_rep,
1340                                  VC4_HDMI_HORZB_HFP));
1341
1342         HDMI_WRITE(HDMI_VERTA0, verta);
1343         HDMI_WRITE(HDMI_VERTA1, verta);
1344
1345         HDMI_WRITE(HDMI_VERTB0, vertb_even);
1346         HDMI_WRITE(HDMI_VERTB1, vertb);
1347
1348         reg = HDMI_READ(HDMI_MISC_CONTROL);
1349         reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1350         reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1351         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1352
1353         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1354
1355         drm_dev_exit(idx);
1356 }
1357
1358 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1359                                  struct drm_connector_state *state,
1360                                  struct drm_display_mode *mode)
1361 {
1362         struct drm_device *drm = vc4_hdmi->connector.dev;
1363         const struct vc4_hdmi_connector_state *vc4_state =
1364                 conn_state_to_vc4_hdmi_conn_state(state);
1365         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1366         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1367         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1368         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1369         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1370                                    VC5_HDMI_VERTA_VSP) |
1371                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1372                                    VC5_HDMI_VERTA_VFP) |
1373                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1374         u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1375                                    VC5_HDMI_VERTB_VSPO) |
1376                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1377                                    interlaced,
1378                                    VC4_HDMI_VERTB_VBP));
1379         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1380                           VC4_SET_FIELD(mode->crtc_vtotal -
1381                                         mode->crtc_vsync_end,
1382                                         VC4_HDMI_VERTB_VBP));
1383         unsigned long flags;
1384         unsigned char gcp;
1385         bool gcp_en;
1386         u32 reg;
1387         int idx;
1388
1389         if (!drm_dev_enter(drm, &idx))
1390                 return;
1391
1392         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1393
1394         HDMI_WRITE(HDMI_HORZA,
1395                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1396                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1397                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1398                                  VC5_HDMI_HORZA_HAP) |
1399                    VC4_SET_FIELD((mode->hsync_start -
1400                                   mode->hdisplay) * pixel_rep,
1401                                  VC5_HDMI_HORZA_HFP));
1402
1403         HDMI_WRITE(HDMI_HORZB,
1404                    VC4_SET_FIELD((mode->htotal -
1405                                   mode->hsync_end) * pixel_rep,
1406                                  VC5_HDMI_HORZB_HBP) |
1407                    VC4_SET_FIELD((mode->hsync_end -
1408                                   mode->hsync_start) * pixel_rep,
1409                                  VC5_HDMI_HORZB_HSP));
1410
1411         HDMI_WRITE(HDMI_VERTA0, verta);
1412         HDMI_WRITE(HDMI_VERTA1, verta);
1413
1414         HDMI_WRITE(HDMI_VERTB0, vertb_even);
1415         HDMI_WRITE(HDMI_VERTB1, vertb);
1416
1417         switch (vc4_state->output_bpc) {
1418         case 12:
1419                 gcp = 6;
1420                 gcp_en = true;
1421                 break;
1422         case 10:
1423                 gcp = 5;
1424                 gcp_en = true;
1425                 break;
1426         case 8:
1427         default:
1428                 gcp = 4;
1429                 gcp_en = false;
1430                 break;
1431         }
1432
1433         /*
1434          * YCC422 is always 36-bit and not considered deep colour so
1435          * doesn't signal in GCP
1436          */
1437         if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {
1438                 gcp = 4;
1439                 gcp_en = false;
1440         }
1441
1442         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1443         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1444                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1445         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1446                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1447         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1448
1449         reg = HDMI_READ(HDMI_GCP_WORD_1);
1450         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1451         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1452         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1453
1454         reg = HDMI_READ(HDMI_GCP_CONFIG);
1455         reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1456         reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
1457         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1458
1459         reg = HDMI_READ(HDMI_MISC_CONTROL);
1460         reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1461         reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1462         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1463
1464         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1465
1466         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1467
1468         drm_dev_exit(idx);
1469 }
1470
1471 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1472 {
1473         struct drm_device *drm = vc4_hdmi->connector.dev;
1474         unsigned long flags;
1475         u32 drift;
1476         int ret;
1477         int idx;
1478
1479         if (!drm_dev_enter(drm, &idx))
1480                 return;
1481
1482         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1483
1484         drift = HDMI_READ(HDMI_FIFO_CTL);
1485         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1486
1487         HDMI_WRITE(HDMI_FIFO_CTL,
1488                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1489         HDMI_WRITE(HDMI_FIFO_CTL,
1490                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1491
1492         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1493
1494         usleep_range(1000, 1100);
1495
1496         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1497
1498         HDMI_WRITE(HDMI_FIFO_CTL,
1499                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1500         HDMI_WRITE(HDMI_FIFO_CTL,
1501                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1502
1503         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1504
1505         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1506                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1507         WARN_ONCE(ret, "Timeout waiting for "
1508                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1509
1510         drm_dev_exit(idx);
1511 }
1512
1513 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1514                                                 struct drm_atomic_state *state)
1515 {
1516         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1517         struct drm_device *drm = vc4_hdmi->connector.dev;
1518         struct drm_connector *connector = &vc4_hdmi->connector;
1519         struct drm_connector_state *conn_state =
1520                 drm_atomic_get_new_connector_state(state, connector);
1521         struct vc4_hdmi_connector_state *vc4_conn_state =
1522                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1523         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1524         unsigned long pixel_rate = vc4_conn_state->pixel_rate;
1525         unsigned long bvb_rate, hsm_rate;
1526         unsigned long flags;
1527         int ret;
1528         int idx;
1529
1530         mutex_lock(&vc4_hdmi->mutex);
1531
1532         if (!drm_dev_enter(drm, &idx))
1533                 goto out;
1534
1535         /*
1536          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1537          * be faster than pixel clock, infinitesimally faster, tested in
1538          * simulation. Otherwise, exact value is unimportant for HDMI
1539          * operation." This conflicts with bcm2835's vc4 documentation, which
1540          * states HSM's clock has to be at least 108% of the pixel clock.
1541          *
1542          * Real life tests reveal that vc4's firmware statement holds up, and
1543          * users are able to use pixel clocks closer to HSM's, namely for
1544          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1545          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1546          * 162MHz.
1547          *
1548          * Additionally, the AXI clock needs to be at least 25% of
1549          * pixel clock, but HSM ends up being the limiting factor.
1550          */
1551         hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
1552         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1553         if (ret) {
1554                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1555                 goto err_dev_exit;
1556         }
1557
1558         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1559         if (ret < 0) {
1560                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1561                 goto err_dev_exit;
1562         }
1563
1564         ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
1565         if (ret) {
1566                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1567                 goto err_put_runtime_pm;
1568         }
1569
1570         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1571         if (ret) {
1572                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1573                 goto err_put_runtime_pm;
1574         }
1575
1576
1577         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1578
1579         if (pixel_rate > 297000000)
1580                 bvb_rate = 300000000;
1581         else if (pixel_rate > 148500000)
1582                 bvb_rate = 150000000;
1583         else
1584                 bvb_rate = 75000000;
1585
1586         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1587         if (ret) {
1588                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1589                 goto err_disable_pixel_clock;
1590         }
1591
1592         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1593         if (ret) {
1594                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1595                 goto err_disable_pixel_clock;
1596         }
1597
1598         if (vc4_hdmi->variant->phy_init)
1599                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1600
1601         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1602
1603         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1604                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1605                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1606                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1607
1608         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1609
1610         if (vc4_hdmi->variant->set_timings)
1611                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1612
1613         drm_dev_exit(idx);
1614
1615         mutex_unlock(&vc4_hdmi->mutex);
1616
1617         return;
1618
1619 err_disable_pixel_clock:
1620         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1621 err_put_runtime_pm:
1622         pm_runtime_put(&vc4_hdmi->pdev->dev);
1623 err_dev_exit:
1624         drm_dev_exit(idx);
1625 out:
1626         mutex_unlock(&vc4_hdmi->mutex);
1627         return;
1628 }
1629
1630 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1631                                              struct drm_atomic_state *state)
1632 {
1633         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1634         struct drm_device *drm = vc4_hdmi->connector.dev;
1635         struct drm_connector *connector = &vc4_hdmi->connector;
1636         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1637         struct drm_connector_state *conn_state =
1638                 drm_atomic_get_new_connector_state(state, connector);
1639         unsigned long flags;
1640         int idx;
1641
1642         mutex_lock(&vc4_hdmi->mutex);
1643
1644         if (!drm_dev_enter(drm, &idx))
1645                 return;
1646
1647         if (vc4_hdmi->variant->csc_setup)
1648                 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1649
1650         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1651         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1652         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1653
1654         drm_dev_exit(idx);
1655
1656         mutex_unlock(&vc4_hdmi->mutex);
1657 }
1658
1659 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1660                                               struct drm_atomic_state *state)
1661 {
1662         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1663         struct drm_device *drm = vc4_hdmi->connector.dev;
1664         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1665         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1666         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1667         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1668         unsigned long flags;
1669         int ret;
1670         int idx;
1671
1672         mutex_lock(&vc4_hdmi->mutex);
1673
1674         if (!drm_dev_enter(drm, &idx))
1675                 return;
1676
1677         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1678
1679         HDMI_WRITE(HDMI_VID_CTL,
1680                    VC4_HD_VID_CTL_ENABLE |
1681                    VC4_HD_VID_CTL_CLRRGB |
1682                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1683                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1684                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1685                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1686
1687         HDMI_WRITE(HDMI_VID_CTL,
1688                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1689
1690         if (vc4_encoder->hdmi_monitor) {
1691                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1692                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1693                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1694
1695                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1696
1697                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1698                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1699                 WARN_ONCE(ret, "Timeout waiting for "
1700                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1701         } else {
1702                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1703                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1704                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1705                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1706                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1707                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1708
1709                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1710
1711                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1712                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1713                 WARN_ONCE(ret, "Timeout waiting for "
1714                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1715         }
1716
1717         if (vc4_encoder->hdmi_monitor) {
1718                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1719
1720                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1721                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1722
1723                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1724                            VC4_HDMI_RAM_PACKET_ENABLE);
1725
1726                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1727                 vc4_hdmi->output_enabled = true;
1728
1729                 vc4_hdmi_set_infoframes(encoder);
1730         }
1731
1732         vc4_hdmi_recenter_fifo(vc4_hdmi);
1733         vc4_hdmi_enable_scrambling(encoder);
1734
1735         drm_dev_exit(idx);
1736         mutex_unlock(&vc4_hdmi->mutex);
1737 }
1738
1739 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1740                                              struct drm_crtc_state *crtc_state,
1741                                              struct drm_connector_state *conn_state)
1742 {
1743         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1744         struct vc4_hdmi_connector_state *vc4_state =
1745                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1746
1747         mutex_lock(&vc4_hdmi->mutex);
1748         vc4_hdmi->output_bpc = vc4_state->output_bpc;
1749         vc4_hdmi->output_format = vc4_state->output_format;
1750         vc4_hdmi->broadcast_rgb = vc4_state->broadcast_rgb;
1751         memcpy(&vc4_hdmi->saved_adjusted_mode,
1752                &crtc_state->adjusted_mode,
1753                sizeof(vc4_hdmi->saved_adjusted_mode));
1754         mutex_unlock(&vc4_hdmi->mutex);
1755 }
1756
1757 static bool
1758 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi,
1759                                   const struct drm_display_info *info,
1760                                   const struct drm_display_mode *mode,
1761                                   unsigned int format, unsigned int bpc)
1762 {
1763         struct drm_device *dev = vc4_hdmi->connector.dev;
1764         u8 vic = drm_match_cea_mode(mode);
1765
1766         if (vic == 1 && bpc != 8) {
1767                 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc);
1768                 return false;
1769         }
1770
1771         if (!info->is_hdmi &&
1772             (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) {
1773                 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n");
1774                 return false;
1775         }
1776
1777         switch (format) {
1778         case VC4_HDMI_OUTPUT_RGB:
1779                 drm_dbg(dev, "RGB Format, checking the constraints.\n");
1780
1781                 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1782                         drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1783                         return false;
1784                 }
1785
1786                 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1787                         drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1788                         return false;
1789                 }
1790
1791                 drm_dbg(dev, "RGB format supported in that configuration.\n");
1792
1793                 return true;
1794
1795         case VC4_HDMI_OUTPUT_YUV422:
1796                 drm_dbg(dev, "YUV422 format, checking the constraints.\n");
1797
1798                 if (!(info->color_formats & DRM_COLOR_FORMAT_YCRCB422)) {
1799                         drm_dbg(dev, "Sink doesn't support YUV422.\n");
1800                         return false;
1801                 }
1802
1803                 if (bpc != 12) {
1804                         drm_dbg(dev, "YUV422 only supports 12 bpc.\n");
1805                         return false;
1806                 }
1807
1808                 drm_dbg(dev, "YUV422 format supported in that configuration.\n");
1809
1810                 return true;
1811
1812         case VC4_HDMI_OUTPUT_YUV444:
1813                 drm_dbg(dev, "YUV444 format, checking the constraints.\n");
1814
1815                 if (!(info->color_formats & DRM_COLOR_FORMAT_YCRCB444)) {
1816                         drm_dbg(dev, "Sink doesn't support YUV444.\n");
1817                         return false;
1818                 }
1819
1820                 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1821                         drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1822                         return false;
1823                 }
1824
1825                 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1826                         drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1827                         return false;
1828                 }
1829
1830                 drm_dbg(dev, "YUV444 format supported in that configuration.\n");
1831
1832                 return true;
1833         }
1834
1835         return false;
1836 }
1837
1838 static enum drm_mode_status
1839 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
1840                              unsigned long long clock)
1841 {
1842         const struct drm_connector *connector = &vc4_hdmi->connector;
1843         const struct drm_display_info *info = &connector->display_info;
1844         struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
1845
1846         if (clock > vc4_hdmi->variant->max_pixel_clock)
1847                 return MODE_CLOCK_HIGH;
1848
1849         if (!vc4->hvs->vc5_hdmi_enable_scrambling && clock > HDMI_14_MAX_TMDS_CLK)
1850                 return MODE_CLOCK_HIGH;
1851
1852         if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000))
1853                 return MODE_CLOCK_HIGH;
1854
1855         return MODE_OK;
1856 }
1857
1858 static unsigned long long
1859 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
1860                                     unsigned int bpc,
1861                                     enum vc4_hdmi_output_format fmt)
1862 {
1863         unsigned long long clock = mode->clock * 1000;
1864
1865         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1866                 clock = clock * 2;
1867
1868         if (fmt == VC4_HDMI_OUTPUT_YUV422)
1869                 bpc = 8;
1870
1871         return clock * bpc / 8;
1872 }
1873
1874 static int
1875 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
1876                                struct vc4_hdmi_connector_state *vc4_state,
1877                                const struct drm_display_mode *mode,
1878                                unsigned int bpc, unsigned int fmt)
1879 {
1880         unsigned long long clock;
1881
1882         clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
1883         if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, clock) != MODE_OK)
1884                 return -EINVAL;
1885
1886         vc4_state->pixel_rate = clock;
1887
1888         return 0;
1889 }
1890
1891 static int
1892 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi,
1893                                 struct vc4_hdmi_connector_state *vc4_state,
1894                                 const struct drm_display_mode *mode,
1895                                 unsigned int bpc)
1896 {
1897         struct drm_device *dev = vc4_hdmi->connector.dev;
1898         const struct drm_connector *connector = &vc4_hdmi->connector;
1899         const struct drm_display_info *info = &connector->display_info;
1900         unsigned int format;
1901
1902         drm_dbg(dev, "Trying with an RGB output\n");
1903
1904         format = VC4_HDMI_OUTPUT_RGB;
1905         if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1906                 int ret;
1907
1908                 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1909                                                      mode, bpc, format);
1910                 if (!ret) {
1911                         vc4_state->output_format = format;
1912                         return 0;
1913                 }
1914         }
1915
1916         drm_dbg(dev, "Failed, Trying with an YUV422 output\n");
1917
1918         format = VC4_HDMI_OUTPUT_YUV422;
1919         if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1920                 int ret;
1921
1922                 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1923                                                      mode, bpc, format);
1924                 if (!ret) {
1925                         vc4_state->output_format = format;
1926                         return 0;
1927                 }
1928         }
1929
1930         drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n");
1931
1932         return -EINVAL;
1933 }
1934
1935 static int
1936 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi,
1937                                 struct vc4_hdmi_connector_state *vc4_state,
1938                                 const struct drm_display_mode *mode)
1939 {
1940         struct drm_device *dev = vc4_hdmi->connector.dev;
1941         struct drm_connector_state *conn_state = &vc4_state->base;
1942         unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12);
1943         unsigned int bpc;
1944         int ret;
1945
1946         for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
1947                 drm_dbg(dev, "Trying with a %d bpc output\n", bpc);
1948
1949                 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state,
1950                                                       mode, bpc);
1951                 if (ret)
1952                         continue;
1953
1954                 vc4_state->output_bpc = bpc;
1955
1956                 drm_dbg(dev,
1957                         "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n",
1958                         mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
1959                         vc4_state->output_bpc,
1960                         vc4_hdmi_output_fmt_str(vc4_state->output_format),
1961                         vc4_state->pixel_rate);
1962
1963                 break;
1964         }
1965
1966         return ret;
1967 }
1968
1969 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
1970 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
1971
1972 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1973                                          struct drm_crtc_state *crtc_state,
1974                                          struct drm_connector_state *conn_state)
1975 {
1976         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1977         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1978         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1979         struct drm_connector *connector = &vc4_hdmi->connector;
1980         struct drm_connector_state *old_conn_state = drm_atomic_get_old_connector_state(conn_state->state, connector);
1981         struct vc4_hdmi_connector_state *old_vc4_state = conn_state_to_vc4_hdmi_conn_state(old_conn_state);
1982         struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
1983         unsigned long long pixel_rate = mode->clock * 1000;
1984         unsigned long long tmds_rate;
1985         int ret;
1986
1987         if (vc4_hdmi->variant->unsupported_odd_h_timings) {
1988                 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1989                         /* Only try to fixup DBLCLK modes to get 480i and 576i
1990                          * working.
1991                          * A generic solution for all modes with odd horizontal
1992                          * timing values seems impossible based on trying to
1993                          * solve it for 1366x768 monitors.
1994                          */
1995                         if ((mode->hsync_start - mode->hdisplay) & 1)
1996                                 mode->hsync_start--;
1997                         if ((mode->hsync_end - mode->hsync_start) & 1)
1998                                 mode->hsync_end--;
1999                 }
2000
2001                 /* Now check whether we still have odd values remaining */
2002                 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
2003                     (mode->hsync_end % 2) || (mode->htotal % 2))
2004                         return -EINVAL;
2005         }
2006
2007         /* 4096x2160@60 is not reliable without overclocking core */
2008         if (mode->hdisplay > 3840 && mode->vdisplay >= 2160 &&
2009             drm_mode_vrefresh(mode) >= 50 &&
2010             !vc4->hvs->vc5_hdmi_enable_4096by2160)
2011                 return -EINVAL;
2012
2013         /*
2014          * The 1440p@60 pixel rate is in the same range than the first
2015          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
2016          * bandwidth). Slightly lower the frequency to bring it out of
2017          * the WiFi range.
2018          */
2019         tmds_rate = pixel_rate * 10;
2020         if (vc4_hdmi->disable_wifi_frequencies &&
2021             (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
2022              tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
2023                 mode->clock = 238560;
2024                 pixel_rate = mode->clock * 1000;
2025         }
2026
2027         ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode);
2028         if (ret)
2029                 return ret;
2030
2031         /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */
2032         if (vc4_state->output_bpc != old_vc4_state->output_bpc ||
2033             vc4_state->output_format != old_vc4_state->output_format)
2034                 crtc_state->mode_changed = true;
2035
2036         return 0;
2037 }
2038
2039 static enum drm_mode_status
2040 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
2041                             const struct drm_display_mode *mode)
2042 {
2043         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
2044         const struct drm_connector *connector = &vc4_hdmi->connector;
2045         struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
2046
2047         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
2048             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
2049             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
2050              (mode->hsync_end % 2) || (mode->htotal % 2)))
2051                 return MODE_H_ILLEGAL;
2052
2053         if (mode->hdisplay > 3840 && mode->vdisplay >= 2160 &&
2054             drm_mode_vrefresh(mode) >= 50 &&
2055             !vc4->hvs->vc5_hdmi_enable_4096by2160)
2056                 return MODE_CLOCK_HIGH;
2057
2058         return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode->clock * 1000);
2059 }
2060
2061 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
2062         .atomic_check = vc4_hdmi_encoder_atomic_check,
2063         .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
2064         .mode_valid = vc4_hdmi_encoder_mode_valid,
2065 };
2066
2067 static int vc4_hdmi_late_register(struct drm_encoder *encoder)
2068 {
2069         struct drm_device *drm = encoder->dev;
2070         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
2071         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2072         int ret;
2073
2074         ret = vc4_debugfs_add_file(drm->primary, variant->debugfs_name,
2075                                    vc4_hdmi_debugfs_regs,
2076                                    vc4_hdmi);
2077         if (ret)
2078                 return ret;
2079
2080         return 0;
2081 }
2082
2083 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
2084         .late_register = vc4_hdmi_late_register,
2085 };
2086
2087 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2088 {
2089         int i;
2090         u32 channel_map = 0;
2091
2092         for (i = 0; i < 8; i++) {
2093                 if (channel_mask & BIT(i))
2094                         channel_map |= i << (3 * i);
2095         }
2096         return channel_map;
2097 }
2098
2099 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2100 {
2101         int i;
2102         u32 channel_map = 0;
2103
2104         for (i = 0; i < 8; i++) {
2105                 if (channel_mask & BIT(i))
2106                         channel_map |= i << (4 * i);
2107         }
2108         return channel_map;
2109 }
2110
2111 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
2112 {
2113         struct drm_device *drm = vc4_hdmi->connector.dev;
2114         unsigned long flags;
2115         u32 hotplug;
2116         int idx;
2117
2118         if (!drm_dev_enter(drm, &idx))
2119                 return false;
2120
2121         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2122         hotplug = HDMI_READ(HDMI_HOTPLUG);
2123         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2124
2125         drm_dev_exit(idx);
2126
2127         return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
2128 }
2129
2130 /* HDMI audio codec callbacks */
2131 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
2132                                          unsigned int samplerate)
2133 {
2134         struct drm_device *drm = vc4_hdmi->connector.dev;
2135         u32 hsm_clock;
2136         unsigned long flags;
2137         unsigned long n, m;
2138         int idx;
2139
2140         if (!drm_dev_enter(drm, &idx))
2141                 return;
2142
2143         hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
2144         rational_best_approximation(hsm_clock, samplerate,
2145                                     VC4_HD_MAI_SMP_N_MASK >>
2146                                     VC4_HD_MAI_SMP_N_SHIFT,
2147                                     (VC4_HD_MAI_SMP_M_MASK >>
2148                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
2149                                     &n, &m);
2150
2151         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2152         HDMI_WRITE(HDMI_MAI_SMP,
2153                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
2154                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
2155         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2156
2157         drm_dev_exit(idx);
2158 }
2159
2160 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
2161 {
2162         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
2163         u32 n, cts;
2164         u64 tmp;
2165
2166         lockdep_assert_held(&vc4_hdmi->mutex);
2167         lockdep_assert_held(&vc4_hdmi->hw_lock);
2168
2169         n = 128 * samplerate / 1000;
2170         tmp = (u64)(mode->clock * 1000) * n;
2171         do_div(tmp, 128 * samplerate);
2172         cts = tmp;
2173
2174         HDMI_WRITE(HDMI_CRP_CFG,
2175                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
2176                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
2177
2178         /*
2179          * We could get slightly more accurate clocks in some cases by
2180          * providing a CTS_1 value.  The two CTS values are alternated
2181          * between based on the period fields
2182          */
2183         HDMI_WRITE(HDMI_CTS_0, cts);
2184         HDMI_WRITE(HDMI_CTS_1, cts);
2185 }
2186
2187 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
2188 {
2189         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
2190
2191         return snd_soc_card_get_drvdata(card);
2192 }
2193
2194 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
2195 {
2196         lockdep_assert_held(&vc4_hdmi->mutex);
2197
2198         /*
2199          * If the encoder is currently in DVI mode, treat the codec DAI
2200          * as missing.
2201          */
2202         if (!vc4_hdmi->encoder.hdmi_monitor)
2203                 return false;
2204
2205         return true;
2206 }
2207
2208 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
2209 {
2210         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2211         struct drm_device *drm = vc4_hdmi->connector.dev;
2212         unsigned long flags;
2213         int ret = 0;
2214         int idx;
2215
2216         mutex_lock(&vc4_hdmi->mutex);
2217
2218         if (!drm_dev_enter(drm, &idx)) {
2219                 ret = -ENODEV;
2220                 goto out;
2221         }
2222
2223         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2224                 ret = -ENODEV;
2225                 goto out_dev_exit;
2226         }
2227
2228         vc4_hdmi->audio.streaming = true;
2229
2230         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2231         HDMI_WRITE(HDMI_MAI_CTL,
2232                    VC4_HD_MAI_CTL_RESET |
2233                    VC4_HD_MAI_CTL_FLUSH |
2234                    VC4_HD_MAI_CTL_DLATE |
2235                    VC4_HD_MAI_CTL_ERRORE |
2236                    VC4_HD_MAI_CTL_ERRORF);
2237         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2238
2239         if (vc4_hdmi->variant->phy_rng_enable)
2240                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
2241
2242 out_dev_exit:
2243         drm_dev_exit(idx);
2244 out:
2245         mutex_unlock(&vc4_hdmi->mutex);
2246
2247         return ret;
2248 }
2249
2250 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
2251 {
2252         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
2253         struct device *dev = &vc4_hdmi->pdev->dev;
2254         unsigned long flags;
2255         int ret;
2256
2257         lockdep_assert_held(&vc4_hdmi->mutex);
2258
2259         vc4_hdmi->audio.streaming = false;
2260         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
2261         if (ret)
2262                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
2263
2264         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2265
2266         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
2267         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
2268         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
2269
2270         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2271 }
2272
2273 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
2274 {
2275         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2276         struct drm_device *drm = vc4_hdmi->connector.dev;
2277         unsigned long flags;
2278         int idx;
2279
2280         mutex_lock(&vc4_hdmi->mutex);
2281
2282         if (!drm_dev_enter(drm, &idx))
2283                 goto out;
2284
2285         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2286
2287         HDMI_WRITE(HDMI_MAI_CTL,
2288                    VC4_HD_MAI_CTL_DLATE |
2289                    VC4_HD_MAI_CTL_ERRORE |
2290                    VC4_HD_MAI_CTL_ERRORF);
2291
2292         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2293
2294         if (vc4_hdmi->variant->phy_rng_disable)
2295                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
2296
2297         vc4_hdmi->audio.streaming = false;
2298         vc4_hdmi_audio_reset(vc4_hdmi);
2299
2300         drm_dev_exit(idx);
2301
2302 out:
2303         mutex_unlock(&vc4_hdmi->mutex);
2304 }
2305
2306 static int sample_rate_to_mai_fmt(int samplerate)
2307 {
2308         switch (samplerate) {
2309         case 8000:
2310                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
2311         case 11025:
2312                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
2313         case 12000:
2314                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
2315         case 16000:
2316                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
2317         case 22050:
2318                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
2319         case 24000:
2320                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
2321         case 32000:
2322                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
2323         case 44100:
2324                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
2325         case 48000:
2326                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
2327         case 64000:
2328                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
2329         case 88200:
2330                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
2331         case 96000:
2332                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
2333         case 128000:
2334                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2335         case 176400:
2336                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2337         case 192000:
2338                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2339         default:
2340                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2341         }
2342 }
2343
2344 /* HDMI audio codec callbacks */
2345 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
2346                                   struct hdmi_codec_daifmt *daifmt,
2347                                   struct hdmi_codec_params *params)
2348 {
2349         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2350         struct drm_device *drm = vc4_hdmi->connector.dev;
2351         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
2352         unsigned int sample_rate = params->sample_rate;
2353         unsigned int channels = params->channels;
2354         unsigned long flags;
2355         u32 audio_packet_config, channel_mask;
2356         u32 channel_map;
2357         u32 mai_audio_format;
2358         u32 mai_sample_rate;
2359         int ret = 0;
2360         int idx;
2361
2362         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2363                 sample_rate, params->sample_width, channels);
2364
2365         mutex_lock(&vc4_hdmi->mutex);
2366
2367         if (!drm_dev_enter(drm, &idx)) {
2368                 ret = -ENODEV;
2369                 goto out;
2370         }
2371
2372         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2373                 ret = -EINVAL;
2374                 goto out_dev_exit;
2375         }
2376
2377         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2378
2379         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2380         HDMI_WRITE(HDMI_MAI_CTL,
2381                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2382                    VC4_HD_MAI_CTL_WHOLSMP |
2383                    VC4_HD_MAI_CTL_CHALIGN |
2384                    VC4_HD_MAI_CTL_ENABLE);
2385
2386         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2387         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2388             params->channels == 8)
2389                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2390         else
2391                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2392         HDMI_WRITE(HDMI_MAI_FMT,
2393                    VC4_SET_FIELD(mai_sample_rate,
2394                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2395                    VC4_SET_FIELD(mai_audio_format,
2396                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2397
2398         /* The B frame identifier should match the value used by alsa-lib (8) */
2399         audio_packet_config =
2400                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2401                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2402                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2403
2404         channel_mask = GENMASK(channels - 1, 0);
2405         audio_packet_config |= VC4_SET_FIELD(channel_mask,
2406                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2407
2408         /* Set the MAI threshold */
2409         HDMI_WRITE(HDMI_MAI_THR,
2410                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
2411                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
2412                    VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
2413                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
2414
2415         HDMI_WRITE(HDMI_MAI_CONFIG,
2416                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2417                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2418                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2419
2420         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2421         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2422         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2423
2424         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2425
2426         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2427
2428         memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
2429         if (vc4_hdmi->output_enabled)
2430                 vc4_hdmi_set_audio_infoframe(encoder);
2431
2432 out_dev_exit:
2433         drm_dev_exit(idx);
2434 out:
2435         mutex_unlock(&vc4_hdmi->mutex);
2436
2437         return ret;
2438 }
2439
2440 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2441         .name = "vc4-hdmi-cpu-dai-component",
2442 };
2443
2444 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2445 {
2446         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2447
2448         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2449
2450         return 0;
2451 }
2452
2453 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2454         .name = "vc4-hdmi-cpu-dai",
2455         .probe  = vc4_hdmi_audio_cpu_dai_probe,
2456         .playback = {
2457                 .stream_name = "Playback",
2458                 .channels_min = 1,
2459                 .channels_max = 8,
2460                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2461                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2462                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2463                          SNDRV_PCM_RATE_192000,
2464                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2465         },
2466 };
2467
2468 static const struct snd_dmaengine_pcm_config pcm_conf = {
2469         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2470         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2471 };
2472
2473 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
2474                                   uint8_t *buf, size_t len)
2475 {
2476         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2477         struct drm_connector *connector = &vc4_hdmi->connector;
2478
2479         mutex_lock(&vc4_hdmi->mutex);
2480         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2481         mutex_unlock(&vc4_hdmi->mutex);
2482
2483         return 0;
2484 }
2485
2486 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
2487         .get_eld = vc4_hdmi_audio_get_eld,
2488         .prepare = vc4_hdmi_audio_prepare,
2489         .audio_shutdown = vc4_hdmi_audio_shutdown,
2490         .audio_startup = vc4_hdmi_audio_startup,
2491 };
2492
2493 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
2494         .ops = &vc4_hdmi_codec_ops,
2495         .max_i2s_channels = 8,
2496         .i2s = 1,
2497 };
2498
2499 static void vc4_hdmi_audio_codec_release(void *ptr)
2500 {
2501         struct vc4_hdmi *vc4_hdmi = ptr;
2502
2503         platform_device_unregister(vc4_hdmi->audio.codec_pdev);
2504         vc4_hdmi->audio.codec_pdev = NULL;
2505 }
2506
2507 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2508 {
2509         const struct vc4_hdmi_register *mai_data =
2510                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2511         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2512         struct snd_soc_card *card = &vc4_hdmi->audio.card;
2513         struct device *dev = &vc4_hdmi->pdev->dev;
2514         struct platform_device *codec_pdev;
2515         const __be32 *addr;
2516         int index;
2517         int ret;
2518         int len;
2519
2520         /*
2521          * ASoC makes it a bit hard to retrieve a pointer to the
2522          * vc4_hdmi structure. Registering the card will overwrite our
2523          * device drvdata with a pointer to the snd_soc_card structure,
2524          * which can then be used to retrieve whatever drvdata we want
2525          * to associate.
2526          *
2527          * However, that doesn't fly in the case where we wouldn't
2528          * register an ASoC card (because of an old DT that is missing
2529          * the dmas properties for example), then the card isn't
2530          * registered and the device drvdata wouldn't be set.
2531          *
2532          * We can deal with both cases by making sure a snd_soc_card
2533          * pointer and a vc4_hdmi structure are pointing to the same
2534          * memory address, so we can treat them indistinctly without any
2535          * issue.
2536          */
2537         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2538         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2539
2540         if (!of_find_property(dev->of_node, "dmas", &len) ||
2541             len == 0) {
2542                 dev_warn(dev,
2543                          "'dmas' DT property is missing or empty, no HDMI audio\n");
2544                 return 0;
2545         }
2546
2547         if (mai_data->reg != VC4_HD) {
2548                 WARN_ONCE(true, "MAI isn't in the HD block\n");
2549                 return -EINVAL;
2550         }
2551
2552         /*
2553          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2554          * the bus address specified in the DT, because the physical address
2555          * (the one returned by platform_get_resource()) is not appropriate
2556          * for DMA transfers.
2557          * This VC/MMU should probably be exposed to avoid this kind of hacks.
2558          */
2559         index = of_property_match_string(dev->of_node, "reg-names", "hd");
2560         /* Before BCM2711, we don't have a named register range */
2561         if (index < 0)
2562                 index = 1;
2563
2564         addr = of_get_address(dev->of_node, index, NULL, NULL);
2565
2566         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2567         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2568         vc4_hdmi->audio.dma_data.maxburst = 2;
2569
2570         /*
2571          * NOTE: Strictly speaking, we should probably use a DRM-managed
2572          * registration there to avoid removing all the audio components
2573          * by the time the driver doesn't have any user anymore.
2574          *
2575          * However, the ASoC core uses a number of devm_kzalloc calls
2576          * when registering, even when using non-device-managed
2577          * functions (such as in snd_soc_register_component()).
2578          *
2579          * If we call snd_soc_unregister_component() in a DRM-managed
2580          * action, the device-managed actions have already been executed
2581          * and thus we would access memory that has been freed.
2582          *
2583          * Using device-managed hooks here probably leaves us open to a
2584          * bunch of issues if userspace still has a handle on the ALSA
2585          * device when the device is removed. However, this is mitigated
2586          * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2587          * path to prevent the access to the device resources if it
2588          * isn't there anymore.
2589          *
2590          * Then, the vc4_hdmi structure is DRM-managed and thus only
2591          * freed whenever the last user has closed the DRM device file.
2592          * It should thus outlive ALSA in most situations.
2593          */
2594         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2595         if (ret) {
2596                 dev_err(dev, "Could not register PCM component: %d\n", ret);
2597                 return ret;
2598         }
2599
2600         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2601                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
2602         if (ret) {
2603                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2604                 return ret;
2605         }
2606
2607         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
2608                                                    PLATFORM_DEVID_AUTO,
2609                                                    &vc4_hdmi_codec_pdata,
2610                                                    sizeof(vc4_hdmi_codec_pdata));
2611         if (IS_ERR(codec_pdev)) {
2612                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
2613                 return PTR_ERR(codec_pdev);
2614         }
2615         vc4_hdmi->audio.codec_pdev = codec_pdev;
2616
2617         ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi);
2618         if (ret)
2619                 return ret;
2620
2621         dai_link->cpus          = &vc4_hdmi->audio.cpu;
2622         dai_link->codecs        = &vc4_hdmi->audio.codec;
2623         dai_link->platforms     = &vc4_hdmi->audio.platform;
2624
2625         dai_link->num_cpus      = 1;
2626         dai_link->num_codecs    = 1;
2627         dai_link->num_platforms = 1;
2628
2629         dai_link->name = "MAI";
2630         dai_link->stream_name = "MAI PCM";
2631         dai_link->codecs->dai_name = "i2s-hifi";
2632         dai_link->cpus->dai_name = dev_name(dev);
2633         dai_link->codecs->name = dev_name(&codec_pdev->dev);
2634         dai_link->platforms->name = dev_name(dev);
2635
2636         card->dai_link = dai_link;
2637         card->num_links = 1;
2638         card->name = vc4_hdmi->variant->card_name;
2639         card->driver_name = "vc4-hdmi";
2640         card->dev = dev;
2641         card->owner = THIS_MODULE;
2642
2643         /*
2644          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2645          * stores a pointer to the snd card object in dev->driver_data. This
2646          * means we cannot use it for something else. The hdmi back-pointer is
2647          * now stored in card->drvdata and should be retrieved with
2648          * snd_soc_card_get_drvdata() if needed.
2649          */
2650         snd_soc_card_set_drvdata(card, vc4_hdmi);
2651         ret = devm_snd_soc_register_card(dev, card);
2652         if (ret)
2653                 dev_err_probe(dev, ret, "Could not register sound card\n");
2654
2655         return ret;
2656
2657 }
2658
2659 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2660 {
2661         struct vc4_hdmi *vc4_hdmi = priv;
2662         struct drm_connector *connector = &vc4_hdmi->connector;
2663         struct drm_device *dev = connector->dev;
2664
2665         if (dev && dev->registered)
2666                 drm_connector_helper_hpd_irq_event(connector);
2667
2668         return IRQ_HANDLED;
2669 }
2670
2671 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2672 {
2673         struct drm_connector *connector = &vc4_hdmi->connector;
2674         struct platform_device *pdev = vc4_hdmi->pdev;
2675         int ret;
2676
2677         if (vc4_hdmi->variant->external_irq_controller) {
2678                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2679                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2680
2681                 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2682                                                 NULL,
2683                                                 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2684                                                 "vc4 hdmi hpd connected", vc4_hdmi);
2685                 if (ret)
2686                         return ret;
2687
2688                 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2689                                                 NULL,
2690                                                 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2691                                                 "vc4 hdmi hpd disconnected", vc4_hdmi);
2692                 if (ret)
2693                         return ret;
2694
2695                 connector->polled = DRM_CONNECTOR_POLL_HPD;
2696         }
2697
2698         return 0;
2699 }
2700
2701 #ifdef CONFIG_DRM_VC4_HDMI_CEC
2702 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2703 {
2704         struct vc4_hdmi *vc4_hdmi = priv;
2705
2706         if (vc4_hdmi->cec_rx_msg.len)
2707                 cec_received_msg(vc4_hdmi->cec_adap,
2708                                  &vc4_hdmi->cec_rx_msg);
2709
2710         return IRQ_HANDLED;
2711 }
2712
2713 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2714 {
2715         struct vc4_hdmi *vc4_hdmi = priv;
2716
2717         if (vc4_hdmi->cec_tx_ok) {
2718                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2719                                   0, 0, 0, 0);
2720         } else {
2721                 /*
2722                  * This CEC implementation makes 1 retry, so if we
2723                  * get a NACK, then that means it made 2 attempts.
2724                  */
2725                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2726                                   0, 2, 0, 0);
2727         }
2728         return IRQ_HANDLED;
2729 }
2730
2731 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2732 {
2733         struct vc4_hdmi *vc4_hdmi = priv;
2734         irqreturn_t ret;
2735
2736         if (vc4_hdmi->cec_irq_was_rx)
2737                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2738         else
2739                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2740
2741         return ret;
2742 }
2743
2744 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2745 {
2746         struct drm_device *dev = vc4_hdmi->connector.dev;
2747         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2748         unsigned int i;
2749
2750         lockdep_assert_held(&vc4_hdmi->hw_lock);
2751
2752         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2753                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2754
2755         if (msg->len > 16) {
2756                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2757                 return;
2758         }
2759
2760         for (i = 0; i < msg->len; i += 4) {
2761                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2762
2763                 msg->msg[i] = val & 0xff;
2764                 msg->msg[i + 1] = (val >> 8) & 0xff;
2765                 msg->msg[i + 2] = (val >> 16) & 0xff;
2766                 msg->msg[i + 3] = (val >> 24) & 0xff;
2767         }
2768 }
2769
2770 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2771 {
2772         u32 cntrl1;
2773
2774         /*
2775          * We don't need to protect the register access using
2776          * drm_dev_enter() there because the interrupt handler lifetime
2777          * is tied to the device itself, and not to the DRM device.
2778          *
2779          * So when the device will be gone, one of the first thing we
2780          * will be doing will be to unregister the interrupt handler,
2781          * and then unregister the DRM device. drm_dev_enter() would
2782          * thus always succeed if we are here.
2783          */
2784
2785         lockdep_assert_held(&vc4_hdmi->hw_lock);
2786
2787         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2788         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2789         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2790         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2791
2792         return IRQ_WAKE_THREAD;
2793 }
2794
2795 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2796 {
2797         struct vc4_hdmi *vc4_hdmi = priv;
2798         irqreturn_t ret;
2799
2800         spin_lock(&vc4_hdmi->hw_lock);
2801         ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2802         spin_unlock(&vc4_hdmi->hw_lock);
2803
2804         return ret;
2805 }
2806
2807 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2808 {
2809         u32 cntrl1;
2810
2811         lockdep_assert_held(&vc4_hdmi->hw_lock);
2812
2813         /*
2814          * We don't need to protect the register access using
2815          * drm_dev_enter() there because the interrupt handler lifetime
2816          * is tied to the device itself, and not to the DRM device.
2817          *
2818          * So when the device will be gone, one of the first thing we
2819          * will be doing will be to unregister the interrupt handler,
2820          * and then unregister the DRM device. drm_dev_enter() would
2821          * thus always succeed if we are here.
2822          */
2823
2824         vc4_hdmi->cec_rx_msg.len = 0;
2825         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2826         vc4_cec_read_msg(vc4_hdmi, cntrl1);
2827         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2828         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2829         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2830
2831         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2832
2833         return IRQ_WAKE_THREAD;
2834 }
2835
2836 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
2837 {
2838         struct vc4_hdmi *vc4_hdmi = priv;
2839         irqreturn_t ret;
2840
2841         spin_lock(&vc4_hdmi->hw_lock);
2842         ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2843         spin_unlock(&vc4_hdmi->hw_lock);
2844
2845         return ret;
2846 }
2847
2848 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2849 {
2850         struct vc4_hdmi *vc4_hdmi = priv;
2851         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2852         irqreturn_t ret;
2853         u32 cntrl5;
2854
2855         /*
2856          * We don't need to protect the register access using
2857          * drm_dev_enter() there because the interrupt handler lifetime
2858          * is tied to the device itself, and not to the DRM device.
2859          *
2860          * So when the device will be gone, one of the first thing we
2861          * will be doing will be to unregister the interrupt handler,
2862          * and then unregister the DRM device. drm_dev_enter() would
2863          * thus always succeed if we are here.
2864          */
2865
2866         if (!(stat & VC4_HDMI_CPU_CEC))
2867                 return IRQ_NONE;
2868
2869         spin_lock(&vc4_hdmi->hw_lock);
2870         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2871         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2872         if (vc4_hdmi->cec_irq_was_rx)
2873                 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2874         else
2875                 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2876
2877         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2878         spin_unlock(&vc4_hdmi->hw_lock);
2879
2880         return ret;
2881 }
2882
2883 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2884 {
2885         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2886         struct drm_device *drm = vc4_hdmi->connector.dev;
2887         /* clock period in microseconds */
2888         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2889         unsigned long flags;
2890         u32 val;
2891         int ret;
2892         int idx;
2893
2894         /*
2895          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2896          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2897          * .detect or .get_modes might call .adap_enable, which leads to this
2898          * function being called with that mutex held.
2899          *
2900          * Concurrency is not an issue for the moment since we don't share any
2901          * state with KMS, so we can ignore the lock for now, but we need to
2902          * keep it in mind if we were to change that assumption.
2903          */
2904
2905         if (!drm_dev_enter(drm, &idx))
2906                 /*
2907                  * We can't return an error code, because the CEC
2908                  * framework will emit WARN_ON messages at unbind
2909                  * otherwise.
2910                  */
2911                 return 0;
2912
2913         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2914         if (ret) {
2915                 drm_dev_exit(idx);
2916                 return ret;
2917         }
2918
2919         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2920
2921         val = HDMI_READ(HDMI_CEC_CNTRL_5);
2922         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2923                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2924                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2925         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2926                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2927
2928         HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2929                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2930         HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2931         HDMI_WRITE(HDMI_CEC_CNTRL_2,
2932                    ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2933                    ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2934                    ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2935                    ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2936                    ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2937         HDMI_WRITE(HDMI_CEC_CNTRL_3,
2938                    ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2939                    ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2940                    ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2941                    ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2942         HDMI_WRITE(HDMI_CEC_CNTRL_4,
2943                    ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2944                    ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2945                    ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2946                    ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2947
2948         if (!vc4_hdmi->variant->external_irq_controller)
2949                 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2950
2951         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2952
2953         drm_dev_exit(idx);
2954
2955         return 0;
2956 }
2957
2958 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2959 {
2960         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2961         struct drm_device *drm = vc4_hdmi->connector.dev;
2962         unsigned long flags;
2963         int idx;
2964
2965         if (!drm_dev_enter(drm, &idx))
2966                 /*
2967                  * We can't return an error code, because the CEC
2968                  * framework will emit WARN_ON messages at unbind
2969                  * otherwise.
2970                  */
2971                 return 0;
2972
2973         /*
2974          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2975          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2976          * .detect or .get_modes might call .adap_enable, which leads to this
2977          * function being called with that mutex held.
2978          *
2979          * Concurrency is not an issue for the moment since we don't share any
2980          * state with KMS, so we can ignore the lock for now, but we need to
2981          * keep it in mind if we were to change that assumption.
2982          */
2983
2984         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2985
2986         if (!vc4_hdmi->variant->external_irq_controller)
2987                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2988
2989         HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2990                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2991
2992         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2993
2994         pm_runtime_put(&vc4_hdmi->pdev->dev);
2995
2996         drm_dev_exit(idx);
2997
2998         return 0;
2999 }
3000
3001 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
3002 {
3003         if (enable)
3004                 return vc4_hdmi_cec_enable(adap);
3005         else
3006                 return vc4_hdmi_cec_disable(adap);
3007 }
3008
3009 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
3010 {
3011         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
3012         struct drm_device *drm = vc4_hdmi->connector.dev;
3013         unsigned long flags;
3014         int idx;
3015
3016         /*
3017          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
3018          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
3019          * .detect or .get_modes might call .adap_enable, which leads to this
3020          * function being called with that mutex held.
3021          *
3022          * Concurrency is not an issue for the moment since we don't share any
3023          * state with KMS, so we can ignore the lock for now, but we need to
3024          * keep it in mind if we were to change that assumption.
3025          */
3026
3027         if (!drm_dev_enter(drm, &idx))
3028                 /*
3029                  * We can't return an error code, because the CEC
3030                  * framework will emit WARN_ON messages at unbind
3031                  * otherwise.
3032                  */
3033                 return 0;
3034
3035         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3036         HDMI_WRITE(HDMI_CEC_CNTRL_1,
3037                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
3038                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
3039         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3040
3041         drm_dev_exit(idx);
3042
3043         return 0;
3044 }
3045
3046 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
3047                                       u32 signal_free_time, struct cec_msg *msg)
3048 {
3049         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
3050         struct drm_device *dev = vc4_hdmi->connector.dev;
3051         unsigned long flags;
3052         u32 val;
3053         unsigned int i;
3054         int idx;
3055
3056         /*
3057          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
3058          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
3059          * .detect or .get_modes might call .adap_enable, which leads to this
3060          * function being called with that mutex held.
3061          *
3062          * Concurrency is not an issue for the moment since we don't share any
3063          * state with KMS, so we can ignore the lock for now, but we need to
3064          * keep it in mind if we were to change that assumption.
3065          */
3066
3067         if (!drm_dev_enter(dev, &idx))
3068                 return -ENODEV;
3069
3070         if (msg->len > 16) {
3071                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
3072                 drm_dev_exit(idx);
3073                 return -ENOMEM;
3074         }
3075
3076         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3077
3078         for (i = 0; i < msg->len; i += 4)
3079                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
3080                            (msg->msg[i]) |
3081                            (msg->msg[i + 1] << 8) |
3082                            (msg->msg[i + 2] << 16) |
3083                            (msg->msg[i + 3] << 24));
3084
3085         val = HDMI_READ(HDMI_CEC_CNTRL_1);
3086         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
3087         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
3088         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
3089         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
3090         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
3091
3092         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
3093
3094         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3095
3096         drm_dev_exit(idx);
3097
3098         return 0;
3099 }
3100
3101 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
3102         .adap_enable = vc4_hdmi_cec_adap_enable,
3103         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
3104         .adap_transmit = vc4_hdmi_cec_adap_transmit,
3105 };
3106
3107 static void vc4_hdmi_cec_release(void *ptr)
3108 {
3109         struct vc4_hdmi *vc4_hdmi = ptr;
3110
3111         cec_unregister_adapter(vc4_hdmi->cec_adap);
3112         vc4_hdmi->cec_adap = NULL;
3113 }
3114
3115 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3116 {
3117         struct cec_connector_info conn_info;
3118         struct platform_device *pdev = vc4_hdmi->pdev;
3119         struct device *dev = &pdev->dev;
3120         unsigned long flags;
3121         int ret;
3122
3123         if (!of_find_property(dev->of_node, "interrupts", NULL)) {
3124                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
3125                 return 0;
3126         }
3127
3128         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
3129                                                   vc4_hdmi, "vc4",
3130                                                   CEC_CAP_DEFAULTS |
3131                                                   CEC_CAP_CONNECTOR_INFO, 1);
3132         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
3133         if (ret < 0)
3134                 return ret;
3135
3136         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
3137         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
3138
3139         if (vc4_hdmi->variant->external_irq_controller) {
3140                 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
3141                                                 vc4_cec_irq_handler_rx_bare,
3142                                                 vc4_cec_irq_handler_rx_thread, 0,
3143                                                 "vc4 hdmi cec rx", vc4_hdmi);
3144                 if (ret)
3145                         goto err_delete_cec_adap;
3146
3147                 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
3148                                                 vc4_cec_irq_handler_tx_bare,
3149                                                 vc4_cec_irq_handler_tx_thread, 0,
3150                                                 "vc4 hdmi cec tx", vc4_hdmi);
3151                 if (ret)
3152                         goto err_delete_cec_adap;
3153         } else {
3154                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3155                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3156                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3157
3158                 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
3159                                                 vc4_cec_irq_handler,
3160                                                 vc4_cec_irq_handler_thread, 0,
3161                                                 "vc4 hdmi cec", vc4_hdmi);
3162                 if (ret)
3163                         goto err_delete_cec_adap;
3164         }
3165
3166         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
3167         if (ret < 0)
3168                 goto err_delete_cec_adap;
3169
3170         /*
3171          * NOTE: Strictly speaking, we should probably use a DRM-managed
3172          * registration there to avoid removing the CEC adapter by the
3173          * time the DRM driver doesn't have any user anymore.
3174          *
3175          * However, the CEC framework already cleans up the CEC adapter
3176          * only when the last user has closed its file descriptor, so we
3177          * don't need to handle it in DRM.
3178          *
3179          * By the time the device-managed hook is executed, we will give
3180          * up our reference to the CEC adapter and therefore don't
3181          * really care when it's actually freed.
3182          *
3183          * There's still a problematic sequence: if we unregister our
3184          * CEC adapter, but the userspace keeps a handle on the CEC
3185          * adapter but not the DRM device for some reason. In such a
3186          * case, our vc4_hdmi structure will be freed, but the
3187          * cec_adapter structure will have a dangling pointer to what
3188          * used to be our HDMI controller. If we get a CEC call at that
3189          * moment, we could end up with a use-after-free. Fortunately,
3190          * the CEC framework already handles this too, by calling
3191          * cec_is_registered() in cec_ioctl() and cec_poll().
3192          */
3193         ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
3194         if (ret)
3195                 return ret;
3196
3197         return 0;
3198
3199 err_delete_cec_adap:
3200         cec_delete_adapter(vc4_hdmi->cec_adap);
3201
3202         return ret;
3203 }
3204
3205 static int vc4_hdmi_cec_resume(struct vc4_hdmi *vc4_hdmi)
3206 {
3207         unsigned long flags;
3208         u32 value;
3209
3210         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3211         value = HDMI_READ(HDMI_CEC_CNTRL_1);
3212         /* Set the logical address to Unregistered */
3213         value |= VC4_HDMI_CEC_ADDR_MASK;
3214         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3215         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3216
3217         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3218
3219         if (!vc4_hdmi->variant->external_irq_controller) {
3220                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3221                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3222                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3223         }
3224
3225         return 0;
3226 }
3227 #else
3228 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3229 {
3230         return 0;
3231 }
3232
3233 static int vc4_hdmi_cec_resume(struct vc4_hdmi *vc4_hdmi)
3234 {
3235         return 0;
3236 }
3237 #endif
3238
3239 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
3240 {
3241         struct debugfs_reg32 *regs = ptr;
3242
3243         kfree(regs);
3244 }
3245
3246 static int vc4_hdmi_build_regset(struct drm_device *drm,
3247                                  struct vc4_hdmi *vc4_hdmi,
3248                                  struct debugfs_regset32 *regset,
3249                                  enum vc4_hdmi_regs reg)
3250 {
3251         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
3252         struct debugfs_reg32 *regs, *new_regs;
3253         unsigned int count = 0;
3254         unsigned int i;
3255         int ret;
3256
3257         regs = kcalloc(variant->num_registers, sizeof(*regs),
3258                        GFP_KERNEL);
3259         if (!regs)
3260                 return -ENOMEM;
3261
3262         for (i = 0; i < variant->num_registers; i++) {
3263                 const struct vc4_hdmi_register *field = &variant->registers[i];
3264
3265                 if (field->reg != reg)
3266                         continue;
3267
3268                 regs[count].name = field->name;
3269                 regs[count].offset = field->offset;
3270                 count++;
3271         }
3272
3273         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
3274         if (!new_regs)
3275                 return -ENOMEM;
3276
3277         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
3278         regset->regs = new_regs;
3279         regset->nregs = count;
3280
3281         ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
3282         if (ret)
3283                 return ret;
3284
3285         return 0;
3286 }
3287
3288 static int vc4_hdmi_init_resources(struct drm_device *drm,
3289                                    struct vc4_hdmi *vc4_hdmi)
3290 {
3291         struct platform_device *pdev = vc4_hdmi->pdev;
3292         struct device *dev = &pdev->dev;
3293         int ret;
3294
3295         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
3296         if (IS_ERR(vc4_hdmi->hdmicore_regs))
3297                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
3298
3299         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
3300         if (IS_ERR(vc4_hdmi->hd_regs))
3301                 return PTR_ERR(vc4_hdmi->hd_regs);
3302
3303         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3304         if (ret)
3305                 return ret;
3306
3307         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3308         if (ret)
3309                 return ret;
3310
3311         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
3312         if (IS_ERR(vc4_hdmi->pixel_clock)) {
3313                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
3314                 if (ret != -EPROBE_DEFER)
3315                         DRM_ERROR("Failed to get pixel clock\n");
3316                 return ret;
3317         }
3318
3319         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3320         if (IS_ERR(vc4_hdmi->hsm_clock)) {
3321                 DRM_ERROR("Failed to get HDMI state machine clock\n");
3322                 return PTR_ERR(vc4_hdmi->hsm_clock);
3323         }
3324         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
3325         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
3326
3327         return 0;
3328 }
3329
3330 static int vc5_hdmi_init_resources(struct drm_device *drm,
3331                                    struct vc4_hdmi *vc4_hdmi)
3332 {
3333         struct platform_device *pdev = vc4_hdmi->pdev;
3334         struct device *dev = &pdev->dev;
3335         struct resource *res;
3336         int ret;
3337
3338         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
3339         if (!res)
3340                 return -ENODEV;
3341
3342         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
3343                                                resource_size(res));
3344         if (!vc4_hdmi->hdmicore_regs)
3345                 return -ENOMEM;
3346
3347         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
3348         if (!res)
3349                 return -ENODEV;
3350
3351         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
3352         if (!vc4_hdmi->hd_regs)
3353                 return -ENOMEM;
3354
3355         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
3356         if (!res)
3357                 return -ENODEV;
3358
3359         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
3360         if (!vc4_hdmi->cec_regs)
3361                 return -ENOMEM;
3362
3363         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
3364         if (!res)
3365                 return -ENODEV;
3366
3367         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
3368         if (!vc4_hdmi->csc_regs)
3369                 return -ENOMEM;
3370
3371         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
3372         if (!res)
3373                 return -ENODEV;
3374
3375         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
3376         if (!vc4_hdmi->dvp_regs)
3377                 return -ENOMEM;
3378
3379         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
3380         if (!res)
3381                 return -ENODEV;
3382
3383         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
3384         if (!vc4_hdmi->phy_regs)
3385                 return -ENOMEM;
3386
3387         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
3388         if (!res)
3389                 return -ENODEV;
3390
3391         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
3392         if (!vc4_hdmi->ram_regs)
3393                 return -ENOMEM;
3394
3395         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
3396         if (!res)
3397                 return -ENODEV;
3398
3399         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
3400         if (!vc4_hdmi->rm_regs)
3401                 return -ENOMEM;
3402
3403         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3404         if (IS_ERR(vc4_hdmi->hsm_clock)) {
3405                 DRM_ERROR("Failed to get HDMI state machine clock\n");
3406                 return PTR_ERR(vc4_hdmi->hsm_clock);
3407         }
3408
3409         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3410         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3411                 DRM_ERROR("Failed to get pixel bvb clock\n");
3412                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3413         }
3414
3415         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3416         if (IS_ERR(vc4_hdmi->audio_clock)) {
3417                 DRM_ERROR("Failed to get audio clock\n");
3418                 return PTR_ERR(vc4_hdmi->audio_clock);
3419         }
3420
3421         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3422         if (IS_ERR(vc4_hdmi->cec_clock)) {
3423                 DRM_ERROR("Failed to get CEC clock\n");
3424                 return PTR_ERR(vc4_hdmi->cec_clock);
3425         }
3426
3427         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3428         if (IS_ERR(vc4_hdmi->reset)) {
3429                 DRM_ERROR("Failed to get HDMI reset line\n");
3430                 return PTR_ERR(vc4_hdmi->reset);
3431         }
3432
3433         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3434         if (ret)
3435                 return ret;
3436
3437         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3438         if (ret)
3439                 return ret;
3440
3441         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3442         if (ret)
3443                 return ret;
3444
3445         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3446         if (ret)
3447                 return ret;
3448
3449         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3450         if (ret)
3451                 return ret;
3452
3453         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3454         if (ret)
3455                 return ret;
3456
3457         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3458         if (ret)
3459                 return ret;
3460
3461         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3462         if (ret)
3463                 return ret;
3464
3465         return 0;
3466 }
3467
3468 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev)
3469 {
3470         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3471
3472         clk_disable_unprepare(vc4_hdmi->hsm_clock);
3473
3474         return 0;
3475 }
3476
3477 static int vc4_hdmi_runtime_resume(struct device *dev)
3478 {
3479         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3480         int ret;
3481
3482         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
3483         if (ret)
3484                 return ret;
3485
3486         if (vc4_hdmi->variant->reset)
3487                 vc4_hdmi->variant->reset(vc4_hdmi);
3488
3489         ret = vc4_hdmi_cec_resume(vc4_hdmi);
3490         if (ret) {
3491                 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3492                 return ret;
3493         }
3494
3495         return 0;
3496 }
3497
3498 static void vc4_hdmi_put_ddc_device(void *ptr)
3499 {
3500         struct vc4_hdmi *vc4_hdmi = ptr;
3501
3502         put_device(&vc4_hdmi->ddc->dev);
3503 }
3504
3505 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3506 {
3507         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3508         struct platform_device *pdev = to_platform_device(dev);
3509         struct drm_device *drm = dev_get_drvdata(master);
3510         struct vc4_hdmi *vc4_hdmi;
3511         struct drm_encoder *encoder;
3512         struct device_node *ddc_node;
3513         int ret;
3514
3515         vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3516         if (!vc4_hdmi)
3517                 return -ENOMEM;
3518
3519         ret = drmm_mutex_init(drm, &vc4_hdmi->mutex);
3520         if (ret)
3521                 return ret;
3522
3523         spin_lock_init(&vc4_hdmi->hw_lock);
3524         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3525
3526         dev_set_drvdata(dev, vc4_hdmi);
3527         encoder = &vc4_hdmi->encoder.base.base;
3528         vc4_hdmi->encoder.base.type = variant->encoder_type;
3529         vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3530         vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3531         vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3532         vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3533         vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3534         vc4_hdmi->pdev = pdev;
3535         vc4_hdmi->variant = variant;
3536
3537         /*
3538          * Since we don't know the state of the controller and its
3539          * display (if any), let's assume it's always enabled.
3540          * vc4_hdmi_disable_scrambling() will thus run at boot, make
3541          * sure it's disabled, and avoid any inconsistency.
3542          */
3543         if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3544                 vc4_hdmi->scdc_enabled = true;
3545
3546         ret = variant->init_resources(drm, vc4_hdmi);
3547         if (ret)
3548                 return ret;
3549
3550         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3551         if (!ddc_node) {
3552                 DRM_ERROR("Failed to find ddc node in device tree\n");
3553                 return -ENODEV;
3554         }
3555
3556         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3557         of_node_put(ddc_node);
3558         if (!vc4_hdmi->ddc) {
3559                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
3560                 return -EPROBE_DEFER;
3561         }
3562
3563         ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3564         if (ret)
3565                 return ret;
3566
3567         /* Only use the GPIO HPD pin if present in the DT, otherwise
3568          * we'll use the HDMI core's register.
3569          */
3570         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3571         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3572                 return PTR_ERR(vc4_hdmi->hpd_gpio);
3573         }
3574
3575         vc4_hdmi->disable_wifi_frequencies =
3576                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3577
3578         /*
3579          * If we boot without any cable connected to the HDMI connector,
3580          * the firmware will skip the HSM initialization and leave it
3581          * with a rate of 0, resulting in a bus lockup when we're
3582          * accessing the registers even if it's enabled.
3583          *
3584          * Let's put a sensible default at runtime_resume so that we
3585          * don't end up in this situation.
3586          */
3587         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
3588         if (ret)
3589                 return ret;
3590
3591         ret = devm_pm_runtime_enable(dev);
3592         if (ret)
3593                 return ret;
3594
3595         ret = pm_runtime_resume_and_get(dev);
3596         if (ret)
3597                 return ret;
3598
3599         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3600              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
3601             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3602                 clk_prepare_enable(vc4_hdmi->pixel_clock);
3603                 clk_prepare_enable(vc4_hdmi->hsm_clock);
3604                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3605         }
3606
3607         ret = drmm_encoder_init(drm, encoder,
3608                                 &vc4_hdmi_encoder_funcs,
3609                                 DRM_MODE_ENCODER_TMDS,
3610                                 NULL);
3611         if (ret)
3612                 goto err_put_runtime_pm;
3613
3614         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3615
3616         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3617         if (ret)
3618                 goto err_put_runtime_pm;
3619
3620         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3621         if (ret)
3622                 goto err_put_runtime_pm;
3623
3624         ret = vc4_hdmi_cec_init(vc4_hdmi);
3625         if (ret)
3626                 goto err_put_runtime_pm;
3627
3628         ret = vc4_hdmi_audio_init(vc4_hdmi);
3629         if (ret)
3630                 goto err_put_runtime_pm;
3631
3632         pm_runtime_put_sync(dev);
3633
3634         return 0;
3635
3636 err_put_runtime_pm:
3637         pm_runtime_put_sync(dev);
3638
3639         return ret;
3640 }
3641
3642 static const struct component_ops vc4_hdmi_ops = {
3643         .bind   = vc4_hdmi_bind,
3644 };
3645
3646 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3647 {
3648         return component_add(&pdev->dev, &vc4_hdmi_ops);
3649 }
3650
3651 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
3652 {
3653         component_del(&pdev->dev, &vc4_hdmi_ops);
3654         return 0;
3655 }
3656
3657 static const struct vc4_hdmi_variant bcm2835_variant = {
3658         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3659         .debugfs_name           = "hdmi_regs",
3660         .card_name              = "vc4-hdmi",
3661         .max_pixel_clock        = 162000000,
3662         .registers              = vc4_hdmi_fields,
3663         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
3664
3665         .init_resources         = vc4_hdmi_init_resources,
3666         .csc_setup              = vc4_hdmi_csc_setup,
3667         .reset                  = vc4_hdmi_reset,
3668         .set_timings            = vc4_hdmi_set_timings,
3669         .phy_init               = vc4_hdmi_phy_init,
3670         .phy_disable            = vc4_hdmi_phy_disable,
3671         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
3672         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
3673         .channel_map            = vc4_hdmi_channel_map,
3674         .supports_hdr           = false,
3675 };
3676
3677 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3678         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3679         .debugfs_name           = "hdmi0_regs",
3680         .card_name              = "vc4-hdmi-0",
3681         .max_pixel_clock        = 600000000,
3682         .registers              = vc5_hdmi_hdmi0_fields,
3683         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3684         .phy_lane_mapping       = {
3685                 PHY_LANE_0,
3686                 PHY_LANE_1,
3687                 PHY_LANE_2,
3688                 PHY_LANE_CK,
3689         },
3690         .unsupported_odd_h_timings      = true,
3691         .external_irq_controller        = true,
3692
3693         .init_resources         = vc5_hdmi_init_resources,
3694         .csc_setup              = vc5_hdmi_csc_setup,
3695         .reset                  = vc5_hdmi_reset,
3696         .set_timings            = vc5_hdmi_set_timings,
3697         .phy_init               = vc5_hdmi_phy_init,
3698         .phy_disable            = vc5_hdmi_phy_disable,
3699         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
3700         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
3701         .channel_map            = vc5_hdmi_channel_map,
3702         .supports_hdr           = true,
3703         .hp_detect              = vc5_hdmi_hp_detect,
3704 };
3705
3706 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3707         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
3708         .debugfs_name           = "hdmi1_regs",
3709         .card_name              = "vc4-hdmi-1",
3710         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
3711         .registers              = vc5_hdmi_hdmi1_fields,
3712         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3713         .phy_lane_mapping       = {
3714                 PHY_LANE_1,
3715                 PHY_LANE_0,
3716                 PHY_LANE_CK,
3717                 PHY_LANE_2,
3718         },
3719         .unsupported_odd_h_timings      = true,
3720         .external_irq_controller        = true,
3721
3722         .init_resources         = vc5_hdmi_init_resources,
3723         .csc_setup              = vc5_hdmi_csc_setup,
3724         .reset                  = vc5_hdmi_reset,
3725         .set_timings            = vc5_hdmi_set_timings,
3726         .phy_init               = vc5_hdmi_phy_init,
3727         .phy_disable            = vc5_hdmi_phy_disable,
3728         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
3729         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
3730         .channel_map            = vc5_hdmi_channel_map,
3731         .supports_hdr           = true,
3732         .hp_detect              = vc5_hdmi_hp_detect,
3733 };
3734
3735 static const struct of_device_id vc4_hdmi_dt_match[] = {
3736         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3737         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3738         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3739         {}
3740 };
3741
3742 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3743         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3744                            vc4_hdmi_runtime_resume,
3745                            NULL)
3746 };
3747
3748 struct platform_driver vc4_hdmi_driver = {
3749         .probe = vc4_hdmi_dev_probe,
3750         .remove = vc4_hdmi_dev_remove,
3751         .driver = {
3752                 .name = "vc4_hdmi",
3753                 .of_match_table = vc4_hdmi_dt_match,
3754                 .pm = &vc4_hdmi_pm_ops,
3755         },
3756 };