drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_drv.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_probe_helper.h>
  38 #include <drm/drm_simple_kms_helper.h>
  39 #include <drm/drm_scdc_helper.h>
  40 #include <linux/clk.h>
  41 #include <linux/component.h>
  42 #include <linux/gpio/consumer.h>
  43 #include <linux/i2c.h>
  44 #include <linux/module.h>
  45 #include <linux/moduleparam.h>
  46 #include <linux/of_address.h>
  47 #include <linux/of_gpio.h>
  48 #include <linux/of_platform.h>
  49 #include <linux/pm_runtime.h>
  50 #include <linux/rational.h>
  51 #include <linux/reset.h>
  52 #include <sound/dmaengine_pcm.h>
  53 #include <sound/hdmi-codec.h>
  54 #include <sound/pcm_drm_eld.h>
  55 #include <sound/pcm_params.h>
  56 #include <sound/soc.h>
  57 #include "media/cec.h"
  58 #include "vc4_drv.h"
  59 #include "vc4_hdmi.h"
  60 #include "vc4_hdmi_regs.h"
  61 #include "vc4_regs.h"
  62
  63 /*
  64  * "Broadcast RGB" property.
  65  * Allows overriding of HDMI full or limited range RGB
  66  */
  67 #define VC4_BROADCAST_RGB_AUTO 0
  68 #define VC4_BROADCAST_RGB_FULL 1
  69 #define VC4_BROADCAST_RGB_LIMITED 2
  70
  71 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  72 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  73 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  74 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  75 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  76 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  77
  78 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  79 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  80 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  81 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  82
  83 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  84 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  85 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  86 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  87 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  88 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  89
  90 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  91 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  92
  93 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  94 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  95 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  96 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  97
  98 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  99
 100 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
 101 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
 102
 103 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
 104 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
 105
 106 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
 107
 108 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
 109 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
 110
 111 # define VC4_HD_M_SW_RST                        BIT(2)
 112 # define VC4_HD_M_ENABLE                        BIT(0)
 113
 114 #define HSM_MIN_CLOCK_FREQ      120000000
 115 #define CEC_CLOCK_FREQ 40000
 116
 117 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 118
 119 /* bit field to force hotplug detection. bit0 = HDMI0 */
 120 static int force_hotplug = 0;
 121 module_param(force_hotplug, int, 0644);
 122
 123 static const char * const output_format_str[] = {
 124         [VC4_HDMI_OUTPUT_RGB]           = "RGB",
 125         [VC4_HDMI_OUTPUT_YUV420]        = "YUV 4:2:0",
 126         [VC4_HDMI_OUTPUT_YUV422]        = "YUV 4:2:2",
 127         [VC4_HDMI_OUTPUT_YUV444]        = "YUV 4:4:4",
 128 };
 129
 130 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt)
 131 {
 132         if (fmt >= ARRAY_SIZE(output_format_str))
 133                 return "invalid";
 134
 135         return output_format_str[fmt];
 136 }
 137
 138 static unsigned long long
 139 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
 140                                     unsigned int bpc, enum vc4_hdmi_output_format fmt);
 141
 142 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder)
 143 {
 144         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 145         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 146
 147         lockdep_assert_held(&vc4_hdmi->mutex);
 148
 149         if (!display->is_hdmi)
 150                 return false;
 151
 152         if (!display->hdmi.scdc.supported ||
 153             !display->hdmi.scdc.scrambling.supported)
 154                 return false;
 155
 156         return true;
 157 }
 158
 159 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
 160                                            unsigned int bpc,
 161                                            enum vc4_hdmi_output_format fmt)
 162 {
 163         unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
 164
 165         return clock > HDMI_14_MAX_TMDS_CLK;
 166 }
 167
 168 static bool vc4_hdmi_is_full_range(struct vc4_hdmi *vc4_hdmi,
 169                                    const struct drm_display_mode *mode)
 170 {
 171         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 172
 173         if (vc4_hdmi->broadcast_rgb == VC4_BROADCAST_RGB_LIMITED)
 174                 return false;
 175         else if (vc4_hdmi->broadcast_rgb == VC4_BROADCAST_RGB_FULL)
 176                 return true;
 177         return !display->is_hdmi ||
 178                 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
 179 }
 180
 181 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 182 {
 183         struct drm_info_node *node = (struct drm_info_node *)m->private;
 184         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
 185         struct drm_device *drm = vc4_hdmi->connector.dev;
 186         struct drm_printer p = drm_seq_file_printer(m);
 187         int idx;
 188
 189         if (!drm_dev_enter(drm, &idx))
 190                 return -ENODEV;
 191
 192         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 193         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 194         drm_print_regset32(&p, &vc4_hdmi->cec_regset);
 195         drm_print_regset32(&p, &vc4_hdmi->csc_regset);
 196         drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
 197         drm_print_regset32(&p, &vc4_hdmi->phy_regset);
 198         drm_print_regset32(&p, &vc4_hdmi->ram_regset);
 199         drm_print_regset32(&p, &vc4_hdmi->rm_regset);
 200
 201         drm_dev_exit(idx);
 202
 203         return 0;
 204 }
 205
 206 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 207 {
 208         struct drm_device *drm = vc4_hdmi->connector.dev;
 209         unsigned long flags;
 210         int idx;
 211
 212         /*
 213          * We can be called by our bind callback, when the
 214          * connector->dev pointer might not be initialised yet.
 215          */
 216         if (drm && !drm_dev_enter(drm, &idx))
 217                 return;
 218
 219         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 220
 221         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 222         udelay(1);
 223         HDMI_WRITE(HDMI_M_CTL, 0);
 224
 225         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 226
 227         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 228                    VC4_HDMI_SW_RESET_HDMI |
 229                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 230
 231         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 232
 233         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 234
 235         if (drm)
 236                 drm_dev_exit(idx);
 237 }
 238
 239 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 240 {
 241         struct drm_device *drm = vc4_hdmi->connector.dev;
 242         unsigned long flags;
 243         int idx;
 244
 245         /*
 246          * We can be called by our bind callback, when the
 247          * connector->dev pointer might not be initialised yet.
 248          */
 249         if (drm && !drm_dev_enter(drm, &idx))
 250                 return;
 251
 252         reset_control_reset(vc4_hdmi->reset);
 253
 254         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 255
 256         HDMI_WRITE(HDMI_DVP_CTL, 0);
 257
 258         HDMI_WRITE(HDMI_CLOCK_STOP,
 259                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 260
 261         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 262
 263         if (drm)
 264                 drm_dev_exit(idx);
 265 }
 266
 267 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 268 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 269 {
 270         struct drm_device *drm = vc4_hdmi->connector.dev;
 271         unsigned long cec_rate;
 272         unsigned long flags;
 273         u16 clk_cnt;
 274         u32 value;
 275         int idx;
 276
 277         /*
 278          * This function is called by our runtime_resume implementation
 279          * and thus at bind time, when we haven't registered our
 280          * connector yet and thus don't have a pointer to the DRM
 281          * device.
 282          */
 283         if (drm && !drm_dev_enter(drm, &idx))
 284                 return;
 285
 286         cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
 287
 288         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 289
 290         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 291         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 292
 293         /*
 294          * Set the clock divider: the hsm_clock rate and this divider
 295          * setting will give a 40 kHz CEC clock.
 296          */
 297         clk_cnt = cec_rate / CEC_CLOCK_FREQ;
 298         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 299         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 300
 301         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 302
 303         if (drm)
 304                 drm_dev_exit(idx);
 305 }
 306 #else
 307 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 308 #endif
 309
 310 static int reset_pipe(struct drm_crtc *crtc,
 311                         struct drm_modeset_acquire_ctx *ctx)
 312 {
 313         struct drm_atomic_state *state;
 314         struct drm_crtc_state *crtc_state;
 315         int ret;
 316
 317         state = drm_atomic_state_alloc(crtc->dev);
 318         if (!state)
 319                 return -ENOMEM;
 320
 321         state->acquire_ctx = ctx;
 322
 323         crtc_state = drm_atomic_get_crtc_state(state, crtc);
 324         if (IS_ERR(crtc_state)) {
 325                 ret = PTR_ERR(crtc_state);
 326                 goto out;
 327         }
 328
 329         crtc_state->connectors_changed = true;
 330
 331         ret = drm_atomic_commit(state);
 332 out:
 333         drm_atomic_state_put(state);
 334
 335         return ret;
 336 }
 337
 338 static int vc4_hdmi_reset_link(struct drm_connector *connector,
 339                                struct drm_modeset_acquire_ctx *ctx)
 340 {
 341         struct drm_device *drm = connector->dev;
 342         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 343         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
 344         struct drm_connector_state *conn_state;
 345         struct drm_crtc_state *crtc_state;
 346         struct drm_crtc *crtc;
 347         bool scrambling_needed;
 348         u8 config;
 349         int ret;
 350
 351         if (!connector)
 352                 return 0;
 353
 354         ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx);
 355         if (ret)
 356                 return ret;
 357
 358         conn_state = connector->state;
 359         crtc = conn_state->crtc;
 360         if (!crtc)
 361                 return 0;
 362
 363         ret = drm_modeset_lock(&crtc->mutex, ctx);
 364         if (ret)
 365                 return ret;
 366
 367         crtc_state = crtc->state;
 368         if (!crtc_state->active)
 369                 return 0;
 370
 371         if (!vc4_hdmi_supports_scrambling(encoder))
 372                 return 0;
 373
 374         scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
 375                                                            vc4_hdmi->output_bpc,
 376                                                            vc4_hdmi->output_format);
 377         if (!scrambling_needed)
 378                 return 0;
 379
 380         if (conn_state->commit &&
 381             !try_wait_for_completion(&conn_state->commit->hw_done))
 382                 return 0;
 383
 384         ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
 385         if (ret < 0) {
 386                 drm_err(drm, "Failed to read TMDS config: %d\n", ret);
 387                 return 0;
 388         }
 389
 390         if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed)
 391                 return 0;
 392
 393         /*
 394          * HDMI 2.0 says that one should not send scrambled data
 395          * prior to configuring the sink scrambling, and that
 396          * TMDS clock/data transmission should be suspended when
 397          * changing the TMDS clock rate in the sink. So let's
 398          * just do a full modeset here, even though some sinks
 399          * would be perfectly happy if were to just reconfigure
 400          * the SCDC settings on the fly.
 401          */
 402         return reset_pipe(crtc, ctx);
 403 }
 404
 405 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi,
 406                                     struct drm_modeset_acquire_ctx *ctx,
 407                                     enum drm_connector_status status)
 408 {
 409         struct drm_connector *connector = &vc4_hdmi->connector;
 410         struct edid *edid;
 411
 412         /*
 413          * NOTE: This function should really be called with
 414          * vc4_hdmi->mutex held, but doing so results in reentrancy
 415          * issues since cec_s_phys_addr_from_edid might call
 416          * .adap_enable, which leads to that funtion being called with
 417          * our mutex held.
 418          *
 419          * A similar situation occurs with
 420          * drm_atomic_helper_connector_hdmi_reset_link() that will call
 421          * into our KMS hooks if the scrambling was enabled.
 422          *
 423          * Concurrency isn't an issue at the moment since we don't share
 424          * any state with any of the other frameworks so we can ignore
 425          * the lock for now.
 426          */
 427
 428         if (status == connector->status)
 429                 return;
 430
 431         if (status == connector_status_disconnected) {
 432                 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 433                 return;
 434         }
 435
 436         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 437         if (!edid)
 438                 return;
 439
 440         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 441         kfree(edid);
 442
 443         vc4_hdmi_reset_link(connector, ctx);
 444 }
 445
 446 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
 447                                          struct drm_modeset_acquire_ctx *ctx,
 448                                          bool force)
 449 {
 450         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 451         enum drm_connector_status status = connector_status_disconnected;
 452
 453         /*
 454          * NOTE: This function should really take vc4_hdmi->mutex, but
 455          * doing so results in reentrancy issues since
 456          * vc4_hdmi_handle_hotplug() can call into other functions that
 457          * would take the mutex while it's held here.
 458          *
 459          * Concurrency isn't an issue at the moment since we don't share
 460          * any state with any of the other frameworks so we can ignore
 461          * the lock for now.
 462          */
 463
 464         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 465
 466         if (force_hotplug & BIT(vc4_hdmi->encoder.type - VC4_ENCODER_TYPE_HDMI0))
 467                 status = connector_status_connected;
 468         else if (vc4_hdmi->hpd_gpio) {
 469                 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
 470                         status = connector_status_connected;
 471         } else {
 472                 if (vc4_hdmi->variant->hp_detect &&
 473                     vc4_hdmi->variant->hp_detect(vc4_hdmi))
 474                         status = connector_status_connected;
 475         }
 476
 477         vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status);
 478         pm_runtime_put(&vc4_hdmi->pdev->dev);
 479
 480         return status;
 481 }
 482
 483 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 484 {
 485         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 486         struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
 487         int ret = 0;
 488         struct edid *edid;
 489
 490         /*
 491          * NOTE: This function should really take vc4_hdmi->mutex, but
 492          * doing so results in reentrancy issues since
 493          * cec_s_phys_addr_from_edid might call .adap_enable, which
 494          * leads to that funtion being called with our mutex held.
 495          *
 496          * Concurrency isn't an issue at the moment since we don't share
 497          * any state with any of the other frameworks so we can ignore
 498          * the lock for now.
 499          */
 500
 501         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 502         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 503         if (!edid)
 504                 return -ENODEV;
 505
 506         drm_connector_update_edid_property(connector, edid);
 507         ret = drm_add_edid_modes(connector, edid);
 508         kfree(edid);
 509
 510         if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) {
 511                 struct drm_device *drm = connector->dev;
 512                 const struct drm_display_mode *mode;
 513
 514                 list_for_each_entry(mode, &connector->probed_modes, head) {
 515                         if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) {
 516                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 517                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 518                         }
 519                 }
 520         }
 521
 522         return ret;
 523 }
 524
 525 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 526                                            struct drm_atomic_state *state)
 527 {
 528         struct drm_connector_state *old_state =
 529                 drm_atomic_get_old_connector_state(state, connector);
 530         struct vc4_hdmi_connector_state *old_vc4_state = conn_state_to_vc4_hdmi_conn_state(old_state);
 531         struct drm_connector_state *new_state =
 532                 drm_atomic_get_new_connector_state(state, connector);
 533         struct vc4_hdmi_connector_state *new_vc4_state = conn_state_to_vc4_hdmi_conn_state(new_state);
 534         struct drm_crtc *crtc = new_state->crtc;
 535
 536         if (!crtc)
 537                 return 0;
 538
 539         if (old_state->colorspace != new_state->colorspace ||
 540             old_vc4_state->broadcast_rgb != new_vc4_state->broadcast_rgb ||
 541             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 542                 struct drm_crtc_state *crtc_state;
 543
 544                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 545                 if (IS_ERR(crtc_state))
 546                         return PTR_ERR(crtc_state);
 547
 548                 crtc_state->mode_changed = true;
 549         }
 550
 551         return 0;
 552 }
 553
 554 /**
 555  * vc4_hdmi_connector_atomic_get_property - hook for
 556  *                                              connector->atomic_get_property.
 557  * @connector: Connector to get the property for.
 558  * @state: Connector state to retrieve the property from.
 559  * @property: Property to retrieve.
 560  * @val: Return value for the property.
 561  *
 562  * Returns the atomic property value for a digital connector.
 563  */
 564 int vc4_hdmi_connector_get_property(struct drm_connector *connector,
 565                                     const struct drm_connector_state *state,
 566                                     struct drm_property *property,
 567                                     uint64_t *val)
 568 {
 569         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 570         const struct vc4_hdmi_connector_state *vc4_conn_state =
 571                                 const_conn_state_to_vc4_hdmi_conn_state(state);
 572
 573         if (property == vc4_hdmi->broadcast_rgb_property) {
 574                 *val = vc4_conn_state->broadcast_rgb;
 575         } else {
 576                 DRM_DEBUG_ATOMIC("Unknown property [PROP:%d:%s]\n",
 577                                  property->base.id, property->name);
 578                 return -EINVAL;
 579         }
 580
 581         return 0;
 582 }
 583
 584 /**
 585  * vc4_hdmi_connector_atomic_set_property - hook for
 586  *                                              connector->atomic_set_property.
 587  * @connector: Connector to set the property for.
 588  * @state: Connector state to set the property on.
 589  * @property: Property to set.
 590  * @val: New value for the property.
 591  *
 592  * Sets the atomic property value for a digital connector.
 593  */
 594 int vc4_hdmi_connector_set_property(struct drm_connector *connector,
 595                                     struct drm_connector_state *state,
 596                                     struct drm_property *property,
 597                                     uint64_t val)
 598 {
 599         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 600         struct vc4_hdmi_connector_state *vc4_conn_state =
 601                                 conn_state_to_vc4_hdmi_conn_state(state);
 602
 603         if (property == vc4_hdmi->broadcast_rgb_property) {
 604                 vc4_conn_state->broadcast_rgb = val;
 605                 return 0;
 606         }
 607
 608         DRM_DEBUG_ATOMIC("Unknown property [PROP:%d:%s]\n",
 609                          property->base.id, property->name);
 610         return -EINVAL;
 611 }
 612
 613 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 614 {
 615         struct vc4_hdmi_connector_state *old_state =
 616                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 617         struct vc4_hdmi_connector_state *new_state =
 618                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 619
 620         if (connector->state)
 621                 __drm_atomic_helper_connector_destroy_state(connector->state);
 622
 623         kfree(old_state);
 624         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 625
 626         if (!new_state)
 627                 return;
 628
 629         new_state->base.max_bpc = 8;
 630         new_state->base.max_requested_bpc = 8;
 631         new_state->output_format = VC4_HDMI_OUTPUT_RGB;
 632         drm_atomic_helper_connector_tv_reset(connector);
 633 }
 634
 635 static struct drm_connector_state *
 636 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 637 {
 638         struct drm_connector_state *conn_state = connector->state;
 639         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 640         struct vc4_hdmi_connector_state *new_state;
 641
 642         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 643         if (!new_state)
 644                 return NULL;
 645
 646         new_state->pixel_rate = vc4_state->pixel_rate;
 647         new_state->output_bpc = vc4_state->output_bpc;
 648         new_state->output_format = vc4_state->output_format;
 649         new_state->broadcast_rgb = vc4_state->broadcast_rgb;
 650         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 651
 652         return &new_state->base;
 653 }
 654
 655 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 656         .fill_modes = drm_helper_probe_single_connector_modes,
 657         .reset = vc4_hdmi_connector_reset,
 658         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 659         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 660         .atomic_get_property = vc4_hdmi_connector_get_property,
 661         .atomic_set_property = vc4_hdmi_connector_set_property,
 662 };
 663
 664 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 665         .detect_ctx = vc4_hdmi_connector_detect_ctx,
 666         .get_modes = vc4_hdmi_connector_get_modes,
 667         .atomic_check = vc4_hdmi_connector_atomic_check,
 668 };
 669
 670 static const struct drm_prop_enum_list broadcast_rgb_names[] = {
 671         { VC4_BROADCAST_RGB_AUTO, "Automatic" },
 672         { VC4_BROADCAST_RGB_FULL, "Full" },
 673         { VC4_BROADCAST_RGB_LIMITED, "Limited 16:235" },
 674 };
 675
 676 static void
 677 vc4_hdmi_attach_broadcast_rgb_property(struct drm_device *dev,
 678                                        struct vc4_hdmi *vc4_hdmi)
 679 {
 680         struct drm_property *prop = vc4_hdmi->broadcast_rgb_property;
 681
 682         if (!prop) {
 683                 prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
 684                                                 "Broadcast RGB",
 685                                                 broadcast_rgb_names,
 686                                                 ARRAY_SIZE(broadcast_rgb_names));
 687                 if (!prop)
 688                         return;
 689
 690                 vc4_hdmi->broadcast_rgb_property = prop;
 691         }
 692
 693         drm_object_attach_property(&vc4_hdmi->connector.base, prop, 0);
 694 }
 695
 696 static int vc4_hdmi_connector_init(struct drm_device *dev,
 697                                    struct vc4_hdmi *vc4_hdmi)
 698 {
 699         struct drm_connector *connector = &vc4_hdmi->connector;
 700         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
 701         int ret;
 702
 703         ret = drmm_connector_init(dev, connector,
 704                                   &vc4_hdmi_connector_funcs,
 705                                   DRM_MODE_CONNECTOR_HDMIA,
 706                                   vc4_hdmi->ddc);
 707         if (ret)
 708                 return ret;
 709
 710         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 711
 712         /*
 713          * Some of the properties below require access to state, like bpc.
 714          * Allocate some default initial connector state with our reset helper.
 715          */
 716         if (connector->funcs->reset)
 717                 connector->funcs->reset(connector);
 718
 719         /* Create and attach TV margin props to this connector. */
 720         ret = drm_mode_create_tv_margin_properties(dev);
 721         if (ret)
 722                 return ret;
 723
 724         ret = drm_mode_create_hdmi_colorspace_property(connector);
 725         if (ret)
 726                 return ret;
 727
 728         drm_connector_attach_colorspace_property(connector);
 729         drm_connector_attach_tv_margin_properties(connector);
 730         drm_connector_attach_max_bpc_property(connector, 8, 12);
 731
 732         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 733                              DRM_CONNECTOR_POLL_DISCONNECT);
 734
 735         connector->interlace_allowed = 1;
 736         connector->doublescan_allowed = 0;
 737         connector->stereo_allowed = 1;
 738
 739         if (vc4_hdmi->variant->supports_hdr)
 740                 drm_connector_attach_hdr_output_metadata_property(connector);
 741
 742         vc4_hdmi_attach_broadcast_rgb_property(dev, vc4_hdmi);
 743
 744         drm_connector_attach_encoder(connector, encoder);
 745
 746         return 0;
 747 }
 748
 749 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 750                                 enum hdmi_infoframe_type type,
 751                                 bool poll)
 752 {
 753         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 754         struct drm_device *drm = vc4_hdmi->connector.dev;
 755         u32 packet_id = type - 0x80;
 756         unsigned long flags;
 757         int ret = 0;
 758         int idx;
 759
 760         if (!drm_dev_enter(drm, &idx))
 761                 return -ENODEV;
 762
 763         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 764         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 765                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 766         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 767
 768         if (poll) {
 769                 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 770                                  BIT(packet_id)), 100);
 771         }
 772
 773         drm_dev_exit(idx);
 774         return ret;
 775 }
 776
 777 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 778                                      union hdmi_infoframe *frame)
 779 {
 780         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 781         struct drm_device *drm = vc4_hdmi->connector.dev;
 782         u32 packet_id = frame->any.type - 0x80;
 783         const struct vc4_hdmi_register *ram_packet_start =
 784                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 785         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 786         u32 packet_reg_next = ram_packet_start->offset +
 787                 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
 788         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 789                                                        ram_packet_start->reg);
 790         uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
 791         unsigned long flags;
 792         ssize_t len, i;
 793         int ret;
 794         int idx;
 795
 796         if (!drm_dev_enter(drm, &idx))
 797                 return;
 798
 799         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 800                     VC4_HDMI_RAM_PACKET_ENABLE),
 801                   "Packet RAM has to be on to store the packet.");
 802
 803         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 804         if (len < 0)
 805                 goto out;
 806
 807         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 808         if (ret) {
 809                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 810                 goto out;
 811         }
 812
 813         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 814
 815         for (i = 0; i < len; i += 7) {
 816                 writel(buffer[i + 0] << 0 |
 817                        buffer[i + 1] << 8 |
 818                        buffer[i + 2] << 16,
 819                        base + packet_reg);
 820                 packet_reg += 4;
 821
 822                 writel(buffer[i + 3] << 0 |
 823                        buffer[i + 4] << 8 |
 824                        buffer[i + 5] << 16 |
 825                        buffer[i + 6] << 24,
 826                        base + packet_reg);
 827                 packet_reg += 4;
 828         }
 829
 830         /*
 831          * clear remainder of packet ram as it's included in the
 832          * infoframe and triggers a checksum error on hdmi analyser
 833          */
 834         for (; packet_reg < packet_reg_next; packet_reg += 4)
 835                 writel(0, base + packet_reg);
 836
 837         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 838                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 839
 840         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 841
 842         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 843                         BIT(packet_id)), 100);
 844         if (ret)
 845                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 846
 847 out:
 848         drm_dev_exit(idx);
 849 }
 850
 851 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
 852                                               enum vc4_hdmi_output_format fmt)
 853 {
 854         switch (fmt) {
 855         case VC4_HDMI_OUTPUT_RGB:
 856                 frame->colorspace = HDMI_COLORSPACE_RGB;
 857                 break;
 858
 859         case VC4_HDMI_OUTPUT_YUV420:
 860                 frame->colorspace = HDMI_COLORSPACE_YUV420;
 861                 break;
 862
 863         case VC4_HDMI_OUTPUT_YUV422:
 864                 frame->colorspace = HDMI_COLORSPACE_YUV422;
 865                 break;
 866
 867         case VC4_HDMI_OUTPUT_YUV444:
 868                 frame->colorspace = HDMI_COLORSPACE_YUV444;
 869                 break;
 870
 871         default:
 872                 break;
 873         }
 874 }
 875
 876 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 877 {
 878         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 879         struct drm_connector *connector = &vc4_hdmi->connector;
 880         struct drm_connector_state *cstate = connector->state;
 881         struct vc4_hdmi_connector_state *vc4_state =
 882                 conn_state_to_vc4_hdmi_conn_state(cstate);
 883         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 884         union hdmi_infoframe frame;
 885         int ret;
 886
 887         lockdep_assert_held(&vc4_hdmi->mutex);
 888
 889         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 890                                                        connector, mode);
 891         if (ret < 0) {
 892                 DRM_ERROR("couldn't fill AVI infoframe\n");
 893                 return;
 894         }
 895
 896         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 897                                            connector, mode,
 898                                            vc4_hdmi_is_full_range(vc4_hdmi, mode) ?
 899                                            HDMI_QUANTIZATION_RANGE_FULL :
 900                                            HDMI_QUANTIZATION_RANGE_LIMITED);
 901         drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
 902         vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format);
 903         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 904
 905         vc4_hdmi_write_infoframe(encoder, &frame);
 906 }
 907
 908 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 909 {
 910         union hdmi_infoframe frame;
 911         int ret;
 912
 913         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 914         if (ret < 0) {
 915                 DRM_ERROR("couldn't fill SPD infoframe\n");
 916                 return;
 917         }
 918
 919         frame.spd.sdi = HDMI_SPD_SDI_PC;
 920
 921         vc4_hdmi_write_infoframe(encoder, &frame);
 922 }
 923
 924 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 925 {
 926         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 927         struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
 928         union hdmi_infoframe frame;
 929
 930         memcpy(&frame.audio, audio, sizeof(*audio));
 931         vc4_hdmi_write_infoframe(encoder, &frame);
 932 }
 933
 934 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 935 {
 936         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 937         struct drm_connector *connector = &vc4_hdmi->connector;
 938         struct drm_connector_state *conn_state = connector->state;
 939         union hdmi_infoframe frame;
 940
 941         lockdep_assert_held(&vc4_hdmi->mutex);
 942
 943         if (!vc4_hdmi->variant->supports_hdr)
 944                 return;
 945
 946         if (!conn_state->hdr_output_metadata)
 947                 return;
 948
 949         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 950                 return;
 951
 952         vc4_hdmi_write_infoframe(encoder, &frame);
 953 }
 954
 955 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 956 {
 957         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 958
 959         lockdep_assert_held(&vc4_hdmi->mutex);
 960
 961         vc4_hdmi_set_avi_infoframe(encoder);
 962         vc4_hdmi_set_spd_infoframe(encoder);
 963         /*
 964          * If audio was streaming, then we need to reenabled the audio
 965          * infoframe here during encoder_enable.
 966          */
 967         if (vc4_hdmi->audio.streaming)
 968                 vc4_hdmi_set_audio_infoframe(encoder);
 969
 970         vc4_hdmi_set_hdr_infoframe(encoder);
 971 }
 972
 973 #define SCRAMBLING_POLLING_DELAY_MS     1000
 974
 975 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 976 {
 977         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 978         struct drm_device *drm = vc4_hdmi->connector.dev;
 979         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 980         unsigned long flags;
 981         int idx;
 982
 983         lockdep_assert_held(&vc4_hdmi->mutex);
 984
 985         if (!vc4_hdmi_supports_scrambling(encoder))
 986                 return;
 987
 988         if (!vc4_hdmi_mode_needs_scrambling(mode,
 989                                             vc4_hdmi->output_bpc,
 990                                             vc4_hdmi->output_format))
 991                 return;
 992
 993         if (!drm_dev_enter(drm, &idx))
 994                 return;
 995
 996         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 997         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 998
 999         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1000         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
1001                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
1002         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1003
1004         drm_dev_exit(idx);
1005
1006         vc4_hdmi->scdc_enabled = true;
1007
1008         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
1009                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
1010 }
1011
1012 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
1013 {
1014         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1015         struct drm_device *drm = vc4_hdmi->connector.dev;
1016         unsigned long flags;
1017         int idx;
1018
1019         lockdep_assert_held(&vc4_hdmi->mutex);
1020
1021         if (!vc4_hdmi->scdc_enabled)
1022                 return;
1023
1024         vc4_hdmi->scdc_enabled = false;
1025
1026         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
1027                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
1028
1029         if (!drm_dev_enter(drm, &idx))
1030                 return;
1031
1032         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1033         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
1034                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
1035         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1036
1037         drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
1038         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
1039
1040         drm_dev_exit(idx);
1041 }
1042
1043 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
1044 {
1045         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
1046                                                  struct vc4_hdmi,
1047                                                  scrambling_work);
1048
1049         if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
1050                 return;
1051
1052         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
1053         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
1054
1055         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
1056                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
1057 }
1058
1059 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
1060                                                struct drm_atomic_state *state)
1061 {
1062         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1063         struct drm_device *drm = vc4_hdmi->connector.dev;
1064         unsigned long flags;
1065         int idx;
1066
1067         mutex_lock(&vc4_hdmi->mutex);
1068
1069         vc4_hdmi->output_enabled = false;
1070
1071         if (!drm_dev_enter(drm, &idx))
1072                 goto out;
1073
1074         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1075
1076         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
1077
1078         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
1079
1080         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1081
1082         mdelay(1);
1083
1084         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1085         HDMI_WRITE(HDMI_VID_CTL,
1086                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
1087         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1088
1089         vc4_hdmi_disable_scrambling(encoder);
1090
1091         drm_dev_exit(idx);
1092
1093 out:
1094         mutex_unlock(&vc4_hdmi->mutex);
1095 }
1096
1097 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
1098                                                  struct drm_atomic_state *state)
1099 {
1100         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1101         struct drm_device *drm = vc4_hdmi->connector.dev;
1102         unsigned long flags;
1103         int ret;
1104         int idx;
1105
1106         mutex_lock(&vc4_hdmi->mutex);
1107
1108         if (!drm_dev_enter(drm, &idx))
1109                 goto out;
1110
1111         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1112         HDMI_WRITE(HDMI_VID_CTL,
1113                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
1114         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1115
1116         if (vc4_hdmi->variant->phy_disable)
1117                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
1118
1119         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
1120         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1121
1122         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
1123         if (ret < 0)
1124                 DRM_ERROR("Failed to release power domain: %d\n", ret);
1125
1126         drm_dev_exit(idx);
1127
1128 out:
1129         mutex_unlock(&vc4_hdmi->mutex);
1130 }
1131
1132 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1133                                struct drm_connector_state *state,
1134                                const struct drm_display_mode *mode)
1135 {
1136         struct drm_device *drm = vc4_hdmi->connector.dev;
1137         unsigned long flags;
1138         u32 csc_ctl;
1139         int idx;
1140
1141         if (!drm_dev_enter(drm, &idx))
1142                 return;
1143
1144         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1145
1146         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
1147                                 VC4_HD_CSC_CTL_ORDER);
1148
1149         if (!vc4_hdmi_is_full_range(vc4_hdmi, mode)) {
1150                 /* CEA VICs other than #1 requre limited range RGB
1151                  * output unless overridden by an AVI infoframe.
1152                  * Apply a colorspace conversion to squash 0-255 down
1153                  * to 16-235.  The matrix here is:
1154                  *
1155                  * [ 0      0      0.8594 16]
1156                  * [ 0      0.8594 0      16]
1157                  * [ 0.8594 0      0      16]
1158                  * [ 0      0      0       1]
1159                  */
1160                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
1161                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
1162                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1163                                          VC4_HD_CSC_CTL_MODE);
1164
1165                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
1166                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
1167                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
1168                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
1169                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
1170                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
1171         }
1172
1173         /* The RGB order applies even when CSC is disabled. */
1174         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1175
1176         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1177
1178         drm_dev_exit(idx);
1179 }
1180
1181 /*
1182  * If we need to output Full Range RGB, then use the unity matrix
1183  *
1184  * [ 1      0      0      0]
1185  * [ 0      1      0      0]
1186  * [ 0      0      1      0]
1187  *
1188  * CEA VICs other than #1 require limited range RGB output unless
1189  * overridden by an AVI infoframe. Apply a colorspace conversion to
1190  * squash 0-255 down to 16-235. The matrix here is:
1191  *
1192  * [ 0.8594 0      0      16]
1193  * [ 0      0.8594 0      16]
1194  * [ 0      0      0.8594 16]
1195  *
1196  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1197  */
1198 static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = {
1199         {
1200                 /* Full range - unity */
1201                 { 0x2000, 0x0000, 0x0000, 0x0000 },
1202                 { 0x0000, 0x2000, 0x0000, 0x0000 },
1203                 { 0x0000, 0x0000, 0x2000, 0x0000 },
1204         }, {
1205                 /* Limited range */
1206                 { 0x1b80, 0x0000, 0x0000, 0x0400 },
1207                 { 0x0000, 0x1b80, 0x0000, 0x0400 },
1208                 { 0x0000, 0x0000, 0x1b80, 0x0400 },
1209         }
1210 };
1211
1212 /*
1213  * Conversion between Full Range RGB and YUV using the BT.601 Colorspace
1214  *
1215  * Full range
1216  * [    0.299000   0.587000   0.114000   0.000000 ]
1217  * [   -0.168736  -0.331264   0.500000 128.000000 ]
1218  * [    0.500000  -0.418688  -0.081312 128.000000 ]
1219  *
1220  * Limited range
1221  * [    0.255785   0.502160   0.097523  16.000000 ]
1222  * [   -0.147644  -0.289856   0.437500 128.000000 ]
1223  * [    0.437500  -0.366352  -0.071148 128.000000 ]
1224  *
1225  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1226  */
1227 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = {
1228         {
1229                 /* Full range */
1230                 { 0x0991, 0x12c9, 0x03a6, 0x0000 },
1231                 { 0xfa9b, 0xf567, 0x1000, 0x2000 },
1232                 { 0x1000, 0xf29b, 0xfd67, 0x2000 },
1233         }, {
1234                 /* Limited range */
1235                 { 0x082f, 0x1012, 0x031f, 0x0400 },
1236                 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1237                 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1238         }
1239 };
1240
1241 /*
1242  * Conversion between Full Range RGB and YUV using the BT.709 Colorspace
1243  *
1244  * Full range
1245  * [    0.212600   0.715200   0.072200   0.000000 ]
1246  * [   -0.114572  -0.385428   0.500000 128.000000 ]
1247  * [    0.500000  -0.454153  -0.045847 128.000000 ]
1248  *
1249  * Limited range
1250  * [    0.181873   0.611831   0.061765  16.000000 ]
1251  * [   -0.100251  -0.337249   0.437500 128.000000 ]
1252  * [    0.437500  -0.397384  -0.040116 128.000000 ]
1253  *
1254  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1255  */
1256 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = {
1257         {
1258                 /* Full range */
1259                 { 0x06ce, 0x16e3, 0x024f, 0x0000 },
1260                 { 0xfc56, 0xf3ac, 0x1000, 0x2000 },
1261                 { 0x1000, 0xf179, 0xfe89, 0x2000 },
1262         }, {
1263                 /* Limited range        */
1264                 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1265                 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1266                 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1267         }
1268 };
1269
1270 /*
1271  * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace
1272  *
1273  * Full range
1274  * [    0.262700   0.678000   0.059300   0.000000 ]
1275  * [   -0.139630  -0.360370   0.500000 128.000000 ]
1276  * [    0.500000  -0.459786  -0.040214 128.000000 ]
1277  *
1278  * Limited range
1279  * [    0.224732   0.580008   0.050729  16.000000 ]
1280  * [   -0.122176  -0.315324   0.437500 128.000000 ]
1281  * [    0.437500  -0.402312  -0.035188 128.000000 ]
1282  *
1283  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1284  */
1285 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = {
1286         {
1287                 /* Full range */
1288                 { 0x0868, 0x15b2, 0x01e6, 0x0000 },
1289                 { 0xfb89, 0xf479, 0x1000, 0x2000 },
1290                 { 0x1000, 0xf14a, 0xfeb8, 0x2000 },
1291         }, {
1292                 /* Limited range */
1293                 { 0x0731, 0x128f, 0x01a0, 0x0400 },
1294                 { 0xfc18, 0xf5ea, 0x0e00, 0x2000 },
1295                 { 0x0e00, 0xf321, 0xfee1, 0x2000 },
1296         }
1297 };
1298
1299 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1300                                     const u16 coeffs[3][4])
1301 {
1302         lockdep_assert_held(&vc4_hdmi->hw_lock);
1303
1304         HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1305         HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1306         HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1307         HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1308         HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1309         HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1310 }
1311
1312 static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi,
1313                                          const u16 coeffs[3][4])
1314 {
1315         lockdep_assert_held(&vc4_hdmi->hw_lock);
1316
1317         /* YUV444 needs the CSC matrices using the channels in a different order */
1318         HDMI_WRITE(HDMI_CSC_12_11, (coeffs[2][1] << 16) | coeffs[2][0]);
1319         HDMI_WRITE(HDMI_CSC_14_13, (coeffs[2][3] << 16) | coeffs[2][2]);
1320         HDMI_WRITE(HDMI_CSC_22_21, (coeffs[0][1] << 16) | coeffs[0][0]);
1321         HDMI_WRITE(HDMI_CSC_24_23, (coeffs[0][3] << 16) | coeffs[0][2]);
1322         HDMI_WRITE(HDMI_CSC_32_31, (coeffs[1][1] << 16) | coeffs[1][0]);
1323         HDMI_WRITE(HDMI_CSC_34_33, (coeffs[1][3] << 16) | coeffs[1][2]);
1324 }
1325
1326 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1327                                struct drm_connector_state *state,
1328                                const struct drm_display_mode *mode)
1329 {
1330         struct drm_device *drm = vc4_hdmi->connector.dev;
1331         struct vc4_hdmi_connector_state *vc4_state =
1332                 conn_state_to_vc4_hdmi_conn_state(state);
1333         unsigned int lim_range = vc4_hdmi_is_full_range(vc4_hdmi, mode) ? 0 : 1;
1334         const u16 (*csc)[4];
1335         unsigned long flags;
1336         u32 if_cfg = 0;
1337         u32 if_xbar = 0x543210;
1338         u32 csc_chan_ctl = 0;
1339         u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1340                                                                VC5_MT_CP_CSC_CTL_MODE);
1341         int idx;
1342
1343         if (!drm_dev_enter(drm, &idx))
1344                 return;
1345
1346         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1347
1348         switch (vc4_state->output_format) {
1349         case VC4_HDMI_OUTPUT_YUV444:
1350         case VC4_HDMI_OUTPUT_YUV422:
1351                 switch (state->colorspace) {
1352                 default:
1353                 case DRM_MODE_COLORIMETRY_NO_DATA:
1354                 case DRM_MODE_COLORIMETRY_BT709_YCC:
1355                 case DRM_MODE_COLORIMETRY_XVYCC_709:
1356                 case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED:
1357                 case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT:
1358                         csc = vc5_hdmi_csc_full_rgb_to_yuv_bt709[lim_range];
1359                         break;
1360                 case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC:
1361                 case DRM_MODE_COLORIMETRY_XVYCC_601:
1362                 case DRM_MODE_COLORIMETRY_SYCC_601:
1363                 case DRM_MODE_COLORIMETRY_OPYCC_601:
1364                 case DRM_MODE_COLORIMETRY_BT601_YCC:
1365                         csc = vc5_hdmi_csc_full_rgb_to_yuv_bt601[lim_range];
1366                         break;
1367                 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1368                 case DRM_MODE_COLORIMETRY_BT2020_YCC:
1369                 case DRM_MODE_COLORIMETRY_BT2020_RGB:
1370                 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1371                 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1372                         csc = vc5_hdmi_csc_full_rgb_to_yuv_bt2020[lim_range];
1373                         break;
1374                 }
1375
1376                 if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {
1377                         csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1378                                                  VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1379                                 VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1380                                 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1381
1382                         csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1383                                                       VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1384
1385                         if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1386                                                 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1387
1388                         vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc);
1389                 } else {
1390                         vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc);
1391                 }
1392
1393                 break;
1394
1395         case VC4_HDMI_OUTPUT_RGB:
1396                 if_xbar = 0x354021;
1397
1398                 vc5_hdmi_set_csc_coeffs(vc4_hdmi,
1399                                         vc5_hdmi_csc_full_rgb_to_rgb[lim_range]);
1400                 break;
1401
1402         default:
1403                 break;
1404         }
1405
1406         HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1407         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1408         HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1409         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1410
1411         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1412
1413         drm_dev_exit(idx);
1414 }
1415
1416 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1417                                  struct drm_connector_state *state,
1418                                  const struct drm_display_mode *mode)
1419 {
1420         struct drm_device *drm = vc4_hdmi->connector.dev;
1421         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1422         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1423         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1424         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1425         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1426                                    VC4_HDMI_VERTA_VSP) |
1427                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1428                                    VC4_HDMI_VERTA_VFP) |
1429                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1430         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1431                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1432                                    interlaced,
1433                                    VC4_HDMI_VERTB_VBP));
1434         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1435                           VC4_SET_FIELD(mode->crtc_vtotal -
1436                                         mode->crtc_vsync_end,
1437                                         VC4_HDMI_VERTB_VBP));
1438         unsigned long flags;
1439         u32 reg;
1440         int idx;
1441
1442         if (!drm_dev_enter(drm, &idx))
1443                 return;
1444
1445         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1446
1447         HDMI_WRITE(HDMI_HORZA,
1448                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1449                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1450                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1451                                  VC4_HDMI_HORZA_HAP));
1452
1453         HDMI_WRITE(HDMI_HORZB,
1454                    VC4_SET_FIELD((mode->htotal -
1455                                   mode->hsync_end) * pixel_rep,
1456                                  VC4_HDMI_HORZB_HBP) |
1457                    VC4_SET_FIELD((mode->hsync_end -
1458                                   mode->hsync_start) * pixel_rep,
1459                                  VC4_HDMI_HORZB_HSP) |
1460                    VC4_SET_FIELD((mode->hsync_start -
1461                                   mode->hdisplay) * pixel_rep,
1462                                  VC4_HDMI_HORZB_HFP));
1463
1464         HDMI_WRITE(HDMI_VERTA0, verta);
1465         HDMI_WRITE(HDMI_VERTA1, verta);
1466
1467         HDMI_WRITE(HDMI_VERTB0, vertb_even);
1468         HDMI_WRITE(HDMI_VERTB1, vertb);
1469
1470         reg = HDMI_READ(HDMI_MISC_CONTROL);
1471         reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1472         reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1473         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1474
1475         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1476
1477         drm_dev_exit(idx);
1478 }
1479
1480 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1481                                  struct drm_connector_state *state,
1482                                  const struct drm_display_mode *mode)
1483 {
1484         struct drm_device *drm = vc4_hdmi->connector.dev;
1485         const struct vc4_hdmi_connector_state *vc4_state =
1486                 conn_state_to_vc4_hdmi_conn_state(state);
1487         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1488         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1489         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1490         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1491         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1492                                    VC5_HDMI_VERTA_VSP) |
1493                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1494                                    VC5_HDMI_VERTA_VFP) |
1495                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1496         u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1497                                    VC5_HDMI_VERTB_VSPO) |
1498                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1499                                    interlaced,
1500                                    VC4_HDMI_VERTB_VBP));
1501         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1502                           VC4_SET_FIELD(mode->crtc_vtotal -
1503                                         mode->crtc_vsync_end,
1504                                         VC4_HDMI_VERTB_VBP));
1505         unsigned long flags;
1506         unsigned char gcp;
1507         bool gcp_en;
1508         u32 reg;
1509         int idx;
1510
1511         if (!drm_dev_enter(drm, &idx))
1512                 return;
1513
1514         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1515
1516         HDMI_WRITE(HDMI_HORZA,
1517                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1518                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1519                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1520                                  VC5_HDMI_HORZA_HAP) |
1521                    VC4_SET_FIELD((mode->hsync_start -
1522                                   mode->hdisplay) * pixel_rep,
1523                                  VC5_HDMI_HORZA_HFP));
1524
1525         HDMI_WRITE(HDMI_HORZB,
1526                    VC4_SET_FIELD((mode->htotal -
1527                                   mode->hsync_end) * pixel_rep,
1528                                  VC5_HDMI_HORZB_HBP) |
1529                    VC4_SET_FIELD((mode->hsync_end -
1530                                   mode->hsync_start) * pixel_rep,
1531                                  VC5_HDMI_HORZB_HSP));
1532
1533         HDMI_WRITE(HDMI_VERTA0, verta);
1534         HDMI_WRITE(HDMI_VERTA1, verta);
1535
1536         HDMI_WRITE(HDMI_VERTB0, vertb_even);
1537         HDMI_WRITE(HDMI_VERTB1, vertb);
1538
1539         switch (vc4_state->output_bpc) {
1540         case 12:
1541                 gcp = 6;
1542                 gcp_en = true;
1543                 break;
1544         case 10:
1545                 gcp = 5;
1546                 gcp_en = true;
1547                 break;
1548         case 8:
1549         default:
1550                 gcp = 4;
1551                 gcp_en = false;
1552                 break;
1553         }
1554
1555         /*
1556          * YCC422 is always 36-bit and not considered deep colour so
1557          * doesn't signal in GCP
1558          */
1559         if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {
1560                 gcp = 4;
1561                 gcp_en = false;
1562         }
1563
1564         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1565         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1566                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1567         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1568                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1569         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1570
1571         reg = HDMI_READ(HDMI_GCP_WORD_1);
1572         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1573         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1574         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1575
1576         reg = HDMI_READ(HDMI_GCP_CONFIG);
1577         reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1578         reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
1579         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1580
1581         reg = HDMI_READ(HDMI_MISC_CONTROL);
1582         reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1583         reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1584         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1585
1586         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1587
1588         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1589
1590         drm_dev_exit(idx);
1591 }
1592
1593 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1594 {
1595         struct drm_device *drm = vc4_hdmi->connector.dev;
1596         unsigned long flags;
1597         u32 drift;
1598         int ret;
1599         int idx;
1600
1601         if (!drm_dev_enter(drm, &idx))
1602                 return;
1603
1604         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1605
1606         drift = HDMI_READ(HDMI_FIFO_CTL);
1607         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1608
1609         HDMI_WRITE(HDMI_FIFO_CTL,
1610                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1611         HDMI_WRITE(HDMI_FIFO_CTL,
1612                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1613
1614         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1615
1616         usleep_range(1000, 1100);
1617
1618         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1619
1620         HDMI_WRITE(HDMI_FIFO_CTL,
1621                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1622         HDMI_WRITE(HDMI_FIFO_CTL,
1623                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1624
1625         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1626
1627         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1628                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1629         WARN_ONCE(ret, "Timeout waiting for "
1630                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1631
1632         drm_dev_exit(idx);
1633 }
1634
1635 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1636                                                 struct drm_atomic_state *state)
1637 {
1638         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1639         struct drm_device *drm = vc4_hdmi->connector.dev;
1640         struct drm_connector *connector = &vc4_hdmi->connector;
1641         struct drm_connector_state *conn_state =
1642                 drm_atomic_get_new_connector_state(state, connector);
1643         struct vc4_hdmi_connector_state *vc4_conn_state =
1644                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1645         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1646         unsigned long pixel_rate = vc4_conn_state->pixel_rate;
1647         unsigned long bvb_rate, hsm_rate;
1648         unsigned long flags;
1649         int ret;
1650         int idx;
1651
1652         mutex_lock(&vc4_hdmi->mutex);
1653
1654         if (!drm_dev_enter(drm, &idx))
1655                 goto out;
1656
1657         /*
1658          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1659          * be faster than pixel clock, infinitesimally faster, tested in
1660          * simulation. Otherwise, exact value is unimportant for HDMI
1661          * operation." This conflicts with bcm2835's vc4 documentation, which
1662          * states HSM's clock has to be at least 108% of the pixel clock.
1663          *
1664          * Real life tests reveal that vc4's firmware statement holds up, and
1665          * users are able to use pixel clocks closer to HSM's, namely for
1666          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1667          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1668          * 162MHz.
1669          *
1670          * Additionally, the AXI clock needs to be at least 25% of
1671          * pixel clock, but HSM ends up being the limiting factor.
1672          */
1673         hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
1674         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1675         if (ret) {
1676                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1677                 goto err_dev_exit;
1678         }
1679
1680         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1681         if (ret < 0) {
1682                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1683                 goto err_dev_exit;
1684         }
1685
1686         ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
1687         if (ret) {
1688                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1689                 goto err_put_runtime_pm;
1690         }
1691
1692         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1693         if (ret) {
1694                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1695                 goto err_put_runtime_pm;
1696         }
1697
1698
1699         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1700
1701         if (pixel_rate > 297000000)
1702                 bvb_rate = 300000000;
1703         else if (pixel_rate > 148500000)
1704                 bvb_rate = 150000000;
1705         else
1706                 bvb_rate = 75000000;
1707
1708         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1709         if (ret) {
1710                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1711                 goto err_disable_pixel_clock;
1712         }
1713
1714         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1715         if (ret) {
1716                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1717                 goto err_disable_pixel_clock;
1718         }
1719
1720         if (vc4_hdmi->variant->phy_init)
1721                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1722
1723         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1724
1725         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1726                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1727                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1728                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1729
1730         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1731
1732         if (vc4_hdmi->variant->set_timings)
1733                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1734
1735         drm_dev_exit(idx);
1736
1737         mutex_unlock(&vc4_hdmi->mutex);
1738
1739         return;
1740
1741 err_disable_pixel_clock:
1742         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1743 err_put_runtime_pm:
1744         pm_runtime_put(&vc4_hdmi->pdev->dev);
1745 err_dev_exit:
1746         drm_dev_exit(idx);
1747 out:
1748         mutex_unlock(&vc4_hdmi->mutex);
1749         return;
1750 }
1751
1752 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1753                                              struct drm_atomic_state *state)
1754 {
1755         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1756         struct drm_device *drm = vc4_hdmi->connector.dev;
1757         struct drm_connector *connector = &vc4_hdmi->connector;
1758         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1759         struct drm_connector_state *conn_state =
1760                 drm_atomic_get_new_connector_state(state, connector);
1761         unsigned long flags;
1762         int idx;
1763
1764         mutex_lock(&vc4_hdmi->mutex);
1765
1766         if (!drm_dev_enter(drm, &idx))
1767                 return;
1768
1769         if (vc4_hdmi->variant->csc_setup)
1770                 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1771
1772         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1773         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1774         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1775
1776         drm_dev_exit(idx);
1777
1778         mutex_unlock(&vc4_hdmi->mutex);
1779 }
1780
1781 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1782                                               struct drm_atomic_state *state)
1783 {
1784         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1785         struct drm_device *drm = vc4_hdmi->connector.dev;
1786         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1787         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1788         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1789         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1790         unsigned long flags;
1791         int ret;
1792         int idx;
1793
1794         mutex_lock(&vc4_hdmi->mutex);
1795
1796         if (!drm_dev_enter(drm, &idx))
1797                 return;
1798
1799         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1800
1801         HDMI_WRITE(HDMI_VID_CTL,
1802                    VC4_HD_VID_CTL_ENABLE |
1803                    VC4_HD_VID_CTL_CLRRGB |
1804                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1805                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1806                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1807                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1808
1809         HDMI_WRITE(HDMI_VID_CTL,
1810                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1811
1812         if (display->is_hdmi) {
1813                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1814                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1815                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1816
1817                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1818
1819                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1820                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1821                 WARN_ONCE(ret, "Timeout waiting for "
1822                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1823         } else {
1824                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1825                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1826                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1827                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1828                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1829                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1830
1831                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1832
1833                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1834                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1835                 WARN_ONCE(ret, "Timeout waiting for "
1836                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1837         }
1838
1839         if (display->is_hdmi) {
1840                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1841
1842                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1843                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1844
1845                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1846                            VC4_HDMI_RAM_PACKET_ENABLE);
1847
1848                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1849                 vc4_hdmi->output_enabled = true;
1850
1851                 vc4_hdmi_set_infoframes(encoder);
1852         }
1853
1854         vc4_hdmi_recenter_fifo(vc4_hdmi);
1855         vc4_hdmi_enable_scrambling(encoder);
1856
1857         drm_dev_exit(idx);
1858         mutex_unlock(&vc4_hdmi->mutex);
1859 }
1860
1861 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1862                                              struct drm_crtc_state *crtc_state,
1863                                              struct drm_connector_state *conn_state)
1864 {
1865         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1866         struct vc4_hdmi_connector_state *vc4_state =
1867                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1868
1869         mutex_lock(&vc4_hdmi->mutex);
1870         vc4_hdmi->output_bpc = vc4_state->output_bpc;
1871         vc4_hdmi->output_format = vc4_state->output_format;
1872         vc4_hdmi->broadcast_rgb = vc4_state->broadcast_rgb;
1873         memcpy(&vc4_hdmi->saved_adjusted_mode,
1874                &crtc_state->adjusted_mode,
1875                sizeof(vc4_hdmi->saved_adjusted_mode));
1876         mutex_unlock(&vc4_hdmi->mutex);
1877 }
1878
1879 static bool
1880 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi,
1881                                   const struct drm_display_info *info,
1882                                   const struct drm_display_mode *mode,
1883                                   unsigned int format, unsigned int bpc)
1884 {
1885         struct drm_device *dev = vc4_hdmi->connector.dev;
1886         u8 vic = drm_match_cea_mode(mode);
1887
1888         if (vic == 1 && bpc != 8) {
1889                 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc);
1890                 return false;
1891         }
1892
1893         if (!info->is_hdmi &&
1894             (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) {
1895                 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n");
1896                 return false;
1897         }
1898
1899         switch (format) {
1900         case VC4_HDMI_OUTPUT_RGB:
1901                 drm_dbg(dev, "RGB Format, checking the constraints.\n");
1902
1903                 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1904                         drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1905                         return false;
1906                 }
1907
1908                 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1909                         drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1910                         return false;
1911                 }
1912
1913                 drm_dbg(dev, "RGB format supported in that configuration.\n");
1914
1915                 return true;
1916
1917         case VC4_HDMI_OUTPUT_YUV422:
1918                 drm_dbg(dev, "YUV422 format, checking the constraints.\n");
1919
1920                 if (!(info->color_formats & DRM_COLOR_FORMAT_YCRCB422)) {
1921                         drm_dbg(dev, "Sink doesn't support YUV422.\n");
1922                         return false;
1923                 }
1924
1925                 if (bpc != 12) {
1926                         drm_dbg(dev, "YUV422 only supports 12 bpc.\n");
1927                         return false;
1928                 }
1929
1930                 drm_dbg(dev, "YUV422 format supported in that configuration.\n");
1931
1932                 return true;
1933
1934         case VC4_HDMI_OUTPUT_YUV444:
1935                 drm_dbg(dev, "YUV444 format, checking the constraints.\n");
1936
1937                 if (!(info->color_formats & DRM_COLOR_FORMAT_YCRCB444)) {
1938                         drm_dbg(dev, "Sink doesn't support YUV444.\n");
1939                         return false;
1940                 }
1941
1942                 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1943                         drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1944                         return false;
1945                 }
1946
1947                 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1948                         drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1949                         return false;
1950                 }
1951
1952                 drm_dbg(dev, "YUV444 format supported in that configuration.\n");
1953
1954                 return true;
1955         }
1956
1957         return false;
1958 }
1959
1960 static enum drm_mode_status
1961 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
1962                              unsigned long long clock)
1963 {
1964         const struct drm_connector *connector = &vc4_hdmi->connector;
1965         const struct drm_display_info *info = &connector->display_info;
1966         struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
1967
1968         if (clock > vc4_hdmi->variant->max_pixel_clock)
1969                 return MODE_CLOCK_HIGH;
1970
1971         if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK)
1972                 return MODE_CLOCK_HIGH;
1973
1974         if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000))
1975                 return MODE_CLOCK_HIGH;
1976
1977         return MODE_OK;
1978 }
1979
1980 static unsigned long long
1981 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
1982                                     unsigned int bpc,
1983                                     enum vc4_hdmi_output_format fmt)
1984 {
1985         unsigned long long clock = mode->clock * 1000;
1986
1987         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1988                 clock = clock * 2;
1989
1990         if (fmt == VC4_HDMI_OUTPUT_YUV422)
1991                 bpc = 8;
1992
1993         return clock * bpc / 8;
1994 }
1995
1996 static int
1997 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
1998                                struct vc4_hdmi_connector_state *vc4_state,
1999                                const struct drm_display_mode *mode,
2000                                unsigned int bpc, unsigned int fmt)
2001 {
2002         unsigned long long clock;
2003
2004         clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
2005         if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, clock) != MODE_OK)
2006                 return -EINVAL;
2007
2008         vc4_state->pixel_rate = clock;
2009
2010         return 0;
2011 }
2012
2013 static int
2014 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi,
2015                                 struct vc4_hdmi_connector_state *vc4_state,
2016                                 const struct drm_display_mode *mode,
2017                                 unsigned int bpc)
2018 {
2019         struct drm_device *dev = vc4_hdmi->connector.dev;
2020         const struct drm_connector *connector = &vc4_hdmi->connector;
2021         const struct drm_display_info *info = &connector->display_info;
2022         unsigned int format;
2023
2024         drm_dbg(dev, "Trying with an RGB output\n");
2025
2026         format = VC4_HDMI_OUTPUT_RGB;
2027         if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
2028                 int ret;
2029
2030                 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
2031                                                      mode, bpc, format);
2032                 if (!ret) {
2033                         vc4_state->output_format = format;
2034                         return 0;
2035                 }
2036         }
2037
2038         drm_dbg(dev, "Failed, Trying with an YUV422 output\n");
2039
2040         format = VC4_HDMI_OUTPUT_YUV422;
2041         if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
2042                 int ret;
2043
2044                 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
2045                                                      mode, bpc, format);
2046                 if (!ret) {
2047                         vc4_state->output_format = format;
2048                         return 0;
2049                 }
2050         }
2051
2052         drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n");
2053
2054         return -EINVAL;
2055 }
2056
2057 static int
2058 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi,
2059                                 struct vc4_hdmi_connector_state *vc4_state,
2060                                 const struct drm_display_mode *mode)
2061 {
2062         struct drm_device *dev = vc4_hdmi->connector.dev;
2063         struct drm_connector_state *conn_state = &vc4_state->base;
2064         unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12);
2065         unsigned int bpc;
2066         int ret;
2067
2068         for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
2069                 drm_dbg(dev, "Trying with a %d bpc output\n", bpc);
2070
2071                 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state,
2072                                                       mode, bpc);
2073                 if (ret)
2074                         continue;
2075
2076                 vc4_state->output_bpc = bpc;
2077
2078                 drm_dbg(dev,
2079                         "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n",
2080                         mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
2081                         vc4_state->output_bpc,
2082                         vc4_hdmi_output_fmt_str(vc4_state->output_format),
2083                         vc4_state->pixel_rate);
2084
2085                 break;
2086         }
2087
2088         return ret;
2089 }
2090
2091 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
2092 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
2093
2094 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
2095                                          struct drm_crtc_state *crtc_state,
2096                                          struct drm_connector_state *conn_state)
2097 {
2098         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
2099         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
2100         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
2101         struct drm_connector *connector = &vc4_hdmi->connector;
2102         struct drm_connector_state *old_conn_state = drm_atomic_get_old_connector_state(conn_state->state, connector);
2103         struct vc4_hdmi_connector_state *old_vc4_state = conn_state_to_vc4_hdmi_conn_state(old_conn_state);
2104         unsigned long long pixel_rate = mode->clock * 1000;
2105         unsigned long long tmds_rate;
2106         int ret;
2107
2108         if (vc4_hdmi->variant->unsupported_odd_h_timings) {
2109                 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2110                         /* Only try to fixup DBLCLK modes to get 480i and 576i
2111                          * working.
2112                          * A generic solution for all modes with odd horizontal
2113                          * timing values seems impossible based on trying to
2114                          * solve it for 1366x768 monitors.
2115                          */
2116                         if ((mode->hsync_start - mode->hdisplay) & 1)
2117                                 mode->hsync_start--;
2118                         if ((mode->hsync_end - mode->hsync_start) & 1)
2119                                 mode->hsync_end--;
2120                 }
2121
2122                 /* Now check whether we still have odd values remaining */
2123                 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
2124                     (mode->hsync_end % 2) || (mode->htotal % 2))
2125                         return -EINVAL;
2126         }
2127
2128         /*
2129          * The 1440p@60 pixel rate is in the same range than the first
2130          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
2131          * bandwidth). Slightly lower the frequency to bring it out of
2132          * the WiFi range.
2133          */
2134         tmds_rate = pixel_rate * 10;
2135         if (vc4_hdmi->disable_wifi_frequencies &&
2136             (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
2137              tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
2138                 mode->clock = 238560;
2139                 pixel_rate = mode->clock * 1000;
2140         }
2141
2142         ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode);
2143         if (ret)
2144                 return ret;
2145
2146         /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */
2147         if (vc4_state->output_bpc != old_vc4_state->output_bpc ||
2148             vc4_state->output_format != old_vc4_state->output_format)
2149                 crtc_state->mode_changed = true;
2150
2151         return 0;
2152 }
2153
2154 static enum drm_mode_status
2155 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
2156                             const struct drm_display_mode *mode)
2157 {
2158         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
2159
2160         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
2161             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
2162             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
2163              (mode->hsync_end % 2) || (mode->htotal % 2)))
2164                 return MODE_H_ILLEGAL;
2165
2166         return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode->clock * 1000);
2167 }
2168
2169 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
2170         .atomic_check = vc4_hdmi_encoder_atomic_check,
2171         .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
2172         .mode_valid = vc4_hdmi_encoder_mode_valid,
2173 };
2174
2175 static int vc4_hdmi_late_register(struct drm_encoder *encoder)
2176 {
2177         struct drm_device *drm = encoder->dev;
2178         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
2179         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2180         int ret;
2181
2182         ret = vc4_debugfs_add_file(drm->primary, variant->debugfs_name,
2183                                    vc4_hdmi_debugfs_regs,
2184                                    vc4_hdmi);
2185         if (ret)
2186                 return ret;
2187
2188         return 0;
2189 }
2190
2191 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
2192         .late_register = vc4_hdmi_late_register,
2193 };
2194
2195 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2196 {
2197         int i;
2198         u32 channel_map = 0;
2199
2200         for (i = 0; i < 8; i++) {
2201                 if (channel_mask & BIT(i))
2202                         channel_map |= i << (3 * i);
2203         }
2204         return channel_map;
2205 }
2206
2207 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2208 {
2209         int i;
2210         u32 channel_map = 0;
2211
2212         for (i = 0; i < 8; i++) {
2213                 if (channel_mask & BIT(i))
2214                         channel_map |= i << (4 * i);
2215         }
2216         return channel_map;
2217 }
2218
2219 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
2220 {
2221         struct drm_device *drm = vc4_hdmi->connector.dev;
2222         unsigned long flags;
2223         u32 hotplug;
2224         int idx;
2225
2226         if (!drm_dev_enter(drm, &idx))
2227                 return false;
2228
2229         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2230         hotplug = HDMI_READ(HDMI_HOTPLUG);
2231         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2232
2233         drm_dev_exit(idx);
2234
2235         return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
2236 }
2237
2238 /* HDMI audio codec callbacks */
2239 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
2240                                          unsigned int samplerate)
2241 {
2242         struct drm_device *drm = vc4_hdmi->connector.dev;
2243         u32 hsm_clock;
2244         unsigned long flags;
2245         unsigned long n, m;
2246         int idx;
2247
2248         if (!drm_dev_enter(drm, &idx))
2249                 return;
2250
2251         hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
2252         rational_best_approximation(hsm_clock, samplerate,
2253                                     VC4_HD_MAI_SMP_N_MASK >>
2254                                     VC4_HD_MAI_SMP_N_SHIFT,
2255                                     (VC4_HD_MAI_SMP_M_MASK >>
2256                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
2257                                     &n, &m);
2258
2259         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2260         HDMI_WRITE(HDMI_MAI_SMP,
2261                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
2262                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
2263         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2264
2265         drm_dev_exit(idx);
2266 }
2267
2268 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
2269 {
2270         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
2271         u32 n, cts;
2272         u64 tmp;
2273
2274         lockdep_assert_held(&vc4_hdmi->mutex);
2275         lockdep_assert_held(&vc4_hdmi->hw_lock);
2276
2277         n = 128 * samplerate / 1000;
2278         tmp = (u64)(mode->clock * 1000) * n;
2279         do_div(tmp, 128 * samplerate);
2280         cts = tmp;
2281
2282         HDMI_WRITE(HDMI_CRP_CFG,
2283                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
2284                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
2285
2286         /*
2287          * We could get slightly more accurate clocks in some cases by
2288          * providing a CTS_1 value.  The two CTS values are alternated
2289          * between based on the period fields
2290          */
2291         HDMI_WRITE(HDMI_CTS_0, cts);
2292         HDMI_WRITE(HDMI_CTS_1, cts);
2293 }
2294
2295 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
2296 {
2297         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
2298
2299         return snd_soc_card_get_drvdata(card);
2300 }
2301
2302 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
2303 {
2304         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
2305
2306         lockdep_assert_held(&vc4_hdmi->mutex);
2307
2308         /*
2309          * If the encoder is currently in DVI mode, treat the codec DAI
2310          * as missing.
2311          */
2312         if (!display->is_hdmi)
2313                 return false;
2314
2315         return true;
2316 }
2317
2318 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
2319 {
2320         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2321         struct drm_device *drm = vc4_hdmi->connector.dev;
2322         unsigned long flags;
2323         int ret = 0;
2324         int idx;
2325
2326         mutex_lock(&vc4_hdmi->mutex);
2327
2328         if (!drm_dev_enter(drm, &idx)) {
2329                 ret = -ENODEV;
2330                 goto out;
2331         }
2332
2333         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2334                 ret = -ENODEV;
2335                 goto out_dev_exit;
2336         }
2337
2338         vc4_hdmi->audio.streaming = true;
2339
2340         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2341         HDMI_WRITE(HDMI_MAI_CTL,
2342                    VC4_HD_MAI_CTL_RESET |
2343                    VC4_HD_MAI_CTL_FLUSH |
2344                    VC4_HD_MAI_CTL_DLATE |
2345                    VC4_HD_MAI_CTL_ERRORE |
2346                    VC4_HD_MAI_CTL_ERRORF);
2347         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2348
2349         if (vc4_hdmi->variant->phy_rng_enable)
2350                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
2351
2352 out_dev_exit:
2353         drm_dev_exit(idx);
2354 out:
2355         mutex_unlock(&vc4_hdmi->mutex);
2356
2357         return ret;
2358 }
2359
2360 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
2361 {
2362         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2363         struct device *dev = &vc4_hdmi->pdev->dev;
2364         unsigned long flags;
2365         int ret;
2366
2367         lockdep_assert_held(&vc4_hdmi->mutex);
2368
2369         vc4_hdmi->audio.streaming = false;
2370         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
2371         if (ret)
2372                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
2373
2374         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2375
2376         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
2377         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
2378         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
2379
2380         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2381 }
2382
2383 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
2384 {
2385         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2386         struct drm_device *drm = vc4_hdmi->connector.dev;
2387         unsigned long flags;
2388         int idx;
2389
2390         mutex_lock(&vc4_hdmi->mutex);
2391
2392         if (!drm_dev_enter(drm, &idx))
2393                 goto out;
2394
2395         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2396
2397         HDMI_WRITE(HDMI_MAI_CTL,
2398                    VC4_HD_MAI_CTL_DLATE |
2399                    VC4_HD_MAI_CTL_ERRORE |
2400                    VC4_HD_MAI_CTL_ERRORF);
2401
2402         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2403
2404         if (vc4_hdmi->variant->phy_rng_disable)
2405                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
2406
2407         vc4_hdmi->audio.streaming = false;
2408         vc4_hdmi_audio_reset(vc4_hdmi);
2409
2410         drm_dev_exit(idx);
2411
2412 out:
2413         mutex_unlock(&vc4_hdmi->mutex);
2414 }
2415
2416 static int sample_rate_to_mai_fmt(int samplerate)
2417 {
2418         switch (samplerate) {
2419         case 8000:
2420                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
2421         case 11025:
2422                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
2423         case 12000:
2424                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
2425         case 16000:
2426                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
2427         case 22050:
2428                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
2429         case 24000:
2430                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
2431         case 32000:
2432                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
2433         case 44100:
2434                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
2435         case 48000:
2436                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
2437         case 64000:
2438                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
2439         case 88200:
2440                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
2441         case 96000:
2442                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
2443         case 128000:
2444                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2445         case 176400:
2446                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2447         case 192000:
2448                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2449         default:
2450                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2451         }
2452 }
2453
2454 /* HDMI audio codec callbacks */
2455 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
2456                                   struct hdmi_codec_daifmt *daifmt,
2457                                   struct hdmi_codec_params *params)
2458 {
2459         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2460         struct drm_device *drm = vc4_hdmi->connector.dev;
2461         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2462         unsigned int sample_rate = params->sample_rate;
2463         unsigned int channels = params->channels;
2464         unsigned long flags;
2465         u32 audio_packet_config, channel_mask;
2466         u32 channel_map;
2467         u32 mai_audio_format;
2468         u32 mai_sample_rate;
2469         int ret = 0;
2470         int idx;
2471
2472         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2473                 sample_rate, params->sample_width, channels);
2474
2475         mutex_lock(&vc4_hdmi->mutex);
2476
2477         if (!drm_dev_enter(drm, &idx)) {
2478                 ret = -ENODEV;
2479                 goto out;
2480         }
2481
2482         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2483                 ret = -EINVAL;
2484                 goto out_dev_exit;
2485         }
2486
2487         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2488
2489         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2490         HDMI_WRITE(HDMI_MAI_CTL,
2491                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2492                    VC4_HD_MAI_CTL_WHOLSMP |
2493                    VC4_HD_MAI_CTL_CHALIGN |
2494                    VC4_HD_MAI_CTL_ENABLE);
2495
2496         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2497         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2498             params->channels == 8)
2499                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2500         else
2501                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2502         HDMI_WRITE(HDMI_MAI_FMT,
2503                    VC4_SET_FIELD(mai_sample_rate,
2504                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2505                    VC4_SET_FIELD(mai_audio_format,
2506                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2507
2508         /* The B frame identifier should match the value used by alsa-lib (8) */
2509         audio_packet_config =
2510                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2511                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2512                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2513
2514         channel_mask = GENMASK(channels - 1, 0);
2515         audio_packet_config |= VC4_SET_FIELD(channel_mask,
2516                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2517
2518         /* Set the MAI threshold */
2519         HDMI_WRITE(HDMI_MAI_THR,
2520                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
2521                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
2522                    VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
2523                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
2524
2525         HDMI_WRITE(HDMI_MAI_CONFIG,
2526                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2527                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2528                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2529
2530         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2531         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2532         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2533
2534         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2535
2536         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2537
2538         memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
2539         if (vc4_hdmi->output_enabled)
2540                 vc4_hdmi_set_audio_infoframe(encoder);
2541
2542 out_dev_exit:
2543         drm_dev_exit(idx);
2544 out:
2545         mutex_unlock(&vc4_hdmi->mutex);
2546
2547         return ret;
2548 }
2549
2550 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2551         .name = "vc4-hdmi-cpu-dai-component",
2552 };
2553
2554 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2555 {
2556         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2557
2558         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2559
2560         return 0;
2561 }
2562
2563 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2564         .name = "vc4-hdmi-cpu-dai",
2565         .probe  = vc4_hdmi_audio_cpu_dai_probe,
2566         .playback = {
2567                 .stream_name = "Playback",
2568                 .channels_min = 1,
2569                 .channels_max = 8,
2570                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2571                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2572                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2573                          SNDRV_PCM_RATE_192000,
2574                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2575         },
2576 };
2577
2578 static const struct snd_dmaengine_pcm_config pcm_conf = {
2579         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2580         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2581 };
2582
2583 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
2584                                   uint8_t *buf, size_t len)
2585 {
2586         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2587         struct drm_connector *connector = &vc4_hdmi->connector;
2588
2589         mutex_lock(&vc4_hdmi->mutex);
2590         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2591         mutex_unlock(&vc4_hdmi->mutex);
2592
2593         return 0;
2594 }
2595
2596 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
2597         .get_eld = vc4_hdmi_audio_get_eld,
2598         .prepare = vc4_hdmi_audio_prepare,
2599         .audio_shutdown = vc4_hdmi_audio_shutdown,
2600         .audio_startup = vc4_hdmi_audio_startup,
2601 };
2602
2603 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
2604         .ops = &vc4_hdmi_codec_ops,
2605         .max_i2s_channels = 8,
2606         .i2s = 1,
2607 };
2608
2609 static void vc4_hdmi_audio_codec_release(void *ptr)
2610 {
2611         struct vc4_hdmi *vc4_hdmi = ptr;
2612
2613         platform_device_unregister(vc4_hdmi->audio.codec_pdev);
2614         vc4_hdmi->audio.codec_pdev = NULL;
2615 }
2616
2617 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2618 {
2619         const struct vc4_hdmi_register *mai_data =
2620                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2621         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2622         struct snd_soc_card *card = &vc4_hdmi->audio.card;
2623         struct device *dev = &vc4_hdmi->pdev->dev;
2624         struct platform_device *codec_pdev;
2625         const __be32 *addr;
2626         int index;
2627         int ret;
2628         int len;
2629
2630         /*
2631          * ASoC makes it a bit hard to retrieve a pointer to the
2632          * vc4_hdmi structure. Registering the card will overwrite our
2633          * device drvdata with a pointer to the snd_soc_card structure,
2634          * which can then be used to retrieve whatever drvdata we want
2635          * to associate.
2636          *
2637          * However, that doesn't fly in the case where we wouldn't
2638          * register an ASoC card (because of an old DT that is missing
2639          * the dmas properties for example), then the card isn't
2640          * registered and the device drvdata wouldn't be set.
2641          *
2642          * We can deal with both cases by making sure a snd_soc_card
2643          * pointer and a vc4_hdmi structure are pointing to the same
2644          * memory address, so we can treat them indistinctly without any
2645          * issue.
2646          */
2647         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2648         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2649
2650         if (!of_find_property(dev->of_node, "dmas", &len) ||
2651             len == 0) {
2652                 dev_warn(dev,
2653                          "'dmas' DT property is missing or empty, no HDMI audio\n");
2654                 return 0;
2655         }
2656
2657         if (mai_data->reg != VC4_HD) {
2658                 WARN_ONCE(true, "MAI isn't in the HD block\n");
2659                 return -EINVAL;
2660         }
2661
2662         /*
2663          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2664          * the bus address specified in the DT, because the physical address
2665          * (the one returned by platform_get_resource()) is not appropriate
2666          * for DMA transfers.
2667          * This VC/MMU should probably be exposed to avoid this kind of hacks.
2668          */
2669         index = of_property_match_string(dev->of_node, "reg-names", "hd");
2670         /* Before BCM2711, we don't have a named register range */
2671         if (index < 0)
2672                 index = 1;
2673
2674         addr = of_get_address(dev->of_node, index, NULL, NULL);
2675
2676         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2677         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2678         vc4_hdmi->audio.dma_data.maxburst = 2;
2679
2680         /*
2681          * NOTE: Strictly speaking, we should probably use a DRM-managed
2682          * registration there to avoid removing all the audio components
2683          * by the time the driver doesn't have any user anymore.
2684          *
2685          * However, the ASoC core uses a number of devm_kzalloc calls
2686          * when registering, even when using non-device-managed
2687          * functions (such as in snd_soc_register_component()).
2688          *
2689          * If we call snd_soc_unregister_component() in a DRM-managed
2690          * action, the device-managed actions have already been executed
2691          * and thus we would access memory that has been freed.
2692          *
2693          * Using device-managed hooks here probably leaves us open to a
2694          * bunch of issues if userspace still has a handle on the ALSA
2695          * device when the device is removed. However, this is mitigated
2696          * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2697          * path to prevent the access to the device resources if it
2698          * isn't there anymore.
2699          *
2700          * Then, the vc4_hdmi structure is DRM-managed and thus only
2701          * freed whenever the last user has closed the DRM device file.
2702          * It should thus outlive ALSA in most situations.
2703          */
2704         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2705         if (ret) {
2706                 dev_err(dev, "Could not register PCM component: %d\n", ret);
2707                 return ret;
2708         }
2709
2710         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2711                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
2712         if (ret) {
2713                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2714                 return ret;
2715         }
2716
2717         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
2718                                                    PLATFORM_DEVID_AUTO,
2719                                                    &vc4_hdmi_codec_pdata,
2720                                                    sizeof(vc4_hdmi_codec_pdata));
2721         if (IS_ERR(codec_pdev)) {
2722                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
2723                 return PTR_ERR(codec_pdev);
2724         }
2725         vc4_hdmi->audio.codec_pdev = codec_pdev;
2726
2727         ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi);
2728         if (ret)
2729                 return ret;
2730
2731         dai_link->cpus          = &vc4_hdmi->audio.cpu;
2732         dai_link->codecs        = &vc4_hdmi->audio.codec;
2733         dai_link->platforms     = &vc4_hdmi->audio.platform;
2734
2735         dai_link->num_cpus      = 1;
2736         dai_link->num_codecs    = 1;
2737         dai_link->num_platforms = 1;
2738
2739         dai_link->name = "MAI";
2740         dai_link->stream_name = "MAI PCM";
2741         dai_link->codecs->dai_name = "i2s-hifi";
2742         dai_link->cpus->dai_name = dev_name(dev);
2743         dai_link->codecs->name = dev_name(&codec_pdev->dev);
2744         dai_link->platforms->name = dev_name(dev);
2745
2746         card->dai_link = dai_link;
2747         card->num_links = 1;
2748         card->name = vc4_hdmi->variant->card_name;
2749         card->driver_name = "vc4-hdmi";
2750         card->dev = dev;
2751         card->owner = THIS_MODULE;
2752
2753         /*
2754          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2755          * stores a pointer to the snd card object in dev->driver_data. This
2756          * means we cannot use it for something else. The hdmi back-pointer is
2757          * now stored in card->drvdata and should be retrieved with
2758          * snd_soc_card_get_drvdata() if needed.
2759          */
2760         snd_soc_card_set_drvdata(card, vc4_hdmi);
2761         ret = devm_snd_soc_register_card(dev, card);
2762         if (ret)
2763                 dev_err_probe(dev, ret, "Could not register sound card\n");
2764
2765         return ret;
2766
2767 }
2768
2769 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2770 {
2771         struct vc4_hdmi *vc4_hdmi = priv;
2772         struct drm_connector *connector = &vc4_hdmi->connector;
2773         struct drm_device *dev = connector->dev;
2774
2775         if (dev && dev->registered)
2776                 drm_connector_helper_hpd_irq_event(connector);
2777
2778         return IRQ_HANDLED;
2779 }
2780
2781 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2782 {
2783         struct drm_connector *connector = &vc4_hdmi->connector;
2784         struct platform_device *pdev = vc4_hdmi->pdev;
2785         int ret;
2786
2787         if (vc4_hdmi->variant->external_irq_controller) {
2788                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2789                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2790
2791                 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2792                                                 NULL,
2793                                                 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2794                                                 "vc4 hdmi hpd connected", vc4_hdmi);
2795                 if (ret)
2796                         return ret;
2797
2798                 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2799                                                 NULL,
2800                                                 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2801                                                 "vc4 hdmi hpd disconnected", vc4_hdmi);
2802                 if (ret)
2803                         return ret;
2804
2805                 connector->polled = DRM_CONNECTOR_POLL_HPD;
2806         }
2807
2808         return 0;
2809 }
2810
2811 #ifdef CONFIG_DRM_VC4_HDMI_CEC
2812 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2813 {
2814         struct vc4_hdmi *vc4_hdmi = priv;
2815
2816         if (vc4_hdmi->cec_rx_msg.len)
2817                 cec_received_msg(vc4_hdmi->cec_adap,
2818                                  &vc4_hdmi->cec_rx_msg);
2819
2820         return IRQ_HANDLED;
2821 }
2822
2823 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2824 {
2825         struct vc4_hdmi *vc4_hdmi = priv;
2826
2827         if (vc4_hdmi->cec_tx_ok) {
2828                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2829                                   0, 0, 0, 0);
2830         } else {
2831                 /*
2832                  * This CEC implementation makes 1 retry, so if we
2833                  * get a NACK, then that means it made 2 attempts.
2834                  */
2835                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2836                                   0, 2, 0, 0);
2837         }
2838         return IRQ_HANDLED;
2839 }
2840
2841 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2842 {
2843         struct vc4_hdmi *vc4_hdmi = priv;
2844         irqreturn_t ret;
2845
2846         if (vc4_hdmi->cec_irq_was_rx)
2847                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2848         else
2849                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2850
2851         return ret;
2852 }
2853
2854 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2855 {
2856         struct drm_device *dev = vc4_hdmi->connector.dev;
2857         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2858         unsigned int i;
2859
2860         lockdep_assert_held(&vc4_hdmi->hw_lock);
2861
2862         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2863                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2864
2865         if (msg->len > 16) {
2866                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2867                 return;
2868         }
2869
2870         for (i = 0; i < msg->len; i += 4) {
2871                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2872
2873                 msg->msg[i] = val & 0xff;
2874                 msg->msg[i + 1] = (val >> 8) & 0xff;
2875                 msg->msg[i + 2] = (val >> 16) & 0xff;
2876                 msg->msg[i + 3] = (val >> 24) & 0xff;
2877         }
2878 }
2879
2880 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2881 {
2882         u32 cntrl1;
2883
2884         /*
2885          * We don't need to protect the register access using
2886          * drm_dev_enter() there because the interrupt handler lifetime
2887          * is tied to the device itself, and not to the DRM device.
2888          *
2889          * So when the device will be gone, one of the first thing we
2890          * will be doing will be to unregister the interrupt handler,
2891          * and then unregister the DRM device. drm_dev_enter() would
2892          * thus always succeed if we are here.
2893          */
2894
2895         lockdep_assert_held(&vc4_hdmi->hw_lock);
2896
2897         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2898         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2899         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2900         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2901
2902         return IRQ_WAKE_THREAD;
2903 }
2904
2905 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2906 {
2907         struct vc4_hdmi *vc4_hdmi = priv;
2908         irqreturn_t ret;
2909
2910         spin_lock(&vc4_hdmi->hw_lock);
2911         ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2912         spin_unlock(&vc4_hdmi->hw_lock);
2913
2914         return ret;
2915 }
2916
2917 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2918 {
2919         u32 cntrl1;
2920
2921         lockdep_assert_held(&vc4_hdmi->hw_lock);
2922
2923         /*
2924          * We don't need to protect the register access using
2925          * drm_dev_enter() there because the interrupt handler lifetime
2926          * is tied to the device itself, and not to the DRM device.
2927          *
2928          * So when the device will be gone, one of the first thing we
2929          * will be doing will be to unregister the interrupt handler,
2930          * and then unregister the DRM device. drm_dev_enter() would
2931          * thus always succeed if we are here.
2932          */
2933
2934         vc4_hdmi->cec_rx_msg.len = 0;
2935         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2936         vc4_cec_read_msg(vc4_hdmi, cntrl1);
2937         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2938         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2939         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2940
2941         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2942
2943         return IRQ_WAKE_THREAD;
2944 }
2945
2946 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
2947 {
2948         struct vc4_hdmi *vc4_hdmi = priv;
2949         irqreturn_t ret;
2950
2951         spin_lock(&vc4_hdmi->hw_lock);
2952         ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2953         spin_unlock(&vc4_hdmi->hw_lock);
2954
2955         return ret;
2956 }
2957
2958 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2959 {
2960         struct vc4_hdmi *vc4_hdmi = priv;
2961         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2962         irqreturn_t ret;
2963         u32 cntrl5;
2964
2965         /*
2966          * We don't need to protect the register access using
2967          * drm_dev_enter() there because the interrupt handler lifetime
2968          * is tied to the device itself, and not to the DRM device.
2969          *
2970          * So when the device will be gone, one of the first thing we
2971          * will be doing will be to unregister the interrupt handler,
2972          * and then unregister the DRM device. drm_dev_enter() would
2973          * thus always succeed if we are here.
2974          */
2975
2976         if (!(stat & VC4_HDMI_CPU_CEC))
2977                 return IRQ_NONE;
2978
2979         spin_lock(&vc4_hdmi->hw_lock);
2980         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2981         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2982         if (vc4_hdmi->cec_irq_was_rx)
2983                 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2984         else
2985                 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2986
2987         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2988         spin_unlock(&vc4_hdmi->hw_lock);
2989
2990         return ret;
2991 }
2992
2993 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2994 {
2995         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2996         struct drm_device *drm = vc4_hdmi->connector.dev;
2997         /* clock period in microseconds */
2998         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2999         unsigned long flags;
3000         u32 val;
3001         int ret;
3002         int idx;
3003
3004         if (!drm_dev_enter(drm, &idx))
3005                 /*
3006                  * We can't return an error code, because the CEC
3007                  * framework will emit WARN_ON messages at unbind
3008                  * otherwise.
3009                  */
3010                 return 0;
3011
3012         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
3013         if (ret) {
3014                 drm_dev_exit(idx);
3015                 return ret;
3016         }
3017
3018         mutex_lock(&vc4_hdmi->mutex);
3019
3020         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3021
3022         val = HDMI_READ(HDMI_CEC_CNTRL_5);
3023         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
3024                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
3025                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
3026         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
3027                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
3028
3029         HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
3030                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
3031         HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
3032         HDMI_WRITE(HDMI_CEC_CNTRL_2,
3033                    ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
3034                    ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
3035                    ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
3036                    ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
3037                    ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
3038         HDMI_WRITE(HDMI_CEC_CNTRL_3,
3039                    ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
3040                    ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
3041                    ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
3042                    ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
3043         HDMI_WRITE(HDMI_CEC_CNTRL_4,
3044                    ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
3045                    ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
3046                    ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
3047                    ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
3048
3049         if (!vc4_hdmi->variant->external_irq_controller)
3050                 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
3051
3052         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3053
3054         mutex_unlock(&vc4_hdmi->mutex);
3055         drm_dev_exit(idx);
3056
3057         return 0;
3058 }
3059
3060 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
3061 {
3062         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
3063         struct drm_device *drm = vc4_hdmi->connector.dev;
3064         unsigned long flags;
3065         int idx;
3066
3067         if (!drm_dev_enter(drm, &idx))
3068                 /*
3069                  * We can't return an error code, because the CEC
3070                  * framework will emit WARN_ON messages at unbind
3071                  * otherwise.
3072                  */
3073                 return 0;
3074
3075         mutex_lock(&vc4_hdmi->mutex);
3076
3077         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3078
3079         if (!vc4_hdmi->variant->external_irq_controller)
3080                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
3081
3082         HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
3083                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
3084
3085         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3086
3087         mutex_unlock(&vc4_hdmi->mutex);
3088
3089         pm_runtime_put(&vc4_hdmi->pdev->dev);
3090
3091         drm_dev_exit(idx);
3092
3093         return 0;
3094 }
3095
3096 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
3097 {
3098         if (enable)
3099                 return vc4_hdmi_cec_enable(adap);
3100         else
3101                 return vc4_hdmi_cec_disable(adap);
3102 }
3103
3104 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
3105 {
3106         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
3107         struct drm_device *drm = vc4_hdmi->connector.dev;
3108         unsigned long flags;
3109         int idx;
3110
3111         if (!drm_dev_enter(drm, &idx))
3112                 /*
3113                  * We can't return an error code, because the CEC
3114                  * framework will emit WARN_ON messages at unbind
3115                  * otherwise.
3116                  */
3117                 return 0;
3118
3119         mutex_lock(&vc4_hdmi->mutex);
3120         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3121         HDMI_WRITE(HDMI_CEC_CNTRL_1,
3122                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
3123                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
3124         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3125         mutex_unlock(&vc4_hdmi->mutex);
3126
3127         drm_dev_exit(idx);
3128
3129         return 0;
3130 }
3131
3132 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
3133                                       u32 signal_free_time, struct cec_msg *msg)
3134 {
3135         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
3136         struct drm_device *dev = vc4_hdmi->connector.dev;
3137         unsigned long flags;
3138         u32 val;
3139         unsigned int i;
3140         int idx;
3141
3142         if (!drm_dev_enter(dev, &idx))
3143                 return -ENODEV;
3144
3145         if (msg->len > 16) {
3146                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
3147                 drm_dev_exit(idx);
3148                 return -ENOMEM;
3149         }
3150
3151         mutex_lock(&vc4_hdmi->mutex);
3152
3153         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3154
3155         for (i = 0; i < msg->len; i += 4)
3156                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
3157                            (msg->msg[i]) |
3158                            (msg->msg[i + 1] << 8) |
3159                            (msg->msg[i + 2] << 16) |
3160                            (msg->msg[i + 3] << 24));
3161
3162         val = HDMI_READ(HDMI_CEC_CNTRL_1);
3163         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
3164         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
3165         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
3166         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
3167         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
3168
3169         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
3170
3171         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3172         mutex_unlock(&vc4_hdmi->mutex);
3173         drm_dev_exit(idx);
3174
3175         return 0;
3176 }
3177
3178 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
3179         .adap_enable = vc4_hdmi_cec_adap_enable,
3180         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
3181         .adap_transmit = vc4_hdmi_cec_adap_transmit,
3182 };
3183
3184 static void vc4_hdmi_cec_release(void *ptr)
3185 {
3186         struct vc4_hdmi *vc4_hdmi = ptr;
3187
3188         cec_unregister_adapter(vc4_hdmi->cec_adap);
3189         vc4_hdmi->cec_adap = NULL;
3190 }
3191
3192 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3193 {
3194         struct cec_connector_info conn_info;
3195         struct platform_device *pdev = vc4_hdmi->pdev;
3196         struct device *dev = &pdev->dev;
3197         unsigned long flags;
3198         int ret;
3199
3200         if (!of_find_property(dev->of_node, "interrupts", NULL)) {
3201                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
3202                 return 0;
3203         }
3204
3205         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
3206                                                   vc4_hdmi, "vc4",
3207                                                   CEC_CAP_DEFAULTS |
3208                                                   CEC_CAP_CONNECTOR_INFO, 1);
3209         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
3210         if (ret < 0)
3211                 return ret;
3212
3213         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
3214         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
3215
3216         if (vc4_hdmi->variant->external_irq_controller) {
3217                 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
3218                                                 vc4_cec_irq_handler_rx_bare,
3219                                                 vc4_cec_irq_handler_rx_thread, 0,
3220                                                 "vc4 hdmi cec rx", vc4_hdmi);
3221                 if (ret)
3222                         goto err_delete_cec_adap;
3223
3224                 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
3225                                                 vc4_cec_irq_handler_tx_bare,
3226                                                 vc4_cec_irq_handler_tx_thread, 0,
3227                                                 "vc4 hdmi cec tx", vc4_hdmi);
3228                 if (ret)
3229                         goto err_delete_cec_adap;
3230         } else {
3231                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3232                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3233                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3234
3235                 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
3236                                                 vc4_cec_irq_handler,
3237                                                 vc4_cec_irq_handler_thread, 0,
3238                                                 "vc4 hdmi cec", vc4_hdmi);
3239                 if (ret)
3240                         goto err_delete_cec_adap;
3241         }
3242
3243         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
3244         if (ret < 0)
3245                 goto err_delete_cec_adap;
3246
3247         /*
3248          * NOTE: Strictly speaking, we should probably use a DRM-managed
3249          * registration there to avoid removing the CEC adapter by the
3250          * time the DRM driver doesn't have any user anymore.
3251          *
3252          * However, the CEC framework already cleans up the CEC adapter
3253          * only when the last user has closed its file descriptor, so we
3254          * don't need to handle it in DRM.
3255          *
3256          * By the time the device-managed hook is executed, we will give
3257          * up our reference to the CEC adapter and therefore don't
3258          * really care when it's actually freed.
3259          *
3260          * There's still a problematic sequence: if we unregister our
3261          * CEC adapter, but the userspace keeps a handle on the CEC
3262          * adapter but not the DRM device for some reason. In such a
3263          * case, our vc4_hdmi structure will be freed, but the
3264          * cec_adapter structure will have a dangling pointer to what
3265          * used to be our HDMI controller. If we get a CEC call at that
3266          * moment, we could end up with a use-after-free. Fortunately,
3267          * the CEC framework already handles this too, by calling
3268          * cec_is_registered() in cec_ioctl() and cec_poll().
3269          */
3270         ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
3271         if (ret)
3272                 return ret;
3273
3274         return 0;
3275
3276 err_delete_cec_adap:
3277         cec_delete_adapter(vc4_hdmi->cec_adap);
3278
3279         return ret;
3280 }
3281
3282 static int vc4_hdmi_cec_resume(struct vc4_hdmi *vc4_hdmi)
3283 {
3284         unsigned long flags;
3285         u32 value;
3286
3287         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3288         value = HDMI_READ(HDMI_CEC_CNTRL_1);
3289         /* Set the logical address to Unregistered */
3290         value |= VC4_HDMI_CEC_ADDR_MASK;
3291         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3292         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3293
3294         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3295
3296         if (!vc4_hdmi->variant->external_irq_controller) {
3297                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3298                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3299                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3300         }
3301
3302         return 0;
3303 }
3304 #else
3305 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3306 {
3307         return 0;
3308 }
3309
3310 static int vc4_hdmi_cec_resume(struct vc4_hdmi *vc4_hdmi)
3311 {
3312         return 0;
3313 }
3314 #endif
3315
3316 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
3317 {
3318         struct debugfs_reg32 *regs = ptr;
3319
3320         kfree(regs);
3321 }
3322
3323 static int vc4_hdmi_build_regset(struct drm_device *drm,
3324                                  struct vc4_hdmi *vc4_hdmi,
3325                                  struct debugfs_regset32 *regset,
3326                                  enum vc4_hdmi_regs reg)
3327 {
3328         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
3329         struct debugfs_reg32 *regs, *new_regs;
3330         unsigned int count = 0;
3331         unsigned int i;
3332         int ret;
3333
3334         regs = kcalloc(variant->num_registers, sizeof(*regs),
3335                        GFP_KERNEL);
3336         if (!regs)
3337                 return -ENOMEM;
3338
3339         for (i = 0; i < variant->num_registers; i++) {
3340                 const struct vc4_hdmi_register *field = &variant->registers[i];
3341
3342                 if (field->reg != reg)
3343                         continue;
3344
3345                 regs[count].name = field->name;
3346                 regs[count].offset = field->offset;
3347                 count++;
3348         }
3349
3350         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
3351         if (!new_regs)
3352                 return -ENOMEM;
3353
3354         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
3355         regset->regs = new_regs;
3356         regset->nregs = count;
3357
3358         ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
3359         if (ret)
3360                 return ret;
3361
3362         return 0;
3363 }
3364
3365 static int vc4_hdmi_init_resources(struct drm_device *drm,
3366                                    struct vc4_hdmi *vc4_hdmi)
3367 {
3368         struct platform_device *pdev = vc4_hdmi->pdev;
3369         struct device *dev = &pdev->dev;
3370         int ret;
3371
3372         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
3373         if (IS_ERR(vc4_hdmi->hdmicore_regs))
3374                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
3375
3376         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
3377         if (IS_ERR(vc4_hdmi->hd_regs))
3378                 return PTR_ERR(vc4_hdmi->hd_regs);
3379
3380         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3381         if (ret)
3382                 return ret;
3383
3384         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3385         if (ret)
3386                 return ret;
3387
3388         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
3389         if (IS_ERR(vc4_hdmi->pixel_clock)) {
3390                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
3391                 if (ret != -EPROBE_DEFER)
3392                         DRM_ERROR("Failed to get pixel clock\n");
3393                 return ret;
3394         }
3395
3396         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3397         if (IS_ERR(vc4_hdmi->hsm_clock)) {
3398                 DRM_ERROR("Failed to get HDMI state machine clock\n");
3399                 return PTR_ERR(vc4_hdmi->hsm_clock);
3400         }
3401         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
3402         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
3403
3404         return 0;
3405 }
3406
3407 static int vc5_hdmi_init_resources(struct drm_device *drm,
3408                                    struct vc4_hdmi *vc4_hdmi)
3409 {
3410         struct platform_device *pdev = vc4_hdmi->pdev;
3411         struct device *dev = &pdev->dev;
3412         struct resource *res;
3413         int ret;
3414
3415         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
3416         if (!res)
3417                 return -ENODEV;
3418
3419         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
3420                                                resource_size(res));
3421         if (!vc4_hdmi->hdmicore_regs)
3422                 return -ENOMEM;
3423
3424         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
3425         if (!res)
3426                 return -ENODEV;
3427
3428         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
3429         if (!vc4_hdmi->hd_regs)
3430                 return -ENOMEM;
3431
3432         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
3433         if (!res)
3434                 return -ENODEV;
3435
3436         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
3437         if (!vc4_hdmi->cec_regs)
3438                 return -ENOMEM;
3439
3440         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
3441         if (!res)
3442                 return -ENODEV;
3443
3444         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
3445         if (!vc4_hdmi->csc_regs)
3446                 return -ENOMEM;
3447
3448         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
3449         if (!res)
3450                 return -ENODEV;
3451
3452         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
3453         if (!vc4_hdmi->dvp_regs)
3454                 return -ENOMEM;
3455
3456         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
3457         if (!res)
3458                 return -ENODEV;
3459
3460         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
3461         if (!vc4_hdmi->phy_regs)
3462                 return -ENOMEM;
3463
3464         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
3465         if (!res)
3466                 return -ENODEV;
3467
3468         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
3469         if (!vc4_hdmi->ram_regs)
3470                 return -ENOMEM;
3471
3472         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
3473         if (!res)
3474                 return -ENODEV;
3475
3476         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
3477         if (!vc4_hdmi->rm_regs)
3478                 return -ENOMEM;
3479
3480         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3481         if (IS_ERR(vc4_hdmi->hsm_clock)) {
3482                 DRM_ERROR("Failed to get HDMI state machine clock\n");
3483                 return PTR_ERR(vc4_hdmi->hsm_clock);
3484         }
3485
3486         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3487         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3488                 DRM_ERROR("Failed to get pixel bvb clock\n");
3489                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3490         }
3491
3492         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3493         if (IS_ERR(vc4_hdmi->audio_clock)) {
3494                 DRM_ERROR("Failed to get audio clock\n");
3495                 return PTR_ERR(vc4_hdmi->audio_clock);
3496         }
3497
3498         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3499         if (IS_ERR(vc4_hdmi->cec_clock)) {
3500                 DRM_ERROR("Failed to get CEC clock\n");
3501                 return PTR_ERR(vc4_hdmi->cec_clock);
3502         }
3503
3504         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3505         if (IS_ERR(vc4_hdmi->reset)) {
3506                 DRM_ERROR("Failed to get HDMI reset line\n");
3507                 return PTR_ERR(vc4_hdmi->reset);
3508         }
3509
3510         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3511         if (ret)
3512                 return ret;
3513
3514         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3515         if (ret)
3516                 return ret;
3517
3518         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3519         if (ret)
3520                 return ret;
3521
3522         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3523         if (ret)
3524                 return ret;
3525
3526         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3527         if (ret)
3528                 return ret;
3529
3530         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3531         if (ret)
3532                 return ret;
3533
3534         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3535         if (ret)
3536                 return ret;
3537
3538         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3539         if (ret)
3540                 return ret;
3541
3542         return 0;
3543 }
3544
3545 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev)
3546 {
3547         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3548
3549         clk_disable_unprepare(vc4_hdmi->hsm_clock);
3550
3551         return 0;
3552 }
3553
3554 static int vc4_hdmi_runtime_resume(struct device *dev)
3555 {
3556         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3557         int ret;
3558
3559         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
3560         if (ret)
3561                 return ret;
3562
3563         if (vc4_hdmi->variant->reset)
3564                 vc4_hdmi->variant->reset(vc4_hdmi);
3565
3566         ret = vc4_hdmi_cec_resume(vc4_hdmi);
3567         if (ret) {
3568                 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3569                 return ret;
3570         }
3571
3572         return 0;
3573 }
3574
3575 static void vc4_hdmi_put_ddc_device(void *ptr)
3576 {
3577         struct vc4_hdmi *vc4_hdmi = ptr;
3578
3579         put_device(&vc4_hdmi->ddc->dev);
3580 }
3581
3582 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3583 {
3584         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3585         struct platform_device *pdev = to_platform_device(dev);
3586         struct drm_device *drm = dev_get_drvdata(master);
3587         struct vc4_hdmi *vc4_hdmi;
3588         struct drm_encoder *encoder;
3589         struct device_node *ddc_node;
3590         int ret;
3591
3592         vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3593         if (!vc4_hdmi)
3594                 return -ENOMEM;
3595
3596         ret = drmm_mutex_init(drm, &vc4_hdmi->mutex);
3597         if (ret)
3598                 return ret;
3599
3600         spin_lock_init(&vc4_hdmi->hw_lock);
3601         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3602
3603         dev_set_drvdata(dev, vc4_hdmi);
3604         encoder = &vc4_hdmi->encoder.base;
3605         vc4_hdmi->encoder.type = variant->encoder_type;
3606         vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3607         vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3608         vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3609         vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3610         vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3611         vc4_hdmi->pdev = pdev;
3612         vc4_hdmi->variant = variant;
3613
3614         /*
3615          * Since we don't know the state of the controller and its
3616          * display (if any), let's assume it's always enabled.
3617          * vc4_hdmi_disable_scrambling() will thus run at boot, make
3618          * sure it's disabled, and avoid any inconsistency.
3619          */
3620         if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3621                 vc4_hdmi->scdc_enabled = true;
3622
3623         ret = variant->init_resources(drm, vc4_hdmi);
3624         if (ret)
3625                 return ret;
3626
3627         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3628         if (!ddc_node) {
3629                 DRM_ERROR("Failed to find ddc node in device tree\n");
3630                 return -ENODEV;
3631         }
3632
3633         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3634         of_node_put(ddc_node);
3635         if (!vc4_hdmi->ddc) {
3636                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
3637                 return -EPROBE_DEFER;
3638         }
3639
3640         ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3641         if (ret)
3642                 return ret;
3643
3644         /* Only use the GPIO HPD pin if present in the DT, otherwise
3645          * we'll use the HDMI core's register.
3646          */
3647         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3648         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3649                 return PTR_ERR(vc4_hdmi->hpd_gpio);
3650         }
3651
3652         vc4_hdmi->disable_wifi_frequencies =
3653                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3654
3655         /*
3656          * If we boot without any cable connected to the HDMI connector,
3657          * the firmware will skip the HSM initialization and leave it
3658          * with a rate of 0, resulting in a bus lockup when we're
3659          * accessing the registers even if it's enabled.
3660          *
3661          * Let's put a sensible default at runtime_resume so that we
3662          * don't end up in this situation.
3663          */
3664         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
3665         if (ret)
3666                 return ret;
3667
3668         ret = devm_pm_runtime_enable(dev);
3669         if (ret)
3670                 return ret;
3671
3672         ret = pm_runtime_resume_and_get(dev);
3673         if (ret)
3674                 return ret;
3675
3676         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3677              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
3678             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3679                 clk_prepare_enable(vc4_hdmi->pixel_clock);
3680                 clk_prepare_enable(vc4_hdmi->hsm_clock);
3681                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3682         }
3683
3684         ret = drmm_encoder_init(drm, encoder,
3685                                 &vc4_hdmi_encoder_funcs,
3686                                 DRM_MODE_ENCODER_TMDS,
3687                                 NULL);
3688         if (ret)
3689                 goto err_put_runtime_pm;
3690
3691         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3692
3693         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3694         if (ret)
3695                 goto err_put_runtime_pm;
3696
3697         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3698         if (ret)
3699                 goto err_put_runtime_pm;
3700
3701         ret = vc4_hdmi_cec_init(vc4_hdmi);
3702         if (ret)
3703                 goto err_put_runtime_pm;
3704
3705         ret = vc4_hdmi_audio_init(vc4_hdmi);
3706         if (ret)
3707                 goto err_put_runtime_pm;
3708
3709         pm_runtime_put_sync(dev);
3710
3711         return 0;
3712
3713 err_put_runtime_pm:
3714         pm_runtime_put_sync(dev);
3715
3716         return ret;
3717 }
3718
3719 static const struct component_ops vc4_hdmi_ops = {
3720         .bind   = vc4_hdmi_bind,
3721 };
3722
3723 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3724 {
3725         return component_add(&pdev->dev, &vc4_hdmi_ops);
3726 }
3727
3728 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
3729 {
3730         component_del(&pdev->dev, &vc4_hdmi_ops);
3731         return 0;
3732 }
3733
3734 static const struct vc4_hdmi_variant bcm2835_variant = {
3735         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3736         .debugfs_name           = "hdmi_regs",
3737         .card_name              = "vc4-hdmi",
3738         .max_pixel_clock        = 162000000,
3739         .registers              = vc4_hdmi_fields,
3740         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
3741
3742         .init_resources         = vc4_hdmi_init_resources,
3743         .csc_setup              = vc4_hdmi_csc_setup,
3744         .reset                  = vc4_hdmi_reset,
3745         .set_timings            = vc4_hdmi_set_timings,
3746         .phy_init               = vc4_hdmi_phy_init,
3747         .phy_disable            = vc4_hdmi_phy_disable,
3748         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
3749         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
3750         .channel_map            = vc4_hdmi_channel_map,
3751         .supports_hdr           = false,
3752 };
3753
3754 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3755         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3756         .debugfs_name           = "hdmi0_regs",
3757         .card_name              = "vc4-hdmi-0",
3758         .max_pixel_clock        = 600000000,
3759         .registers              = vc5_hdmi_hdmi0_fields,
3760         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3761         .phy_lane_mapping       = {
3762                 PHY_LANE_0,
3763                 PHY_LANE_1,
3764                 PHY_LANE_2,
3765                 PHY_LANE_CK,
3766         },
3767         .unsupported_odd_h_timings      = true,
3768         .external_irq_controller        = true,
3769
3770         .init_resources         = vc5_hdmi_init_resources,
3771         .csc_setup              = vc5_hdmi_csc_setup,
3772         .reset                  = vc5_hdmi_reset,
3773         .set_timings            = vc5_hdmi_set_timings,
3774         .phy_init               = vc5_hdmi_phy_init,
3775         .phy_disable            = vc5_hdmi_phy_disable,
3776         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
3777         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
3778         .channel_map            = vc5_hdmi_channel_map,
3779         .supports_hdr           = true,
3780         .hp_detect              = vc5_hdmi_hp_detect,
3781 };
3782
3783 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3784         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
3785         .debugfs_name           = "hdmi1_regs",
3786         .card_name              = "vc4-hdmi-1",
3787         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
3788         .registers              = vc5_hdmi_hdmi1_fields,
3789         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3790         .phy_lane_mapping       = {
3791                 PHY_LANE_1,
3792                 PHY_LANE_0,
3793                 PHY_LANE_CK,
3794                 PHY_LANE_2,
3795         },
3796         .unsupported_odd_h_timings      = true,
3797         .external_irq_controller        = true,
3798
3799         .init_resources         = vc5_hdmi_init_resources,
3800         .csc_setup              = vc5_hdmi_csc_setup,
3801         .reset                  = vc5_hdmi_reset,
3802         .set_timings            = vc5_hdmi_set_timings,
3803         .phy_init               = vc5_hdmi_phy_init,
3804         .phy_disable            = vc5_hdmi_phy_disable,
3805         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
3806         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
3807         .channel_map            = vc5_hdmi_channel_map,
3808         .supports_hdr           = true,
3809         .hp_detect              = vc5_hdmi_hp_detect,
3810 };
3811
3812 static const struct of_device_id vc4_hdmi_dt_match[] = {
3813         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3814         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3815         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3816         {}
3817 };
3818
3819 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3820         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3821                            vc4_hdmi_runtime_resume,
3822                            NULL)
3823 };
3824
3825 struct platform_driver vc4_hdmi_driver = {
3826         .probe = vc4_hdmi_dev_probe,
3827         .remove = vc4_hdmi_dev_remove,
3828         .driver = {
3829                 .name = "vc4_hdmi",
3830                 .of_match_table = vc4_hdmi_dt_match,
3831                 .pm = &vc4_hdmi_pm_ops,
3832         },
3833 };