drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <linux/clk.h>
  38 #include <linux/component.h>
  39 #include <linux/extcon-provider.h>
  40 #include <linux/i2c.h>
  41 #include <linux/of_address.h>
  42 #include <linux/of_gpio.h>
  43 #include <linux/of_platform.h>
  44 #include <linux/pm_runtime.h>
  45 #include <linux/rational.h>
  46 #include <linux/reset.h>
  47 #include <sound/dmaengine_pcm.h>
  48 #include <sound/pcm_drm_eld.h>
  49 #include <sound/pcm_params.h>
  50 #include <sound/soc.h>
  51 #include "media/cec.h"
  52 #include "vc4_drv.h"
  53 #include "vc4_hdmi.h"
  54 #include "vc4_hdmi_regs.h"
  55 #include "vc4_regs.h"
  56
  57 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  58 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  59 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  60 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  61 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  62 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  63
  64 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  65 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  66 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  67 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  68
  69 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  70 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  71 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  72 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  73 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  74 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  75
  76 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  77 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  78
  79 # define VC4_HD_M_SW_RST                        BIT(2)
  80 # define VC4_HD_M_ENABLE                        BIT(0)
  81
  82 #define CEC_CLOCK_FREQ 40000
  83 #define VC4_HSM_CLOCK 163682864
  84 #define VC4_HSM_MID_CLOCK 149985000
  85
  86 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
  87 {
  88         struct drm_info_node *node = (struct drm_info_node *)m->private;
  89         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
  90         struct drm_printer p = drm_seq_file_printer(m);
  91
  92         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
  93         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
  94
  95         return 0;
  96 }
  97
  98 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
  99 {
 100         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 101         udelay(1);
 102         HDMI_WRITE(HDMI_M_CTL, 0);
 103
 104         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 105
 106         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 107                    VC4_HDMI_SW_RESET_HDMI |
 108                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 109
 110         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 111 }
 112
 113 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 114 {
 115         reset_control_reset(vc4_hdmi->reset);
 116
 117         HDMI_WRITE(HDMI_DVP_CTL, 0);
 118 }
 119
 120 static enum drm_connector_status
 121 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 122 {
 123         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 124         bool connected = false;
 125         enum drm_connector_status status;
 126
 127         if (vc4_hdmi->hpd_gpio) {
 128                 if (gpio_get_value_cansleep(vc4_hdmi->hpd_gpio) ^
 129                     vc4_hdmi->hpd_active_low)
 130                         connected = true;
 131         } else if (drm_probe_ddc(vc4_hdmi->ddc))
 132                 connected = true;
 133         if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
 134                 connected = true;
 135         if (connected) {
 136                 if (connector->status != connector_status_connected) {
 137                         struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
 138
 139                         if (edid) {
 140                                 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 141                                 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
 142                                 drm_connector_update_edid_property(connector, edid);
 143                                 kfree(edid);
 144                         }
 145                 }
 146                 status = connector_status_connected;
 147                 goto out;
 148         }
 149         cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 150         status = connector_status_disconnected;
 151
 152 out:
 153 #ifdef CONFIG_EXTCON
 154         if (status != vc4_hdmi->status) {
 155                 extcon_set_state_sync(vc4_hdmi->edev, EXTCON_DISP_HDMI,
 156                                       (status == connector_status_connected ?
 157                                       true : false));
 158                 vc4_hdmi->status = status;
 159         }
 160 #endif
 161         return status;
 162 }
 163
 164 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 165 {
 166         drm_connector_unregister(connector);
 167         drm_connector_cleanup(connector);
 168 }
 169
 170 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 171 {
 172         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 173         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 174         int ret = 0;
 175         struct edid *edid;
 176
 177         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 178         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 179         if (!edid)
 180                 return -ENODEV;
 181
 182         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 183
 184         drm_connector_update_edid_property(connector, edid);
 185         ret = drm_add_edid_modes(connector, edid);
 186         kfree(edid);
 187
 188         return ret;
 189 }
 190
 191 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 192 {
 193         drm_atomic_helper_connector_reset(connector);
 194         drm_atomic_helper_connector_tv_reset(connector);
 195 }
 196
 197 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 198         .detect = vc4_hdmi_connector_detect,
 199         .fill_modes = drm_helper_probe_single_connector_modes,
 200         .destroy = vc4_hdmi_connector_destroy,
 201         .reset = vc4_hdmi_connector_reset,
 202         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 203         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 204 };
 205
 206 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 207         .get_modes = vc4_hdmi_connector_get_modes,
 208 };
 209
 210 static int vc4_hdmi_connector_init(struct drm_device *dev,
 211                                    struct vc4_hdmi *vc4_hdmi)
 212 {
 213         struct drm_connector *connector = &vc4_hdmi->connector;
 214         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 215         int ret;
 216
 217         drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs,
 218                            DRM_MODE_CONNECTOR_HDMIA);
 219         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 220
 221         /* Create and attach TV margin props to this connector. */
 222         ret = drm_mode_create_tv_margin_properties(dev);
 223         if (ret)
 224                 return ret;
 225
 226         drm_connector_attach_tv_margin_properties(connector);
 227
 228         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 229                              DRM_CONNECTOR_POLL_DISCONNECT);
 230
 231         connector->interlace_allowed = 1;
 232         connector->doublescan_allowed = 0;
 233
 234         drm_connector_attach_encoder(connector, encoder);
 235
 236         return 0;
 237 }
 238
 239 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder)
 240 {
 241         drm_encoder_cleanup(encoder);
 242 }
 243
 244 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
 245         .destroy = vc4_hdmi_encoder_destroy,
 246 };
 247
 248 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 249                                 enum hdmi_infoframe_type type)
 250 {
 251         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 252         u32 packet_id = type - 0x80;
 253
 254         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 255                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 256
 257         return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 258                           BIT(packet_id)), 100);
 259 }
 260
 261 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 262                                      union hdmi_infoframe *frame)
 263 {
 264         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 265         u32 packet_id = frame->any.type - 0x80;
 266         const struct vc4_hdmi_register *ram_packet_start =
 267                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 268         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 269         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 270                                                        ram_packet_start->reg);
 271         uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
 272         ssize_t len, i;
 273         int ret;
 274
 275         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 276                     VC4_HDMI_RAM_PACKET_ENABLE),
 277                   "Packet RAM has to be on to store the packet.");
 278
 279         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 280         if (len < 0)
 281                 return;
 282
 283         ret = vc4_hdmi_stop_packet(encoder, frame->any.type);
 284         if (ret) {
 285                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 286                 return;
 287         }
 288
 289         for (i = 0; i < len; i += 7) {
 290                 writel(buffer[i + 0] << 0 |
 291                        buffer[i + 1] << 8 |
 292                        buffer[i + 2] << 16,
 293                        base + packet_reg);
 294                 packet_reg += 4;
 295
 296                 writel(buffer[i + 3] << 0 |
 297                        buffer[i + 4] << 8 |
 298                        buffer[i + 5] << 16 |
 299                        buffer[i + 6] << 24,
 300                        base + packet_reg);
 301                 packet_reg += 4;
 302         }
 303
 304         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 305                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 306         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 307                         BIT(packet_id)), 100);
 308         if (ret)
 309                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 310 }
 311
 312 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 313 {
 314         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 315         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 316         struct drm_connector *connector = &vc4_hdmi->connector;
 317         struct drm_connector_state *cstate = connector->state;
 318         struct drm_crtc *crtc = encoder->crtc;
 319         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 320         union hdmi_infoframe frame;
 321         int ret;
 322
 323         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 324                                                        connector, mode);
 325         if (ret < 0) {
 326                 DRM_ERROR("couldn't fill AVI infoframe\n");
 327                 return;
 328         }
 329
 330         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 331                                            connector, mode,
 332                                            vc4_encoder->limited_rgb_range ?
 333                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 334                                            HDMI_QUANTIZATION_RANGE_FULL);
 335
 336         frame.avi.right_bar = cstate->tv.margins.right;
 337         frame.avi.left_bar = cstate->tv.margins.left;
 338         frame.avi.top_bar = cstate->tv.margins.top;
 339         frame.avi.bottom_bar = cstate->tv.margins.bottom;
 340
 341         vc4_hdmi_write_infoframe(encoder, &frame);
 342 }
 343
 344 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 345 {
 346         union hdmi_infoframe frame;
 347         int ret;
 348
 349         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 350         if (ret < 0) {
 351                 DRM_ERROR("couldn't fill SPD infoframe\n");
 352                 return;
 353         }
 354
 355         frame.spd.sdi = HDMI_SPD_SDI_PC;
 356
 357         vc4_hdmi_write_infoframe(encoder, &frame);
 358 }
 359
 360 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 361 {
 362         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 363         union hdmi_infoframe frame;
 364         int ret;
 365
 366         ret = hdmi_audio_infoframe_init(&frame.audio);
 367
 368         frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
 369         frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
 370         frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
 371         frame.audio.channels = vc4_hdmi->audio.channels;
 372
 373         vc4_hdmi_write_infoframe(encoder, &frame);
 374 }
 375
 376 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 377 {
 378         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 379
 380         vc4_hdmi_set_avi_infoframe(encoder);
 381         vc4_hdmi_set_spd_infoframe(encoder);
 382         /*
 383          * If audio was streaming, then we need to reenabled the audio
 384          * infoframe here during encoder_enable.
 385          */
 386         if (vc4_hdmi->audio.streaming)
 387                 vc4_hdmi_set_audio_infoframe(encoder);
 388 }
 389
 390 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 391 {
 392         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 393         int ret;
 394
 395         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 396
 397         if (vc4_hdmi->variant->phy_disable)
 398                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 399
 400         HDMI_WRITE(HDMI_VID_CTL,
 401                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 402
 403         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 404         clk_disable_unprepare(vc4_hdmi->hsm_clock);
 405         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 406
 407         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 408         if (ret < 0)
 409                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 410 }
 411
 412 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 413 {
 414         u32 csc_ctl;
 415
 416         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 417                                 VC4_HD_CSC_CTL_ORDER);
 418
 419         if (enable) {
 420                 /* CEA VICs other than #1 requre limited range RGB
 421                  * output unless overridden by an AVI infoframe.
 422                  * Apply a colorspace conversion to squash 0-255 down
 423                  * to 16-235.  The matrix here is:
 424                  *
 425                  * [ 0      0      0.8594 16]
 426                  * [ 0      0.8594 0      16]
 427                  * [ 0.8594 0      0      16]
 428                  * [ 0      0      0       1]
 429                  */
 430                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 431                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 432                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 433                                          VC4_HD_CSC_CTL_MODE);
 434
 435                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 436                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 437                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 438                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 439                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 440                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 441         }
 442
 443         /* The RGB order applies even when CSC is disabled. */
 444         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 445 }
 446
 447 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 448 {
 449         u32 csc_ctl;
 450
 451         csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
 452
 453         if (enable) {
 454                 /* CEA VICs other than #1 requre limited range RGB
 455                  * output unless overridden by an AVI infoframe.
 456                  * Apply a colorspace conversion to squash 0-255 down
 457                  * to 16-235.  The matrix here is:
 458                  *
 459                  * [ 0.8594 0      0      16]
 460                  * [ 0      0.8594 0      16]
 461                  * [ 0      0      0.8594 16]
 462                  * [ 0      0      0       1]
 463                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 464                  */
 465                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
 466                 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
 467                 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
 468                 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
 469                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 470                 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
 471         } else {
 472                 /* Still use the matrix for full range, but make it unity.
 473                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 474                  */
 475                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
 476                 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
 477                 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
 478                 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
 479                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 480                 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
 481         }
 482
 483         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 484 }
 485
 486 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 487                                  struct drm_display_mode *mode)
 488 {
 489         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 490         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 491         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 492         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 493         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 494                                    VC4_HDMI_VERTA_VSP) |
 495                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 496                                    VC4_HDMI_VERTA_VFP) |
 497                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 498         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 499                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 500                                    VC4_HDMI_VERTB_VBP));
 501         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 502                           VC4_SET_FIELD(mode->crtc_vtotal -
 503                                         mode->crtc_vsync_end -
 504                                         interlaced,
 505                                         VC4_HDMI_VERTB_VBP));
 506
 507         HDMI_WRITE(HDMI_HORZA,
 508                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 509                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 510                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 511                                  VC4_HDMI_HORZA_HAP));
 512
 513         HDMI_WRITE(HDMI_HORZB,
 514                    VC4_SET_FIELD((mode->htotal -
 515                                   mode->hsync_end) * pixel_rep,
 516                                  VC4_HDMI_HORZB_HBP) |
 517                    VC4_SET_FIELD((mode->hsync_end -
 518                                   mode->hsync_start) * pixel_rep,
 519                                  VC4_HDMI_HORZB_HSP) |
 520                    VC4_SET_FIELD((mode->hsync_start -
 521                                   mode->hdisplay) * pixel_rep,
 522                                  VC4_HDMI_HORZB_HFP));
 523
 524         HDMI_WRITE(HDMI_VERTA0, verta);
 525         HDMI_WRITE(HDMI_VERTA1, verta);
 526
 527         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 528         HDMI_WRITE(HDMI_VERTB1, vertb);
 529
 530         HDMI_WRITE(HDMI_VID_CTL,
 531                  (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
 532                  (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
 533 }
 534
 535 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 536                                  struct drm_display_mode *mode)
 537 {
 538         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 539         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 540         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 541         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 542         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 543                                    VC5_HDMI_VERTA_VSP) |
 544                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 545                                    VC5_HDMI_VERTA_VFP) |
 546                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
 547         u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 548                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 549                                    VC4_HDMI_VERTB_VBP));
 550         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 551                           VC4_SET_FIELD(mode->crtc_vtotal -
 552                                         mode->crtc_vsync_end -
 553                                         interlaced,
 554                                         VC4_HDMI_VERTB_VBP));
 555
 556         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
 557         HDMI_WRITE(HDMI_HORZA,
 558                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
 559                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
 560                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 561                                  VC5_HDMI_HORZA_HAP) |
 562                    VC4_SET_FIELD((mode->hsync_start -
 563                                   mode->hdisplay) * pixel_rep,
 564                                  VC5_HDMI_HORZA_HFP));
 565
 566         HDMI_WRITE(HDMI_HORZB,
 567                    VC4_SET_FIELD((mode->htotal -
 568                                   mode->hsync_end) * pixel_rep,
 569                                  VC5_HDMI_HORZB_HBP) |
 570                    VC4_SET_FIELD((mode->hsync_end -
 571                                   mode->hsync_start) * pixel_rep,
 572                                  VC5_HDMI_HORZB_HSP));
 573
 574         HDMI_WRITE(HDMI_VERTA0, verta);
 575         HDMI_WRITE(HDMI_VERTA1, verta);
 576
 577         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 578         HDMI_WRITE(HDMI_VERTB1, vertb);
 579
 580         HDMI_WRITE(HDMI_VID_CTL,
 581                  (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
 582                  (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
 583
 584         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
 585 }
 586
 587 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
 588 {
 589         u32 drift;
 590         int ret;
 591
 592         drift = HDMI_READ(HDMI_FIFO_CTL);
 593         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 594
 595         HDMI_WRITE(HDMI_FIFO_CTL,
 596                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 597         HDMI_WRITE(HDMI_FIFO_CTL,
 598                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 599         usleep_range(1000, 1100);
 600         HDMI_WRITE(HDMI_FIFO_CTL,
 601                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 602         HDMI_WRITE(HDMI_FIFO_CTL,
 603                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 604
 605         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
 606                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
 607         WARN_ONCE(ret, "Timeout waiting for "
 608                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
 609 }
 610
 611 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
 612 {
 613         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 614         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 615         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 616         unsigned long pixel_rate, hsm_rate;
 617         int ret;
 618
 619         ret = pm_runtime_get_sync(&vc4_hdmi->pdev->dev);
 620         if (ret < 0) {
 621                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
 622                 return;
 623         }
 624
 625         pixel_rate = mode->clock * 1000 * ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1);
 626         ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
 627         if (ret) {
 628                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
 629                 return;
 630         }
 631
 632         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
 633         if (ret) {
 634                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
 635                 return;
 636         }
 637
 638         /*
 639          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
 640          * be faster than pixel clock, infinitesimally faster, tested in
 641          * simulation. Otherwise, exact value is unimportant for HDMI
 642          * operation." This conflicts with bcm2835's vc4 documentation, which
 643          * states HSM's clock has to be at least 108% of the pixel clock.
 644          *
 645          * Real life tests reveal that vc4's firmware statement holds up, and
 646          * users are able to use pixel clocks closer to HSM's, namely for
 647          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
 648          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
 649          * 162MHz.
 650          *
 651          * Additionally, the AXI clock needs to be at least 25% of
 652          * pixel clock, but HSM ends up being the limiting factor.
 653          */
 654         hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
 655         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
 656         if (ret) {
 657                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
 658                 return;
 659         }
 660
 661         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
 662         if (ret) {
 663                 DRM_ERROR("Failed to turn on HSM clock: %d\n", ret);
 664                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
 665                 return;
 666         }
 667
 668         ret = clk_set_rate(vc4_hdmi->pixel_bvb_clock,
 669                         (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));
 670         if (ret) {
 671                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
 672                 clk_disable_unprepare(vc4_hdmi->hsm_clock);
 673                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
 674                 return;
 675         }
 676
 677         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
 678         if (ret) {
 679                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
 680                 clk_disable_unprepare(vc4_hdmi->hsm_clock);
 681                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
 682                 return;
 683         }
 684
 685         if (vc4_hdmi->variant->reset)
 686                 vc4_hdmi->variant->reset(vc4_hdmi);
 687
 688         if (vc4_hdmi->variant->phy_init)
 689                 vc4_hdmi->variant->phy_init(vc4_hdmi, mode);
 690
 691         HDMI_WRITE(HDMI_VID_CTL, 0);
 692
 693         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 694                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
 695                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
 696                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
 697
 698         if (vc4_hdmi->variant->set_timings)
 699                 vc4_hdmi->variant->set_timings(vc4_hdmi, mode);
 700
 701         if (vc4_encoder->hdmi_monitor &&
 702             drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
 703                 if (vc4_hdmi->variant->csc_setup)
 704                         vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
 705
 706                 vc4_encoder->limited_rgb_range = true;
 707         } else {
 708                 if (vc4_hdmi->variant->csc_setup)
 709                         vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
 710
 711                 vc4_encoder->limited_rgb_range = false;
 712         }
 713
 714         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
 715
 716         HDMI_WRITE(HDMI_VID_CTL,
 717                    HDMI_READ(HDMI_VID_CTL) |
 718                    VC4_HD_VID_CTL_ENABLE |
 719                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
 720                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET);
 721
 722         if (vc4_encoder->hdmi_monitor) {
 723                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 724                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
 725                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 726
 727                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
 728                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
 729                 WARN_ONCE(ret, "Timeout waiting for "
 730                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 731         } else {
 732                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 733                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 734                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
 735                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 736                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
 737                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 738
 739                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
 740                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
 741                 WARN_ONCE(ret, "Timeout waiting for "
 742                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 743         }
 744
 745         if (vc4_encoder->hdmi_monitor) {
 746                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
 747                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
 748                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 749                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
 750                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
 751
 752                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 753                            VC4_HDMI_RAM_PACKET_ENABLE);
 754
 755                 vc4_hdmi_set_infoframes(encoder);
 756         }
 757
 758         vc4_hdmi_recenter_fifo(vc4_hdmi);
 759 }
 760
 761 static enum drm_mode_status
 762 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
 763                             const struct drm_display_mode *mode)
 764 {
 765         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 766
 767         if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
 768                 return MODE_CLOCK_HIGH;
 769
 770         return MODE_OK;
 771 }
 772
 773 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
 774         .mode_valid = vc4_hdmi_encoder_mode_valid,
 775         .disable = vc4_hdmi_encoder_disable,
 776         .enable = vc4_hdmi_encoder_enable,
 777 };
 778
 779 static u32 vc4_hdmi_get_hsm_clock(struct vc4_hdmi *vc4_hdmi)
 780 {
 781         return clk_get_rate(vc4_hdmi->hsm_clock);
 782 }
 783
 784 static u32 vc5_hdmi_get_hsm_clock(struct vc4_hdmi *vc4_hdmi)
 785 {
 786         return 120000000;
 787 }
 788
 789 static u32 vc4_hdmi_calc_hsm_clock(struct vc4_hdmi *vc4_hdmi, unsigned long pixel_rate)
 790 {
 791         /*
 792          * This is the rate that is set by the firmware.  The number
 793          * needs to be a bit higher than the pixel clock rate
 794          * (generally 148.5Mhz).
 795          */
 796         return VC4_HSM_CLOCK;
 797 }
 798
 799 static u32 vc5_hdmi_calc_hsm_clock(struct vc4_hdmi *vc4_hdmi, unsigned long pixel_rate)
 800 {
 801         /*
 802          * The HSM rate needs to be slightly greater than the pixel clock, with
 803          * a minimum of 108MHz.
 804          * Use 101% as this is what the firmware uses.
 805          */
 806
 807         return max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
 808 }
 809
 810 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
 811 {
 812         int i;
 813         u32 channel_map = 0;
 814
 815         for (i = 0; i < 8; i++) {
 816                 if (channel_mask & BIT(i))
 817                         channel_map |= i << (3 * i);
 818         }
 819         return channel_map;
 820 }
 821
 822 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
 823 {
 824         int i;
 825         u32 channel_map = 0;
 826
 827         for (i = 0; i < 8; i++) {
 828                 if (channel_mask & BIT(i))
 829                         channel_map |= i << (4 * i);
 830         }
 831         return channel_map;
 832 }
 833
 834 /* HDMI audio codec callbacks */
 835 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi)
 836 {
 837         u32 hsm_clock = vc4_hdmi->variant->get_hsm_clock(vc4_hdmi);
 838         unsigned long n, m;
 839
 840         rational_best_approximation(hsm_clock, vc4_hdmi->audio.samplerate,
 841                                     VC4_HD_MAI_SMP_N_MASK >>
 842                                     VC4_HD_MAI_SMP_N_SHIFT,
 843                                     (VC4_HD_MAI_SMP_M_MASK >>
 844                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
 845                                     &n, &m);
 846
 847         HDMI_WRITE(HDMI_MAI_SMP,
 848                  VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
 849                  VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
 850 }
 851
 852 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi)
 853 {
 854         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 855         struct drm_crtc *crtc = encoder->crtc;
 856         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 857         u32 samplerate = vc4_hdmi->audio.samplerate;
 858         u32 n, cts;
 859         u64 tmp;
 860
 861         n = 128 * samplerate / 1000;
 862         tmp = (u64)(mode->clock * 1000) * n;
 863         do_div(tmp, 128 * samplerate);
 864         cts = tmp;
 865
 866         HDMI_WRITE(HDMI_CRP_CFG,
 867                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
 868                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
 869
 870         /*
 871          * We could get slightly more accurate clocks in some cases by
 872          * providing a CTS_1 value.  The two CTS values are alternated
 873          * between based on the period fields
 874          */
 875         HDMI_WRITE(HDMI_CTS_0, cts);
 876         HDMI_WRITE(HDMI_CTS_1, cts);
 877 }
 878
 879 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
 880 {
 881         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
 882
 883         return snd_soc_card_get_drvdata(card);
 884 }
 885
 886 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
 887                                   struct snd_soc_dai *dai)
 888 {
 889         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
 890         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 891         struct drm_connector *connector = &vc4_hdmi->connector;
 892         int ret;
 893
 894         if (vc4_hdmi->audio.substream && vc4_hdmi->audio.substream != substream)
 895                 return -EINVAL;
 896
 897         vc4_hdmi->audio.substream = substream;
 898
 899         /*
 900          * If the HDMI encoder hasn't probed, or the encoder is
 901          * currently in DVI mode, treat the codec dai as missing.
 902          */
 903         if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 904                                 VC4_HDMI_RAM_PACKET_ENABLE))
 905                 return -ENODEV;
 906
 907         ret = snd_pcm_hw_constraint_eld(substream->runtime, connector->eld);
 908         if (ret)
 909                 return ret;
 910
 911         return 0;
 912 }
 913
 914 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 915 {
 916         return 0;
 917 }
 918
 919 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
 920 {
 921         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 922         struct device *dev = &vc4_hdmi->pdev->dev;
 923         int ret;
 924
 925         vc4_hdmi->audio.streaming = false;
 926         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO);
 927         if (ret)
 928                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
 929
 930         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
 931         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
 932         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
 933 }
 934
 935 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
 936                                     struct snd_soc_dai *dai)
 937 {
 938         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
 939
 940         if (substream != vc4_hdmi->audio.substream)
 941                 return;
 942
 943         vc4_hdmi_audio_reset(vc4_hdmi);
 944
 945         vc4_hdmi->audio.substream = NULL;
 946 }
 947
 948 /* HDMI audio codec callbacks */
 949 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
 950                                     struct snd_pcm_hw_params *params,
 951                                     struct snd_soc_dai *dai)
 952 {
 953         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
 954         struct device *dev = &vc4_hdmi->pdev->dev;
 955         u32 audio_packet_config, channel_mask;
 956         u32 channel_map;
 957
 958         if (substream != vc4_hdmi->audio.substream)
 959                 return -EINVAL;
 960
 961         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
 962                 params_rate(params), params_width(params),
 963                 params_channels(params));
 964
 965         vc4_hdmi->audio.channels = params_channels(params);
 966         vc4_hdmi->audio.samplerate = params_rate(params);
 967
 968         HDMI_WRITE(HDMI_MAI_CTL,
 969                  VC4_HD_MAI_CTL_RESET |
 970                  VC4_HD_MAI_CTL_FLUSH |
 971                  VC4_HD_MAI_CTL_DLATE |
 972                  VC4_HD_MAI_CTL_ERRORE |
 973                  VC4_HD_MAI_CTL_ERRORF);
 974
 975         vc4_hdmi_audio_set_mai_clock(vc4_hdmi);
 976
 977         /* The B frame identifier should match the value used by alsa-lib (8) */
 978         audio_packet_config =
 979                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
 980                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
 981                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
 982
 983         channel_mask = GENMASK(vc4_hdmi->audio.channels - 1, 0);
 984         audio_packet_config |= VC4_SET_FIELD(channel_mask,
 985                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
 986
 987         /* Set the MAI threshold.  This logic mimics the firmware's. */
 988         if (vc4_hdmi->audio.samplerate > 96000) {
 989                 HDMI_WRITE(HDMI_MAI_THR,
 990                          VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
 991                          VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
 992         } else if (vc4_hdmi->audio.samplerate > 48000) {
 993                 HDMI_WRITE(HDMI_MAI_THR,
 994                          VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
 995                          VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
 996         } else {
 997                 HDMI_WRITE(HDMI_MAI_THR,
 998                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
 999                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1000                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1001                          VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1002         }
1003
1004         HDMI_WRITE(HDMI_MAI_CONFIG,
1005                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1006                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1007
1008         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1009         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1010         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1011         vc4_hdmi_set_n_cts(vc4_hdmi);
1012
1013         return 0;
1014 }
1015
1016 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
1017                                   struct snd_soc_dai *dai)
1018 {
1019         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1020         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1021
1022         switch (cmd) {
1023         case SNDRV_PCM_TRIGGER_START:
1024                 vc4_hdmi_set_audio_infoframe(encoder);
1025                 vc4_hdmi->audio.streaming = true;
1026
1027                 if (vc4_hdmi->variant->phy_rng_enable)
1028                         vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1029
1030                 HDMI_WRITE(HDMI_MAI_CTL,
1031                          VC4_SET_FIELD(vc4_hdmi->audio.channels,
1032                                        VC4_HD_MAI_CTL_CHNUM) |
1033                                        VC4_HD_MAI_CTL_WHOLSMP |
1034                                        VC4_HD_MAI_CTL_CHALIGN |
1035                          VC4_HD_MAI_CTL_ENABLE);
1036                 break;
1037         case SNDRV_PCM_TRIGGER_STOP:
1038                 HDMI_WRITE(HDMI_MAI_CTL,
1039                          VC4_HD_MAI_CTL_DLATE |
1040                          VC4_HD_MAI_CTL_ERRORE |
1041                          VC4_HD_MAI_CTL_ERRORF);
1042
1043                 if (vc4_hdmi->variant->phy_rng_disable)
1044                         vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1045
1046                 vc4_hdmi->audio.streaming = false;
1047
1048                 break;
1049         default:
1050                 break;
1051         }
1052
1053         return 0;
1054 }
1055
1056 static inline struct vc4_hdmi *
1057 snd_component_to_hdmi(struct snd_soc_component *component)
1058 {
1059         struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
1060
1061         return snd_soc_card_get_drvdata(card);
1062 }
1063
1064 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
1065                                        struct snd_ctl_elem_info *uinfo)
1066 {
1067         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1068         struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1069         struct drm_connector *connector = &vc4_hdmi->connector;
1070
1071         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1072         uinfo->count = sizeof(connector->eld);
1073
1074         return 0;
1075 }
1076
1077 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
1078                                       struct snd_ctl_elem_value *ucontrol)
1079 {
1080         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1081         struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1082         struct drm_connector *connector = &vc4_hdmi->connector;
1083
1084         memcpy(ucontrol->value.bytes.data, connector->eld,
1085                sizeof(connector->eld));
1086
1087         return 0;
1088 }
1089
1090 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
1091         {
1092                 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1093                           SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1094                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1095                 .name = "ELD",
1096                 .info = vc4_hdmi_audio_eld_ctl_info,
1097                 .get = vc4_hdmi_audio_eld_ctl_get,
1098         },
1099 };
1100
1101 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
1102         SND_SOC_DAPM_OUTPUT("TX"),
1103 };
1104
1105 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
1106         { "TX", NULL, "Playback" },
1107 };
1108
1109 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = {
1110         .controls               = vc4_hdmi_audio_controls,
1111         .num_controls           = ARRAY_SIZE(vc4_hdmi_audio_controls),
1112         .dapm_widgets           = vc4_hdmi_audio_widgets,
1113         .num_dapm_widgets       = ARRAY_SIZE(vc4_hdmi_audio_widgets),
1114         .dapm_routes            = vc4_hdmi_audio_routes,
1115         .num_dapm_routes        = ARRAY_SIZE(vc4_hdmi_audio_routes),
1116         .idle_bias_on           = 1,
1117         .use_pmdown_time        = 1,
1118         .endianness             = 1,
1119         .non_legacy_dai_naming  = 1,
1120 };
1121
1122 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
1123         .startup = vc4_hdmi_audio_startup,
1124         .shutdown = vc4_hdmi_audio_shutdown,
1125         .hw_params = vc4_hdmi_audio_hw_params,
1126         .set_fmt = vc4_hdmi_audio_set_fmt,
1127         .trigger = vc4_hdmi_audio_trigger,
1128 };
1129
1130 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
1131         .name = "vc4-hdmi-hifi",
1132         .playback = {
1133                 .stream_name = "Playback",
1134                 .channels_min = 2,
1135                 .channels_max = 8,
1136                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1137                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1138                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1139                          SNDRV_PCM_RATE_192000,
1140                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1141         },
1142 };
1143
1144 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1145         .name = "vc4-hdmi-cpu-dai-component",
1146 };
1147
1148 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1149 {
1150         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1151
1152         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1153
1154         return 0;
1155 }
1156
1157 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1158         .name = "vc4-hdmi-cpu-dai",
1159         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1160         .playback = {
1161                 .stream_name = "Playback",
1162                 .channels_min = 1,
1163                 .channels_max = 8,
1164                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1165                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1166                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1167                          SNDRV_PCM_RATE_192000,
1168                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1169         },
1170         .ops = &vc4_hdmi_audio_dai_ops,
1171 };
1172
1173 static const struct snd_dmaengine_pcm_config pcm_conf = {
1174         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1175         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1176 };
1177
1178 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1179 {
1180         const struct vc4_hdmi_register *mai_data =
1181                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1182         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1183         struct snd_soc_card *card = &vc4_hdmi->audio.card;
1184         struct device *dev = &vc4_hdmi->pdev->dev;
1185         const __be32 *addr;
1186         int index;
1187         int ret;
1188         int len;
1189
1190         if (!vc4_hdmi->variant->audio_available)
1191                 return 0;
1192
1193         if (!of_find_property(dev->of_node, "dmas", &len) ||
1194             len == 0) {
1195                 dev_warn(dev,
1196                          "'dmas' DT property is missing or empty, no HDMI audio\n");
1197                 return 0;
1198         }
1199
1200         if (mai_data->reg != VC4_HD) {
1201                 WARN_ONCE(true, "MAI isn't in the HD block\n");
1202                 return -EINVAL;
1203         }
1204
1205         /*
1206          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1207          * the bus address specified in the DT, because the physical address
1208          * (the one returned by platform_get_resource()) is not appropriate
1209          * for DMA transfers.
1210          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1211          */
1212         index = of_property_match_string(dev->of_node, "reg-names", "hd");
1213         addr = of_get_address(dev->of_node, index, NULL, NULL);
1214
1215         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1216         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1217         vc4_hdmi->audio.dma_data.maxburst = 2;
1218
1219         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1220         if (ret) {
1221                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1222                 return ret;
1223         }
1224
1225         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1226                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1227         if (ret) {
1228                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1229                 return ret;
1230         }
1231
1232         /* register component and codec dai */
1233         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv,
1234                                      &vc4_hdmi_audio_codec_dai_drv, 1);
1235         if (ret) {
1236                 dev_err(dev, "Could not register component: %d\n", ret);
1237                 return ret;
1238         }
1239
1240         dai_link->cpus          = &vc4_hdmi->audio.cpu;
1241         dai_link->codecs        = &vc4_hdmi->audio.codec;
1242         dai_link->platforms     = &vc4_hdmi->audio.platform;
1243
1244         dai_link->num_cpus      = 1;
1245         dai_link->num_codecs    = 1;
1246         dai_link->num_platforms = 1;
1247
1248         dai_link->name = "MAI";
1249         dai_link->stream_name = "MAI PCM";
1250         dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1251         dai_link->cpus->dai_name = dev_name(dev);
1252         dai_link->codecs->name = dev_name(dev);
1253         dai_link->platforms->name = dev_name(dev);
1254
1255         card->dai_link = dai_link;
1256         card->num_links = 1;
1257         card->name = vc4_hdmi->variant->id ? "vc4-hdmi1" : "vc4-hdmi";
1258         card->driver_name = "vc4-hdmi";
1259         card->dev = dev;
1260
1261         /*
1262          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1263          * stores a pointer to the snd card object in dev->driver_data. This
1264          * means we cannot use it for something else. The hdmi back-pointer is
1265          * now stored in card->drvdata and should be retrieved with
1266          * snd_soc_card_get_drvdata() if needed.
1267          */
1268         snd_soc_card_set_drvdata(card, vc4_hdmi);
1269         ret = devm_snd_soc_register_card(dev, card);
1270         if (ret)
1271                 dev_err(dev, "Could not register sound card: %d\n", ret);
1272
1273         return ret;
1274
1275 }
1276
1277 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1278 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1279 {
1280         struct vc4_hdmi *vc4_hdmi = priv;
1281
1282         if (vc4_hdmi->cec_irq_was_rx) {
1283                 if (vc4_hdmi->cec_rx_msg.len)
1284                         cec_received_msg(vc4_hdmi->cec_adap,
1285                                          &vc4_hdmi->cec_rx_msg);
1286         } else if (vc4_hdmi->cec_tx_ok) {
1287                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1288                                   0, 0, 0, 0);
1289         } else {
1290                 /*
1291                  * This CEC implementation makes 1 retry, so if we
1292                  * get a NACK, then that means it made 2 attempts.
1293                  */
1294                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1295                                   0, 2, 0, 0);
1296         }
1297         return IRQ_HANDLED;
1298 }
1299
1300 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1301 {
1302         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1303         unsigned int i;
1304
1305         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1306                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1307
1308         if (msg->len > 16) {
1309                 DRM_ERROR("Attempting to read too much data (%d)\n", msg->len);
1310                 return;
1311         }
1312         for (i = 0; i < msg->len; i += 4) {
1313                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i>>2));
1314
1315                 msg->msg[i] = val & 0xff;
1316                 msg->msg[i + 1] = (val >> 8) & 0xff;
1317                 msg->msg[i + 2] = (val >> 16) & 0xff;
1318                 msg->msg[i + 3] = (val >> 24) & 0xff;
1319         }
1320 }
1321
1322 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1323 {
1324         struct vc4_hdmi *vc4_hdmi = priv;
1325         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1326         u32 cntrl1, cntrl5;
1327
1328         if (!(stat & vc4_hdmi->variant->cec_mask))
1329                 return IRQ_NONE;
1330         vc4_hdmi->cec_rx_msg.len = 0;
1331         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1332         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1333         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1334         if (vc4_hdmi->cec_irq_was_rx) {
1335                 vc4_cec_read_msg(vc4_hdmi, cntrl1);
1336                 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1337                 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1338                 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1339         } else {
1340                 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1341                 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1342         }
1343         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1344         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, vc4_hdmi->variant->cec_mask);
1345
1346         return IRQ_WAKE_THREAD;
1347 }
1348
1349 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1350 {
1351         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1352         /* clock period in microseconds */
1353         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1354         u32 val = HDMI_READ(HDMI_CEC_CNTRL_5);
1355
1356         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1357                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1358                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1359         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1360                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1361
1362         if (enable) {
1363                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1364                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1365                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1366                 HDMI_WRITE(HDMI_CEC_CNTRL_2,
1367                          ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1368                          ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1369                          ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1370                          ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1371                          ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1372                 HDMI_WRITE(HDMI_CEC_CNTRL_3,
1373                          ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1374                          ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1375                          ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1376                          ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1377                 HDMI_WRITE(HDMI_CEC_CNTRL_4,
1378                          ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1379                          ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1380                          ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1381                          ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1382
1383                 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, vc4_hdmi->variant->cec_mask);
1384         } else {
1385                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, vc4_hdmi->variant->cec_mask);
1386                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1387                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1388         }
1389         return 0;
1390 }
1391
1392 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1393 {
1394         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1395
1396         HDMI_WRITE(HDMI_CEC_CNTRL_1,
1397                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1398                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1399         return 0;
1400 }
1401
1402 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1403                                       u32 signal_free_time, struct cec_msg *msg)
1404 {
1405         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1406         u32 val;
1407         unsigned int i;
1408
1409         if (msg->len > 16) {
1410                 DRM_ERROR("Attempting to transmit too much data (%d)\n", msg->len);
1411                 return -ENOMEM;
1412         }
1413         for (i = 0; i < msg->len; i += 4)
1414                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i>>2),
1415                            (msg->msg[i]) |
1416                            (msg->msg[i + 1] << 8) |
1417                            (msg->msg[i + 2] << 16) |
1418                            (msg->msg[i + 3] << 24));
1419
1420         val = HDMI_READ(HDMI_CEC_CNTRL_1);
1421         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1422         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1423         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1424         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1425         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1426
1427         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1428         return 0;
1429 }
1430
1431 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1432         .adap_enable = vc4_hdmi_cec_adap_enable,
1433         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1434         .adap_transmit = vc4_hdmi_cec_adap_transmit,
1435 };
1436
1437 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1438 {
1439         struct cec_connector_info conn_info;
1440         struct platform_device *pdev = vc4_hdmi->pdev;
1441         u32 value;
1442         u32 clk_cnt;
1443         int ret;
1444
1445         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1446                                                   vc4_hdmi, "vc4",
1447                                                   CEC_CAP_DEFAULTS |
1448                                                   CEC_CAP_CONNECTOR_INFO, 1);
1449         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
1450         if (ret < 0)
1451                 return ret;
1452
1453         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
1454         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
1455
1456         HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
1457         value = HDMI_READ(HDMI_CEC_CNTRL_1);
1458         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
1459         /*
1460          * Set the logical address to Unregistered and set the clock
1461          * divider: the hsm_clock rate and this divider setting will
1462          * give a 40 kHz CEC clock.
1463          */
1464         clk_cnt = vc4_hdmi->variant->cec_input_clock / CEC_CLOCK_FREQ;
1465         value |= VC4_HDMI_CEC_ADDR_MASK |
1466                  ((clk_cnt-1) << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
1467         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
1468         ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),
1469                                         vc4_cec_irq_handler,
1470                                         vc4_cec_irq_handler_thread,
1471                                         IRQF_SHARED,
1472                                         "vc4 hdmi cec", vc4_hdmi);
1473         if (ret)
1474                 goto err_delete_cec_adap;
1475
1476         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
1477         if (ret < 0)
1478                 goto err_delete_cec_adap;
1479
1480         return 0;
1481
1482 err_delete_cec_adap:
1483         cec_delete_adapter(vc4_hdmi->cec_adap);
1484
1485         return ret;
1486 }
1487
1488 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
1489 {
1490         cec_unregister_adapter(vc4_hdmi->cec_adap);
1491 }
1492 #else
1493 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1494 {
1495         return 0;
1496 }
1497
1498 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
1499
1500 #endif
1501
1502 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
1503                                  struct debugfs_regset32 *regset,
1504                                  enum vc4_hdmi_regs reg)
1505 {
1506         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1507         struct debugfs_reg32 *regs;
1508         unsigned int count = 0;
1509         unsigned int i;
1510
1511         regs = kzalloc(variant->num_registers * sizeof(*regs),
1512                        GFP_KERNEL);
1513         if (!regs)
1514                 return -ENOMEM;
1515
1516         for (i = 0; i < variant->num_registers; i++) {
1517                 const struct vc4_hdmi_register *field = &variant->registers[i];
1518
1519                 if (field->reg != reg)
1520                         continue;
1521
1522                 regs[count].name = field->name;
1523                 regs[count].offset = field->offset;
1524                 count++;
1525         }
1526
1527         regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
1528         if (!regs)
1529                 return -ENOMEM;
1530
1531         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
1532         regset->regs = regs;
1533         regset->nregs = count;
1534
1535         return 0;
1536 }
1537
1538 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1539 {
1540         struct platform_device *pdev = vc4_hdmi->pdev;
1541         struct device *dev = &pdev->dev;
1542         int ret;
1543
1544         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1545         if (IS_ERR(vc4_hdmi->hdmicore_regs))
1546                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1547
1548         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
1549         if (ret)
1550                 return ret;
1551
1552         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1553         if (IS_ERR(vc4_hdmi->hd_regs))
1554                 return PTR_ERR(vc4_hdmi->hd_regs);
1555
1556         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
1557         if (ret)
1558                 return ret;
1559
1560         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1561         if (IS_ERR(vc4_hdmi->pixel_clock)) {
1562                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
1563                 if (ret != -EPROBE_DEFER)
1564                         DRM_ERROR("Failed to get pixel clock\n");
1565                 return ret;
1566         }
1567
1568         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1569         if (IS_ERR(vc4_hdmi->hsm_clock)) {
1570                 DRM_ERROR("Failed to get HDMI state machine clock\n");
1571                 return PTR_ERR(vc4_hdmi->hsm_clock);
1572         }
1573
1574         return 0;
1575 }
1576
1577 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1578 {
1579         struct platform_device *pdev = vc4_hdmi->pdev;
1580         struct device *dev = &pdev->dev;
1581         struct resource *res;
1582
1583         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
1584         if (!res)
1585                 return -ENODEV;
1586
1587         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
1588                                                resource_size(res));
1589         if (IS_ERR(vc4_hdmi->hdmicore_regs))
1590                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1591
1592         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
1593         if (!res)
1594                 return -ENODEV;
1595
1596         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
1597         if (IS_ERR(vc4_hdmi->hd_regs))
1598                 return PTR_ERR(vc4_hdmi->hd_regs);
1599
1600         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
1601         if (!res)
1602                 return -ENODEV;
1603
1604         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
1605         if (IS_ERR(vc4_hdmi->cec_regs))
1606                 return PTR_ERR(vc4_hdmi->cec_regs);
1607
1608         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
1609         if (!res)
1610                 return -ENODEV;
1611
1612         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
1613         if (IS_ERR(vc4_hdmi->csc_regs))
1614                 return PTR_ERR(vc4_hdmi->csc_regs);
1615
1616         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
1617         if (!res)
1618                 return -ENODEV;
1619
1620         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
1621         if (IS_ERR(vc4_hdmi->dvp_regs))
1622                 return PTR_ERR(vc4_hdmi->dvp_regs);
1623
1624         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr2");
1625         if (!res)
1626                 return -ENODEV;
1627
1628         vc4_hdmi->intr2_regs = devm_ioremap(dev, res->start, resource_size(res));
1629         if (IS_ERR(vc4_hdmi->intr2_regs))
1630                 return PTR_ERR(vc4_hdmi->intr2_regs);
1631
1632         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
1633         if (!res)
1634                 return -ENODEV;
1635
1636         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
1637         if (IS_ERR(vc4_hdmi->phy_regs))
1638                 return PTR_ERR(vc4_hdmi->phy_regs);
1639
1640         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
1641         if (!res)
1642                 return -ENODEV;
1643
1644         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
1645         if (IS_ERR(vc4_hdmi->ram_regs))
1646                 return PTR_ERR(vc4_hdmi->ram_regs);
1647
1648         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
1649         if (!res)
1650                 return -ENODEV;
1651
1652         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
1653         if (IS_ERR(vc4_hdmi->rm_regs))
1654                 return PTR_ERR(vc4_hdmi->rm_regs);
1655
1656         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1657         if (IS_ERR(vc4_hdmi->hsm_clock)) {
1658                 DRM_ERROR("Failed to get HDMI state machine clock\n");
1659                 return PTR_ERR(vc4_hdmi->hsm_clock);
1660         }
1661
1662         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
1663         if (IS_ERR(vc4_hdmi->reset)) {
1664                 DRM_ERROR("Failed to get HDMI reset line\n");
1665                 return PTR_ERR(vc4_hdmi->reset);
1666         }
1667
1668         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
1669         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
1670                 DRM_ERROR("Failed to get pixel bvb clock\n");
1671                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
1672         }
1673
1674         return 0;
1675 }
1676
1677 #ifdef CONFIG_EXTCON
1678 static const unsigned int vc4_hdmi_extcon_cable[] = {
1679         EXTCON_DISP_HDMI,
1680         EXTCON_NONE,
1681 };
1682 #endif
1683
1684 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
1685 {
1686         struct platform_device *pdev = to_platform_device(dev);
1687         struct drm_device *drm = dev_get_drvdata(master);
1688         const struct vc4_hdmi_variant *variant;
1689         struct vc4_hdmi *vc4_hdmi;
1690         struct drm_encoder *encoder;
1691         struct device_node *ddc_node;
1692         u32 value;
1693         int ret;
1694
1695         vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
1696         if (!vc4_hdmi)
1697                 return -ENOMEM;
1698         vc4_hdmi->pdev = pdev;
1699         variant = of_device_get_match_data(dev);
1700         vc4_hdmi->variant = variant;
1701         vc4_hdmi->encoder.base.type = variant->id ? VC4_ENCODER_TYPE_HDMI1 : VC4_ENCODER_TYPE_HDMI0;
1702         encoder = &vc4_hdmi->encoder.base.base;
1703
1704         ret = variant->init_resources(vc4_hdmi);
1705         if (ret)
1706                 return ret;
1707
1708         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
1709         if (!ddc_node) {
1710                 DRM_ERROR("Failed to find ddc node in device tree\n");
1711                 return -ENODEV;
1712         }
1713
1714         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1715         of_node_put(ddc_node);
1716         if (!vc4_hdmi->ddc) {
1717                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
1718                 return -EPROBE_DEFER;
1719         }
1720
1721 #ifdef CONFIG_EXTCON
1722         vc4_hdmi->status = connector_status_disconnected;
1723
1724         /* Initialize extcon device */
1725         vc4_hdmi->edev = devm_extcon_dev_allocate(dev, vc4_hdmi_extcon_cable);
1726         if (IS_ERR(vc4_hdmi->edev)) {
1727                 dev_err(dev, "failed to allocate memory for extcon\n");
1728                 return PTR_ERR(vc4_hdmi->edev);
1729         }
1730
1731         ret = devm_extcon_dev_register(dev, vc4_hdmi->edev);
1732         if (ret) {
1733                 dev_err(dev, "failed to register extcon device\n");
1734                 return ret;
1735         }
1736 #endif
1737
1738         /* Only use the GPIO HPD pin if present in the DT, otherwise
1739          * we'll use the HDMI core's register.
1740          */
1741         if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
1742                 enum of_gpio_flags hpd_gpio_flags;
1743
1744                 vc4_hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
1745                                                          "hpd-gpios", 0,
1746                                                          &hpd_gpio_flags);
1747                 if (vc4_hdmi->hpd_gpio < 0) {
1748                         ret = vc4_hdmi->hpd_gpio;
1749                         goto err_unprepare_hsm;
1750                 }
1751
1752                 vc4_hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
1753         }
1754
1755         pm_runtime_enable(dev);
1756
1757         drm_encoder_init(drm, encoder, &vc4_hdmi_encoder_funcs,
1758                          DRM_MODE_ENCODER_TMDS, NULL);
1759         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
1760
1761         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
1762         if (ret)
1763                 goto err_destroy_encoder;
1764
1765         ret = vc4_hdmi_cec_init(vc4_hdmi);
1766         if (ret)
1767                 goto err_destroy_conn;
1768
1769         ret = vc4_hdmi_audio_init(vc4_hdmi);
1770         if (ret)
1771                 goto err_free_cec;
1772
1773         vc4_debugfs_add_file(drm,
1774                              variant->id ? "hdmi1_regs" : "hdmi_regs",
1775                              vc4_hdmi_debugfs_regs,
1776                              vc4_hdmi);
1777
1778         return 0;
1779
1780 err_free_cec:
1781         vc4_hdmi_cec_exit(vc4_hdmi);
1782 err_destroy_conn:
1783         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
1784 err_destroy_encoder:
1785         vc4_hdmi_encoder_destroy(encoder);
1786 err_unprepare_hsm:
1787         pm_runtime_disable(dev);
1788         put_device(&vc4_hdmi->ddc->dev);
1789
1790         return ret;
1791 }
1792
1793 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
1794                             void *data)
1795 {
1796         /*
1797          * snd_soc_register_card will set the device drvdata pointer
1798          * to the card being registered.
1799          */
1800         struct snd_soc_card *card = dev_get_drvdata(dev);
1801         struct vc4_hdmi *vc4_hdmi = snd_soc_card_get_drvdata(card);
1802
1803         kfree(vc4_hdmi->hdmi_regset.regs);
1804         kfree(vc4_hdmi->hd_regset.regs);
1805
1806         vc4_hdmi_cec_exit(vc4_hdmi);
1807         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
1808         vc4_hdmi_encoder_destroy(&vc4_hdmi->encoder.base.base);
1809
1810         pm_runtime_disable(dev);
1811
1812         put_device(&vc4_hdmi->ddc->dev);
1813 }
1814
1815 static const struct component_ops vc4_hdmi_ops = {
1816         .bind   = vc4_hdmi_bind,
1817         .unbind = vc4_hdmi_unbind,
1818 };
1819
1820 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
1821 {
1822         return component_add(&pdev->dev, &vc4_hdmi_ops);
1823 }
1824
1825 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
1826 {
1827         component_del(&pdev->dev, &vc4_hdmi_ops);
1828         return 0;
1829 }
1830
1831 static const struct vc4_hdmi_variant bcm2835_variant = {
1832         .max_pixel_clock        = 162000000,
1833         .cec_input_clock        = VC4_HSM_CLOCK,
1834         .audio_available        = true,
1835         .registers              = vc4_hdmi_fields,
1836         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
1837
1838         .init_resources         = vc4_hdmi_init_resources,
1839         .csc_setup              = vc4_hdmi_csc_setup,
1840         .reset                  = vc4_hdmi_reset,
1841         .set_timings            = vc4_hdmi_set_timings,
1842         .phy_init               = vc4_hdmi_phy_init,
1843         .phy_disable            = vc4_hdmi_phy_disable,
1844         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
1845         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
1846         .get_hsm_clock          = vc4_hdmi_get_hsm_clock,
1847         .calc_hsm_clock         = vc4_hdmi_calc_hsm_clock,
1848         .channel_map            = vc4_hdmi_channel_map,
1849
1850         .cec_mask = VC4_HDMI_CPU_CEC,
1851 };
1852
1853 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
1854         .id                     = 0,
1855         .audio_available        = true,
1856         .max_pixel_clock        = 297000000,
1857         .cec_input_clock        = 27000000,
1858         .registers              = vc5_hdmi_hdmi0_fields,
1859         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
1860         .phy_lane_mapping       = {
1861                 PHY_LANE_0,
1862                 PHY_LANE_1,
1863                 PHY_LANE_2,
1864                 PHY_LANE_CK,
1865         },
1866
1867         .init_resources         = vc5_hdmi_init_resources,
1868         .csc_setup              = vc5_hdmi_csc_setup,
1869         .reset                  = vc5_hdmi_reset,
1870         .set_timings            = vc5_hdmi_set_timings,
1871         .phy_init               = vc5_hdmi_phy_init,
1872         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
1873         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
1874         .get_hsm_clock          = vc5_hdmi_get_hsm_clock,
1875         .calc_hsm_clock         = vc5_hdmi_calc_hsm_clock,
1876         .channel_map            = vc5_hdmi_channel_map,
1877
1878         .cec_mask = VC5_HDMI0_CPU_CEC_RX | VC5_HDMI0_CPU_CEC_TX,
1879 };
1880
1881 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
1882         .id                     = 1,
1883         .audio_available        = true,
1884         .max_pixel_clock        = 297000000,
1885         .cec_input_clock        = 27000000,
1886         .registers              = vc5_hdmi_hdmi1_fields,
1887         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
1888         .phy_lane_mapping       = {
1889                 PHY_LANE_1,
1890                 PHY_LANE_0,
1891                 PHY_LANE_CK,
1892                 PHY_LANE_2,
1893         },
1894
1895         .init_resources         = vc5_hdmi_init_resources,
1896         .csc_setup              = vc5_hdmi_csc_setup,
1897         .reset                  = vc5_hdmi_reset,
1898         .set_timings            = vc5_hdmi_set_timings,
1899         .phy_init               = vc5_hdmi_phy_init,
1900         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
1901         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
1902         .get_hsm_clock          = vc5_hdmi_get_hsm_clock,
1903         .calc_hsm_clock         = vc5_hdmi_calc_hsm_clock,
1904         .channel_map            = vc5_hdmi_channel_map,
1905
1906         .cec_mask = VC5_HDMI1_CPU_CEC_RX | VC5_HDMI1_CPU_CEC_TX,
1907 };
1908
1909 static const struct of_device_id vc4_hdmi_dt_match[] = {
1910         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
1911         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
1912         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
1913         {}
1914 };
1915
1916 struct platform_driver vc4_hdmi_driver = {
1917         .probe = vc4_hdmi_dev_probe,
1918         .remove = vc4_hdmi_dev_remove,
1919         .driver = {
1920                 .name = "vc4_hdmi",
1921                 .of_match_table = vc4_hdmi_dt_match,
1922         },
1923 };