drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <drm/drm_simple_kms_helper.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include <linux/clk.h>
  40 #include <linux/component.h>
  41 #include <linux/gpio/consumer.h>
  42 #include <linux/i2c.h>
  43 #include <linux/of_address.h>
  44 #include <linux/of_gpio.h>
  45 #include <linux/of_platform.h>
  46 #include <linux/pm_runtime.h>
  47 #include <linux/rational.h>
  48 #include <linux/reset.h>
  49 #include <sound/dmaengine_pcm.h>
  50 #include <sound/hdmi-codec.h>
  51 #include <sound/pcm_drm_eld.h>
  52 #include <sound/pcm_params.h>
  53 #include <sound/soc.h>
  54 #include "media/cec.h"
  55 #include "vc4_drv.h"
  56 #include "vc4_hdmi.h"
  57 #include "vc4_hdmi_regs.h"
  58 #include "vc4_regs.h"
  59
  60 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  61 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  62 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  63 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  64 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  65 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  66
  67 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  68 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  69 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  70 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  71
  72 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  73 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  74 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  75 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  76 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  77 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  78
  79 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  80 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  81
  82 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  83
  84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  85 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  86
  87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  88 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  89
  90 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  91
  92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
  93 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
  94
  95 # define VC4_HD_M_SW_RST                        BIT(2)
  96 # define VC4_HD_M_ENABLE                        BIT(0)
  97
  98 #define HSM_MIN_CLOCK_FREQ      120000000
  99 #define CEC_CLOCK_FREQ 40000
 100
 101 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 102
 103 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode)
 104 {
 105         return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK;
 106 }
 107
 108 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 109 {
 110         struct drm_info_node *node = (struct drm_info_node *)m->private;
 111         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
 112         struct drm_printer p = drm_seq_file_printer(m);
 113
 114         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 115         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 116
 117         return 0;
 118 }
 119
 120 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 121 {
 122         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 123         udelay(1);
 124         HDMI_WRITE(HDMI_M_CTL, 0);
 125
 126         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 127
 128         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 129                    VC4_HDMI_SW_RESET_HDMI |
 130                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 131
 132         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 133 }
 134
 135 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 136 {
 137         reset_control_reset(vc4_hdmi->reset);
 138
 139         HDMI_WRITE(HDMI_DVP_CTL, 0);
 140
 141         HDMI_WRITE(HDMI_CLOCK_STOP,
 142                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 143 }
 144
 145 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 146 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 147 {
 148         u16 clk_cnt;
 149         u32 value;
 150
 151         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 152         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 153
 154         /*
 155          * Set the clock divider: the hsm_clock rate and this divider
 156          * setting will give a 40 kHz CEC clock.
 157          */
 158         clk_cnt = clk_get_rate(vc4_hdmi->cec_clock) / CEC_CLOCK_FREQ;
 159         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 160         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 161 }
 162 #else
 163 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 164 #endif
 165
 166 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder);
 167
 168 static enum drm_connector_status
 169 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 170 {
 171         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 172         bool connected = false;
 173
 174         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 175
 176         if (vc4_hdmi->hpd_gpio &&
 177             gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) {
 178                 connected = true;
 179         } else if (drm_probe_ddc(vc4_hdmi->ddc)) {
 180                 connected = true;
 181         } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) {
 182                 connected = true;
 183         }
 184
 185         if (connected) {
 186                 if (connector->status != connector_status_connected) {
 187                         struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
 188
 189                         if (edid) {
 190                                 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 191                                 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
 192                                 kfree(edid);
 193                         }
 194                 }
 195
 196                 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base);
 197                 pm_runtime_put(&vc4_hdmi->pdev->dev);
 198                 return connector_status_connected;
 199         }
 200
 201         cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 202         pm_runtime_put(&vc4_hdmi->pdev->dev);
 203         return connector_status_disconnected;
 204 }
 205
 206 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 207 {
 208         drm_connector_unregister(connector);
 209         drm_connector_cleanup(connector);
 210 }
 211
 212 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 213 {
 214         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 215         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 216         int ret = 0;
 217         struct edid *edid;
 218
 219         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 220         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 221         if (!edid)
 222                 return -ENODEV;
 223
 224         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 225
 226         drm_connector_update_edid_property(connector, edid);
 227         ret = drm_add_edid_modes(connector, edid);
 228         kfree(edid);
 229
 230         if (vc4_hdmi->disable_4kp60) {
 231                 struct drm_device *drm = connector->dev;
 232                 struct drm_display_mode *mode;
 233
 234                 list_for_each_entry(mode, &connector->probed_modes, head) {
 235                         if (vc4_hdmi_mode_needs_scrambling(mode)) {
 236                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 237                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 238                         }
 239                 }
 240         }
 241
 242         return ret;
 243 }
 244
 245 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 246                                            struct drm_atomic_state *state)
 247 {
 248         struct drm_connector_state *old_state =
 249                 drm_atomic_get_old_connector_state(state, connector);
 250         struct drm_connector_state *new_state =
 251                 drm_atomic_get_new_connector_state(state, connector);
 252         struct drm_crtc *crtc = new_state->crtc;
 253
 254         if (!crtc)
 255                 return 0;
 256
 257         if (old_state->colorspace != new_state->colorspace ||
 258             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 259                 struct drm_crtc_state *crtc_state;
 260
 261                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 262                 if (IS_ERR(crtc_state))
 263                         return PTR_ERR(crtc_state);
 264
 265                 crtc_state->mode_changed = true;
 266         }
 267
 268         return 0;
 269 }
 270
 271 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 272 {
 273         struct vc4_hdmi_connector_state *old_state =
 274                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 275         struct vc4_hdmi_connector_state *new_state =
 276                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 277
 278         if (connector->state)
 279                 __drm_atomic_helper_connector_destroy_state(connector->state);
 280
 281         kfree(old_state);
 282         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 283
 284         if (!new_state)
 285                 return;
 286
 287         new_state->base.max_bpc = 8;
 288         new_state->base.max_requested_bpc = 8;
 289         drm_atomic_helper_connector_tv_reset(connector);
 290 }
 291
 292 static struct drm_connector_state *
 293 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 294 {
 295         struct drm_connector_state *conn_state = connector->state;
 296         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 297         struct vc4_hdmi_connector_state *new_state;
 298
 299         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 300         if (!new_state)
 301                 return NULL;
 302
 303         new_state->pixel_rate = vc4_state->pixel_rate;
 304         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 305
 306         return &new_state->base;
 307 }
 308
 309 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 310         .detect = vc4_hdmi_connector_detect,
 311         .fill_modes = drm_helper_probe_single_connector_modes,
 312         .destroy = vc4_hdmi_connector_destroy,
 313         .reset = vc4_hdmi_connector_reset,
 314         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 315         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 316 };
 317
 318 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 319         .get_modes = vc4_hdmi_connector_get_modes,
 320         .atomic_check = vc4_hdmi_connector_atomic_check,
 321 };
 322
 323 static int vc4_hdmi_connector_init(struct drm_device *dev,
 324                                    struct vc4_hdmi *vc4_hdmi)
 325 {
 326         struct drm_connector *connector = &vc4_hdmi->connector;
 327         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 328         int ret;
 329
 330         drm_connector_init_with_ddc(dev, connector,
 331                                     &vc4_hdmi_connector_funcs,
 332                                     DRM_MODE_CONNECTOR_HDMIA,
 333                                     vc4_hdmi->ddc);
 334         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 335
 336         /*
 337          * Some of the properties below require access to state, like bpc.
 338          * Allocate some default initial connector state with our reset helper.
 339          */
 340         if (connector->funcs->reset)
 341                 connector->funcs->reset(connector);
 342
 343         /* Create and attach TV margin props to this connector. */
 344         ret = drm_mode_create_tv_margin_properties(dev);
 345         if (ret)
 346                 return ret;
 347
 348         ret = drm_mode_create_hdmi_colorspace_property(connector);
 349         if (ret)
 350                 return ret;
 351
 352         drm_connector_attach_colorspace_property(connector);
 353         drm_connector_attach_tv_margin_properties(connector);
 354         drm_connector_attach_max_bpc_property(connector, 8, 12);
 355
 356         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 357                              DRM_CONNECTOR_POLL_DISCONNECT);
 358
 359         connector->interlace_allowed = 1;
 360         connector->doublescan_allowed = 0;
 361
 362         if (vc4_hdmi->variant->supports_hdr)
 363                 drm_connector_attach_hdr_output_metadata_property(connector);
 364
 365         drm_connector_attach_encoder(connector, encoder);
 366
 367         return 0;
 368 }
 369
 370 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 371                                 enum hdmi_infoframe_type type,
 372                                 bool poll)
 373 {
 374         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 375         u32 packet_id = type - 0x80;
 376
 377         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 378                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 379
 380         if (!poll)
 381                 return 0;
 382
 383         return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 384                           BIT(packet_id)), 100);
 385 }
 386
 387 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 388                                      union hdmi_infoframe *frame)
 389 {
 390         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 391         u32 packet_id = frame->any.type - 0x80;
 392         const struct vc4_hdmi_register *ram_packet_start =
 393                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 394         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 395         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 396                                                        ram_packet_start->reg);
 397         uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
 398         ssize_t len, i;
 399         int ret;
 400
 401         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 402                     VC4_HDMI_RAM_PACKET_ENABLE),
 403                   "Packet RAM has to be on to store the packet.");
 404
 405         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 406         if (len < 0)
 407                 return;
 408
 409         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 410         if (ret) {
 411                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 412                 return;
 413         }
 414
 415         for (i = 0; i < len; i += 7) {
 416                 writel(buffer[i + 0] << 0 |
 417                        buffer[i + 1] << 8 |
 418                        buffer[i + 2] << 16,
 419                        base + packet_reg);
 420                 packet_reg += 4;
 421
 422                 writel(buffer[i + 3] << 0 |
 423                        buffer[i + 4] << 8 |
 424                        buffer[i + 5] << 16 |
 425                        buffer[i + 6] << 24,
 426                        base + packet_reg);
 427                 packet_reg += 4;
 428         }
 429
 430         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 431                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 432         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 433                         BIT(packet_id)), 100);
 434         if (ret)
 435                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 436 }
 437
 438 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 439 {
 440         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 441         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 442         struct drm_connector *connector = &vc4_hdmi->connector;
 443         struct drm_connector_state *cstate = connector->state;
 444         struct drm_crtc *crtc = encoder->crtc;
 445         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 446         union hdmi_infoframe frame;
 447         int ret;
 448
 449         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 450                                                        connector, mode);
 451         if (ret < 0) {
 452                 DRM_ERROR("couldn't fill AVI infoframe\n");
 453                 return;
 454         }
 455
 456         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 457                                            connector, mode,
 458                                            vc4_encoder->limited_rgb_range ?
 459                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 460                                            HDMI_QUANTIZATION_RANGE_FULL);
 461         drm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate);
 462         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 463
 464         vc4_hdmi_write_infoframe(encoder, &frame);
 465 }
 466
 467 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 468 {
 469         union hdmi_infoframe frame;
 470         int ret;
 471
 472         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 473         if (ret < 0) {
 474                 DRM_ERROR("couldn't fill SPD infoframe\n");
 475                 return;
 476         }
 477
 478         frame.spd.sdi = HDMI_SPD_SDI_PC;
 479
 480         vc4_hdmi_write_infoframe(encoder, &frame);
 481 }
 482
 483 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 484 {
 485         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 486         struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
 487         union hdmi_infoframe frame;
 488
 489         memcpy(&frame.audio, audio, sizeof(*audio));
 490         vc4_hdmi_write_infoframe(encoder, &frame);
 491 }
 492
 493 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 494 {
 495         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 496         struct drm_connector *connector = &vc4_hdmi->connector;
 497         struct drm_connector_state *conn_state = connector->state;
 498         union hdmi_infoframe frame;
 499
 500         if (!vc4_hdmi->variant->supports_hdr)
 501                 return;
 502
 503         if (!conn_state->hdr_output_metadata)
 504                 return;
 505
 506         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 507                 return;
 508
 509         vc4_hdmi_write_infoframe(encoder, &frame);
 510 }
 511
 512 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 513 {
 514         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 515
 516         vc4_hdmi_set_avi_infoframe(encoder);
 517         vc4_hdmi_set_spd_infoframe(encoder);
 518         /*
 519          * If audio was streaming, then we need to reenabled the audio
 520          * infoframe here during encoder_enable.
 521          */
 522         if (vc4_hdmi->audio.streaming)
 523                 vc4_hdmi_set_audio_infoframe(encoder);
 524
 525         vc4_hdmi_set_hdr_infoframe(encoder);
 526 }
 527
 528 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
 529                                          struct drm_display_mode *mode)
 530 {
 531         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 532         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 533         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 534
 535         if (!vc4_encoder->hdmi_monitor)
 536                 return false;
 537
 538         if (!display->hdmi.scdc.supported ||
 539             !display->hdmi.scdc.scrambling.supported)
 540                 return false;
 541
 542         return true;
 543 }
 544
 545 #define SCRAMBLING_POLLING_DELAY_MS     1000
 546
 547 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 548 {
 549         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 550         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 551
 552         if (!vc4_hdmi_supports_scrambling(encoder, mode))
 553                 return;
 554
 555         if (!vc4_hdmi_mode_needs_scrambling(mode))
 556                 return;
 557
 558         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 559         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 560
 561         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
 562                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 563
 564         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 565                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 566 }
 567
 568 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
 569 {
 570         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 571         struct drm_crtc *crtc = encoder->crtc;
 572
 573         /*
 574          * At boot, encoder->crtc will be NULL. Since we don't know the
 575          * state of the scrambler and in order to avoid any
 576          * inconsistency, let's disable it all the time.
 577          */
 578         if (crtc && !vc4_hdmi_supports_scrambling(encoder, &crtc->mode))
 579                 return;
 580
 581         if (crtc && !vc4_hdmi_mode_needs_scrambling(&crtc->mode))
 582                 return;
 583
 584         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
 585                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
 586
 587         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
 588                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 589
 590         drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
 591         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
 592 }
 593
 594 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
 595 {
 596         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
 597                                                  struct vc4_hdmi,
 598                                                  scrambling_work);
 599
 600         if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
 601                 return;
 602
 603         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 604         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 605
 606         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 607                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 608 }
 609
 610 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 611                                                struct drm_atomic_state *state)
 612 {
 613         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 614
 615         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 616
 617         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
 618
 619         mdelay(1);
 620
 621         HDMI_WRITE(HDMI_VID_CTL,
 622                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 623         vc4_hdmi_disable_scrambling(encoder);
 624 }
 625
 626 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
 627                                                  struct drm_atomic_state *state)
 628 {
 629         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 630         int ret;
 631
 632         HDMI_WRITE(HDMI_VID_CTL,
 633                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 634
 635         if (vc4_hdmi->variant->phy_disable)
 636                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 637
 638         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 639         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 640
 641         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 642         if (ret < 0)
 643                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 644 }
 645
 646 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 647 {
 648 }
 649
 650 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 651 {
 652         u32 csc_ctl;
 653
 654         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 655                                 VC4_HD_CSC_CTL_ORDER);
 656
 657         if (enable) {
 658                 /* CEA VICs other than #1 requre limited range RGB
 659                  * output unless overridden by an AVI infoframe.
 660                  * Apply a colorspace conversion to squash 0-255 down
 661                  * to 16-235.  The matrix here is:
 662                  *
 663                  * [ 0      0      0.8594 16]
 664                  * [ 0      0.8594 0      16]
 665                  * [ 0.8594 0      0      16]
 666                  * [ 0      0      0       1]
 667                  */
 668                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 669                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 670                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 671                                          VC4_HD_CSC_CTL_MODE);
 672
 673                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 674                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 675                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 676                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 677                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 678                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 679         }
 680
 681         /* The RGB order applies even when CSC is disabled. */
 682         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 683 }
 684
 685 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 686 {
 687         u32 csc_ctl;
 688
 689         csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
 690
 691         if (enable) {
 692                 /* CEA VICs other than #1 requre limited range RGB
 693                  * output unless overridden by an AVI infoframe.
 694                  * Apply a colorspace conversion to squash 0-255 down
 695                  * to 16-235.  The matrix here is:
 696                  *
 697                  * [ 0.8594 0      0      16]
 698                  * [ 0      0.8594 0      16]
 699                  * [ 0      0      0.8594 16]
 700                  * [ 0      0      0       1]
 701                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 702                  */
 703                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
 704                 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
 705                 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
 706                 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
 707                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 708                 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
 709         } else {
 710                 /* Still use the matrix for full range, but make it unity.
 711                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 712                  */
 713                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
 714                 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
 715                 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
 716                 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
 717                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 718                 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
 719         }
 720
 721         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 722 }
 723
 724 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 725                                  struct drm_connector_state *state,
 726                                  struct drm_display_mode *mode)
 727 {
 728         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 729         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 730         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 731         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 732         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 733                                    VC4_HDMI_VERTA_VSP) |
 734                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 735                                    VC4_HDMI_VERTA_VFP) |
 736                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 737         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 738                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 739                                    VC4_HDMI_VERTB_VBP));
 740         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 741                           VC4_SET_FIELD(mode->crtc_vtotal -
 742                                         mode->crtc_vsync_end -
 743                                         interlaced,
 744                                         VC4_HDMI_VERTB_VBP));
 745
 746         HDMI_WRITE(HDMI_HORZA,
 747                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 748                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 749                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 750                                  VC4_HDMI_HORZA_HAP));
 751
 752         HDMI_WRITE(HDMI_HORZB,
 753                    VC4_SET_FIELD((mode->htotal -
 754                                   mode->hsync_end) * pixel_rep,
 755                                  VC4_HDMI_HORZB_HBP) |
 756                    VC4_SET_FIELD((mode->hsync_end -
 757                                   mode->hsync_start) * pixel_rep,
 758                                  VC4_HDMI_HORZB_HSP) |
 759                    VC4_SET_FIELD((mode->hsync_start -
 760                                   mode->hdisplay) * pixel_rep,
 761                                  VC4_HDMI_HORZB_HFP));
 762
 763         HDMI_WRITE(HDMI_VERTA0, verta);
 764         HDMI_WRITE(HDMI_VERTA1, verta);
 765
 766         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 767         HDMI_WRITE(HDMI_VERTB1, vertb);
 768 }
 769
 770 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 771                                  struct drm_connector_state *state,
 772                                  struct drm_display_mode *mode)
 773 {
 774         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 775         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 776         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 777         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 778         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 779                                    VC5_HDMI_VERTA_VSP) |
 780                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 781                                    VC5_HDMI_VERTA_VFP) |
 782                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
 783         u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 784                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 785                                    VC4_HDMI_VERTB_VBP));
 786         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 787                           VC4_SET_FIELD(mode->crtc_vtotal -
 788                                         mode->crtc_vsync_end -
 789                                         interlaced,
 790                                         VC4_HDMI_VERTB_VBP));
 791         unsigned char gcp;
 792         bool gcp_en;
 793         u32 reg;
 794
 795         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
 796         HDMI_WRITE(HDMI_HORZA,
 797                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
 798                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
 799                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 800                                  VC5_HDMI_HORZA_HAP) |
 801                    VC4_SET_FIELD((mode->hsync_start -
 802                                   mode->hdisplay) * pixel_rep,
 803                                  VC5_HDMI_HORZA_HFP));
 804
 805         HDMI_WRITE(HDMI_HORZB,
 806                    VC4_SET_FIELD((mode->htotal -
 807                                   mode->hsync_end) * pixel_rep,
 808                                  VC5_HDMI_HORZB_HBP) |
 809                    VC4_SET_FIELD((mode->hsync_end -
 810                                   mode->hsync_start) * pixel_rep,
 811                                  VC5_HDMI_HORZB_HSP));
 812
 813         HDMI_WRITE(HDMI_VERTA0, verta);
 814         HDMI_WRITE(HDMI_VERTA1, verta);
 815
 816         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 817         HDMI_WRITE(HDMI_VERTB1, vertb);
 818
 819         switch (state->max_bpc) {
 820         case 12:
 821                 gcp = 6;
 822                 gcp_en = true;
 823                 break;
 824         case 10:
 825                 gcp = 5;
 826                 gcp_en = true;
 827                 break;
 828         case 8:
 829         default:
 830                 gcp = 4;
 831                 gcp_en = false;
 832                 break;
 833         }
 834
 835         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
 836         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
 837                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
 838         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
 839                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
 840         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
 841
 842         reg = HDMI_READ(HDMI_GCP_WORD_1);
 843         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
 844         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
 845         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
 846
 847         reg = HDMI_READ(HDMI_GCP_CONFIG);
 848         reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
 849         reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
 850         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
 851
 852         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
 853 }
 854
 855 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
 856 {
 857         u32 drift;
 858         int ret;
 859
 860         drift = HDMI_READ(HDMI_FIFO_CTL);
 861         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 862
 863         HDMI_WRITE(HDMI_FIFO_CTL,
 864                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 865         HDMI_WRITE(HDMI_FIFO_CTL,
 866                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 867         usleep_range(1000, 1100);
 868         HDMI_WRITE(HDMI_FIFO_CTL,
 869                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 870         HDMI_WRITE(HDMI_FIFO_CTL,
 871                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 872
 873         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
 874                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
 875         WARN_ONCE(ret, "Timeout waiting for "
 876                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
 877 }
 878
 879 static struct drm_connector_state *
 880 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder,
 881                                      struct drm_atomic_state *state)
 882 {
 883         struct drm_connector_state *conn_state;
 884         struct drm_connector *connector;
 885         unsigned int i;
 886
 887         for_each_new_connector_in_state(state, connector, conn_state, i) {
 888                 if (conn_state->best_encoder == encoder)
 889                         return conn_state;
 890         }
 891
 892         return NULL;
 893 }
 894
 895 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
 896                                                 struct drm_atomic_state *state)
 897 {
 898         struct drm_connector_state *conn_state =
 899                 vc4_hdmi_encoder_get_connector_state(encoder, state);
 900         struct vc4_hdmi_connector_state *vc4_conn_state =
 901                 conn_state_to_vc4_hdmi_conn_state(conn_state);
 902         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 903         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 904         unsigned long pixel_rate = vc4_conn_state->pixel_rate;
 905         unsigned long bvb_rate, hsm_rate;
 906         int ret;
 907
 908         /*
 909          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
 910          * be faster than pixel clock, infinitesimally faster, tested in
 911          * simulation. Otherwise, exact value is unimportant for HDMI
 912          * operation." This conflicts with bcm2835's vc4 documentation, which
 913          * states HSM's clock has to be at least 108% of the pixel clock.
 914          *
 915          * Real life tests reveal that vc4's firmware statement holds up, and
 916          * users are able to use pixel clocks closer to HSM's, namely for
 917          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
 918          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
 919          * 162MHz.
 920          *
 921          * Additionally, the AXI clock needs to be at least 25% of
 922          * pixel clock, but HSM ends up being the limiting factor.
 923          */
 924         hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
 925         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
 926         if (ret) {
 927                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
 928                 return;
 929         }
 930
 931         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
 932         if (ret < 0) {
 933                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
 934                 return;
 935         }
 936
 937         ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
 938         if (ret) {
 939                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
 940                 goto err_put_runtime_pm;
 941         }
 942
 943         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
 944         if (ret) {
 945                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
 946                 goto err_put_runtime_pm;
 947         }
 948
 949
 950         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
 951
 952         if (pixel_rate > 297000000)
 953                 bvb_rate = 300000000;
 954         else if (pixel_rate > 148500000)
 955                 bvb_rate = 150000000;
 956         else
 957                 bvb_rate = 75000000;
 958
 959         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
 960         if (ret) {
 961                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
 962                 goto err_disable_pixel_clock;
 963         }
 964
 965         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
 966         if (ret) {
 967                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
 968                 goto err_disable_pixel_clock;
 969         }
 970
 971         if (vc4_hdmi->variant->phy_init)
 972                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
 973
 974         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 975                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
 976                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
 977                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
 978
 979         if (vc4_hdmi->variant->set_timings)
 980                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
 981
 982         return;
 983
 984 err_disable_pixel_clock:
 985         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 986 err_put_runtime_pm:
 987         pm_runtime_put(&vc4_hdmi->pdev->dev);
 988
 989         return;
 990 }
 991
 992 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
 993                                              struct drm_atomic_state *state)
 994 {
 995         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 996         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 997         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 998
 999         if (vc4_encoder->hdmi_monitor &&
1000             drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
1001                 if (vc4_hdmi->variant->csc_setup)
1002                         vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
1003
1004                 vc4_encoder->limited_rgb_range = true;
1005         } else {
1006                 if (vc4_hdmi->variant->csc_setup)
1007                         vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
1008
1009                 vc4_encoder->limited_rgb_range = false;
1010         }
1011
1012         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1013 }
1014
1015 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1016                                               struct drm_atomic_state *state)
1017 {
1018         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1019         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1020         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1021         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1022         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1023         int ret;
1024
1025         HDMI_WRITE(HDMI_VID_CTL,
1026                    VC4_HD_VID_CTL_ENABLE |
1027                    VC4_HD_VID_CTL_CLRRGB |
1028                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1029                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1030                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1031                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1032
1033         HDMI_WRITE(HDMI_VID_CTL,
1034                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1035
1036         if (vc4_encoder->hdmi_monitor) {
1037                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1038                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1039                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1040
1041                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1042                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1043                 WARN_ONCE(ret, "Timeout waiting for "
1044                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1045         } else {
1046                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1047                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1048                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1049                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1050                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1051                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1052
1053                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1054                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1055                 WARN_ONCE(ret, "Timeout waiting for "
1056                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1057         }
1058
1059         if (vc4_encoder->hdmi_monitor) {
1060                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1061                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1062                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1063                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1064                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
1065
1066                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1067                            VC4_HDMI_RAM_PACKET_ENABLE);
1068
1069                 vc4_hdmi_set_infoframes(encoder);
1070         }
1071
1072         vc4_hdmi_recenter_fifo(vc4_hdmi);
1073         vc4_hdmi_enable_scrambling(encoder);
1074 }
1075
1076 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
1077 {
1078 }
1079
1080 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
1081 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
1082
1083 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1084                                          struct drm_crtc_state *crtc_state,
1085                                          struct drm_connector_state *conn_state)
1086 {
1087         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1088         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1089         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1090         unsigned long long pixel_rate = mode->clock * 1000;
1091         unsigned long long tmds_rate;
1092
1093         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1094             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1095             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1096              (mode->hsync_end % 2) || (mode->htotal % 2)))
1097                 return -EINVAL;
1098
1099         /*
1100          * The 1440p@60 pixel rate is in the same range than the first
1101          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1102          * bandwidth). Slightly lower the frequency to bring it out of
1103          * the WiFi range.
1104          */
1105         tmds_rate = pixel_rate * 10;
1106         if (vc4_hdmi->disable_wifi_frequencies &&
1107             (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1108              tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1109                 mode->clock = 238560;
1110                 pixel_rate = mode->clock * 1000;
1111         }
1112
1113         if (conn_state->max_bpc == 12) {
1114                 pixel_rate = pixel_rate * 150;
1115                 do_div(pixel_rate, 100);
1116         } else if (conn_state->max_bpc == 10) {
1117                 pixel_rate = pixel_rate * 125;
1118                 do_div(pixel_rate, 100);
1119         }
1120
1121         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1122                 pixel_rate = pixel_rate * 2;
1123
1124         if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
1125                 return -EINVAL;
1126
1127         if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK))
1128                 return -EINVAL;
1129
1130         vc4_state->pixel_rate = pixel_rate;
1131
1132         return 0;
1133 }
1134
1135 static enum drm_mode_status
1136 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1137                             const struct drm_display_mode *mode)
1138 {
1139         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1140
1141         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1142             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1143             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1144              (mode->hsync_end % 2) || (mode->htotal % 2)))
1145                 return MODE_H_ILLEGAL;
1146
1147         if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
1148                 return MODE_CLOCK_HIGH;
1149
1150         if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode))
1151                 return MODE_CLOCK_HIGH;
1152
1153         return MODE_OK;
1154 }
1155
1156 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1157         .atomic_check = vc4_hdmi_encoder_atomic_check,
1158         .mode_valid = vc4_hdmi_encoder_mode_valid,
1159         .disable = vc4_hdmi_encoder_disable,
1160         .enable = vc4_hdmi_encoder_enable,
1161 };
1162
1163 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1164 {
1165         int i;
1166         u32 channel_map = 0;
1167
1168         for (i = 0; i < 8; i++) {
1169                 if (channel_mask & BIT(i))
1170                         channel_map |= i << (3 * i);
1171         }
1172         return channel_map;
1173 }
1174
1175 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1176 {
1177         int i;
1178         u32 channel_map = 0;
1179
1180         for (i = 0; i < 8; i++) {
1181                 if (channel_mask & BIT(i))
1182                         channel_map |= i << (4 * i);
1183         }
1184         return channel_map;
1185 }
1186
1187 /* HDMI audio codec callbacks */
1188 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1189                                          unsigned int samplerate)
1190 {
1191         u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1192         unsigned long n, m;
1193
1194         rational_best_approximation(hsm_clock, samplerate,
1195                                     VC4_HD_MAI_SMP_N_MASK >>
1196                                     VC4_HD_MAI_SMP_N_SHIFT,
1197                                     (VC4_HD_MAI_SMP_M_MASK >>
1198                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
1199                                     &n, &m);
1200
1201         HDMI_WRITE(HDMI_MAI_SMP,
1202                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1203                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1204 }
1205
1206 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1207 {
1208         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1209         struct drm_crtc *crtc = encoder->crtc;
1210         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1211         u32 n, cts;
1212         u64 tmp;
1213
1214         n = 128 * samplerate / 1000;
1215         tmp = (u64)(mode->clock * 1000) * n;
1216         do_div(tmp, 128 * samplerate);
1217         cts = tmp;
1218
1219         HDMI_WRITE(HDMI_CRP_CFG,
1220                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1221                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1222
1223         /*
1224          * We could get slightly more accurate clocks in some cases by
1225          * providing a CTS_1 value.  The two CTS values are alternated
1226          * between based on the period fields
1227          */
1228         HDMI_WRITE(HDMI_CTS_0, cts);
1229         HDMI_WRITE(HDMI_CTS_1, cts);
1230 }
1231
1232 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1233 {
1234         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1235
1236         return snd_soc_card_get_drvdata(card);
1237 }
1238
1239 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1240 {
1241         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1242         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1243
1244         /*
1245          * If the HDMI encoder hasn't probed, or the encoder is
1246          * currently in DVI mode, treat the codec dai as missing.
1247          */
1248         if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1249                                 VC4_HDMI_RAM_PACKET_ENABLE))
1250                 return -ENODEV;
1251
1252         vc4_hdmi->audio.streaming = true;
1253
1254         HDMI_WRITE(HDMI_MAI_CTL,
1255                    VC4_HD_MAI_CTL_RESET |
1256                    VC4_HD_MAI_CTL_FLUSH |
1257                    VC4_HD_MAI_CTL_DLATE |
1258                    VC4_HD_MAI_CTL_ERRORE |
1259                    VC4_HD_MAI_CTL_ERRORF);
1260
1261         if (vc4_hdmi->variant->phy_rng_enable)
1262                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1263
1264         return 0;
1265 }
1266
1267 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1268 {
1269         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1270         struct device *dev = &vc4_hdmi->pdev->dev;
1271         int ret;
1272
1273         vc4_hdmi->audio.streaming = false;
1274         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1275         if (ret)
1276                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1277
1278         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1279         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1280         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1281 }
1282
1283 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1284 {
1285         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1286
1287         HDMI_WRITE(HDMI_MAI_CTL,
1288                    VC4_HD_MAI_CTL_DLATE |
1289                    VC4_HD_MAI_CTL_ERRORE |
1290                    VC4_HD_MAI_CTL_ERRORF);
1291
1292         if (vc4_hdmi->variant->phy_rng_disable)
1293                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1294
1295         vc4_hdmi->audio.streaming = false;
1296         vc4_hdmi_audio_reset(vc4_hdmi);
1297 }
1298
1299 static int sample_rate_to_mai_fmt(int samplerate)
1300 {
1301         switch (samplerate) {
1302         case 8000:
1303                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1304         case 11025:
1305                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1306         case 12000:
1307                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1308         case 16000:
1309                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1310         case 22050:
1311                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1312         case 24000:
1313                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1314         case 32000:
1315                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1316         case 44100:
1317                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1318         case 48000:
1319                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1320         case 64000:
1321                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
1322         case 88200:
1323                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
1324         case 96000:
1325                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
1326         case 128000:
1327                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
1328         case 176400:
1329                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
1330         case 192000:
1331                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
1332         default:
1333                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
1334         }
1335 }
1336
1337 /* HDMI audio codec callbacks */
1338 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
1339                                   struct hdmi_codec_daifmt *daifmt,
1340                                   struct hdmi_codec_params *params)
1341 {
1342         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1343         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1344         unsigned int sample_rate = params->sample_rate;
1345         unsigned int channels = params->channels;
1346         u32 audio_packet_config, channel_mask;
1347         u32 channel_map;
1348         u32 mai_audio_format;
1349         u32 mai_sample_rate;
1350
1351         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1352                 sample_rate, params->sample_width, channels);
1353
1354         HDMI_WRITE(HDMI_MAI_CTL,
1355                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
1356                    VC4_HD_MAI_CTL_WHOLSMP |
1357                    VC4_HD_MAI_CTL_CHALIGN |
1358                    VC4_HD_MAI_CTL_ENABLE);
1359
1360         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
1361
1362         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
1363         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
1364             params->channels == 8)
1365                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
1366         else
1367                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
1368         HDMI_WRITE(HDMI_MAI_FMT,
1369                    VC4_SET_FIELD(mai_sample_rate,
1370                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
1371                    VC4_SET_FIELD(mai_audio_format,
1372                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
1373
1374         /* The B frame identifier should match the value used by alsa-lib (8) */
1375         audio_packet_config =
1376                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1377                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1378                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1379
1380         channel_mask = GENMASK(channels - 1, 0);
1381         audio_packet_config |= VC4_SET_FIELD(channel_mask,
1382                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1383
1384         /* Set the MAI threshold */
1385         HDMI_WRITE(HDMI_MAI_THR,
1386                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1387                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1388                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1389                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1390
1391         HDMI_WRITE(HDMI_MAI_CONFIG,
1392                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1393                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
1394                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1395
1396         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1397         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1398         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1399         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
1400
1401         memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
1402         vc4_hdmi_set_audio_infoframe(encoder);
1403
1404         return 0;
1405 }
1406
1407 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1408         .name = "vc4-hdmi-cpu-dai-component",
1409 };
1410
1411 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1412 {
1413         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1414
1415         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1416
1417         return 0;
1418 }
1419
1420 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1421         .name = "vc4-hdmi-cpu-dai",
1422         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1423         .playback = {
1424                 .stream_name = "Playback",
1425                 .channels_min = 1,
1426                 .channels_max = 8,
1427                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1428                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1429                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1430                          SNDRV_PCM_RATE_192000,
1431                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1432         },
1433 };
1434
1435 static const struct snd_dmaengine_pcm_config pcm_conf = {
1436         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1437         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1438 };
1439
1440 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
1441                                   uint8_t *buf, size_t len)
1442 {
1443         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1444         struct drm_connector *connector = &vc4_hdmi->connector;
1445
1446         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1447
1448         return 0;
1449 }
1450
1451 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
1452         .get_eld = vc4_hdmi_audio_get_eld,
1453         .prepare = vc4_hdmi_audio_prepare,
1454         .audio_shutdown = vc4_hdmi_audio_shutdown,
1455         .audio_startup = vc4_hdmi_audio_startup,
1456 };
1457
1458 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
1459         .ops = &vc4_hdmi_codec_ops,
1460         .max_i2s_channels = 8,
1461         .i2s = 1,
1462 };
1463
1464 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1465 {
1466         const struct vc4_hdmi_register *mai_data =
1467                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1468         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1469         struct snd_soc_card *card = &vc4_hdmi->audio.card;
1470         struct device *dev = &vc4_hdmi->pdev->dev;
1471         struct platform_device *codec_pdev;
1472         const __be32 *addr;
1473         int index;
1474         int ret;
1475
1476         if (!of_find_property(dev->of_node, "dmas", NULL)) {
1477                 dev_warn(dev,
1478                          "'dmas' DT property is missing, no HDMI audio\n");
1479                 return 0;
1480         }
1481
1482         if (mai_data->reg != VC4_HD) {
1483                 WARN_ONCE(true, "MAI isn't in the HD block\n");
1484                 return -EINVAL;
1485         }
1486
1487         /*
1488          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1489          * the bus address specified in the DT, because the physical address
1490          * (the one returned by platform_get_resource()) is not appropriate
1491          * for DMA transfers.
1492          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1493          */
1494         index = of_property_match_string(dev->of_node, "reg-names", "hd");
1495         /* Before BCM2711, we don't have a named register range */
1496         if (index < 0)
1497                 index = 1;
1498
1499         addr = of_get_address(dev->of_node, index, NULL, NULL);
1500
1501         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1502         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1503         vc4_hdmi->audio.dma_data.maxburst = 2;
1504
1505         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1506         if (ret) {
1507                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1508                 return ret;
1509         }
1510
1511         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1512                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1513         if (ret) {
1514                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1515                 return ret;
1516         }
1517
1518         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1519                                                    PLATFORM_DEVID_AUTO,
1520                                                    &vc4_hdmi_codec_pdata,
1521                                                    sizeof(vc4_hdmi_codec_pdata));
1522         if (IS_ERR(codec_pdev)) {
1523                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
1524                 return PTR_ERR(codec_pdev);
1525         }
1526         vc4_hdmi->audio.codec_pdev = codec_pdev;
1527
1528         dai_link->cpus          = &vc4_hdmi->audio.cpu;
1529         dai_link->codecs        = &vc4_hdmi->audio.codec;
1530         dai_link->platforms     = &vc4_hdmi->audio.platform;
1531
1532         dai_link->num_cpus      = 1;
1533         dai_link->num_codecs    = 1;
1534         dai_link->num_platforms = 1;
1535
1536         dai_link->name = "MAI";
1537         dai_link->stream_name = "MAI PCM";
1538         dai_link->codecs->dai_name = "i2s-hifi";
1539         dai_link->cpus->dai_name = dev_name(dev);
1540         dai_link->codecs->name = dev_name(&codec_pdev->dev);
1541         dai_link->platforms->name = dev_name(dev);
1542
1543         card->dai_link = dai_link;
1544         card->num_links = 1;
1545         card->name = vc4_hdmi->variant->card_name;
1546         card->driver_name = "vc4-hdmi";
1547         card->dev = dev;
1548         card->owner = THIS_MODULE;
1549
1550         /*
1551          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1552          * stores a pointer to the snd card object in dev->driver_data. This
1553          * means we cannot use it for something else. The hdmi back-pointer is
1554          * now stored in card->drvdata and should be retrieved with
1555          * snd_soc_card_get_drvdata() if needed.
1556          */
1557         snd_soc_card_set_drvdata(card, vc4_hdmi);
1558         ret = devm_snd_soc_register_card(dev, card);
1559         if (ret)
1560                 dev_err_probe(dev, ret, "Could not register sound card\n");
1561
1562         return ret;
1563
1564 }
1565
1566 static void vc4_hdmi_audio_exit(struct vc4_hdmi *vc4_hdmi)
1567 {
1568         platform_device_unregister(vc4_hdmi->audio.codec_pdev);
1569         vc4_hdmi->audio.codec_pdev = NULL;
1570 }
1571
1572 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
1573 {
1574         struct vc4_hdmi *vc4_hdmi = priv;
1575         struct drm_device *dev = vc4_hdmi->connector.dev;
1576
1577         if (dev && dev->registered)
1578                 drm_kms_helper_hotplug_event(dev);
1579
1580         return IRQ_HANDLED;
1581 }
1582
1583 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
1584 {
1585         struct drm_connector *connector = &vc4_hdmi->connector;
1586         struct platform_device *pdev = vc4_hdmi->pdev;
1587         int ret;
1588
1589         if (vc4_hdmi->variant->external_irq_controller) {
1590                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
1591                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
1592
1593                 ret = request_threaded_irq(hpd_con,
1594                                            NULL,
1595                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1596                                            "vc4 hdmi hpd connected", vc4_hdmi);
1597                 if (ret)
1598                         return ret;
1599
1600                 ret = request_threaded_irq(hpd_rm,
1601                                            NULL,
1602                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1603                                            "vc4 hdmi hpd disconnected", vc4_hdmi);
1604                 if (ret) {
1605                         free_irq(hpd_con, vc4_hdmi);
1606                         return ret;
1607                 }
1608
1609                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1610         }
1611
1612         return 0;
1613 }
1614
1615 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi)
1616 {
1617         struct platform_device *pdev = vc4_hdmi->pdev;
1618
1619         if (vc4_hdmi->variant->external_irq_controller) {
1620                 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi);
1621                 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi);
1622         }
1623 }
1624
1625 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1626 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1627 {
1628         struct vc4_hdmi *vc4_hdmi = priv;
1629
1630         if (vc4_hdmi->cec_rx_msg.len)
1631                 cec_received_msg(vc4_hdmi->cec_adap,
1632                                  &vc4_hdmi->cec_rx_msg);
1633
1634         return IRQ_HANDLED;
1635 }
1636
1637 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1638 {
1639         struct vc4_hdmi *vc4_hdmi = priv;
1640
1641         if (vc4_hdmi->cec_tx_ok) {
1642                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1643                                   0, 0, 0, 0);
1644         } else {
1645                 /*
1646                  * This CEC implementation makes 1 retry, so if we
1647                  * get a NACK, then that means it made 2 attempts.
1648                  */
1649                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1650                                   0, 2, 0, 0);
1651         }
1652         return IRQ_HANDLED;
1653 }
1654
1655 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1656 {
1657         struct vc4_hdmi *vc4_hdmi = priv;
1658         irqreturn_t ret;
1659
1660         if (vc4_hdmi->cec_irq_was_rx)
1661                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1662         else
1663                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1664
1665         return ret;
1666 }
1667
1668 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1669 {
1670         struct drm_device *dev = vc4_hdmi->connector.dev;
1671         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1672         unsigned int i;
1673
1674         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1675                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1676
1677         if (msg->len > 16) {
1678                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1679                 return;
1680         }
1681
1682         for (i = 0; i < msg->len; i += 4) {
1683                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1684
1685                 msg->msg[i] = val & 0xff;
1686                 msg->msg[i + 1] = (val >> 8) & 0xff;
1687                 msg->msg[i + 2] = (val >> 16) & 0xff;
1688                 msg->msg[i + 3] = (val >> 24) & 0xff;
1689         }
1690 }
1691
1692 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1693 {
1694         struct vc4_hdmi *vc4_hdmi = priv;
1695         u32 cntrl1;
1696
1697         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1698         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1699         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1700         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1701
1702         return IRQ_WAKE_THREAD;
1703 }
1704
1705 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1706 {
1707         struct vc4_hdmi *vc4_hdmi = priv;
1708         u32 cntrl1;
1709
1710         vc4_hdmi->cec_rx_msg.len = 0;
1711         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1712         vc4_cec_read_msg(vc4_hdmi, cntrl1);
1713         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1714         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1715         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1716
1717         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1718
1719         return IRQ_WAKE_THREAD;
1720 }
1721
1722 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1723 {
1724         struct vc4_hdmi *vc4_hdmi = priv;
1725         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1726         irqreturn_t ret;
1727         u32 cntrl5;
1728
1729         if (!(stat & VC4_HDMI_CPU_CEC))
1730                 return IRQ_NONE;
1731
1732         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1733         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1734         if (vc4_hdmi->cec_irq_was_rx)
1735                 ret = vc4_cec_irq_handler_rx_bare(irq, priv);
1736         else
1737                 ret = vc4_cec_irq_handler_tx_bare(irq, priv);
1738
1739         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1740         return ret;
1741 }
1742
1743 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1744 {
1745         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1746         /* clock period in microseconds */
1747         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1748         u32 val = HDMI_READ(HDMI_CEC_CNTRL_5);
1749
1750         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1751                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1752                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1753         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1754                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1755
1756         if (enable) {
1757                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1758                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1759                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1760                 HDMI_WRITE(HDMI_CEC_CNTRL_2,
1761                            ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1762                            ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1763                            ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1764                            ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1765                            ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1766                 HDMI_WRITE(HDMI_CEC_CNTRL_3,
1767                            ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1768                            ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1769                            ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1770                            ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1771                 HDMI_WRITE(HDMI_CEC_CNTRL_4,
1772                            ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1773                            ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1774                            ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1775                            ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1776
1777                 if (!vc4_hdmi->variant->external_irq_controller)
1778                         HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1779         } else {
1780                 if (!vc4_hdmi->variant->external_irq_controller)
1781                         HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1782                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1783                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1784         }
1785         return 0;
1786 }
1787
1788 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1789 {
1790         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1791
1792         HDMI_WRITE(HDMI_CEC_CNTRL_1,
1793                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1794                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1795         return 0;
1796 }
1797
1798 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1799                                       u32 signal_free_time, struct cec_msg *msg)
1800 {
1801         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1802         struct drm_device *dev = vc4_hdmi->connector.dev;
1803         u32 val;
1804         unsigned int i;
1805
1806         if (msg->len > 16) {
1807                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
1808                 return -ENOMEM;
1809         }
1810
1811         for (i = 0; i < msg->len; i += 4)
1812                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
1813                            (msg->msg[i]) |
1814                            (msg->msg[i + 1] << 8) |
1815                            (msg->msg[i + 2] << 16) |
1816                            (msg->msg[i + 3] << 24));
1817
1818         val = HDMI_READ(HDMI_CEC_CNTRL_1);
1819         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1820         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1821         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1822         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1823         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1824
1825         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1826         return 0;
1827 }
1828
1829 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1830         .adap_enable = vc4_hdmi_cec_adap_enable,
1831         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1832         .adap_transmit = vc4_hdmi_cec_adap_transmit,
1833 };
1834
1835 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1836 {
1837         struct cec_connector_info conn_info;
1838         struct platform_device *pdev = vc4_hdmi->pdev;
1839         struct device *dev = &pdev->dev;
1840         u32 value;
1841         int ret;
1842
1843         if (!of_find_property(dev->of_node, "interrupts", NULL)) {
1844                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
1845                 return 0;
1846         }
1847
1848         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1849                                                   vc4_hdmi, "vc4",
1850                                                   CEC_CAP_DEFAULTS |
1851                                                   CEC_CAP_CONNECTOR_INFO, 1);
1852         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
1853         if (ret < 0)
1854                 return ret;
1855
1856         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
1857         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
1858
1859         value = HDMI_READ(HDMI_CEC_CNTRL_1);
1860         /* Set the logical address to Unregistered */
1861         value |= VC4_HDMI_CEC_ADDR_MASK;
1862         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
1863
1864         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1865
1866         if (vc4_hdmi->variant->external_irq_controller) {
1867                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"),
1868                                            vc4_cec_irq_handler_rx_bare,
1869                                            vc4_cec_irq_handler_rx_thread, 0,
1870                                            "vc4 hdmi cec rx", vc4_hdmi);
1871                 if (ret)
1872                         goto err_delete_cec_adap;
1873
1874                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"),
1875                                            vc4_cec_irq_handler_tx_bare,
1876                                            vc4_cec_irq_handler_tx_thread, 0,
1877                                            "vc4 hdmi cec tx", vc4_hdmi);
1878                 if (ret)
1879                         goto err_remove_cec_rx_handler;
1880         } else {
1881                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
1882
1883                 ret = request_threaded_irq(platform_get_irq(pdev, 0),
1884                                            vc4_cec_irq_handler,
1885                                            vc4_cec_irq_handler_thread, 0,
1886                                            "vc4 hdmi cec", vc4_hdmi);
1887                 if (ret)
1888                         goto err_delete_cec_adap;
1889         }
1890
1891         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
1892         if (ret < 0)
1893                 goto err_remove_handlers;
1894
1895         return 0;
1896
1897 err_remove_handlers:
1898         if (vc4_hdmi->variant->external_irq_controller)
1899                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
1900         else
1901                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
1902
1903 err_remove_cec_rx_handler:
1904         if (vc4_hdmi->variant->external_irq_controller)
1905                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
1906
1907 err_delete_cec_adap:
1908         cec_delete_adapter(vc4_hdmi->cec_adap);
1909
1910         return ret;
1911 }
1912
1913 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
1914 {
1915         struct platform_device *pdev = vc4_hdmi->pdev;
1916
1917         if (vc4_hdmi->variant->external_irq_controller) {
1918                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
1919                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
1920         } else {
1921                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
1922         }
1923
1924         cec_unregister_adapter(vc4_hdmi->cec_adap);
1925 }
1926 #else
1927 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1928 {
1929         return 0;
1930 }
1931
1932 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
1933
1934 #endif
1935
1936 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
1937                                  struct debugfs_regset32 *regset,
1938                                  enum vc4_hdmi_regs reg)
1939 {
1940         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1941         struct debugfs_reg32 *regs, *new_regs;
1942         unsigned int count = 0;
1943         unsigned int i;
1944
1945         regs = kcalloc(variant->num_registers, sizeof(*regs),
1946                        GFP_KERNEL);
1947         if (!regs)
1948                 return -ENOMEM;
1949
1950         for (i = 0; i < variant->num_registers; i++) {
1951                 const struct vc4_hdmi_register *field = &variant->registers[i];
1952
1953                 if (field->reg != reg)
1954                         continue;
1955
1956                 regs[count].name = field->name;
1957                 regs[count].offset = field->offset;
1958                 count++;
1959         }
1960
1961         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
1962         if (!new_regs)
1963                 return -ENOMEM;
1964
1965         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
1966         regset->regs = new_regs;
1967         regset->nregs = count;
1968
1969         return 0;
1970 }
1971
1972 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1973 {
1974         struct platform_device *pdev = vc4_hdmi->pdev;
1975         struct device *dev = &pdev->dev;
1976         int ret;
1977
1978         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1979         if (IS_ERR(vc4_hdmi->hdmicore_regs))
1980                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1981
1982         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1983         if (IS_ERR(vc4_hdmi->hd_regs))
1984                 return PTR_ERR(vc4_hdmi->hd_regs);
1985
1986         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
1987         if (ret)
1988                 return ret;
1989
1990         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
1991         if (ret)
1992                 return ret;
1993
1994         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1995         if (IS_ERR(vc4_hdmi->pixel_clock)) {
1996                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
1997                 if (ret != -EPROBE_DEFER)
1998                         DRM_ERROR("Failed to get pixel clock\n");
1999                 return ret;
2000         }
2001
2002         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2003         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2004                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2005                 return PTR_ERR(vc4_hdmi->hsm_clock);
2006         }
2007         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2008         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2009
2010         return 0;
2011 }
2012
2013 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2014 {
2015         struct platform_device *pdev = vc4_hdmi->pdev;
2016         struct device *dev = &pdev->dev;
2017         struct resource *res;
2018
2019         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2020         if (!res)
2021                 return -ENODEV;
2022
2023         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2024                                                resource_size(res));
2025         if (!vc4_hdmi->hdmicore_regs)
2026                 return -ENOMEM;
2027
2028         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2029         if (!res)
2030                 return -ENODEV;
2031
2032         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2033         if (!vc4_hdmi->hd_regs)
2034                 return -ENOMEM;
2035
2036         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2037         if (!res)
2038                 return -ENODEV;
2039
2040         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2041         if (!vc4_hdmi->cec_regs)
2042                 return -ENOMEM;
2043
2044         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2045         if (!res)
2046                 return -ENODEV;
2047
2048         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2049         if (!vc4_hdmi->csc_regs)
2050                 return -ENOMEM;
2051
2052         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2053         if (!res)
2054                 return -ENODEV;
2055
2056         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2057         if (!vc4_hdmi->dvp_regs)
2058                 return -ENOMEM;
2059
2060         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2061         if (!res)
2062                 return -ENODEV;
2063
2064         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2065         if (!vc4_hdmi->phy_regs)
2066                 return -ENOMEM;
2067
2068         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2069         if (!res)
2070                 return -ENODEV;
2071
2072         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2073         if (!vc4_hdmi->ram_regs)
2074                 return -ENOMEM;
2075
2076         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2077         if (!res)
2078                 return -ENODEV;
2079
2080         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2081         if (!vc4_hdmi->rm_regs)
2082                 return -ENOMEM;
2083
2084         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2085         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2086                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2087                 return PTR_ERR(vc4_hdmi->hsm_clock);
2088         }
2089
2090         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2091         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2092                 DRM_ERROR("Failed to get pixel bvb clock\n");
2093                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2094         }
2095
2096         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2097         if (IS_ERR(vc4_hdmi->audio_clock)) {
2098                 DRM_ERROR("Failed to get audio clock\n");
2099                 return PTR_ERR(vc4_hdmi->audio_clock);
2100         }
2101
2102         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2103         if (IS_ERR(vc4_hdmi->cec_clock)) {
2104                 DRM_ERROR("Failed to get CEC clock\n");
2105                 return PTR_ERR(vc4_hdmi->cec_clock);
2106         }
2107
2108         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2109         if (IS_ERR(vc4_hdmi->reset)) {
2110                 DRM_ERROR("Failed to get HDMI reset line\n");
2111                 return PTR_ERR(vc4_hdmi->reset);
2112         }
2113
2114         return 0;
2115 }
2116
2117 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev)
2118 {
2119         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2120
2121         clk_disable_unprepare(vc4_hdmi->hsm_clock);
2122
2123         return 0;
2124 }
2125
2126 static int vc4_hdmi_runtime_resume(struct device *dev)
2127 {
2128         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2129         int ret;
2130
2131         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
2132         if (ret)
2133                 return ret;
2134
2135         return 0;
2136 }
2137
2138 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2139 {
2140         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2141         struct platform_device *pdev = to_platform_device(dev);
2142         struct drm_device *drm = dev_get_drvdata(master);
2143         struct vc4_hdmi *vc4_hdmi;
2144         struct drm_encoder *encoder;
2145         struct device_node *ddc_node;
2146         int ret;
2147
2148         vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2149         if (!vc4_hdmi)
2150                 return -ENOMEM;
2151         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2152
2153         dev_set_drvdata(dev, vc4_hdmi);
2154         encoder = &vc4_hdmi->encoder.base.base;
2155         vc4_hdmi->encoder.base.type = variant->encoder_type;
2156         vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2157         vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2158         vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2159         vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2160         vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2161         vc4_hdmi->pdev = pdev;
2162         vc4_hdmi->variant = variant;
2163
2164         ret = variant->init_resources(vc4_hdmi);
2165         if (ret)
2166                 return ret;
2167
2168         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2169         if (!ddc_node) {
2170                 DRM_ERROR("Failed to find ddc node in device tree\n");
2171                 return -ENODEV;
2172         }
2173
2174         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2175         of_node_put(ddc_node);
2176         if (!vc4_hdmi->ddc) {
2177                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2178                 return -EPROBE_DEFER;
2179         }
2180
2181         /* Only use the GPIO HPD pin if present in the DT, otherwise
2182          * we'll use the HDMI core's register.
2183          */
2184         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2185         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
2186                 ret = PTR_ERR(vc4_hdmi->hpd_gpio);
2187                 goto err_put_ddc;
2188         }
2189
2190         vc4_hdmi->disable_wifi_frequencies =
2191                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2192
2193         if (variant->max_pixel_clock == 600000000) {
2194                 struct vc4_dev *vc4 = to_vc4_dev(drm);
2195                 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
2196
2197                 if (max_rate < 550000000)
2198                         vc4_hdmi->disable_4kp60 = true;
2199         }
2200
2201         /*
2202          * If we boot without any cable connected to the HDMI connector,
2203          * the firmware will skip the HSM initialization and leave it
2204          * with a rate of 0, resulting in a bus lockup when we're
2205          * accessing the registers even if it's enabled.
2206          *
2207          * Let's put a sensible default at runtime_resume so that we
2208          * don't end up in this situation.
2209          */
2210         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
2211         if (ret)
2212                 goto err_put_ddc;
2213
2214         /*
2215          * We need to have the device powered up at this point to call
2216          * our reset hook and for the CEC init.
2217          */
2218         ret = vc4_hdmi_runtime_resume(dev);
2219         if (ret)
2220                 goto err_put_ddc;
2221
2222         pm_runtime_get_noresume(dev);
2223         pm_runtime_set_active(dev);
2224         pm_runtime_enable(dev);
2225
2226         if (vc4_hdmi->variant->reset)
2227                 vc4_hdmi->variant->reset(vc4_hdmi);
2228
2229         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
2230              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
2231             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
2232                 clk_prepare_enable(vc4_hdmi->pixel_clock);
2233                 clk_prepare_enable(vc4_hdmi->hsm_clock);
2234                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
2235         }
2236
2237         drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2238         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2239
2240         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2241         if (ret)
2242                 goto err_destroy_encoder;
2243
2244         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
2245         if (ret)
2246                 goto err_destroy_conn;
2247
2248         ret = vc4_hdmi_cec_init(vc4_hdmi);
2249         if (ret)
2250                 goto err_free_hotplug;
2251
2252         ret = vc4_hdmi_audio_init(vc4_hdmi);
2253         if (ret)
2254                 goto err_free_cec;
2255
2256         vc4_debugfs_add_file(drm, variant->debugfs_name,
2257                              vc4_hdmi_debugfs_regs,
2258                              vc4_hdmi);
2259
2260         pm_runtime_put_sync(dev);
2261
2262         return 0;
2263
2264 err_free_cec:
2265         vc4_hdmi_cec_exit(vc4_hdmi);
2266 err_free_hotplug:
2267         vc4_hdmi_hotplug_exit(vc4_hdmi);
2268 err_destroy_conn:
2269         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2270 err_destroy_encoder:
2271         drm_encoder_cleanup(encoder);
2272         pm_runtime_put_sync(dev);
2273         pm_runtime_disable(dev);
2274 err_put_ddc:
2275         put_device(&vc4_hdmi->ddc->dev);
2276
2277         return ret;
2278 }
2279
2280 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2281                             void *data)
2282 {
2283         struct vc4_hdmi *vc4_hdmi;
2284
2285         /*
2286          * ASoC makes it a bit hard to retrieve a pointer to the
2287          * vc4_hdmi structure. Registering the card will overwrite our
2288          * device drvdata with a pointer to the snd_soc_card structure,
2289          * which can then be used to retrieve whatever drvdata we want
2290          * to associate.
2291          *
2292          * However, that doesn't fly in the case where we wouldn't
2293          * register an ASoC card (because of an old DT that is missing
2294          * the dmas properties for example), then the card isn't
2295          * registered and the device drvdata wouldn't be set.
2296          *
2297          * We can deal with both cases by making sure a snd_soc_card
2298          * pointer and a vc4_hdmi structure are pointing to the same
2299          * memory address, so we can treat them indistinctly without any
2300          * issue.
2301          */
2302         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2303         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2304         vc4_hdmi = dev_get_drvdata(dev);
2305
2306         kfree(vc4_hdmi->hdmi_regset.regs);
2307         kfree(vc4_hdmi->hd_regset.regs);
2308
2309         vc4_hdmi_audio_exit(vc4_hdmi);
2310         vc4_hdmi_cec_exit(vc4_hdmi);
2311         vc4_hdmi_hotplug_exit(vc4_hdmi);
2312         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2313         drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2314
2315         pm_runtime_disable(dev);
2316
2317         put_device(&vc4_hdmi->ddc->dev);
2318 }
2319
2320 static const struct component_ops vc4_hdmi_ops = {
2321         .bind   = vc4_hdmi_bind,
2322         .unbind = vc4_hdmi_unbind,
2323 };
2324
2325 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2326 {
2327         return component_add(&pdev->dev, &vc4_hdmi_ops);
2328 }
2329
2330 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2331 {
2332         component_del(&pdev->dev, &vc4_hdmi_ops);
2333         return 0;
2334 }
2335
2336 static const struct vc4_hdmi_variant bcm2835_variant = {
2337         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2338         .debugfs_name           = "hdmi_regs",
2339         .card_name              = "vc4-hdmi",
2340         .max_pixel_clock        = 162000000,
2341         .registers              = vc4_hdmi_fields,
2342         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
2343
2344         .init_resources         = vc4_hdmi_init_resources,
2345         .csc_setup              = vc4_hdmi_csc_setup,
2346         .reset                  = vc4_hdmi_reset,
2347         .set_timings            = vc4_hdmi_set_timings,
2348         .phy_init               = vc4_hdmi_phy_init,
2349         .phy_disable            = vc4_hdmi_phy_disable,
2350         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
2351         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
2352         .channel_map            = vc4_hdmi_channel_map,
2353         .supports_hdr           = false,
2354 };
2355
2356 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2357         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2358         .debugfs_name           = "hdmi0_regs",
2359         .card_name              = "vc4-hdmi-0",
2360         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2361         .registers              = vc5_hdmi_hdmi0_fields,
2362         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2363         .phy_lane_mapping       = {
2364                 PHY_LANE_0,
2365                 PHY_LANE_1,
2366                 PHY_LANE_2,
2367                 PHY_LANE_CK,
2368         },
2369         .unsupported_odd_h_timings      = true,
2370         .external_irq_controller        = true,
2371
2372         .init_resources         = vc5_hdmi_init_resources,
2373         .csc_setup              = vc5_hdmi_csc_setup,
2374         .reset                  = vc5_hdmi_reset,
2375         .set_timings            = vc5_hdmi_set_timings,
2376         .phy_init               = vc5_hdmi_phy_init,
2377         .phy_disable            = vc5_hdmi_phy_disable,
2378         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2379         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2380         .channel_map            = vc5_hdmi_channel_map,
2381         .supports_hdr           = true,
2382 };
2383
2384 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2385         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
2386         .debugfs_name           = "hdmi1_regs",
2387         .card_name              = "vc4-hdmi-1",
2388         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2389         .registers              = vc5_hdmi_hdmi1_fields,
2390         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2391         .phy_lane_mapping       = {
2392                 PHY_LANE_1,
2393                 PHY_LANE_0,
2394                 PHY_LANE_CK,
2395                 PHY_LANE_2,
2396         },
2397         .unsupported_odd_h_timings      = true,
2398         .external_irq_controller        = true,
2399
2400         .init_resources         = vc5_hdmi_init_resources,
2401         .csc_setup              = vc5_hdmi_csc_setup,
2402         .reset                  = vc5_hdmi_reset,
2403         .set_timings            = vc5_hdmi_set_timings,
2404         .phy_init               = vc5_hdmi_phy_init,
2405         .phy_disable            = vc5_hdmi_phy_disable,
2406         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2407         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2408         .channel_map            = vc5_hdmi_channel_map,
2409         .supports_hdr           = true,
2410 };
2411
2412 static const struct of_device_id vc4_hdmi_dt_match[] = {
2413         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2414         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2415         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2416         {}
2417 };
2418
2419 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
2420         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
2421                            vc4_hdmi_runtime_resume,
2422                            NULL)
2423 };
2424
2425 struct platform_driver vc4_hdmi_driver = {
2426         .probe = vc4_hdmi_dev_probe,
2427         .remove = vc4_hdmi_dev_remove,
2428         .driver = {
2429                 .name = "vc4_hdmi",
2430                 .of_match_table = vc4_hdmi_dt_match,
2431                 .pm = &vc4_hdmi_pm_ops,
2432         },
2433 };