drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <drm/drm_simple_kms_helper.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include <linux/clk.h>
  40 #include <linux/component.h>
  41 #include <linux/gpio/consumer.h>
  42 #include <linux/i2c.h>
  43 #include <linux/of_address.h>
  44 #include <linux/of_gpio.h>
  45 #include <linux/of_platform.h>
  46 #include <linux/pm_runtime.h>
  47 #include <linux/rational.h>
  48 #include <linux/reset.h>
  49 #include <sound/dmaengine_pcm.h>
  50 #include <sound/hdmi-codec.h>
  51 #include <sound/pcm_drm_eld.h>
  52 #include <sound/pcm_params.h>
  53 #include <sound/soc.h>
  54 #include "media/cec.h"
  55 #include "vc4_drv.h"
  56 #include "vc4_hdmi.h"
  57 #include "vc4_hdmi_regs.h"
  58 #include "vc4_regs.h"
  59
  60 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  61 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  62 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  63 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  64 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  65 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  66
  67 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  68 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  69 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  70 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  71
  72 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  73 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  74 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  75 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  76 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  77 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  78
  79 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  80 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  81
  82 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  83 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  84
  85 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  86
  87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  88 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  89
  90 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  91 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  92
  93 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  94
  95 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
  96 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
  97
  98 # define VC4_HD_M_SW_RST                        BIT(2)
  99 # define VC4_HD_M_ENABLE                        BIT(0)
 100
 101 #define HSM_MIN_CLOCK_FREQ      120000000
 102 #define CEC_CLOCK_FREQ 40000
 103
 104 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 105
 106 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode)
 107 {
 108         return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK;
 109 }
 110
 111 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 112 {
 113         struct drm_info_node *node = (struct drm_info_node *)m->private;
 114         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
 115         struct drm_printer p = drm_seq_file_printer(m);
 116
 117         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 118         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 119
 120         return 0;
 121 }
 122
 123 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 124 {
 125         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 126         udelay(1);
 127         HDMI_WRITE(HDMI_M_CTL, 0);
 128
 129         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 130
 131         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 132                    VC4_HDMI_SW_RESET_HDMI |
 133                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 134
 135         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 136 }
 137
 138 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 139 {
 140         reset_control_reset(vc4_hdmi->reset);
 141
 142         HDMI_WRITE(HDMI_DVP_CTL, 0);
 143
 144         HDMI_WRITE(HDMI_CLOCK_STOP,
 145                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 146 }
 147
 148 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 149 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 150 {
 151         u16 clk_cnt;
 152         u32 value;
 153
 154         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 155         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 156
 157         /*
 158          * Set the clock divider: the hsm_clock rate and this divider
 159          * setting will give a 40 kHz CEC clock.
 160          */
 161         clk_cnt = clk_get_rate(vc4_hdmi->cec_clock) / CEC_CLOCK_FREQ;
 162         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 163         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 164 }
 165 #else
 166 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 167 #endif
 168
 169 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder);
 170
 171 static enum drm_connector_status
 172 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 173 {
 174         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 175         bool connected = false;
 176
 177         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 178
 179         if (vc4_hdmi->hpd_gpio) {
 180                 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
 181                         connected = true;
 182         } else if (drm_probe_ddc(vc4_hdmi->ddc)) {
 183                 connected = true;
 184         } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) {
 185                 connected = true;
 186         }
 187
 188         if (connected) {
 189                 if (connector->status != connector_status_connected) {
 190                         struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
 191
 192                         if (edid) {
 193                                 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 194                                 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
 195                                 kfree(edid);
 196                         }
 197                 }
 198
 199                 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base);
 200                 pm_runtime_put(&vc4_hdmi->pdev->dev);
 201                 return connector_status_connected;
 202         }
 203
 204         cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 205         pm_runtime_put(&vc4_hdmi->pdev->dev);
 206         return connector_status_disconnected;
 207 }
 208
 209 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 210 {
 211         drm_connector_unregister(connector);
 212         drm_connector_cleanup(connector);
 213 }
 214
 215 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 216 {
 217         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 218         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 219         int ret = 0;
 220         struct edid *edid;
 221
 222         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 223         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 224         if (!edid)
 225                 return -ENODEV;
 226
 227         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 228
 229         drm_connector_update_edid_property(connector, edid);
 230         ret = drm_add_edid_modes(connector, edid);
 231         kfree(edid);
 232
 233         if (vc4_hdmi->disable_4kp60) {
 234                 struct drm_device *drm = connector->dev;
 235                 struct drm_display_mode *mode;
 236
 237                 list_for_each_entry(mode, &connector->probed_modes, head) {
 238                         if (vc4_hdmi_mode_needs_scrambling(mode)) {
 239                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 240                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 241                         }
 242                 }
 243         }
 244
 245         return ret;
 246 }
 247
 248 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 249                                            struct drm_atomic_state *state)
 250 {
 251         struct drm_connector_state *old_state =
 252                 drm_atomic_get_old_connector_state(state, connector);
 253         struct drm_connector_state *new_state =
 254                 drm_atomic_get_new_connector_state(state, connector);
 255         struct drm_crtc *crtc = new_state->crtc;
 256
 257         if (!crtc)
 258                 return 0;
 259
 260         if (old_state->colorspace != new_state->colorspace ||
 261             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 262                 struct drm_crtc_state *crtc_state;
 263
 264                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 265                 if (IS_ERR(crtc_state))
 266                         return PTR_ERR(crtc_state);
 267
 268                 crtc_state->mode_changed = true;
 269         }
 270
 271         return 0;
 272 }
 273
 274 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 275 {
 276         struct vc4_hdmi_connector_state *old_state =
 277                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 278         struct vc4_hdmi_connector_state *new_state =
 279                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 280
 281         if (connector->state)
 282                 __drm_atomic_helper_connector_destroy_state(connector->state);
 283
 284         kfree(old_state);
 285         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 286
 287         if (!new_state)
 288                 return;
 289
 290         new_state->base.max_bpc = 8;
 291         new_state->base.max_requested_bpc = 8;
 292         drm_atomic_helper_connector_tv_reset(connector);
 293 }
 294
 295 static struct drm_connector_state *
 296 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 297 {
 298         struct drm_connector_state *conn_state = connector->state;
 299         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 300         struct vc4_hdmi_connector_state *new_state;
 301
 302         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 303         if (!new_state)
 304                 return NULL;
 305
 306         new_state->pixel_rate = vc4_state->pixel_rate;
 307         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 308
 309         return &new_state->base;
 310 }
 311
 312 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 313         .detect = vc4_hdmi_connector_detect,
 314         .fill_modes = drm_helper_probe_single_connector_modes,
 315         .destroy = vc4_hdmi_connector_destroy,
 316         .reset = vc4_hdmi_connector_reset,
 317         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 318         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 319 };
 320
 321 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 322         .get_modes = vc4_hdmi_connector_get_modes,
 323         .atomic_check = vc4_hdmi_connector_atomic_check,
 324 };
 325
 326 static int vc4_hdmi_connector_init(struct drm_device *dev,
 327                                    struct vc4_hdmi *vc4_hdmi)
 328 {
 329         struct drm_connector *connector = &vc4_hdmi->connector;
 330         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 331         int ret;
 332
 333         drm_connector_init_with_ddc(dev, connector,
 334                                     &vc4_hdmi_connector_funcs,
 335                                     DRM_MODE_CONNECTOR_HDMIA,
 336                                     vc4_hdmi->ddc);
 337         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 338
 339         /*
 340          * Some of the properties below require access to state, like bpc.
 341          * Allocate some default initial connector state with our reset helper.
 342          */
 343         if (connector->funcs->reset)
 344                 connector->funcs->reset(connector);
 345
 346         /* Create and attach TV margin props to this connector. */
 347         ret = drm_mode_create_tv_margin_properties(dev);
 348         if (ret)
 349                 return ret;
 350
 351         ret = drm_mode_create_hdmi_colorspace_property(connector);
 352         if (ret)
 353                 return ret;
 354
 355         drm_connector_attach_colorspace_property(connector);
 356         drm_connector_attach_tv_margin_properties(connector);
 357         drm_connector_attach_max_bpc_property(connector, 8, 12);
 358
 359         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 360                              DRM_CONNECTOR_POLL_DISCONNECT);
 361
 362         connector->interlace_allowed = 1;
 363         connector->doublescan_allowed = 0;
 364
 365         if (vc4_hdmi->variant->supports_hdr)
 366                 drm_connector_attach_hdr_output_metadata_property(connector);
 367
 368         drm_connector_attach_encoder(connector, encoder);
 369
 370         return 0;
 371 }
 372
 373 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 374                                 enum hdmi_infoframe_type type,
 375                                 bool poll)
 376 {
 377         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 378         u32 packet_id = type - 0x80;
 379
 380         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 381                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 382
 383         if (!poll)
 384                 return 0;
 385
 386         return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 387                           BIT(packet_id)), 100);
 388 }
 389
 390 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 391                                      union hdmi_infoframe *frame)
 392 {
 393         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 394         u32 packet_id = frame->any.type - 0x80;
 395         const struct vc4_hdmi_register *ram_packet_start =
 396                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 397         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 398         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 399                                                        ram_packet_start->reg);
 400         uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
 401         ssize_t len, i;
 402         int ret;
 403
 404         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 405                     VC4_HDMI_RAM_PACKET_ENABLE),
 406                   "Packet RAM has to be on to store the packet.");
 407
 408         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 409         if (len < 0)
 410                 return;
 411
 412         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 413         if (ret) {
 414                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 415                 return;
 416         }
 417
 418         for (i = 0; i < len; i += 7) {
 419                 writel(buffer[i + 0] << 0 |
 420                        buffer[i + 1] << 8 |
 421                        buffer[i + 2] << 16,
 422                        base + packet_reg);
 423                 packet_reg += 4;
 424
 425                 writel(buffer[i + 3] << 0 |
 426                        buffer[i + 4] << 8 |
 427                        buffer[i + 5] << 16 |
 428                        buffer[i + 6] << 24,
 429                        base + packet_reg);
 430                 packet_reg += 4;
 431         }
 432
 433         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 434                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 435         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 436                         BIT(packet_id)), 100);
 437         if (ret)
 438                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 439 }
 440
 441 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 442 {
 443         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 444         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 445         struct drm_connector *connector = &vc4_hdmi->connector;
 446         struct drm_connector_state *cstate = connector->state;
 447         struct drm_crtc *crtc = encoder->crtc;
 448         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 449         union hdmi_infoframe frame;
 450         int ret;
 451
 452         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 453                                                        connector, mode);
 454         if (ret < 0) {
 455                 DRM_ERROR("couldn't fill AVI infoframe\n");
 456                 return;
 457         }
 458
 459         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 460                                            connector, mode,
 461                                            vc4_encoder->limited_rgb_range ?
 462                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 463                                            HDMI_QUANTIZATION_RANGE_FULL);
 464         drm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate);
 465         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 466
 467         vc4_hdmi_write_infoframe(encoder, &frame);
 468 }
 469
 470 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 471 {
 472         union hdmi_infoframe frame;
 473         int ret;
 474
 475         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 476         if (ret < 0) {
 477                 DRM_ERROR("couldn't fill SPD infoframe\n");
 478                 return;
 479         }
 480
 481         frame.spd.sdi = HDMI_SPD_SDI_PC;
 482
 483         vc4_hdmi_write_infoframe(encoder, &frame);
 484 }
 485
 486 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 487 {
 488         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 489         struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
 490         union hdmi_infoframe frame;
 491
 492         memcpy(&frame.audio, audio, sizeof(*audio));
 493         vc4_hdmi_write_infoframe(encoder, &frame);
 494 }
 495
 496 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 497 {
 498         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 499         struct drm_connector *connector = &vc4_hdmi->connector;
 500         struct drm_connector_state *conn_state = connector->state;
 501         union hdmi_infoframe frame;
 502
 503         if (!vc4_hdmi->variant->supports_hdr)
 504                 return;
 505
 506         if (!conn_state->hdr_output_metadata)
 507                 return;
 508
 509         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 510                 return;
 511
 512         vc4_hdmi_write_infoframe(encoder, &frame);
 513 }
 514
 515 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 516 {
 517         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 518
 519         vc4_hdmi_set_avi_infoframe(encoder);
 520         vc4_hdmi_set_spd_infoframe(encoder);
 521         /*
 522          * If audio was streaming, then we need to reenabled the audio
 523          * infoframe here during encoder_enable.
 524          */
 525         if (vc4_hdmi->audio.streaming)
 526                 vc4_hdmi_set_audio_infoframe(encoder);
 527
 528         vc4_hdmi_set_hdr_infoframe(encoder);
 529 }
 530
 531 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
 532                                          struct drm_display_mode *mode)
 533 {
 534         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 535         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 536         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 537
 538         if (!vc4_encoder->hdmi_monitor)
 539                 return false;
 540
 541         if (!display->hdmi.scdc.supported ||
 542             !display->hdmi.scdc.scrambling.supported)
 543                 return false;
 544
 545         return true;
 546 }
 547
 548 #define SCRAMBLING_POLLING_DELAY_MS     1000
 549
 550 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 551 {
 552         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 553         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 554
 555         if (!vc4_hdmi_supports_scrambling(encoder, mode))
 556                 return;
 557
 558         if (!vc4_hdmi_mode_needs_scrambling(mode))
 559                 return;
 560
 561         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 562         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 563
 564         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
 565                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 566
 567         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 568                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 569 }
 570
 571 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
 572 {
 573         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 574         struct drm_crtc *crtc = encoder->crtc;
 575
 576         /*
 577          * At boot, encoder->crtc will be NULL. Since we don't know the
 578          * state of the scrambler and in order to avoid any
 579          * inconsistency, let's disable it all the time.
 580          */
 581         if (crtc && !vc4_hdmi_supports_scrambling(encoder, &crtc->mode))
 582                 return;
 583
 584         if (crtc && !vc4_hdmi_mode_needs_scrambling(&crtc->mode))
 585                 return;
 586
 587         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
 588                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
 589
 590         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
 591                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 592
 593         drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
 594         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
 595 }
 596
 597 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
 598 {
 599         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
 600                                                  struct vc4_hdmi,
 601                                                  scrambling_work);
 602
 603         if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
 604                 return;
 605
 606         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 607         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 608
 609         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 610                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 611 }
 612
 613 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 614                                                struct drm_atomic_state *state)
 615 {
 616         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 617
 618         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 619
 620         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
 621
 622         mdelay(1);
 623
 624         HDMI_WRITE(HDMI_VID_CTL,
 625                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 626         vc4_hdmi_disable_scrambling(encoder);
 627 }
 628
 629 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
 630                                                  struct drm_atomic_state *state)
 631 {
 632         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 633         int ret;
 634
 635         HDMI_WRITE(HDMI_VID_CTL,
 636                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 637
 638         if (vc4_hdmi->variant->phy_disable)
 639                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 640
 641         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 642         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 643
 644         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 645         if (ret < 0)
 646                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 647 }
 648
 649 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 650 {
 651 }
 652
 653 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 654 {
 655         u32 csc_ctl;
 656
 657         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 658                                 VC4_HD_CSC_CTL_ORDER);
 659
 660         if (enable) {
 661                 /* CEA VICs other than #1 requre limited range RGB
 662                  * output unless overridden by an AVI infoframe.
 663                  * Apply a colorspace conversion to squash 0-255 down
 664                  * to 16-235.  The matrix here is:
 665                  *
 666                  * [ 0      0      0.8594 16]
 667                  * [ 0      0.8594 0      16]
 668                  * [ 0.8594 0      0      16]
 669                  * [ 0      0      0       1]
 670                  */
 671                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 672                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 673                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 674                                          VC4_HD_CSC_CTL_MODE);
 675
 676                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 677                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 678                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 679                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 680                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 681                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 682         }
 683
 684         /* The RGB order applies even when CSC is disabled. */
 685         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 686 }
 687
 688 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 689 {
 690         u32 csc_ctl;
 691
 692         csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
 693
 694         if (enable) {
 695                 /* CEA VICs other than #1 requre limited range RGB
 696                  * output unless overridden by an AVI infoframe.
 697                  * Apply a colorspace conversion to squash 0-255 down
 698                  * to 16-235.  The matrix here is:
 699                  *
 700                  * [ 0.8594 0      0      16]
 701                  * [ 0      0.8594 0      16]
 702                  * [ 0      0      0.8594 16]
 703                  * [ 0      0      0       1]
 704                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 705                  */
 706                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
 707                 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
 708                 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
 709                 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
 710                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 711                 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
 712         } else {
 713                 /* Still use the matrix for full range, but make it unity.
 714                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 715                  */
 716                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
 717                 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
 718                 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
 719                 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
 720                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 721                 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
 722         }
 723
 724         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 725 }
 726
 727 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 728                                  struct drm_connector_state *state,
 729                                  struct drm_display_mode *mode)
 730 {
 731         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 732         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 733         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 734         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 735         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 736                                    VC4_HDMI_VERTA_VSP) |
 737                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 738                                    VC4_HDMI_VERTA_VFP) |
 739                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 740         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 741                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 742                                    VC4_HDMI_VERTB_VBP));
 743         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 744                           VC4_SET_FIELD(mode->crtc_vtotal -
 745                                         mode->crtc_vsync_end -
 746                                         interlaced,
 747                                         VC4_HDMI_VERTB_VBP));
 748
 749         HDMI_WRITE(HDMI_HORZA,
 750                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 751                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 752                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 753                                  VC4_HDMI_HORZA_HAP));
 754
 755         HDMI_WRITE(HDMI_HORZB,
 756                    VC4_SET_FIELD((mode->htotal -
 757                                   mode->hsync_end) * pixel_rep,
 758                                  VC4_HDMI_HORZB_HBP) |
 759                    VC4_SET_FIELD((mode->hsync_end -
 760                                   mode->hsync_start) * pixel_rep,
 761                                  VC4_HDMI_HORZB_HSP) |
 762                    VC4_SET_FIELD((mode->hsync_start -
 763                                   mode->hdisplay) * pixel_rep,
 764                                  VC4_HDMI_HORZB_HFP));
 765
 766         HDMI_WRITE(HDMI_VERTA0, verta);
 767         HDMI_WRITE(HDMI_VERTA1, verta);
 768
 769         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 770         HDMI_WRITE(HDMI_VERTB1, vertb);
 771 }
 772
 773 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 774                                  struct drm_connector_state *state,
 775                                  struct drm_display_mode *mode)
 776 {
 777         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 778         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 779         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 780         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 781         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 782                                    VC5_HDMI_VERTA_VSP) |
 783                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 784                                    VC5_HDMI_VERTA_VFP) |
 785                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
 786         u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 787                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 788                                    VC4_HDMI_VERTB_VBP));
 789         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 790                           VC4_SET_FIELD(mode->crtc_vtotal -
 791                                         mode->crtc_vsync_end -
 792                                         interlaced,
 793                                         VC4_HDMI_VERTB_VBP));
 794         unsigned char gcp;
 795         bool gcp_en;
 796         u32 reg;
 797
 798         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
 799         HDMI_WRITE(HDMI_HORZA,
 800                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
 801                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
 802                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 803                                  VC5_HDMI_HORZA_HAP) |
 804                    VC4_SET_FIELD((mode->hsync_start -
 805                                   mode->hdisplay) * pixel_rep,
 806                                  VC5_HDMI_HORZA_HFP));
 807
 808         HDMI_WRITE(HDMI_HORZB,
 809                    VC4_SET_FIELD((mode->htotal -
 810                                   mode->hsync_end) * pixel_rep,
 811                                  VC5_HDMI_HORZB_HBP) |
 812                    VC4_SET_FIELD((mode->hsync_end -
 813                                   mode->hsync_start) * pixel_rep,
 814                                  VC5_HDMI_HORZB_HSP));
 815
 816         HDMI_WRITE(HDMI_VERTA0, verta);
 817         HDMI_WRITE(HDMI_VERTA1, verta);
 818
 819         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 820         HDMI_WRITE(HDMI_VERTB1, vertb);
 821
 822         switch (state->max_bpc) {
 823         case 12:
 824                 gcp = 6;
 825                 gcp_en = true;
 826                 break;
 827         case 10:
 828                 gcp = 5;
 829                 gcp_en = true;
 830                 break;
 831         case 8:
 832         default:
 833                 gcp = 4;
 834                 gcp_en = false;
 835                 break;
 836         }
 837
 838         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
 839         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
 840                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
 841         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
 842                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
 843         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
 844
 845         reg = HDMI_READ(HDMI_GCP_WORD_1);
 846         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
 847         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
 848         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
 849
 850         reg = HDMI_READ(HDMI_GCP_CONFIG);
 851         reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
 852         reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
 853         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
 854
 855         reg = HDMI_READ(HDMI_MISC_CONTROL);
 856         reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
 857         reg |= VC4_SET_FIELD(0, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
 858         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
 859
 860         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
 861 }
 862
 863 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
 864 {
 865         u32 drift;
 866         int ret;
 867
 868         drift = HDMI_READ(HDMI_FIFO_CTL);
 869         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 870
 871         HDMI_WRITE(HDMI_FIFO_CTL,
 872                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 873         HDMI_WRITE(HDMI_FIFO_CTL,
 874                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 875         usleep_range(1000, 1100);
 876         HDMI_WRITE(HDMI_FIFO_CTL,
 877                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 878         HDMI_WRITE(HDMI_FIFO_CTL,
 879                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 880
 881         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
 882                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
 883         WARN_ONCE(ret, "Timeout waiting for "
 884                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
 885 }
 886
 887 static struct drm_connector_state *
 888 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder,
 889                                      struct drm_atomic_state *state)
 890 {
 891         struct drm_connector_state *conn_state;
 892         struct drm_connector *connector;
 893         unsigned int i;
 894
 895         for_each_new_connector_in_state(state, connector, conn_state, i) {
 896                 if (conn_state->best_encoder == encoder)
 897                         return conn_state;
 898         }
 899
 900         return NULL;
 901 }
 902
 903 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
 904                                                 struct drm_atomic_state *state)
 905 {
 906         struct drm_connector_state *conn_state =
 907                 vc4_hdmi_encoder_get_connector_state(encoder, state);
 908         struct vc4_hdmi_connector_state *vc4_conn_state =
 909                 conn_state_to_vc4_hdmi_conn_state(conn_state);
 910         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 911         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 912         unsigned long pixel_rate = vc4_conn_state->pixel_rate;
 913         unsigned long bvb_rate, hsm_rate;
 914         int ret;
 915
 916         /*
 917          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
 918          * be faster than pixel clock, infinitesimally faster, tested in
 919          * simulation. Otherwise, exact value is unimportant for HDMI
 920          * operation." This conflicts with bcm2835's vc4 documentation, which
 921          * states HSM's clock has to be at least 108% of the pixel clock.
 922          *
 923          * Real life tests reveal that vc4's firmware statement holds up, and
 924          * users are able to use pixel clocks closer to HSM's, namely for
 925          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
 926          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
 927          * 162MHz.
 928          *
 929          * Additionally, the AXI clock needs to be at least 25% of
 930          * pixel clock, but HSM ends up being the limiting factor.
 931          */
 932         hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
 933         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
 934         if (ret) {
 935                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
 936                 return;
 937         }
 938
 939         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
 940         if (ret < 0) {
 941                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
 942                 return;
 943         }
 944
 945         ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
 946         if (ret) {
 947                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
 948                 goto err_put_runtime_pm;
 949         }
 950
 951         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
 952         if (ret) {
 953                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
 954                 goto err_put_runtime_pm;
 955         }
 956
 957
 958         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
 959
 960         if (pixel_rate > 297000000)
 961                 bvb_rate = 300000000;
 962         else if (pixel_rate > 148500000)
 963                 bvb_rate = 150000000;
 964         else
 965                 bvb_rate = 75000000;
 966
 967         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
 968         if (ret) {
 969                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
 970                 goto err_disable_pixel_clock;
 971         }
 972
 973         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
 974         if (ret) {
 975                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
 976                 goto err_disable_pixel_clock;
 977         }
 978
 979         if (vc4_hdmi->variant->phy_init)
 980                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
 981
 982         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 983                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
 984                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
 985                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
 986
 987         if (vc4_hdmi->variant->set_timings)
 988                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
 989
 990         return;
 991
 992 err_disable_pixel_clock:
 993         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 994 err_put_runtime_pm:
 995         pm_runtime_put(&vc4_hdmi->pdev->dev);
 996
 997         return;
 998 }
 999
1000 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1001                                              struct drm_atomic_state *state)
1002 {
1003         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1004         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1005         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1006
1007         if (vc4_encoder->hdmi_monitor &&
1008             drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
1009                 if (vc4_hdmi->variant->csc_setup)
1010                         vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
1011
1012                 vc4_encoder->limited_rgb_range = true;
1013         } else {
1014                 if (vc4_hdmi->variant->csc_setup)
1015                         vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
1016
1017                 vc4_encoder->limited_rgb_range = false;
1018         }
1019
1020         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1021 }
1022
1023 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1024                                               struct drm_atomic_state *state)
1025 {
1026         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1027         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1028         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1029         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1030         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1031         int ret;
1032
1033         HDMI_WRITE(HDMI_VID_CTL,
1034                    VC4_HD_VID_CTL_ENABLE |
1035                    VC4_HD_VID_CTL_CLRRGB |
1036                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1037                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1038                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1039                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1040
1041         HDMI_WRITE(HDMI_VID_CTL,
1042                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1043
1044         if (vc4_encoder->hdmi_monitor) {
1045                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1046                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1047                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1048
1049                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1050                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1051                 WARN_ONCE(ret, "Timeout waiting for "
1052                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1053         } else {
1054                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1055                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1056                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1057                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1058                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1059                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1060
1061                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1062                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1063                 WARN_ONCE(ret, "Timeout waiting for "
1064                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1065         }
1066
1067         if (vc4_encoder->hdmi_monitor) {
1068                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1069                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1070                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1071                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1072                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
1073
1074                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1075                            VC4_HDMI_RAM_PACKET_ENABLE);
1076
1077                 vc4_hdmi_set_infoframes(encoder);
1078         }
1079
1080         vc4_hdmi_recenter_fifo(vc4_hdmi);
1081         vc4_hdmi_enable_scrambling(encoder);
1082 }
1083
1084 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
1085 {
1086 }
1087
1088 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
1089 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
1090
1091 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1092                                          struct drm_crtc_state *crtc_state,
1093                                          struct drm_connector_state *conn_state)
1094 {
1095         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1096         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1097         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1098         unsigned long long pixel_rate = mode->clock * 1000;
1099         unsigned long long tmds_rate;
1100
1101         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1102             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1103             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1104              (mode->hsync_end % 2) || (mode->htotal % 2)))
1105                 return -EINVAL;
1106
1107         /*
1108          * The 1440p@60 pixel rate is in the same range than the first
1109          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1110          * bandwidth). Slightly lower the frequency to bring it out of
1111          * the WiFi range.
1112          */
1113         tmds_rate = pixel_rate * 10;
1114         if (vc4_hdmi->disable_wifi_frequencies &&
1115             (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1116              tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1117                 mode->clock = 238560;
1118                 pixel_rate = mode->clock * 1000;
1119         }
1120
1121         if (conn_state->max_bpc == 12) {
1122                 pixel_rate = pixel_rate * 150;
1123                 do_div(pixel_rate, 100);
1124         } else if (conn_state->max_bpc == 10) {
1125                 pixel_rate = pixel_rate * 125;
1126                 do_div(pixel_rate, 100);
1127         }
1128
1129         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1130                 pixel_rate = pixel_rate * 2;
1131
1132         if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
1133                 return -EINVAL;
1134
1135         if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK))
1136                 return -EINVAL;
1137
1138         vc4_state->pixel_rate = pixel_rate;
1139
1140         return 0;
1141 }
1142
1143 static enum drm_mode_status
1144 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1145                             const struct drm_display_mode *mode)
1146 {
1147         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1148
1149         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1150             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1151             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1152              (mode->hsync_end % 2) || (mode->htotal % 2)))
1153                 return MODE_H_ILLEGAL;
1154
1155         if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
1156                 return MODE_CLOCK_HIGH;
1157
1158         if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode))
1159                 return MODE_CLOCK_HIGH;
1160
1161         return MODE_OK;
1162 }
1163
1164 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1165         .atomic_check = vc4_hdmi_encoder_atomic_check,
1166         .mode_valid = vc4_hdmi_encoder_mode_valid,
1167         .disable = vc4_hdmi_encoder_disable,
1168         .enable = vc4_hdmi_encoder_enable,
1169 };
1170
1171 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1172 {
1173         int i;
1174         u32 channel_map = 0;
1175
1176         for (i = 0; i < 8; i++) {
1177                 if (channel_mask & BIT(i))
1178                         channel_map |= i << (3 * i);
1179         }
1180         return channel_map;
1181 }
1182
1183 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1184 {
1185         int i;
1186         u32 channel_map = 0;
1187
1188         for (i = 0; i < 8; i++) {
1189                 if (channel_mask & BIT(i))
1190                         channel_map |= i << (4 * i);
1191         }
1192         return channel_map;
1193 }
1194
1195 /* HDMI audio codec callbacks */
1196 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1197                                          unsigned int samplerate)
1198 {
1199         u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1200         unsigned long n, m;
1201
1202         rational_best_approximation(hsm_clock, samplerate,
1203                                     VC4_HD_MAI_SMP_N_MASK >>
1204                                     VC4_HD_MAI_SMP_N_SHIFT,
1205                                     (VC4_HD_MAI_SMP_M_MASK >>
1206                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
1207                                     &n, &m);
1208
1209         HDMI_WRITE(HDMI_MAI_SMP,
1210                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1211                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1212 }
1213
1214 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1215 {
1216         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1217         struct drm_crtc *crtc = encoder->crtc;
1218         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1219         u32 n, cts;
1220         u64 tmp;
1221
1222         n = 128 * samplerate / 1000;
1223         tmp = (u64)(mode->clock * 1000) * n;
1224         do_div(tmp, 128 * samplerate);
1225         cts = tmp;
1226
1227         HDMI_WRITE(HDMI_CRP_CFG,
1228                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1229                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1230
1231         /*
1232          * We could get slightly more accurate clocks in some cases by
1233          * providing a CTS_1 value.  The two CTS values are alternated
1234          * between based on the period fields
1235          */
1236         HDMI_WRITE(HDMI_CTS_0, cts);
1237         HDMI_WRITE(HDMI_CTS_1, cts);
1238 }
1239
1240 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1241 {
1242         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1243
1244         return snd_soc_card_get_drvdata(card);
1245 }
1246
1247 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1248 {
1249         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1250         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1251
1252         /*
1253          * If the HDMI encoder hasn't probed, or the encoder is
1254          * currently in DVI mode, treat the codec dai as missing.
1255          */
1256         if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1257                                 VC4_HDMI_RAM_PACKET_ENABLE))
1258                 return -ENODEV;
1259
1260         vc4_hdmi->audio.streaming = true;
1261
1262         HDMI_WRITE(HDMI_MAI_CTL,
1263                    VC4_HD_MAI_CTL_RESET |
1264                    VC4_HD_MAI_CTL_FLUSH |
1265                    VC4_HD_MAI_CTL_DLATE |
1266                    VC4_HD_MAI_CTL_ERRORE |
1267                    VC4_HD_MAI_CTL_ERRORF);
1268
1269         if (vc4_hdmi->variant->phy_rng_enable)
1270                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1271
1272         return 0;
1273 }
1274
1275 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1276 {
1277         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1278         struct device *dev = &vc4_hdmi->pdev->dev;
1279         int ret;
1280
1281         vc4_hdmi->audio.streaming = false;
1282         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1283         if (ret)
1284                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1285
1286         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1287         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1288         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1289 }
1290
1291 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1292 {
1293         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1294
1295         HDMI_WRITE(HDMI_MAI_CTL,
1296                    VC4_HD_MAI_CTL_DLATE |
1297                    VC4_HD_MAI_CTL_ERRORE |
1298                    VC4_HD_MAI_CTL_ERRORF);
1299
1300         if (vc4_hdmi->variant->phy_rng_disable)
1301                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1302
1303         vc4_hdmi->audio.streaming = false;
1304         vc4_hdmi_audio_reset(vc4_hdmi);
1305 }
1306
1307 static int sample_rate_to_mai_fmt(int samplerate)
1308 {
1309         switch (samplerate) {
1310         case 8000:
1311                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1312         case 11025:
1313                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1314         case 12000:
1315                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1316         case 16000:
1317                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1318         case 22050:
1319                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1320         case 24000:
1321                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1322         case 32000:
1323                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1324         case 44100:
1325                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1326         case 48000:
1327                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1328         case 64000:
1329                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
1330         case 88200:
1331                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
1332         case 96000:
1333                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
1334         case 128000:
1335                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
1336         case 176400:
1337                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
1338         case 192000:
1339                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
1340         default:
1341                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
1342         }
1343 }
1344
1345 /* HDMI audio codec callbacks */
1346 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
1347                                   struct hdmi_codec_daifmt *daifmt,
1348                                   struct hdmi_codec_params *params)
1349 {
1350         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1351         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1352         unsigned int sample_rate = params->sample_rate;
1353         unsigned int channels = params->channels;
1354         u32 audio_packet_config, channel_mask;
1355         u32 channel_map;
1356         u32 mai_audio_format;
1357         u32 mai_sample_rate;
1358
1359         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1360                 sample_rate, params->sample_width, channels);
1361
1362         HDMI_WRITE(HDMI_MAI_CTL,
1363                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
1364                    VC4_HD_MAI_CTL_WHOLSMP |
1365                    VC4_HD_MAI_CTL_CHALIGN |
1366                    VC4_HD_MAI_CTL_ENABLE);
1367
1368         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
1369
1370         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
1371         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
1372             params->channels == 8)
1373                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
1374         else
1375                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
1376         HDMI_WRITE(HDMI_MAI_FMT,
1377                    VC4_SET_FIELD(mai_sample_rate,
1378                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
1379                    VC4_SET_FIELD(mai_audio_format,
1380                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
1381
1382         /* The B frame identifier should match the value used by alsa-lib (8) */
1383         audio_packet_config =
1384                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1385                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1386                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1387
1388         channel_mask = GENMASK(channels - 1, 0);
1389         audio_packet_config |= VC4_SET_FIELD(channel_mask,
1390                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1391
1392         /* Set the MAI threshold */
1393         HDMI_WRITE(HDMI_MAI_THR,
1394                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
1395                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
1396                    VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
1397                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
1398
1399         HDMI_WRITE(HDMI_MAI_CONFIG,
1400                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1401                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
1402                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1403
1404         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1405         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1406         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1407         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
1408
1409         memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
1410         vc4_hdmi_set_audio_infoframe(encoder);
1411
1412         return 0;
1413 }
1414
1415 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1416         .name = "vc4-hdmi-cpu-dai-component",
1417 };
1418
1419 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1420 {
1421         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1422
1423         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1424
1425         return 0;
1426 }
1427
1428 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1429         .name = "vc4-hdmi-cpu-dai",
1430         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1431         .playback = {
1432                 .stream_name = "Playback",
1433                 .channels_min = 1,
1434                 .channels_max = 8,
1435                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1436                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1437                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1438                          SNDRV_PCM_RATE_192000,
1439                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1440         },
1441 };
1442
1443 static const struct snd_dmaengine_pcm_config pcm_conf = {
1444         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1445         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1446 };
1447
1448 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
1449                                   uint8_t *buf, size_t len)
1450 {
1451         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1452         struct drm_connector *connector = &vc4_hdmi->connector;
1453
1454         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1455
1456         return 0;
1457 }
1458
1459 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
1460         .get_eld = vc4_hdmi_audio_get_eld,
1461         .prepare = vc4_hdmi_audio_prepare,
1462         .audio_shutdown = vc4_hdmi_audio_shutdown,
1463         .audio_startup = vc4_hdmi_audio_startup,
1464 };
1465
1466 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
1467         .ops = &vc4_hdmi_codec_ops,
1468         .max_i2s_channels = 8,
1469         .i2s = 1,
1470 };
1471
1472 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1473 {
1474         const struct vc4_hdmi_register *mai_data =
1475                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1476         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1477         struct snd_soc_card *card = &vc4_hdmi->audio.card;
1478         struct device *dev = &vc4_hdmi->pdev->dev;
1479         struct platform_device *codec_pdev;
1480         const __be32 *addr;
1481         int index, len;
1482         int ret;
1483
1484         if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
1485                 dev_warn(dev,
1486                          "'dmas' DT property is missing or empty, no HDMI audio\n");
1487                 return 0;
1488         }
1489
1490         if (mai_data->reg != VC4_HD) {
1491                 WARN_ONCE(true, "MAI isn't in the HD block\n");
1492                 return -EINVAL;
1493         }
1494
1495         /*
1496          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1497          * the bus address specified in the DT, because the physical address
1498          * (the one returned by platform_get_resource()) is not appropriate
1499          * for DMA transfers.
1500          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1501          */
1502         index = of_property_match_string(dev->of_node, "reg-names", "hd");
1503         /* Before BCM2711, we don't have a named register range */
1504         if (index < 0)
1505                 index = 1;
1506
1507         addr = of_get_address(dev->of_node, index, NULL, NULL);
1508
1509         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1510         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1511         vc4_hdmi->audio.dma_data.maxburst = 2;
1512
1513         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1514         if (ret) {
1515                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1516                 return ret;
1517         }
1518
1519         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1520                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1521         if (ret) {
1522                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1523                 return ret;
1524         }
1525
1526         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1527                                                    PLATFORM_DEVID_AUTO,
1528                                                    &vc4_hdmi_codec_pdata,
1529                                                    sizeof(vc4_hdmi_codec_pdata));
1530         if (IS_ERR(codec_pdev)) {
1531                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
1532                 return PTR_ERR(codec_pdev);
1533         }
1534         vc4_hdmi->audio.codec_pdev = codec_pdev;
1535
1536         dai_link->cpus          = &vc4_hdmi->audio.cpu;
1537         dai_link->codecs        = &vc4_hdmi->audio.codec;
1538         dai_link->platforms     = &vc4_hdmi->audio.platform;
1539
1540         dai_link->num_cpus      = 1;
1541         dai_link->num_codecs    = 1;
1542         dai_link->num_platforms = 1;
1543
1544         dai_link->name = "MAI";
1545         dai_link->stream_name = "MAI PCM";
1546         dai_link->codecs->dai_name = "i2s-hifi";
1547         dai_link->cpus->dai_name = dev_name(dev);
1548         dai_link->codecs->name = dev_name(&codec_pdev->dev);
1549         dai_link->platforms->name = dev_name(dev);
1550
1551         card->dai_link = dai_link;
1552         card->num_links = 1;
1553         card->name = vc4_hdmi->variant->card_name;
1554         card->driver_name = "vc4-hdmi";
1555         card->dev = dev;
1556         card->owner = THIS_MODULE;
1557
1558         /*
1559          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1560          * stores a pointer to the snd card object in dev->driver_data. This
1561          * means we cannot use it for something else. The hdmi back-pointer is
1562          * now stored in card->drvdata and should be retrieved with
1563          * snd_soc_card_get_drvdata() if needed.
1564          */
1565         snd_soc_card_set_drvdata(card, vc4_hdmi);
1566         ret = devm_snd_soc_register_card(dev, card);
1567         if (ret)
1568                 dev_err_probe(dev, ret, "Could not register sound card\n");
1569
1570         return ret;
1571
1572 }
1573
1574 static void vc4_hdmi_audio_exit(struct vc4_hdmi *vc4_hdmi)
1575 {
1576         platform_device_unregister(vc4_hdmi->audio.codec_pdev);
1577         vc4_hdmi->audio.codec_pdev = NULL;
1578 }
1579
1580 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
1581 {
1582         struct vc4_hdmi *vc4_hdmi = priv;
1583         struct drm_device *dev = vc4_hdmi->connector.dev;
1584
1585         if (dev && dev->registered)
1586                 drm_kms_helper_hotplug_event(dev);
1587
1588         return IRQ_HANDLED;
1589 }
1590
1591 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
1592 {
1593         struct drm_connector *connector = &vc4_hdmi->connector;
1594         struct platform_device *pdev = vc4_hdmi->pdev;
1595         int ret;
1596
1597         if (vc4_hdmi->variant->external_irq_controller) {
1598                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
1599                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
1600
1601                 ret = request_threaded_irq(hpd_con,
1602                                            NULL,
1603                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1604                                            "vc4 hdmi hpd connected", vc4_hdmi);
1605                 if (ret)
1606                         return ret;
1607
1608                 ret = request_threaded_irq(hpd_rm,
1609                                            NULL,
1610                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1611                                            "vc4 hdmi hpd disconnected", vc4_hdmi);
1612                 if (ret) {
1613                         free_irq(hpd_con, vc4_hdmi);
1614                         return ret;
1615                 }
1616
1617                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1618         }
1619
1620         return 0;
1621 }
1622
1623 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi)
1624 {
1625         struct platform_device *pdev = vc4_hdmi->pdev;
1626
1627         if (vc4_hdmi->variant->external_irq_controller) {
1628                 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi);
1629                 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi);
1630         }
1631 }
1632
1633 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1634 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1635 {
1636         struct vc4_hdmi *vc4_hdmi = priv;
1637
1638         if (vc4_hdmi->cec_rx_msg.len)
1639                 cec_received_msg(vc4_hdmi->cec_adap,
1640                                  &vc4_hdmi->cec_rx_msg);
1641
1642         return IRQ_HANDLED;
1643 }
1644
1645 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1646 {
1647         struct vc4_hdmi *vc4_hdmi = priv;
1648
1649         if (vc4_hdmi->cec_tx_ok) {
1650                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1651                                   0, 0, 0, 0);
1652         } else {
1653                 /*
1654                  * This CEC implementation makes 1 retry, so if we
1655                  * get a NACK, then that means it made 2 attempts.
1656                  */
1657                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1658                                   0, 2, 0, 0);
1659         }
1660         return IRQ_HANDLED;
1661 }
1662
1663 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1664 {
1665         struct vc4_hdmi *vc4_hdmi = priv;
1666         irqreturn_t ret;
1667
1668         if (vc4_hdmi->cec_irq_was_rx)
1669                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1670         else
1671                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1672
1673         return ret;
1674 }
1675
1676 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1677 {
1678         struct drm_device *dev = vc4_hdmi->connector.dev;
1679         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1680         unsigned int i;
1681
1682         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1683                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1684
1685         if (msg->len > 16) {
1686                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1687                 return;
1688         }
1689
1690         for (i = 0; i < msg->len; i += 4) {
1691                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1692
1693                 msg->msg[i] = val & 0xff;
1694                 msg->msg[i + 1] = (val >> 8) & 0xff;
1695                 msg->msg[i + 2] = (val >> 16) & 0xff;
1696                 msg->msg[i + 3] = (val >> 24) & 0xff;
1697         }
1698 }
1699
1700 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1701 {
1702         struct vc4_hdmi *vc4_hdmi = priv;
1703         u32 cntrl1;
1704
1705         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1706         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1707         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1708         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1709
1710         return IRQ_WAKE_THREAD;
1711 }
1712
1713 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1714 {
1715         struct vc4_hdmi *vc4_hdmi = priv;
1716         u32 cntrl1;
1717
1718         vc4_hdmi->cec_rx_msg.len = 0;
1719         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1720         vc4_cec_read_msg(vc4_hdmi, cntrl1);
1721         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1722         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1723         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1724
1725         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1726
1727         return IRQ_WAKE_THREAD;
1728 }
1729
1730 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1731 {
1732         struct vc4_hdmi *vc4_hdmi = priv;
1733         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1734         irqreturn_t ret;
1735         u32 cntrl5;
1736
1737         if (!(stat & VC4_HDMI_CPU_CEC))
1738                 return IRQ_NONE;
1739
1740         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1741         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1742         if (vc4_hdmi->cec_irq_was_rx)
1743                 ret = vc4_cec_irq_handler_rx_bare(irq, priv);
1744         else
1745                 ret = vc4_cec_irq_handler_tx_bare(irq, priv);
1746
1747         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1748         return ret;
1749 }
1750
1751 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1752 {
1753         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1754         /* clock period in microseconds */
1755         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1756         u32 val = HDMI_READ(HDMI_CEC_CNTRL_5);
1757
1758         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1759                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1760                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1761         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1762                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1763
1764         if (enable) {
1765                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1766                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1767                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1768                 HDMI_WRITE(HDMI_CEC_CNTRL_2,
1769                            ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1770                            ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1771                            ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1772                            ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1773                            ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1774                 HDMI_WRITE(HDMI_CEC_CNTRL_3,
1775                            ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1776                            ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1777                            ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1778                            ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1779                 HDMI_WRITE(HDMI_CEC_CNTRL_4,
1780                            ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1781                            ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1782                            ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1783                            ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1784
1785                 if (!vc4_hdmi->variant->external_irq_controller)
1786                         HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1787         } else {
1788                 if (!vc4_hdmi->variant->external_irq_controller)
1789                         HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1790                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1791                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1792         }
1793         return 0;
1794 }
1795
1796 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1797 {
1798         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1799
1800         HDMI_WRITE(HDMI_CEC_CNTRL_1,
1801                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1802                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1803         return 0;
1804 }
1805
1806 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1807                                       u32 signal_free_time, struct cec_msg *msg)
1808 {
1809         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1810         struct drm_device *dev = vc4_hdmi->connector.dev;
1811         u32 val;
1812         unsigned int i;
1813
1814         if (msg->len > 16) {
1815                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
1816                 return -ENOMEM;
1817         }
1818
1819         for (i = 0; i < msg->len; i += 4)
1820                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
1821                            (msg->msg[i]) |
1822                            (msg->msg[i + 1] << 8) |
1823                            (msg->msg[i + 2] << 16) |
1824                            (msg->msg[i + 3] << 24));
1825
1826         val = HDMI_READ(HDMI_CEC_CNTRL_1);
1827         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1828         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1829         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1830         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1831         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1832
1833         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1834         return 0;
1835 }
1836
1837 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1838         .adap_enable = vc4_hdmi_cec_adap_enable,
1839         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1840         .adap_transmit = vc4_hdmi_cec_adap_transmit,
1841 };
1842
1843 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1844 {
1845         struct cec_connector_info conn_info;
1846         struct platform_device *pdev = vc4_hdmi->pdev;
1847         struct device *dev = &pdev->dev;
1848         u32 value;
1849         int ret;
1850
1851         if (!of_find_property(dev->of_node, "interrupts", NULL)) {
1852                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
1853                 return 0;
1854         }
1855
1856         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1857                                                   vc4_hdmi, "vc4",
1858                                                   CEC_CAP_DEFAULTS |
1859                                                   CEC_CAP_CONNECTOR_INFO, 1);
1860         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
1861         if (ret < 0)
1862                 return ret;
1863
1864         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
1865         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
1866
1867         value = HDMI_READ(HDMI_CEC_CNTRL_1);
1868         /* Set the logical address to Unregistered */
1869         value |= VC4_HDMI_CEC_ADDR_MASK;
1870         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
1871
1872         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1873
1874         if (vc4_hdmi->variant->external_irq_controller) {
1875                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"),
1876                                            vc4_cec_irq_handler_rx_bare,
1877                                            vc4_cec_irq_handler_rx_thread, 0,
1878                                            "vc4 hdmi cec rx", vc4_hdmi);
1879                 if (ret)
1880                         goto err_delete_cec_adap;
1881
1882                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"),
1883                                            vc4_cec_irq_handler_tx_bare,
1884                                            vc4_cec_irq_handler_tx_thread, 0,
1885                                            "vc4 hdmi cec tx", vc4_hdmi);
1886                 if (ret)
1887                         goto err_remove_cec_rx_handler;
1888         } else {
1889                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
1890
1891                 ret = request_threaded_irq(platform_get_irq(pdev, 0),
1892                                            vc4_cec_irq_handler,
1893                                            vc4_cec_irq_handler_thread, 0,
1894                                            "vc4 hdmi cec", vc4_hdmi);
1895                 if (ret)
1896                         goto err_delete_cec_adap;
1897         }
1898
1899         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
1900         if (ret < 0)
1901                 goto err_remove_handlers;
1902
1903         return 0;
1904
1905 err_remove_handlers:
1906         if (vc4_hdmi->variant->external_irq_controller)
1907                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
1908         else
1909                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
1910
1911 err_remove_cec_rx_handler:
1912         if (vc4_hdmi->variant->external_irq_controller)
1913                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
1914
1915 err_delete_cec_adap:
1916         cec_delete_adapter(vc4_hdmi->cec_adap);
1917
1918         return ret;
1919 }
1920
1921 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
1922 {
1923         struct platform_device *pdev = vc4_hdmi->pdev;
1924
1925         if (vc4_hdmi->variant->external_irq_controller) {
1926                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
1927                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
1928         } else {
1929                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
1930         }
1931
1932         cec_unregister_adapter(vc4_hdmi->cec_adap);
1933 }
1934 #else
1935 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1936 {
1937         return 0;
1938 }
1939
1940 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
1941
1942 #endif
1943
1944 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
1945                                  struct debugfs_regset32 *regset,
1946                                  enum vc4_hdmi_regs reg)
1947 {
1948         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1949         struct debugfs_reg32 *regs, *new_regs;
1950         unsigned int count = 0;
1951         unsigned int i;
1952
1953         regs = kcalloc(variant->num_registers, sizeof(*regs),
1954                        GFP_KERNEL);
1955         if (!regs)
1956                 return -ENOMEM;
1957
1958         for (i = 0; i < variant->num_registers; i++) {
1959                 const struct vc4_hdmi_register *field = &variant->registers[i];
1960
1961                 if (field->reg != reg)
1962                         continue;
1963
1964                 regs[count].name = field->name;
1965                 regs[count].offset = field->offset;
1966                 count++;
1967         }
1968
1969         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
1970         if (!new_regs)
1971                 return -ENOMEM;
1972
1973         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
1974         regset->regs = new_regs;
1975         regset->nregs = count;
1976
1977         return 0;
1978 }
1979
1980 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1981 {
1982         struct platform_device *pdev = vc4_hdmi->pdev;
1983         struct device *dev = &pdev->dev;
1984         int ret;
1985
1986         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1987         if (IS_ERR(vc4_hdmi->hdmicore_regs))
1988                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1989
1990         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1991         if (IS_ERR(vc4_hdmi->hd_regs))
1992                 return PTR_ERR(vc4_hdmi->hd_regs);
1993
1994         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
1995         if (ret)
1996                 return ret;
1997
1998         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
1999         if (ret)
2000                 return ret;
2001
2002         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
2003         if (IS_ERR(vc4_hdmi->pixel_clock)) {
2004                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
2005                 if (ret != -EPROBE_DEFER)
2006                         DRM_ERROR("Failed to get pixel clock\n");
2007                 return ret;
2008         }
2009
2010         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2011         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2012                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2013                 return PTR_ERR(vc4_hdmi->hsm_clock);
2014         }
2015         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2016         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2017
2018         return 0;
2019 }
2020
2021 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2022 {
2023         struct platform_device *pdev = vc4_hdmi->pdev;
2024         struct device *dev = &pdev->dev;
2025         struct resource *res;
2026
2027         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2028         if (!res)
2029                 return -ENODEV;
2030
2031         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2032                                                resource_size(res));
2033         if (!vc4_hdmi->hdmicore_regs)
2034                 return -ENOMEM;
2035
2036         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2037         if (!res)
2038                 return -ENODEV;
2039
2040         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2041         if (!vc4_hdmi->hd_regs)
2042                 return -ENOMEM;
2043
2044         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2045         if (!res)
2046                 return -ENODEV;
2047
2048         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2049         if (!vc4_hdmi->cec_regs)
2050                 return -ENOMEM;
2051
2052         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2053         if (!res)
2054                 return -ENODEV;
2055
2056         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2057         if (!vc4_hdmi->csc_regs)
2058                 return -ENOMEM;
2059
2060         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2061         if (!res)
2062                 return -ENODEV;
2063
2064         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2065         if (!vc4_hdmi->dvp_regs)
2066                 return -ENOMEM;
2067
2068         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2069         if (!res)
2070                 return -ENODEV;
2071
2072         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2073         if (!vc4_hdmi->phy_regs)
2074                 return -ENOMEM;
2075
2076         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2077         if (!res)
2078                 return -ENODEV;
2079
2080         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2081         if (!vc4_hdmi->ram_regs)
2082                 return -ENOMEM;
2083
2084         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2085         if (!res)
2086                 return -ENODEV;
2087
2088         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2089         if (!vc4_hdmi->rm_regs)
2090                 return -ENOMEM;
2091
2092         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2093         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2094                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2095                 return PTR_ERR(vc4_hdmi->hsm_clock);
2096         }
2097
2098         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2099         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2100                 DRM_ERROR("Failed to get pixel bvb clock\n");
2101                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2102         }
2103
2104         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2105         if (IS_ERR(vc4_hdmi->audio_clock)) {
2106                 DRM_ERROR("Failed to get audio clock\n");
2107                 return PTR_ERR(vc4_hdmi->audio_clock);
2108         }
2109
2110         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2111         if (IS_ERR(vc4_hdmi->cec_clock)) {
2112                 DRM_ERROR("Failed to get CEC clock\n");
2113                 return PTR_ERR(vc4_hdmi->cec_clock);
2114         }
2115
2116         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2117         if (IS_ERR(vc4_hdmi->reset)) {
2118                 DRM_ERROR("Failed to get HDMI reset line\n");
2119                 return PTR_ERR(vc4_hdmi->reset);
2120         }
2121
2122         return 0;
2123 }
2124
2125 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev)
2126 {
2127         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2128
2129         clk_disable_unprepare(vc4_hdmi->hsm_clock);
2130
2131         return 0;
2132 }
2133
2134 static int vc4_hdmi_runtime_resume(struct device *dev)
2135 {
2136         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2137         int ret;
2138
2139         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
2140         if (ret)
2141                 return ret;
2142
2143         return 0;
2144 }
2145
2146 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2147 {
2148         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2149         struct platform_device *pdev = to_platform_device(dev);
2150         struct drm_device *drm = dev_get_drvdata(master);
2151         struct vc4_hdmi *vc4_hdmi;
2152         struct drm_encoder *encoder;
2153         struct device_node *ddc_node;
2154         int ret;
2155
2156         vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2157         if (!vc4_hdmi)
2158                 return -ENOMEM;
2159         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2160
2161         dev_set_drvdata(dev, vc4_hdmi);
2162         encoder = &vc4_hdmi->encoder.base.base;
2163         vc4_hdmi->encoder.base.type = variant->encoder_type;
2164         vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2165         vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2166         vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2167         vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2168         vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2169         vc4_hdmi->pdev = pdev;
2170         vc4_hdmi->variant = variant;
2171
2172         ret = variant->init_resources(vc4_hdmi);
2173         if (ret)
2174                 return ret;
2175
2176         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2177         if (!ddc_node) {
2178                 DRM_ERROR("Failed to find ddc node in device tree\n");
2179                 return -ENODEV;
2180         }
2181
2182         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2183         of_node_put(ddc_node);
2184         if (!vc4_hdmi->ddc) {
2185                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2186                 return -EPROBE_DEFER;
2187         }
2188
2189         /* Only use the GPIO HPD pin if present in the DT, otherwise
2190          * we'll use the HDMI core's register.
2191          */
2192         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2193         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
2194                 ret = PTR_ERR(vc4_hdmi->hpd_gpio);
2195                 goto err_put_ddc;
2196         }
2197
2198         vc4_hdmi->disable_wifi_frequencies =
2199                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2200
2201         if (variant->max_pixel_clock == 600000000) {
2202                 struct vc4_dev *vc4 = to_vc4_dev(drm);
2203                 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
2204
2205                 if (max_rate < 550000000)
2206                         vc4_hdmi->disable_4kp60 = true;
2207         }
2208
2209         /*
2210          * If we boot without any cable connected to the HDMI connector,
2211          * the firmware will skip the HSM initialization and leave it
2212          * with a rate of 0, resulting in a bus lockup when we're
2213          * accessing the registers even if it's enabled.
2214          *
2215          * Let's put a sensible default at runtime_resume so that we
2216          * don't end up in this situation.
2217          */
2218         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
2219         if (ret)
2220                 goto err_put_ddc;
2221
2222         /*
2223          * We need to have the device powered up at this point to call
2224          * our reset hook and for the CEC init.
2225          */
2226         ret = vc4_hdmi_runtime_resume(dev);
2227         if (ret)
2228                 goto err_put_ddc;
2229
2230         pm_runtime_get_noresume(dev);
2231         pm_runtime_set_active(dev);
2232         pm_runtime_enable(dev);
2233
2234         if (vc4_hdmi->variant->reset)
2235                 vc4_hdmi->variant->reset(vc4_hdmi);
2236
2237         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
2238              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
2239             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
2240                 clk_prepare_enable(vc4_hdmi->pixel_clock);
2241                 clk_prepare_enable(vc4_hdmi->hsm_clock);
2242                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
2243         }
2244
2245         drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2246         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2247
2248         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2249         if (ret)
2250                 goto err_destroy_encoder;
2251
2252         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
2253         if (ret)
2254                 goto err_destroy_conn;
2255
2256         ret = vc4_hdmi_cec_init(vc4_hdmi);
2257         if (ret)
2258                 goto err_free_hotplug;
2259
2260         ret = vc4_hdmi_audio_init(vc4_hdmi);
2261         if (ret)
2262                 goto err_free_cec;
2263
2264         vc4_debugfs_add_file(drm, variant->debugfs_name,
2265                              vc4_hdmi_debugfs_regs,
2266                              vc4_hdmi);
2267
2268         pm_runtime_put_sync(dev);
2269
2270         return 0;
2271
2272 err_free_cec:
2273         vc4_hdmi_cec_exit(vc4_hdmi);
2274 err_free_hotplug:
2275         vc4_hdmi_hotplug_exit(vc4_hdmi);
2276 err_destroy_conn:
2277         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2278 err_destroy_encoder:
2279         drm_encoder_cleanup(encoder);
2280         pm_runtime_put_sync(dev);
2281         pm_runtime_disable(dev);
2282 err_put_ddc:
2283         put_device(&vc4_hdmi->ddc->dev);
2284
2285         return ret;
2286 }
2287
2288 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2289                             void *data)
2290 {
2291         struct vc4_hdmi *vc4_hdmi;
2292
2293         /*
2294          * ASoC makes it a bit hard to retrieve a pointer to the
2295          * vc4_hdmi structure. Registering the card will overwrite our
2296          * device drvdata with a pointer to the snd_soc_card structure,
2297          * which can then be used to retrieve whatever drvdata we want
2298          * to associate.
2299          *
2300          * However, that doesn't fly in the case where we wouldn't
2301          * register an ASoC card (because of an old DT that is missing
2302          * the dmas properties for example), then the card isn't
2303          * registered and the device drvdata wouldn't be set.
2304          *
2305          * We can deal with both cases by making sure a snd_soc_card
2306          * pointer and a vc4_hdmi structure are pointing to the same
2307          * memory address, so we can treat them indistinctly without any
2308          * issue.
2309          */
2310         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2311         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2312         vc4_hdmi = dev_get_drvdata(dev);
2313
2314         kfree(vc4_hdmi->hdmi_regset.regs);
2315         kfree(vc4_hdmi->hd_regset.regs);
2316
2317         vc4_hdmi_audio_exit(vc4_hdmi);
2318         vc4_hdmi_cec_exit(vc4_hdmi);
2319         vc4_hdmi_hotplug_exit(vc4_hdmi);
2320         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2321         drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2322
2323         pm_runtime_disable(dev);
2324
2325         put_device(&vc4_hdmi->ddc->dev);
2326 }
2327
2328 static const struct component_ops vc4_hdmi_ops = {
2329         .bind   = vc4_hdmi_bind,
2330         .unbind = vc4_hdmi_unbind,
2331 };
2332
2333 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2334 {
2335         return component_add(&pdev->dev, &vc4_hdmi_ops);
2336 }
2337
2338 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2339 {
2340         component_del(&pdev->dev, &vc4_hdmi_ops);
2341         return 0;
2342 }
2343
2344 static const struct vc4_hdmi_variant bcm2835_variant = {
2345         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2346         .debugfs_name           = "hdmi_regs",
2347         .card_name              = "vc4-hdmi",
2348         .max_pixel_clock        = 162000000,
2349         .registers              = vc4_hdmi_fields,
2350         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
2351
2352         .init_resources         = vc4_hdmi_init_resources,
2353         .csc_setup              = vc4_hdmi_csc_setup,
2354         .reset                  = vc4_hdmi_reset,
2355         .set_timings            = vc4_hdmi_set_timings,
2356         .phy_init               = vc4_hdmi_phy_init,
2357         .phy_disable            = vc4_hdmi_phy_disable,
2358         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
2359         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
2360         .channel_map            = vc4_hdmi_channel_map,
2361         .supports_hdr           = false,
2362 };
2363
2364 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2365         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2366         .debugfs_name           = "hdmi0_regs",
2367         .card_name              = "vc4-hdmi-0",
2368         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2369         .registers              = vc5_hdmi_hdmi0_fields,
2370         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2371         .phy_lane_mapping       = {
2372                 PHY_LANE_0,
2373                 PHY_LANE_1,
2374                 PHY_LANE_2,
2375                 PHY_LANE_CK,
2376         },
2377         .unsupported_odd_h_timings      = true,
2378         .external_irq_controller        = true,
2379
2380         .init_resources         = vc5_hdmi_init_resources,
2381         .csc_setup              = vc5_hdmi_csc_setup,
2382         .reset                  = vc5_hdmi_reset,
2383         .set_timings            = vc5_hdmi_set_timings,
2384         .phy_init               = vc5_hdmi_phy_init,
2385         .phy_disable            = vc5_hdmi_phy_disable,
2386         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2387         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2388         .channel_map            = vc5_hdmi_channel_map,
2389         .supports_hdr           = true,
2390 };
2391
2392 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2393         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
2394         .debugfs_name           = "hdmi1_regs",
2395         .card_name              = "vc4-hdmi-1",
2396         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2397         .registers              = vc5_hdmi_hdmi1_fields,
2398         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2399         .phy_lane_mapping       = {
2400                 PHY_LANE_1,
2401                 PHY_LANE_0,
2402                 PHY_LANE_CK,
2403                 PHY_LANE_2,
2404         },
2405         .unsupported_odd_h_timings      = true,
2406         .external_irq_controller        = true,
2407
2408         .init_resources         = vc5_hdmi_init_resources,
2409         .csc_setup              = vc5_hdmi_csc_setup,
2410         .reset                  = vc5_hdmi_reset,
2411         .set_timings            = vc5_hdmi_set_timings,
2412         .phy_init               = vc5_hdmi_phy_init,
2413         .phy_disable            = vc5_hdmi_phy_disable,
2414         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2415         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2416         .channel_map            = vc5_hdmi_channel_map,
2417         .supports_hdr           = true,
2418 };
2419
2420 static const struct of_device_id vc4_hdmi_dt_match[] = {
2421         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2422         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2423         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2424         {}
2425 };
2426
2427 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
2428         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
2429                            vc4_hdmi_runtime_resume,
2430                            NULL)
2431 };
2432
2433 struct platform_driver vc4_hdmi_driver = {
2434         .probe = vc4_hdmi_dev_probe,
2435         .remove = vc4_hdmi_dev_remove,
2436         .driver = {
2437                 .name = "vc4_hdmi",
2438                 .of_match_table = vc4_hdmi_dt_match,
2439                 .pm = &vc4_hdmi_pm_ops,
2440         },
2441 };