1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
10 * DOC: VC4 Falcon HDMI module
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_probe_helper.h>
37 #include <drm/drm_simple_kms_helper.h>
38 #include <drm/drm_scdc_helper.h>
39 #include <linux/clk.h>
40 #include <linux/component.h>
41 #include <linux/i2c.h>
42 #include <linux/of_address.h>
43 #include <linux/of_gpio.h>
44 #include <linux/of_platform.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/rational.h>
47 #include <linux/reset.h>
48 #include <sound/dmaengine_pcm.h>
49 #include <sound/hdmi-codec.h>
50 #include <sound/pcm_drm_eld.h>
51 #include <sound/pcm_params.h>
52 #include <sound/soc.h>
53 #include "media/cec.h"
56 #include "vc4_hdmi_regs.h"
59 #define VC5_HDMI_HORZA_HFP_SHIFT 16
60 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
61 #define VC5_HDMI_HORZA_VPOS BIT(15)
62 #define VC5_HDMI_HORZA_HPOS BIT(14)
63 #define VC5_HDMI_HORZA_HAP_SHIFT 0
64 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
66 #define VC5_HDMI_HORZB_HBP_SHIFT 16
67 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
68 #define VC5_HDMI_HORZB_HSP_SHIFT 0
69 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
71 #define VC5_HDMI_VERTA_VSP_SHIFT 24
72 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
73 #define VC5_HDMI_VERTA_VFP_SHIFT 16
74 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
75 #define VC5_HDMI_VERTA_VAL_SHIFT 0
76 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
78 #define VC5_HDMI_VERTB_VSPO_SHIFT 16
79 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
81 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0
87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)
89 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31)
91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
94 # define VC4_HD_M_SW_RST BIT(2)
95 # define VC4_HD_M_ENABLE BIT(0)
97 #define HSM_MIN_CLOCK_FREQ 120000000
98 #define CEC_CLOCK_FREQ 40000
100 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
102 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode)
104 return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK;
107 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
109 struct drm_info_node *node = (struct drm_info_node *)m->private;
110 struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
111 struct drm_printer p = drm_seq_file_printer(m);
113 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
114 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
119 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
121 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
123 HDMI_WRITE(HDMI_M_CTL, 0);
125 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
127 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
128 VC4_HDMI_SW_RESET_HDMI |
129 VC4_HDMI_SW_RESET_FORMAT_DETECT);
131 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
134 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
136 reset_control_reset(vc4_hdmi->reset);
138 HDMI_WRITE(HDMI_DVP_CTL, 0);
140 HDMI_WRITE(HDMI_CLOCK_STOP,
141 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
144 #ifdef CONFIG_DRM_VC4_HDMI_CEC
145 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
150 value = HDMI_READ(HDMI_CEC_CNTRL_1);
151 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
154 * Set the clock divider: the hsm_clock rate and this divider
155 * setting will give a 40 kHz CEC clock.
157 clk_cnt = clk_get_rate(vc4_hdmi->cec_clock) / CEC_CLOCK_FREQ;
158 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
159 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
162 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
165 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder);
167 static enum drm_connector_status
168 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
170 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
171 bool connected = false;
173 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
175 if (vc4_hdmi->hpd_gpio &&
176 gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) {
178 } else if (drm_probe_ddc(vc4_hdmi->ddc)) {
180 } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) {
185 if (connector->status != connector_status_connected) {
186 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
189 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
190 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
195 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base);
196 pm_runtime_put(&vc4_hdmi->pdev->dev);
197 return connector_status_connected;
200 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
201 pm_runtime_put(&vc4_hdmi->pdev->dev);
202 return connector_status_disconnected;
205 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
207 drm_connector_unregister(connector);
208 drm_connector_cleanup(connector);
211 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
213 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
214 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
218 edid = drm_get_edid(connector, vc4_hdmi->ddc);
219 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
223 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
225 drm_connector_update_edid_property(connector, edid);
226 ret = drm_add_edid_modes(connector, edid);
229 if (vc4_hdmi->disable_4kp60) {
230 struct drm_device *drm = connector->dev;
231 struct drm_display_mode *mode;
233 list_for_each_entry(mode, &connector->probed_modes, head) {
234 if (vc4_hdmi_mode_needs_scrambling(mode)) {
235 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
236 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
244 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
245 struct drm_atomic_state *state)
247 struct drm_connector_state *old_state =
248 drm_atomic_get_old_connector_state(state, connector);
249 struct drm_connector_state *new_state =
250 drm_atomic_get_new_connector_state(state, connector);
251 struct drm_crtc *crtc = new_state->crtc;
256 if (old_state->colorspace != new_state->colorspace ||
257 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
258 struct drm_crtc_state *crtc_state;
260 crtc_state = drm_atomic_get_crtc_state(state, crtc);
261 if (IS_ERR(crtc_state))
262 return PTR_ERR(crtc_state);
264 crtc_state->mode_changed = true;
270 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
272 struct vc4_hdmi_connector_state *old_state =
273 conn_state_to_vc4_hdmi_conn_state(connector->state);
274 struct vc4_hdmi_connector_state *new_state =
275 kzalloc(sizeof(*new_state), GFP_KERNEL);
277 if (connector->state)
278 __drm_atomic_helper_connector_destroy_state(connector->state);
281 __drm_atomic_helper_connector_reset(connector, &new_state->base);
286 new_state->base.max_bpc = 8;
287 new_state->base.max_requested_bpc = 8;
288 drm_atomic_helper_connector_tv_reset(connector);
291 static struct drm_connector_state *
292 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
294 struct drm_connector_state *conn_state = connector->state;
295 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
296 struct vc4_hdmi_connector_state *new_state;
298 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
302 new_state->pixel_rate = vc4_state->pixel_rate;
303 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
305 return &new_state->base;
308 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
309 .detect = vc4_hdmi_connector_detect,
310 .fill_modes = drm_helper_probe_single_connector_modes,
311 .destroy = vc4_hdmi_connector_destroy,
312 .reset = vc4_hdmi_connector_reset,
313 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
314 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
317 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
318 .get_modes = vc4_hdmi_connector_get_modes,
319 .atomic_check = vc4_hdmi_connector_atomic_check,
322 static int vc4_hdmi_connector_init(struct drm_device *dev,
323 struct vc4_hdmi *vc4_hdmi)
325 struct drm_connector *connector = &vc4_hdmi->connector;
326 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
329 drm_connector_init_with_ddc(dev, connector,
330 &vc4_hdmi_connector_funcs,
331 DRM_MODE_CONNECTOR_HDMIA,
333 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
336 * Some of the properties below require access to state, like bpc.
337 * Allocate some default initial connector state with our reset helper.
339 if (connector->funcs->reset)
340 connector->funcs->reset(connector);
342 /* Create and attach TV margin props to this connector. */
343 ret = drm_mode_create_tv_margin_properties(dev);
347 ret = drm_mode_create_hdmi_colorspace_property(connector);
351 drm_connector_attach_colorspace_property(connector);
352 drm_connector_attach_tv_margin_properties(connector);
353 drm_connector_attach_max_bpc_property(connector, 8, 12);
355 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
356 DRM_CONNECTOR_POLL_DISCONNECT);
358 connector->interlace_allowed = 1;
359 connector->doublescan_allowed = 0;
361 if (vc4_hdmi->variant->supports_hdr)
362 drm_connector_attach_hdr_output_metadata_property(connector);
364 drm_connector_attach_encoder(connector, encoder);
369 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
370 enum hdmi_infoframe_type type,
373 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
374 u32 packet_id = type - 0x80;
376 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
377 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
382 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
383 BIT(packet_id)), 100);
386 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
387 union hdmi_infoframe *frame)
389 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
390 u32 packet_id = frame->any.type - 0x80;
391 const struct vc4_hdmi_register *ram_packet_start =
392 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
393 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
394 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
395 ram_packet_start->reg);
396 uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
400 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
401 VC4_HDMI_RAM_PACKET_ENABLE),
402 "Packet RAM has to be on to store the packet.");
404 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
408 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
410 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
414 for (i = 0; i < len; i += 7) {
415 writel(buffer[i + 0] << 0 |
421 writel(buffer[i + 3] << 0 |
423 buffer[i + 5] << 16 |
429 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
430 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
431 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
432 BIT(packet_id)), 100);
434 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
437 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
439 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
440 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
441 struct drm_connector *connector = &vc4_hdmi->connector;
442 struct drm_connector_state *cstate = connector->state;
443 struct drm_crtc *crtc = encoder->crtc;
444 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
445 union hdmi_infoframe frame;
448 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
451 DRM_ERROR("couldn't fill AVI infoframe\n");
455 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
457 vc4_encoder->limited_rgb_range ?
458 HDMI_QUANTIZATION_RANGE_LIMITED :
459 HDMI_QUANTIZATION_RANGE_FULL);
460 drm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate);
461 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
463 vc4_hdmi_write_infoframe(encoder, &frame);
466 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
468 union hdmi_infoframe frame;
471 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
473 DRM_ERROR("couldn't fill SPD infoframe\n");
477 frame.spd.sdi = HDMI_SPD_SDI_PC;
479 vc4_hdmi_write_infoframe(encoder, &frame);
482 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
484 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
485 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
486 union hdmi_infoframe frame;
488 memcpy(&frame.audio, audio, sizeof(*audio));
489 vc4_hdmi_write_infoframe(encoder, &frame);
492 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
494 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
495 struct drm_connector *connector = &vc4_hdmi->connector;
496 struct drm_connector_state *conn_state = connector->state;
497 union hdmi_infoframe frame;
499 if (!vc4_hdmi->variant->supports_hdr)
502 if (!conn_state->hdr_output_metadata)
505 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
508 vc4_hdmi_write_infoframe(encoder, &frame);
511 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
513 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
515 vc4_hdmi_set_avi_infoframe(encoder);
516 vc4_hdmi_set_spd_infoframe(encoder);
518 * If audio was streaming, then we need to reenabled the audio
519 * infoframe here during encoder_enable.
521 if (vc4_hdmi->audio.streaming)
522 vc4_hdmi_set_audio_infoframe(encoder);
524 vc4_hdmi_set_hdr_infoframe(encoder);
527 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
528 struct drm_display_mode *mode)
530 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
531 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
532 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
534 if (!vc4_encoder->hdmi_monitor)
537 if (!display->hdmi.scdc.supported ||
538 !display->hdmi.scdc.scrambling.supported)
544 #define SCRAMBLING_POLLING_DELAY_MS 1000
546 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
548 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
549 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
551 if (!vc4_hdmi_supports_scrambling(encoder, mode))
554 if (!vc4_hdmi_mode_needs_scrambling(mode))
557 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
558 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
560 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
561 VC5_HDMI_SCRAMBLER_CTL_ENABLE);
563 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
564 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
567 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
569 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
570 struct drm_crtc *crtc = encoder->crtc;
573 * At boot, encoder->crtc will be NULL. Since we don't know the
574 * state of the scrambler and in order to avoid any
575 * inconsistency, let's disable it all the time.
577 if (crtc && !vc4_hdmi_supports_scrambling(encoder, &crtc->mode))
580 if (crtc && !vc4_hdmi_mode_needs_scrambling(&crtc->mode))
583 if (delayed_work_pending(&vc4_hdmi->scrambling_work))
584 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
586 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
587 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
589 drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
590 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
593 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
595 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
599 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
602 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
603 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
605 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
606 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
609 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
610 struct drm_atomic_state *state)
612 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
614 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
616 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
620 HDMI_WRITE(HDMI_VID_CTL,
621 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
622 vc4_hdmi_disable_scrambling(encoder);
625 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
626 struct drm_atomic_state *state)
628 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
631 HDMI_WRITE(HDMI_VID_CTL,
632 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
634 if (vc4_hdmi->variant->phy_disable)
635 vc4_hdmi->variant->phy_disable(vc4_hdmi);
637 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
638 clk_disable_unprepare(vc4_hdmi->pixel_clock);
640 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
642 DRM_ERROR("Failed to release power domain: %d\n", ret);
645 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
649 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
653 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
654 VC4_HD_CSC_CTL_ORDER);
657 /* CEA VICs other than #1 requre limited range RGB
658 * output unless overridden by an AVI infoframe.
659 * Apply a colorspace conversion to squash 0-255 down
660 * to 16-235. The matrix here is:
667 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
668 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
669 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
670 VC4_HD_CSC_CTL_MODE);
672 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
673 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
674 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
675 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
676 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
677 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
680 /* The RGB order applies even when CSC is disabled. */
681 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
684 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
688 csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
691 /* CEA VICs other than #1 requre limited range RGB
692 * output unless overridden by an AVI infoframe.
693 * Apply a colorspace conversion to squash 0-255 down
694 * to 16-235. The matrix here is:
700 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
702 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
703 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
704 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
705 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
706 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
707 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
709 /* Still use the matrix for full range, but make it unity.
710 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
712 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
713 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
714 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
715 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
716 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
717 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
720 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
723 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
724 struct drm_connector_state *state,
725 struct drm_display_mode *mode)
727 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
728 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
729 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
730 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
731 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
732 VC4_HDMI_VERTA_VSP) |
733 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
734 VC4_HDMI_VERTA_VFP) |
735 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
736 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
737 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
738 VC4_HDMI_VERTB_VBP));
739 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
740 VC4_SET_FIELD(mode->crtc_vtotal -
741 mode->crtc_vsync_end -
743 VC4_HDMI_VERTB_VBP));
745 HDMI_WRITE(HDMI_HORZA,
746 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
747 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
748 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
749 VC4_HDMI_HORZA_HAP));
751 HDMI_WRITE(HDMI_HORZB,
752 VC4_SET_FIELD((mode->htotal -
753 mode->hsync_end) * pixel_rep,
754 VC4_HDMI_HORZB_HBP) |
755 VC4_SET_FIELD((mode->hsync_end -
756 mode->hsync_start) * pixel_rep,
757 VC4_HDMI_HORZB_HSP) |
758 VC4_SET_FIELD((mode->hsync_start -
759 mode->hdisplay) * pixel_rep,
760 VC4_HDMI_HORZB_HFP));
762 HDMI_WRITE(HDMI_VERTA0, verta);
763 HDMI_WRITE(HDMI_VERTA1, verta);
765 HDMI_WRITE(HDMI_VERTB0, vertb_even);
766 HDMI_WRITE(HDMI_VERTB1, vertb);
769 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
770 struct drm_connector_state *state,
771 struct drm_display_mode *mode)
773 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
774 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
775 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
776 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
777 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
778 VC5_HDMI_VERTA_VSP) |
779 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
780 VC5_HDMI_VERTA_VFP) |
781 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
782 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
783 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
784 VC4_HDMI_VERTB_VBP));
785 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
786 VC4_SET_FIELD(mode->crtc_vtotal -
787 mode->crtc_vsync_end -
789 VC4_HDMI_VERTB_VBP));
794 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
795 HDMI_WRITE(HDMI_HORZA,
796 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
797 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
798 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
799 VC5_HDMI_HORZA_HAP) |
800 VC4_SET_FIELD((mode->hsync_start -
801 mode->hdisplay) * pixel_rep,
802 VC5_HDMI_HORZA_HFP));
804 HDMI_WRITE(HDMI_HORZB,
805 VC4_SET_FIELD((mode->htotal -
806 mode->hsync_end) * pixel_rep,
807 VC5_HDMI_HORZB_HBP) |
808 VC4_SET_FIELD((mode->hsync_end -
809 mode->hsync_start) * pixel_rep,
810 VC5_HDMI_HORZB_HSP));
812 HDMI_WRITE(HDMI_VERTA0, verta);
813 HDMI_WRITE(HDMI_VERTA1, verta);
815 HDMI_WRITE(HDMI_VERTB0, vertb_even);
816 HDMI_WRITE(HDMI_VERTB1, vertb);
818 switch (state->max_bpc) {
834 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
835 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
836 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
837 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
838 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
839 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
841 reg = HDMI_READ(HDMI_GCP_WORD_1);
842 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
843 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
844 HDMI_WRITE(HDMI_GCP_WORD_1, reg);
846 reg = HDMI_READ(HDMI_GCP_CONFIG);
847 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
848 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
849 HDMI_WRITE(HDMI_GCP_CONFIG, reg);
851 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
854 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
859 drift = HDMI_READ(HDMI_FIFO_CTL);
860 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
862 HDMI_WRITE(HDMI_FIFO_CTL,
863 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
864 HDMI_WRITE(HDMI_FIFO_CTL,
865 drift | VC4_HDMI_FIFO_CTL_RECENTER);
866 usleep_range(1000, 1100);
867 HDMI_WRITE(HDMI_FIFO_CTL,
868 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
869 HDMI_WRITE(HDMI_FIFO_CTL,
870 drift | VC4_HDMI_FIFO_CTL_RECENTER);
872 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
873 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
874 WARN_ONCE(ret, "Timeout waiting for "
875 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
878 static struct drm_connector_state *
879 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder,
880 struct drm_atomic_state *state)
882 struct drm_connector_state *conn_state;
883 struct drm_connector *connector;
886 for_each_new_connector_in_state(state, connector, conn_state, i) {
887 if (conn_state->best_encoder == encoder)
894 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
895 struct drm_atomic_state *state)
897 struct drm_connector_state *conn_state =
898 vc4_hdmi_encoder_get_connector_state(encoder, state);
899 struct vc4_hdmi_connector_state *vc4_conn_state =
900 conn_state_to_vc4_hdmi_conn_state(conn_state);
901 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
902 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
903 unsigned long pixel_rate = vc4_conn_state->pixel_rate;
904 unsigned long bvb_rate, hsm_rate;
908 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
909 * be faster than pixel clock, infinitesimally faster, tested in
910 * simulation. Otherwise, exact value is unimportant for HDMI
911 * operation." This conflicts with bcm2835's vc4 documentation, which
912 * states HSM's clock has to be at least 108% of the pixel clock.
914 * Real life tests reveal that vc4's firmware statement holds up, and
915 * users are able to use pixel clocks closer to HSM's, namely for
916 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
917 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
920 * Additionally, the AXI clock needs to be at least 25% of
921 * pixel clock, but HSM ends up being the limiting factor.
923 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
924 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
926 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
930 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
932 DRM_ERROR("Failed to retain power domain: %d\n", ret);
936 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
938 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
939 goto err_put_runtime_pm;
942 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
944 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
945 goto err_put_runtime_pm;
949 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
951 if (pixel_rate > 297000000)
952 bvb_rate = 300000000;
953 else if (pixel_rate > 148500000)
954 bvb_rate = 150000000;
958 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
960 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
961 goto err_disable_pixel_clock;
964 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
966 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
967 goto err_disable_pixel_clock;
970 if (vc4_hdmi->variant->phy_init)
971 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
973 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
974 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
975 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
976 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
978 if (vc4_hdmi->variant->set_timings)
979 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
983 err_disable_pixel_clock:
984 clk_disable_unprepare(vc4_hdmi->pixel_clock);
986 pm_runtime_put(&vc4_hdmi->pdev->dev);
991 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
992 struct drm_atomic_state *state)
994 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
995 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
996 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
998 if (vc4_encoder->hdmi_monitor &&
999 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
1000 if (vc4_hdmi->variant->csc_setup)
1001 vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
1003 vc4_encoder->limited_rgb_range = true;
1005 if (vc4_hdmi->variant->csc_setup)
1006 vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
1008 vc4_encoder->limited_rgb_range = false;
1011 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1014 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1015 struct drm_atomic_state *state)
1017 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1018 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1019 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1020 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1021 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1024 HDMI_WRITE(HDMI_VID_CTL,
1025 VC4_HD_VID_CTL_ENABLE |
1026 VC4_HD_VID_CTL_CLRRGB |
1027 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1028 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1029 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1030 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1032 HDMI_WRITE(HDMI_VID_CTL,
1033 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1035 if (vc4_encoder->hdmi_monitor) {
1036 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1037 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1038 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1040 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1041 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1042 WARN_ONCE(ret, "Timeout waiting for "
1043 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1045 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1046 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1047 ~(VC4_HDMI_RAM_PACKET_ENABLE));
1048 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1049 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1050 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1052 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1053 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1054 WARN_ONCE(ret, "Timeout waiting for "
1055 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1058 if (vc4_encoder->hdmi_monitor) {
1059 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1060 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1061 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1062 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1063 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
1065 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1066 VC4_HDMI_RAM_PACKET_ENABLE);
1068 vc4_hdmi_set_infoframes(encoder);
1071 vc4_hdmi_recenter_fifo(vc4_hdmi);
1072 vc4_hdmi_enable_scrambling(encoder);
1075 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
1079 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
1080 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
1082 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1083 struct drm_crtc_state *crtc_state,
1084 struct drm_connector_state *conn_state)
1086 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1087 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1088 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1089 unsigned long long pixel_rate = mode->clock * 1000;
1090 unsigned long long tmds_rate;
1092 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1093 !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1094 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1095 (mode->hsync_end % 2) || (mode->htotal % 2)))
1099 * The 1440p@60 pixel rate is in the same range than the first
1100 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1101 * bandwidth). Slightly lower the frequency to bring it out of
1104 tmds_rate = pixel_rate * 10;
1105 if (vc4_hdmi->disable_wifi_frequencies &&
1106 (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1107 tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1108 mode->clock = 238560;
1109 pixel_rate = mode->clock * 1000;
1112 if (conn_state->max_bpc == 12) {
1113 pixel_rate = pixel_rate * 150;
1114 do_div(pixel_rate, 100);
1115 } else if (conn_state->max_bpc == 10) {
1116 pixel_rate = pixel_rate * 125;
1117 do_div(pixel_rate, 100);
1120 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1121 pixel_rate = pixel_rate * 2;
1123 if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
1126 if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK))
1129 vc4_state->pixel_rate = pixel_rate;
1134 static enum drm_mode_status
1135 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1136 const struct drm_display_mode *mode)
1138 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1140 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1141 !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1142 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1143 (mode->hsync_end % 2) || (mode->htotal % 2)))
1144 return MODE_H_ILLEGAL;
1146 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
1147 return MODE_CLOCK_HIGH;
1149 if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode))
1150 return MODE_CLOCK_HIGH;
1155 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1156 .atomic_check = vc4_hdmi_encoder_atomic_check,
1157 .mode_valid = vc4_hdmi_encoder_mode_valid,
1158 .disable = vc4_hdmi_encoder_disable,
1159 .enable = vc4_hdmi_encoder_enable,
1162 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1165 u32 channel_map = 0;
1167 for (i = 0; i < 8; i++) {
1168 if (channel_mask & BIT(i))
1169 channel_map |= i << (3 * i);
1174 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1177 u32 channel_map = 0;
1179 for (i = 0; i < 8; i++) {
1180 if (channel_mask & BIT(i))
1181 channel_map |= i << (4 * i);
1186 /* HDMI audio codec callbacks */
1187 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1188 unsigned int samplerate)
1190 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1193 rational_best_approximation(hsm_clock, samplerate,
1194 VC4_HD_MAI_SMP_N_MASK >>
1195 VC4_HD_MAI_SMP_N_SHIFT,
1196 (VC4_HD_MAI_SMP_M_MASK >>
1197 VC4_HD_MAI_SMP_M_SHIFT) + 1,
1200 HDMI_WRITE(HDMI_MAI_SMP,
1201 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1202 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1205 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1207 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1208 struct drm_crtc *crtc = encoder->crtc;
1209 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1213 n = 128 * samplerate / 1000;
1214 tmp = (u64)(mode->clock * 1000) * n;
1215 do_div(tmp, 128 * samplerate);
1218 HDMI_WRITE(HDMI_CRP_CFG,
1219 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1220 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1223 * We could get slightly more accurate clocks in some cases by
1224 * providing a CTS_1 value. The two CTS values are alternated
1225 * between based on the period fields
1227 HDMI_WRITE(HDMI_CTS_0, cts);
1228 HDMI_WRITE(HDMI_CTS_1, cts);
1231 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1233 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1235 return snd_soc_card_get_drvdata(card);
1238 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1240 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1241 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1244 * If the HDMI encoder hasn't probed, or the encoder is
1245 * currently in DVI mode, treat the codec dai as missing.
1247 if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1248 VC4_HDMI_RAM_PACKET_ENABLE))
1251 vc4_hdmi->audio.streaming = true;
1253 HDMI_WRITE(HDMI_MAI_CTL,
1254 VC4_HD_MAI_CTL_RESET |
1255 VC4_HD_MAI_CTL_FLUSH |
1256 VC4_HD_MAI_CTL_DLATE |
1257 VC4_HD_MAI_CTL_ERRORE |
1258 VC4_HD_MAI_CTL_ERRORF);
1260 if (vc4_hdmi->variant->phy_rng_enable)
1261 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1266 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1268 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1269 struct device *dev = &vc4_hdmi->pdev->dev;
1272 vc4_hdmi->audio.streaming = false;
1273 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1275 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1277 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1278 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1279 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1282 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1284 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1286 HDMI_WRITE(HDMI_MAI_CTL,
1287 VC4_HD_MAI_CTL_DLATE |
1288 VC4_HD_MAI_CTL_ERRORE |
1289 VC4_HD_MAI_CTL_ERRORF);
1291 if (vc4_hdmi->variant->phy_rng_disable)
1292 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1294 vc4_hdmi->audio.streaming = false;
1295 vc4_hdmi_audio_reset(vc4_hdmi);
1298 static int sample_rate_to_mai_fmt(int samplerate)
1300 switch (samplerate) {
1302 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1304 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1306 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1308 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1310 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1312 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1314 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1316 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1318 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1320 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
1322 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
1324 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
1326 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
1328 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
1330 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
1332 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
1336 /* HDMI audio codec callbacks */
1337 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
1338 struct hdmi_codec_daifmt *daifmt,
1339 struct hdmi_codec_params *params)
1341 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1342 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1343 unsigned int sample_rate = params->sample_rate;
1344 unsigned int channels = params->channels;
1345 u32 audio_packet_config, channel_mask;
1347 u32 mai_audio_format;
1348 u32 mai_sample_rate;
1350 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1351 sample_rate, params->sample_width, channels);
1353 HDMI_WRITE(HDMI_MAI_CTL,
1354 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
1355 VC4_HD_MAI_CTL_WHOLSMP |
1356 VC4_HD_MAI_CTL_CHALIGN |
1357 VC4_HD_MAI_CTL_ENABLE);
1359 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
1361 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
1362 if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
1363 params->channels == 8)
1364 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
1366 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
1367 HDMI_WRITE(HDMI_MAI_FMT,
1368 VC4_SET_FIELD(mai_sample_rate,
1369 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
1370 VC4_SET_FIELD(mai_audio_format,
1371 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
1373 /* The B frame identifier should match the value used by alsa-lib (8) */
1374 audio_packet_config =
1375 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1376 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1377 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1379 channel_mask = GENMASK(channels - 1, 0);
1380 audio_packet_config |= VC4_SET_FIELD(channel_mask,
1381 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1383 /* Set the MAI threshold */
1384 HDMI_WRITE(HDMI_MAI_THR,
1385 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1386 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1387 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1388 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1390 HDMI_WRITE(HDMI_MAI_CONFIG,
1391 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1392 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
1393 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1395 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1396 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1397 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1398 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
1400 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea));
1401 vc4_hdmi_set_audio_infoframe(encoder);
1406 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1407 .name = "vc4-hdmi-cpu-dai-component",
1410 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1412 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1414 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1419 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1420 .name = "vc4-hdmi-cpu-dai",
1421 .probe = vc4_hdmi_audio_cpu_dai_probe,
1423 .stream_name = "Playback",
1426 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1427 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1428 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1429 SNDRV_PCM_RATE_192000,
1430 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1434 static const struct snd_dmaengine_pcm_config pcm_conf = {
1435 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1436 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1439 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
1440 uint8_t *buf, size_t len)
1442 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1443 struct drm_connector *connector = &vc4_hdmi->connector;
1445 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1450 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
1451 .get_eld = vc4_hdmi_audio_get_eld,
1452 .prepare = vc4_hdmi_audio_prepare,
1453 .audio_shutdown = vc4_hdmi_audio_shutdown,
1454 .audio_startup = vc4_hdmi_audio_startup,
1457 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
1458 .ops = &vc4_hdmi_codec_ops,
1459 .max_i2s_channels = 8,
1463 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1465 const struct vc4_hdmi_register *mai_data =
1466 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1467 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1468 struct snd_soc_card *card = &vc4_hdmi->audio.card;
1469 struct device *dev = &vc4_hdmi->pdev->dev;
1470 struct platform_device *codec_pdev;
1475 if (!of_find_property(dev->of_node, "dmas", NULL)) {
1477 "'dmas' DT property is missing, no HDMI audio\n");
1481 if (mai_data->reg != VC4_HD) {
1482 WARN_ONCE(true, "MAI isn't in the HD block\n");
1487 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1488 * the bus address specified in the DT, because the physical address
1489 * (the one returned by platform_get_resource()) is not appropriate
1490 * for DMA transfers.
1491 * This VC/MMU should probably be exposed to avoid this kind of hacks.
1493 index = of_property_match_string(dev->of_node, "reg-names", "hd");
1494 /* Before BCM2711, we don't have a named register range */
1498 addr = of_get_address(dev->of_node, index, NULL, NULL);
1500 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1501 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1502 vc4_hdmi->audio.dma_data.maxburst = 2;
1504 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1506 dev_err(dev, "Could not register PCM component: %d\n", ret);
1510 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1511 &vc4_hdmi_audio_cpu_dai_drv, 1);
1513 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1517 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1518 PLATFORM_DEVID_AUTO,
1519 &vc4_hdmi_codec_pdata,
1520 sizeof(vc4_hdmi_codec_pdata));
1521 if (IS_ERR(codec_pdev)) {
1522 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
1523 return PTR_ERR(codec_pdev);
1526 dai_link->cpus = &vc4_hdmi->audio.cpu;
1527 dai_link->codecs = &vc4_hdmi->audio.codec;
1528 dai_link->platforms = &vc4_hdmi->audio.platform;
1530 dai_link->num_cpus = 1;
1531 dai_link->num_codecs = 1;
1532 dai_link->num_platforms = 1;
1534 dai_link->name = "MAI";
1535 dai_link->stream_name = "MAI PCM";
1536 dai_link->codecs->dai_name = "i2s-hifi";
1537 dai_link->cpus->dai_name = dev_name(dev);
1538 dai_link->codecs->name = dev_name(&codec_pdev->dev);
1539 dai_link->platforms->name = dev_name(dev);
1541 card->dai_link = dai_link;
1542 card->num_links = 1;
1543 card->name = vc4_hdmi->variant->card_name;
1544 card->driver_name = "vc4-hdmi";
1546 card->owner = THIS_MODULE;
1549 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1550 * stores a pointer to the snd card object in dev->driver_data. This
1551 * means we cannot use it for something else. The hdmi back-pointer is
1552 * now stored in card->drvdata and should be retrieved with
1553 * snd_soc_card_get_drvdata() if needed.
1555 snd_soc_card_set_drvdata(card, vc4_hdmi);
1556 ret = devm_snd_soc_register_card(dev, card);
1558 dev_err_probe(dev, ret, "Could not register sound card\n");
1564 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
1566 struct vc4_hdmi *vc4_hdmi = priv;
1567 struct drm_device *dev = vc4_hdmi->connector.dev;
1569 if (dev && dev->registered)
1570 drm_kms_helper_hotplug_event(dev);
1575 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
1577 struct drm_connector *connector = &vc4_hdmi->connector;
1578 struct platform_device *pdev = vc4_hdmi->pdev;
1581 if (vc4_hdmi->variant->external_irq_controller) {
1582 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
1583 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
1585 ret = request_threaded_irq(hpd_con,
1587 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1588 "vc4 hdmi hpd connected", vc4_hdmi);
1592 ret = request_threaded_irq(hpd_rm,
1594 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1595 "vc4 hdmi hpd disconnected", vc4_hdmi);
1597 free_irq(hpd_con, vc4_hdmi);
1601 connector->polled = DRM_CONNECTOR_POLL_HPD;
1607 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi)
1609 struct platform_device *pdev = vc4_hdmi->pdev;
1611 if (vc4_hdmi->variant->external_irq_controller) {
1612 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi);
1613 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi);
1617 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1618 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1620 struct vc4_hdmi *vc4_hdmi = priv;
1622 if (vc4_hdmi->cec_rx_msg.len)
1623 cec_received_msg(vc4_hdmi->cec_adap,
1624 &vc4_hdmi->cec_rx_msg);
1629 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1631 struct vc4_hdmi *vc4_hdmi = priv;
1633 if (vc4_hdmi->cec_tx_ok) {
1634 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1638 * This CEC implementation makes 1 retry, so if we
1639 * get a NACK, then that means it made 2 attempts.
1641 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1647 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1649 struct vc4_hdmi *vc4_hdmi = priv;
1652 if (vc4_hdmi->cec_irq_was_rx)
1653 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1655 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1660 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1662 struct drm_device *dev = vc4_hdmi->connector.dev;
1663 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1666 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1667 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1669 if (msg->len > 16) {
1670 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1674 for (i = 0; i < msg->len; i += 4) {
1675 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1677 msg->msg[i] = val & 0xff;
1678 msg->msg[i + 1] = (val >> 8) & 0xff;
1679 msg->msg[i + 2] = (val >> 16) & 0xff;
1680 msg->msg[i + 3] = (val >> 24) & 0xff;
1684 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1686 struct vc4_hdmi *vc4_hdmi = priv;
1689 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1690 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1691 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1692 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1694 return IRQ_WAKE_THREAD;
1697 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1699 struct vc4_hdmi *vc4_hdmi = priv;
1702 vc4_hdmi->cec_rx_msg.len = 0;
1703 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1704 vc4_cec_read_msg(vc4_hdmi, cntrl1);
1705 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1706 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1707 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1709 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1711 return IRQ_WAKE_THREAD;
1714 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1716 struct vc4_hdmi *vc4_hdmi = priv;
1717 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1721 if (!(stat & VC4_HDMI_CPU_CEC))
1724 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1725 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1726 if (vc4_hdmi->cec_irq_was_rx)
1727 ret = vc4_cec_irq_handler_rx_bare(irq, priv);
1729 ret = vc4_cec_irq_handler_tx_bare(irq, priv);
1731 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1735 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1737 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1738 /* clock period in microseconds */
1739 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1740 u32 val = HDMI_READ(HDMI_CEC_CNTRL_5);
1742 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1743 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1744 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1745 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1746 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1749 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1750 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1751 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1752 HDMI_WRITE(HDMI_CEC_CNTRL_2,
1753 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1754 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1755 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1756 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1757 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1758 HDMI_WRITE(HDMI_CEC_CNTRL_3,
1759 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1760 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1761 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1762 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1763 HDMI_WRITE(HDMI_CEC_CNTRL_4,
1764 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1765 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1766 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1767 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1769 if (!vc4_hdmi->variant->external_irq_controller)
1770 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1772 if (!vc4_hdmi->variant->external_irq_controller)
1773 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1774 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1775 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1780 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1782 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1784 HDMI_WRITE(HDMI_CEC_CNTRL_1,
1785 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1786 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1790 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1791 u32 signal_free_time, struct cec_msg *msg)
1793 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1794 struct drm_device *dev = vc4_hdmi->connector.dev;
1798 if (msg->len > 16) {
1799 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
1803 for (i = 0; i < msg->len; i += 4)
1804 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
1806 (msg->msg[i + 1] << 8) |
1807 (msg->msg[i + 2] << 16) |
1808 (msg->msg[i + 3] << 24));
1810 val = HDMI_READ(HDMI_CEC_CNTRL_1);
1811 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1812 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1813 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1814 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1815 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1817 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1821 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1822 .adap_enable = vc4_hdmi_cec_adap_enable,
1823 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1824 .adap_transmit = vc4_hdmi_cec_adap_transmit,
1827 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1829 struct cec_connector_info conn_info;
1830 struct platform_device *pdev = vc4_hdmi->pdev;
1831 struct device *dev = &pdev->dev;
1835 if (!of_find_property(dev->of_node, "interrupts", NULL)) {
1836 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
1840 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1843 CEC_CAP_CONNECTOR_INFO, 1);
1844 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
1848 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
1849 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
1851 value = HDMI_READ(HDMI_CEC_CNTRL_1);
1852 /* Set the logical address to Unregistered */
1853 value |= VC4_HDMI_CEC_ADDR_MASK;
1854 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
1856 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1858 if (vc4_hdmi->variant->external_irq_controller) {
1859 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"),
1860 vc4_cec_irq_handler_rx_bare,
1861 vc4_cec_irq_handler_rx_thread, 0,
1862 "vc4 hdmi cec rx", vc4_hdmi);
1864 goto err_delete_cec_adap;
1866 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"),
1867 vc4_cec_irq_handler_tx_bare,
1868 vc4_cec_irq_handler_tx_thread, 0,
1869 "vc4 hdmi cec tx", vc4_hdmi);
1871 goto err_remove_cec_rx_handler;
1873 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
1875 ret = request_threaded_irq(platform_get_irq(pdev, 0),
1876 vc4_cec_irq_handler,
1877 vc4_cec_irq_handler_thread, 0,
1878 "vc4 hdmi cec", vc4_hdmi);
1880 goto err_delete_cec_adap;
1883 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
1885 goto err_remove_handlers;
1889 err_remove_handlers:
1890 if (vc4_hdmi->variant->external_irq_controller)
1891 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
1893 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
1895 err_remove_cec_rx_handler:
1896 if (vc4_hdmi->variant->external_irq_controller)
1897 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
1899 err_delete_cec_adap:
1900 cec_delete_adapter(vc4_hdmi->cec_adap);
1905 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
1907 struct platform_device *pdev = vc4_hdmi->pdev;
1909 if (vc4_hdmi->variant->external_irq_controller) {
1910 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
1911 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
1913 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
1916 cec_unregister_adapter(vc4_hdmi->cec_adap);
1919 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1924 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
1928 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
1929 struct debugfs_regset32 *regset,
1930 enum vc4_hdmi_regs reg)
1932 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1933 struct debugfs_reg32 *regs, *new_regs;
1934 unsigned int count = 0;
1937 regs = kcalloc(variant->num_registers, sizeof(*regs),
1942 for (i = 0; i < variant->num_registers; i++) {
1943 const struct vc4_hdmi_register *field = &variant->registers[i];
1945 if (field->reg != reg)
1948 regs[count].name = field->name;
1949 regs[count].offset = field->offset;
1953 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
1957 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
1958 regset->regs = new_regs;
1959 regset->nregs = count;
1964 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1966 struct platform_device *pdev = vc4_hdmi->pdev;
1967 struct device *dev = &pdev->dev;
1970 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1971 if (IS_ERR(vc4_hdmi->hdmicore_regs))
1972 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1974 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1975 if (IS_ERR(vc4_hdmi->hd_regs))
1976 return PTR_ERR(vc4_hdmi->hd_regs);
1978 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
1982 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
1986 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1987 if (IS_ERR(vc4_hdmi->pixel_clock)) {
1988 ret = PTR_ERR(vc4_hdmi->pixel_clock);
1989 if (ret != -EPROBE_DEFER)
1990 DRM_ERROR("Failed to get pixel clock\n");
1994 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1995 if (IS_ERR(vc4_hdmi->hsm_clock)) {
1996 DRM_ERROR("Failed to get HDMI state machine clock\n");
1997 return PTR_ERR(vc4_hdmi->hsm_clock);
1999 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2000 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2005 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2007 struct platform_device *pdev = vc4_hdmi->pdev;
2008 struct device *dev = &pdev->dev;
2009 struct resource *res;
2011 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2015 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2016 resource_size(res));
2017 if (!vc4_hdmi->hdmicore_regs)
2020 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2024 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2025 if (!vc4_hdmi->hd_regs)
2028 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2032 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2033 if (!vc4_hdmi->cec_regs)
2036 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2040 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2041 if (!vc4_hdmi->csc_regs)
2044 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2048 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2049 if (!vc4_hdmi->dvp_regs)
2052 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2056 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2057 if (!vc4_hdmi->phy_regs)
2060 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2064 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2065 if (!vc4_hdmi->ram_regs)
2068 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2072 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2073 if (!vc4_hdmi->rm_regs)
2076 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2077 if (IS_ERR(vc4_hdmi->hsm_clock)) {
2078 DRM_ERROR("Failed to get HDMI state machine clock\n");
2079 return PTR_ERR(vc4_hdmi->hsm_clock);
2082 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2083 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2084 DRM_ERROR("Failed to get pixel bvb clock\n");
2085 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2088 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2089 if (IS_ERR(vc4_hdmi->audio_clock)) {
2090 DRM_ERROR("Failed to get audio clock\n");
2091 return PTR_ERR(vc4_hdmi->audio_clock);
2094 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2095 if (IS_ERR(vc4_hdmi->cec_clock)) {
2096 DRM_ERROR("Failed to get CEC clock\n");
2097 return PTR_ERR(vc4_hdmi->cec_clock);
2100 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2101 if (IS_ERR(vc4_hdmi->reset)) {
2102 DRM_ERROR("Failed to get HDMI reset line\n");
2103 return PTR_ERR(vc4_hdmi->reset);
2109 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev)
2111 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2113 clk_disable_unprepare(vc4_hdmi->hsm_clock);
2118 static int vc4_hdmi_runtime_resume(struct device *dev)
2120 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2123 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
2130 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2132 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2133 struct platform_device *pdev = to_platform_device(dev);
2134 struct drm_device *drm = dev_get_drvdata(master);
2135 struct vc4_hdmi *vc4_hdmi;
2136 struct drm_encoder *encoder;
2137 struct device_node *ddc_node;
2140 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2143 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2145 dev_set_drvdata(dev, vc4_hdmi);
2146 encoder = &vc4_hdmi->encoder.base.base;
2147 vc4_hdmi->encoder.base.type = variant->encoder_type;
2148 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2149 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2150 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2151 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2152 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2153 vc4_hdmi->pdev = pdev;
2154 vc4_hdmi->variant = variant;
2156 ret = variant->init_resources(vc4_hdmi);
2160 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2162 DRM_ERROR("Failed to find ddc node in device tree\n");
2166 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2167 of_node_put(ddc_node);
2168 if (!vc4_hdmi->ddc) {
2169 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2170 return -EPROBE_DEFER;
2173 /* Only use the GPIO HPD pin if present in the DT, otherwise
2174 * we'll use the HDMI core's register.
2176 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2177 if (IS_ERR(vc4_hdmi->hpd_gpio)) {
2178 ret = PTR_ERR(vc4_hdmi->hpd_gpio);
2182 vc4_hdmi->disable_wifi_frequencies =
2183 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2185 if (variant->max_pixel_clock == 600000000) {
2186 struct vc4_dev *vc4 = to_vc4_dev(drm);
2187 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
2189 if (max_rate < 550000000)
2190 vc4_hdmi->disable_4kp60 = true;
2194 * If we boot without any cable connected to the HDMI connector,
2195 * the firmware will skip the HSM initialization and leave it
2196 * with a rate of 0, resulting in a bus lockup when we're
2197 * accessing the registers even if it's enabled.
2199 * Let's put a sensible default at runtime_resume so that we
2200 * don't end up in this situation.
2202 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
2207 * We need to have the device powered up at this point to call
2208 * our reset hook and for the CEC init.
2210 ret = vc4_hdmi_runtime_resume(dev);
2214 pm_runtime_get_noresume(dev);
2215 pm_runtime_set_active(dev);
2216 pm_runtime_enable(dev);
2218 if (vc4_hdmi->variant->reset)
2219 vc4_hdmi->variant->reset(vc4_hdmi);
2221 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
2222 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
2223 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
2224 clk_prepare_enable(vc4_hdmi->pixel_clock);
2225 clk_prepare_enable(vc4_hdmi->hsm_clock);
2226 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
2229 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2230 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2232 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2234 goto err_destroy_encoder;
2236 ret = vc4_hdmi_hotplug_init(vc4_hdmi);
2238 goto err_destroy_conn;
2240 ret = vc4_hdmi_cec_init(vc4_hdmi);
2242 goto err_free_hotplug;
2244 ret = vc4_hdmi_audio_init(vc4_hdmi);
2248 vc4_debugfs_add_file(drm, variant->debugfs_name,
2249 vc4_hdmi_debugfs_regs,
2252 pm_runtime_put_sync(dev);
2257 vc4_hdmi_cec_exit(vc4_hdmi);
2259 vc4_hdmi_hotplug_exit(vc4_hdmi);
2261 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2262 err_destroy_encoder:
2263 drm_encoder_cleanup(encoder);
2264 pm_runtime_put_sync(dev);
2265 pm_runtime_disable(dev);
2267 put_device(&vc4_hdmi->ddc->dev);
2272 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2275 struct vc4_hdmi *vc4_hdmi;
2278 * ASoC makes it a bit hard to retrieve a pointer to the
2279 * vc4_hdmi structure. Registering the card will overwrite our
2280 * device drvdata with a pointer to the snd_soc_card structure,
2281 * which can then be used to retrieve whatever drvdata we want
2284 * However, that doesn't fly in the case where we wouldn't
2285 * register an ASoC card (because of an old DT that is missing
2286 * the dmas properties for example), then the card isn't
2287 * registered and the device drvdata wouldn't be set.
2289 * We can deal with both cases by making sure a snd_soc_card
2290 * pointer and a vc4_hdmi structure are pointing to the same
2291 * memory address, so we can treat them indistinctly without any
2294 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2295 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2296 vc4_hdmi = dev_get_drvdata(dev);
2298 kfree(vc4_hdmi->hdmi_regset.regs);
2299 kfree(vc4_hdmi->hd_regset.regs);
2301 vc4_hdmi_cec_exit(vc4_hdmi);
2302 vc4_hdmi_hotplug_exit(vc4_hdmi);
2303 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2304 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2306 pm_runtime_disable(dev);
2308 put_device(&vc4_hdmi->ddc->dev);
2311 static const struct component_ops vc4_hdmi_ops = {
2312 .bind = vc4_hdmi_bind,
2313 .unbind = vc4_hdmi_unbind,
2316 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2318 return component_add(&pdev->dev, &vc4_hdmi_ops);
2321 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2323 component_del(&pdev->dev, &vc4_hdmi_ops);
2327 static const struct vc4_hdmi_variant bcm2835_variant = {
2328 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
2329 .debugfs_name = "hdmi_regs",
2330 .card_name = "vc4-hdmi",
2331 .max_pixel_clock = 162000000,
2332 .registers = vc4_hdmi_fields,
2333 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
2335 .init_resources = vc4_hdmi_init_resources,
2336 .csc_setup = vc4_hdmi_csc_setup,
2337 .reset = vc4_hdmi_reset,
2338 .set_timings = vc4_hdmi_set_timings,
2339 .phy_init = vc4_hdmi_phy_init,
2340 .phy_disable = vc4_hdmi_phy_disable,
2341 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
2342 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
2343 .channel_map = vc4_hdmi_channel_map,
2344 .supports_hdr = false,
2347 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2348 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
2349 .debugfs_name = "hdmi0_regs",
2350 .card_name = "vc4-hdmi-0",
2351 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
2352 .registers = vc5_hdmi_hdmi0_fields,
2353 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2354 .phy_lane_mapping = {
2360 .unsupported_odd_h_timings = true,
2361 .external_irq_controller = true,
2363 .init_resources = vc5_hdmi_init_resources,
2364 .csc_setup = vc5_hdmi_csc_setup,
2365 .reset = vc5_hdmi_reset,
2366 .set_timings = vc5_hdmi_set_timings,
2367 .phy_init = vc5_hdmi_phy_init,
2368 .phy_disable = vc5_hdmi_phy_disable,
2369 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
2370 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
2371 .channel_map = vc5_hdmi_channel_map,
2372 .supports_hdr = true,
2375 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2376 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
2377 .debugfs_name = "hdmi1_regs",
2378 .card_name = "vc4-hdmi-1",
2379 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
2380 .registers = vc5_hdmi_hdmi1_fields,
2381 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2382 .phy_lane_mapping = {
2388 .unsupported_odd_h_timings = true,
2389 .external_irq_controller = true,
2391 .init_resources = vc5_hdmi_init_resources,
2392 .csc_setup = vc5_hdmi_csc_setup,
2393 .reset = vc5_hdmi_reset,
2394 .set_timings = vc5_hdmi_set_timings,
2395 .phy_init = vc5_hdmi_phy_init,
2396 .phy_disable = vc5_hdmi_phy_disable,
2397 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
2398 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
2399 .channel_map = vc5_hdmi_channel_map,
2400 .supports_hdr = true,
2403 static const struct of_device_id vc4_hdmi_dt_match[] = {
2404 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2405 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2406 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2410 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
2411 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
2412 vc4_hdmi_runtime_resume,
2416 struct platform_driver vc4_hdmi_driver = {
2417 .probe = vc4_hdmi_dev_probe,
2418 .remove = vc4_hdmi_dev_remove,
2421 .of_match_table = vc4_hdmi_dt_match,
2422 .pm = &vc4_hdmi_pm_ops,