1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
10 * DOC: VC4 Falcon HDMI module
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
34 #include <drm/display/drm_hdmi_helper.h>
35 #include <drm/display/drm_scdc_helper.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_probe_helper.h>
38 #include <drm/drm_simple_kms_helper.h>
39 #include <linux/clk.h>
40 #include <linux/component.h>
41 #include <linux/gpio/consumer.h>
42 #include <linux/i2c.h>
43 #include <linux/of_address.h>
44 #include <linux/of_gpio.h>
45 #include <linux/of_platform.h>
46 #include <linux/pm_runtime.h>
47 #include <linux/rational.h>
48 #include <linux/reset.h>
49 #include <sound/dmaengine_pcm.h>
50 #include <sound/hdmi-codec.h>
51 #include <sound/pcm_drm_eld.h>
52 #include <sound/pcm_params.h>
53 #include <sound/soc.h>
54 #include "media/cec.h"
57 #include "vc4_hdmi_regs.h"
60 #define VC5_HDMI_HORZA_HFP_SHIFT 16
61 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
62 #define VC5_HDMI_HORZA_VPOS BIT(15)
63 #define VC5_HDMI_HORZA_HPOS BIT(14)
64 #define VC5_HDMI_HORZA_HAP_SHIFT 0
65 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
67 #define VC5_HDMI_HORZB_HBP_SHIFT 16
68 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
69 #define VC5_HDMI_HORZB_HSP_SHIFT 0
70 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
72 #define VC5_HDMI_VERTA_VSP_SHIFT 24
73 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
74 #define VC5_HDMI_VERTA_VFP_SHIFT 16
75 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
76 #define VC5_HDMI_VERTA_VAL_SHIFT 0
77 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
79 #define VC5_HDMI_VERTB_VSPO_SHIFT 16
80 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
82 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
83 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
84 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
85 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
87 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
89 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
90 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0
93 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)
95 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31)
97 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
98 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
100 # define VC4_HD_M_SW_RST BIT(2)
101 # define VC4_HD_M_ENABLE BIT(0)
103 #define HSM_MIN_CLOCK_FREQ 120000000
104 #define CEC_CLOCK_FREQ 40000
106 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
108 static const char * const output_format_str[] = {
109 [VC4_HDMI_OUTPUT_RGB] = "RGB",
110 [VC4_HDMI_OUTPUT_YUV420] = "YUV 4:2:0",
111 [VC4_HDMI_OUTPUT_YUV422] = "YUV 4:2:2",
112 [VC4_HDMI_OUTPUT_YUV444] = "YUV 4:4:4",
115 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt)
117 if (fmt >= ARRAY_SIZE(output_format_str))
120 return output_format_str[fmt];
123 static unsigned long long
124 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
125 unsigned int bpc, enum vc4_hdmi_output_format fmt);
127 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
129 enum vc4_hdmi_output_format fmt)
131 unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
133 return clock > HDMI_14_MAX_TMDS_CLK;
136 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi,
137 const struct drm_display_mode *mode)
139 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
141 return !display->is_hdmi ||
142 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
145 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
147 struct drm_info_node *node = (struct drm_info_node *)m->private;
148 struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
149 struct drm_printer p = drm_seq_file_printer(m);
151 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
152 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
153 drm_print_regset32(&p, &vc4_hdmi->cec_regset);
154 drm_print_regset32(&p, &vc4_hdmi->csc_regset);
155 drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
156 drm_print_regset32(&p, &vc4_hdmi->phy_regset);
157 drm_print_regset32(&p, &vc4_hdmi->ram_regset);
158 drm_print_regset32(&p, &vc4_hdmi->rm_regset);
163 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
167 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
169 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
171 HDMI_WRITE(HDMI_M_CTL, 0);
173 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
175 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
176 VC4_HDMI_SW_RESET_HDMI |
177 VC4_HDMI_SW_RESET_FORMAT_DETECT);
179 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
181 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
184 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
188 reset_control_reset(vc4_hdmi->reset);
190 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
192 HDMI_WRITE(HDMI_DVP_CTL, 0);
194 HDMI_WRITE(HDMI_CLOCK_STOP,
195 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
197 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
200 #ifdef CONFIG_DRM_VC4_HDMI_CEC
201 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
203 unsigned long cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
208 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
210 value = HDMI_READ(HDMI_CEC_CNTRL_1);
211 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
214 * Set the clock divider: the hsm_clock rate and this divider
215 * setting will give a 40 kHz CEC clock.
217 clk_cnt = cec_rate / CEC_CLOCK_FREQ;
218 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
219 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
221 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
224 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
227 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder);
229 static enum drm_connector_status
230 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
232 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
233 bool connected = false;
235 mutex_lock(&vc4_hdmi->mutex);
237 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
239 if (vc4_hdmi->hpd_gpio) {
240 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
243 if (vc4_hdmi->variant->hp_detect &&
244 vc4_hdmi->variant->hp_detect(vc4_hdmi))
249 if (connector->status != connector_status_connected) {
250 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
253 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
258 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base);
259 pm_runtime_put(&vc4_hdmi->pdev->dev);
260 mutex_unlock(&vc4_hdmi->mutex);
261 return connector_status_connected;
264 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
265 pm_runtime_put(&vc4_hdmi->pdev->dev);
266 mutex_unlock(&vc4_hdmi->mutex);
267 return connector_status_disconnected;
270 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
272 drm_connector_unregister(connector);
273 drm_connector_cleanup(connector);
276 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
278 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
282 mutex_lock(&vc4_hdmi->mutex);
284 edid = drm_get_edid(connector, vc4_hdmi->ddc);
285 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
291 drm_connector_update_edid_property(connector, edid);
292 ret = drm_add_edid_modes(connector, edid);
295 if (vc4_hdmi->disable_4kp60) {
296 struct drm_device *drm = connector->dev;
297 struct drm_display_mode *mode;
299 list_for_each_entry(mode, &connector->probed_modes, head) {
300 if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) {
301 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
302 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
308 mutex_unlock(&vc4_hdmi->mutex);
313 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
314 struct drm_atomic_state *state)
316 struct drm_connector_state *old_state =
317 drm_atomic_get_old_connector_state(state, connector);
318 struct drm_connector_state *new_state =
319 drm_atomic_get_new_connector_state(state, connector);
320 struct drm_crtc *crtc = new_state->crtc;
325 if (old_state->colorspace != new_state->colorspace ||
326 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
327 struct drm_crtc_state *crtc_state;
329 crtc_state = drm_atomic_get_crtc_state(state, crtc);
330 if (IS_ERR(crtc_state))
331 return PTR_ERR(crtc_state);
333 crtc_state->mode_changed = true;
339 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
341 struct vc4_hdmi_connector_state *old_state =
342 conn_state_to_vc4_hdmi_conn_state(connector->state);
343 struct vc4_hdmi_connector_state *new_state =
344 kzalloc(sizeof(*new_state), GFP_KERNEL);
346 if (connector->state)
347 __drm_atomic_helper_connector_destroy_state(connector->state);
350 __drm_atomic_helper_connector_reset(connector, &new_state->base);
355 new_state->base.max_bpc = 8;
356 new_state->base.max_requested_bpc = 8;
357 new_state->output_format = VC4_HDMI_OUTPUT_RGB;
358 drm_atomic_helper_connector_tv_reset(connector);
361 static struct drm_connector_state *
362 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
364 struct drm_connector_state *conn_state = connector->state;
365 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
366 struct vc4_hdmi_connector_state *new_state;
368 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
372 new_state->tmds_char_rate = vc4_state->tmds_char_rate;
373 new_state->output_bpc = vc4_state->output_bpc;
374 new_state->output_format = vc4_state->output_format;
375 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
377 return &new_state->base;
380 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
381 .detect = vc4_hdmi_connector_detect,
382 .fill_modes = drm_helper_probe_single_connector_modes,
383 .destroy = vc4_hdmi_connector_destroy,
384 .reset = vc4_hdmi_connector_reset,
385 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
386 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
389 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
390 .get_modes = vc4_hdmi_connector_get_modes,
391 .atomic_check = vc4_hdmi_connector_atomic_check,
394 static int vc4_hdmi_connector_init(struct drm_device *dev,
395 struct vc4_hdmi *vc4_hdmi)
397 struct drm_connector *connector = &vc4_hdmi->connector;
398 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
401 drm_connector_init_with_ddc(dev, connector,
402 &vc4_hdmi_connector_funcs,
403 DRM_MODE_CONNECTOR_HDMIA,
405 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
408 * Some of the properties below require access to state, like bpc.
409 * Allocate some default initial connector state with our reset helper.
411 if (connector->funcs->reset)
412 connector->funcs->reset(connector);
414 /* Create and attach TV margin props to this connector. */
415 ret = drm_mode_create_tv_margin_properties(dev);
419 ret = drm_mode_create_hdmi_colorspace_property(connector);
423 drm_connector_attach_colorspace_property(connector);
424 drm_connector_attach_tv_margin_properties(connector);
425 drm_connector_attach_max_bpc_property(connector, 8, 12);
427 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
428 DRM_CONNECTOR_POLL_DISCONNECT);
430 connector->interlace_allowed = 1;
431 connector->doublescan_allowed = 0;
432 connector->stereo_allowed = 1;
434 if (vc4_hdmi->variant->supports_hdr)
435 drm_connector_attach_hdr_output_metadata_property(connector);
437 drm_connector_attach_encoder(connector, encoder);
442 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
443 enum hdmi_infoframe_type type,
446 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
447 u32 packet_id = type - 0x80;
450 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
451 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
452 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
453 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
458 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
459 BIT(packet_id)), 100);
462 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
463 union hdmi_infoframe *frame)
465 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
466 u32 packet_id = frame->any.type - 0x80;
467 const struct vc4_hdmi_register *ram_packet_start =
468 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
469 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
470 u32 packet_reg_next = ram_packet_start->offset +
471 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
472 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
473 ram_packet_start->reg);
474 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
479 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
480 VC4_HDMI_RAM_PACKET_ENABLE),
481 "Packet RAM has to be on to store the packet.");
483 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
487 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
489 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
493 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
495 for (i = 0; i < len; i += 7) {
496 writel(buffer[i + 0] << 0 |
502 writel(buffer[i + 3] << 0 |
504 buffer[i + 5] << 16 |
511 * clear remainder of packet ram as it's included in the
512 * infoframe and triggers a checksum error on hdmi analyser
514 for (; packet_reg < packet_reg_next; packet_reg += 4)
515 writel(0, base + packet_reg);
517 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
518 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
520 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
522 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
523 BIT(packet_id)), 100);
525 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
528 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
529 enum vc4_hdmi_output_format fmt)
532 case VC4_HDMI_OUTPUT_RGB:
533 frame->colorspace = HDMI_COLORSPACE_RGB;
536 case VC4_HDMI_OUTPUT_YUV420:
537 frame->colorspace = HDMI_COLORSPACE_YUV420;
540 case VC4_HDMI_OUTPUT_YUV422:
541 frame->colorspace = HDMI_COLORSPACE_YUV422;
544 case VC4_HDMI_OUTPUT_YUV444:
545 frame->colorspace = HDMI_COLORSPACE_YUV444;
553 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
555 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
556 struct drm_connector *connector = &vc4_hdmi->connector;
557 struct drm_connector_state *cstate = connector->state;
558 struct vc4_hdmi_connector_state *vc4_state =
559 conn_state_to_vc4_hdmi_conn_state(cstate);
560 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
561 union hdmi_infoframe frame;
564 lockdep_assert_held(&vc4_hdmi->mutex);
566 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
569 DRM_ERROR("couldn't fill AVI infoframe\n");
573 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
575 vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ?
576 HDMI_QUANTIZATION_RANGE_FULL :
577 HDMI_QUANTIZATION_RANGE_LIMITED);
578 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
579 vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format);
580 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
582 vc4_hdmi_write_infoframe(encoder, &frame);
585 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
587 union hdmi_infoframe frame;
590 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
592 DRM_ERROR("couldn't fill SPD infoframe\n");
596 frame.spd.sdi = HDMI_SPD_SDI_PC;
598 vc4_hdmi_write_infoframe(encoder, &frame);
601 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
603 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
604 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
605 union hdmi_infoframe frame;
607 memcpy(&frame.audio, audio, sizeof(*audio));
609 if (vc4_hdmi->packet_ram_enabled)
610 vc4_hdmi_write_infoframe(encoder, &frame);
613 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
615 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
616 struct drm_connector *connector = &vc4_hdmi->connector;
617 struct drm_connector_state *conn_state = connector->state;
618 union hdmi_infoframe frame;
620 lockdep_assert_held(&vc4_hdmi->mutex);
622 if (!vc4_hdmi->variant->supports_hdr)
625 if (!conn_state->hdr_output_metadata)
628 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
631 vc4_hdmi_write_infoframe(encoder, &frame);
634 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
636 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
638 lockdep_assert_held(&vc4_hdmi->mutex);
640 vc4_hdmi_set_avi_infoframe(encoder);
641 vc4_hdmi_set_spd_infoframe(encoder);
643 * If audio was streaming, then we need to reenabled the audio
644 * infoframe here during encoder_enable.
646 if (vc4_hdmi->audio.streaming)
647 vc4_hdmi_set_audio_infoframe(encoder);
649 vc4_hdmi_set_hdr_infoframe(encoder);
652 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
653 struct drm_display_mode *mode)
655 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
656 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
658 lockdep_assert_held(&vc4_hdmi->mutex);
660 if (!display->is_hdmi)
663 if (!display->hdmi.scdc.supported ||
664 !display->hdmi.scdc.scrambling.supported)
670 #define SCRAMBLING_POLLING_DELAY_MS 1000
672 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
674 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
675 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
678 lockdep_assert_held(&vc4_hdmi->mutex);
680 if (!vc4_hdmi_supports_scrambling(encoder, mode))
683 if (!vc4_hdmi_mode_needs_scrambling(mode,
684 vc4_hdmi->output_bpc,
685 vc4_hdmi->output_format))
688 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
689 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
691 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
692 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
693 VC5_HDMI_SCRAMBLER_CTL_ENABLE);
694 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
696 vc4_hdmi->scdc_enabled = true;
698 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
699 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
702 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
704 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
707 lockdep_assert_held(&vc4_hdmi->mutex);
709 if (!vc4_hdmi->scdc_enabled)
712 vc4_hdmi->scdc_enabled = false;
714 if (delayed_work_pending(&vc4_hdmi->scrambling_work))
715 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
717 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
718 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
719 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
720 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
722 drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
723 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
726 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
728 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
732 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
735 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
736 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
738 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
739 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
742 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
743 struct drm_atomic_state *state)
745 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
748 mutex_lock(&vc4_hdmi->mutex);
750 vc4_hdmi->packet_ram_enabled = false;
752 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
754 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
756 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
758 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
762 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
763 HDMI_WRITE(HDMI_VID_CTL,
764 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
765 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
767 vc4_hdmi_disable_scrambling(encoder);
769 mutex_unlock(&vc4_hdmi->mutex);
772 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
773 struct drm_atomic_state *state)
775 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
779 mutex_lock(&vc4_hdmi->mutex);
781 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
782 HDMI_WRITE(HDMI_VID_CTL,
783 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
784 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
786 if (vc4_hdmi->variant->phy_disable)
787 vc4_hdmi->variant->phy_disable(vc4_hdmi);
789 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
790 clk_disable_unprepare(vc4_hdmi->pixel_clock);
792 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
794 DRM_ERROR("Failed to release power domain: %d\n", ret);
796 mutex_unlock(&vc4_hdmi->mutex);
799 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
800 struct drm_connector_state *state,
801 const struct drm_display_mode *mode)
806 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
808 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
809 VC4_HD_CSC_CTL_ORDER);
811 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) {
812 /* CEA VICs other than #1 requre limited range RGB
813 * output unless overridden by an AVI infoframe.
814 * Apply a colorspace conversion to squash 0-255 down
815 * to 16-235. The matrix here is:
822 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
823 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
824 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
825 VC4_HD_CSC_CTL_MODE);
827 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
828 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
829 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
830 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
831 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
832 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
835 /* The RGB order applies even when CSC is disabled. */
836 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
838 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
842 * If we need to output Full Range RGB, then use the unity matrix
848 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
850 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = {
851 { 0x2000, 0x0000, 0x0000, 0x0000 },
852 { 0x0000, 0x2000, 0x0000, 0x0000 },
853 { 0x0000, 0x0000, 0x2000, 0x0000 },
857 * CEA VICs other than #1 require limited range RGB output unless
858 * overridden by an AVI infoframe. Apply a colorspace conversion to
859 * squash 0-255 down to 16-235. The matrix here is:
865 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
867 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = {
868 { 0x1b80, 0x0000, 0x0000, 0x0400 },
869 { 0x0000, 0x1b80, 0x0000, 0x0400 },
870 { 0x0000, 0x0000, 0x1b80, 0x0400 },
874 * Conversion between Full Range RGB and Full Range YUV422 using the
878 * [ 0.181906 0.611804 0.061758 16 ]
879 * [ -0.100268 -0.337232 0.437500 128 ]
880 * [ 0.437500 -0.397386 -0.040114 128 ]
882 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
884 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709[3][4] = {
885 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
886 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
887 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
891 * Conversion between Full Range RGB and Full Range YUV444 using the
894 * [ -0.100268 -0.337232 0.437500 128 ]
895 * [ 0.437500 -0.397386 -0.040114 128 ]
896 * [ 0.181906 0.611804 0.061758 16 ]
898 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
900 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709[3][4] = {
901 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
902 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
903 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
906 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
907 const u16 coeffs[3][4])
909 lockdep_assert_held(&vc4_hdmi->hw_lock);
911 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
912 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
913 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
914 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
915 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
916 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
919 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
920 struct drm_connector_state *state,
921 const struct drm_display_mode *mode)
923 struct vc4_hdmi_connector_state *vc4_state =
924 conn_state_to_vc4_hdmi_conn_state(state);
927 u32 if_xbar = 0x543210;
928 u32 csc_chan_ctl = 0;
929 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
930 VC5_MT_CP_CSC_CTL_MODE);
932 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
934 switch (vc4_state->output_format) {
935 case VC4_HDMI_OUTPUT_YUV444:
936 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709);
939 case VC4_HDMI_OUTPUT_YUV422:
940 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
941 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
942 VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
943 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
945 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
946 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
948 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
949 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
951 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709);
954 case VC4_HDMI_OUTPUT_RGB:
957 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode))
958 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb);
960 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity);
967 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
968 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
969 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
970 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
972 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
975 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
976 struct drm_connector_state *state,
977 struct drm_display_mode *mode)
979 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
980 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
981 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
982 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
983 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
984 VC4_HDMI_VERTA_VSP) |
985 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
986 VC4_HDMI_VERTA_VFP) |
987 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
988 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
989 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
991 VC4_HDMI_VERTB_VBP));
992 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
993 VC4_SET_FIELD(mode->crtc_vtotal -
994 mode->crtc_vsync_end,
995 VC4_HDMI_VERTB_VBP));
999 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1001 HDMI_WRITE(HDMI_HORZA,
1002 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1003 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1004 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1005 VC4_HDMI_HORZA_HAP));
1007 HDMI_WRITE(HDMI_HORZB,
1008 VC4_SET_FIELD((mode->htotal -
1009 mode->hsync_end) * pixel_rep,
1010 VC4_HDMI_HORZB_HBP) |
1011 VC4_SET_FIELD((mode->hsync_end -
1012 mode->hsync_start) * pixel_rep,
1013 VC4_HDMI_HORZB_HSP) |
1014 VC4_SET_FIELD((mode->hsync_start -
1015 mode->hdisplay) * pixel_rep,
1016 VC4_HDMI_HORZB_HFP));
1018 HDMI_WRITE(HDMI_VERTA0, verta);
1019 HDMI_WRITE(HDMI_VERTA1, verta);
1021 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1022 HDMI_WRITE(HDMI_VERTB1, vertb);
1024 reg = HDMI_READ(HDMI_MISC_CONTROL);
1025 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1026 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1027 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1029 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1032 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1033 struct drm_connector_state *state,
1034 struct drm_display_mode *mode)
1036 const struct vc4_hdmi_connector_state *vc4_state =
1037 conn_state_to_vc4_hdmi_conn_state(state);
1038 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1039 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1040 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1041 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1042 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1043 VC5_HDMI_VERTA_VSP) |
1044 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1045 VC5_HDMI_VERTA_VFP) |
1046 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1047 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1048 VC5_HDMI_VERTB_VSPO) |
1049 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
1050 VC4_HDMI_VERTB_VBP));
1051 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1052 VC4_SET_FIELD(mode->crtc_vtotal -
1053 mode->crtc_vsync_end - interlaced,
1054 VC4_HDMI_VERTB_VBP));
1055 unsigned long flags;
1060 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1062 HDMI_WRITE(HDMI_HORZA,
1063 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1064 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1065 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1066 VC5_HDMI_HORZA_HAP) |
1067 VC4_SET_FIELD((mode->hsync_start -
1068 mode->hdisplay) * pixel_rep,
1069 VC5_HDMI_HORZA_HFP));
1071 HDMI_WRITE(HDMI_HORZB,
1072 VC4_SET_FIELD((mode->htotal -
1073 mode->hsync_end) * pixel_rep,
1074 VC5_HDMI_HORZB_HBP) |
1075 VC4_SET_FIELD((mode->hsync_end -
1076 mode->hsync_start) * pixel_rep,
1077 VC5_HDMI_HORZB_HSP));
1079 HDMI_WRITE(HDMI_VERTA0, verta);
1080 HDMI_WRITE(HDMI_VERTA1, verta);
1082 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1083 HDMI_WRITE(HDMI_VERTB1, vertb);
1085 switch (vc4_state->output_bpc) {
1102 * YCC422 is always 36-bit and not considered deep colour so
1103 * doesn't signal in GCP.
1105 if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {
1110 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1111 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1112 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1113 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1114 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1115 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1117 reg = HDMI_READ(HDMI_GCP_WORD_1);
1118 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1119 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1120 HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1122 reg = HDMI_READ(HDMI_GCP_CONFIG);
1123 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1124 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
1125 HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1127 reg = HDMI_READ(HDMI_MISC_CONTROL);
1128 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1129 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1130 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1132 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1134 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1137 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1139 unsigned long flags;
1143 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1145 drift = HDMI_READ(HDMI_FIFO_CTL);
1146 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1148 HDMI_WRITE(HDMI_FIFO_CTL,
1149 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1150 HDMI_WRITE(HDMI_FIFO_CTL,
1151 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1153 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1155 usleep_range(1000, 1100);
1157 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1159 HDMI_WRITE(HDMI_FIFO_CTL,
1160 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1161 HDMI_WRITE(HDMI_FIFO_CTL,
1162 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1164 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1166 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1167 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1168 WARN_ONCE(ret, "Timeout waiting for "
1169 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1172 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1173 struct drm_atomic_state *state)
1175 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1176 struct drm_connector *connector = &vc4_hdmi->connector;
1177 struct drm_connector_state *conn_state =
1178 drm_atomic_get_new_connector_state(state, connector);
1179 struct vc4_hdmi_connector_state *vc4_conn_state =
1180 conn_state_to_vc4_hdmi_conn_state(conn_state);
1181 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1182 unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate;
1183 unsigned long bvb_rate, hsm_rate;
1184 unsigned long flags;
1187 mutex_lock(&vc4_hdmi->mutex);
1190 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1191 * be faster than pixel clock, infinitesimally faster, tested in
1192 * simulation. Otherwise, exact value is unimportant for HDMI
1193 * operation." This conflicts with bcm2835's vc4 documentation, which
1194 * states HSM's clock has to be at least 108% of the pixel clock.
1196 * Real life tests reveal that vc4's firmware statement holds up, and
1197 * users are able to use pixel clocks closer to HSM's, namely for
1198 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1199 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1202 * Additionally, the AXI clock needs to be at least 25% of
1203 * pixel clock, but HSM ends up being the limiting factor.
1205 hsm_rate = max_t(unsigned long, 120000000, (tmds_char_rate / 100) * 101);
1206 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1208 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1212 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1214 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1218 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1220 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1221 goto err_put_runtime_pm;
1224 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1226 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1227 goto err_put_runtime_pm;
1231 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1233 if (tmds_char_rate > 297000000)
1234 bvb_rate = 300000000;
1235 else if (tmds_char_rate > 148500000)
1236 bvb_rate = 150000000;
1238 bvb_rate = 75000000;
1240 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1242 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1243 goto err_disable_pixel_clock;
1246 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1248 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1249 goto err_disable_pixel_clock;
1252 if (vc4_hdmi->variant->phy_init)
1253 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1255 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1257 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1258 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1259 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1260 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1262 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1264 if (vc4_hdmi->variant->set_timings)
1265 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1267 mutex_unlock(&vc4_hdmi->mutex);
1271 err_disable_pixel_clock:
1272 clk_disable_unprepare(vc4_hdmi->pixel_clock);
1274 pm_runtime_put(&vc4_hdmi->pdev->dev);
1276 mutex_unlock(&vc4_hdmi->mutex);
1280 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1281 struct drm_atomic_state *state)
1283 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1284 struct drm_connector *connector = &vc4_hdmi->connector;
1285 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1286 struct drm_connector_state *conn_state =
1287 drm_atomic_get_new_connector_state(state, connector);
1288 unsigned long flags;
1290 mutex_lock(&vc4_hdmi->mutex);
1292 if (vc4_hdmi->variant->csc_setup)
1293 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1295 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1296 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1297 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1299 mutex_unlock(&vc4_hdmi->mutex);
1302 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1303 struct drm_atomic_state *state)
1305 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1306 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1307 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1308 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1309 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1310 unsigned long flags;
1313 mutex_lock(&vc4_hdmi->mutex);
1315 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1317 HDMI_WRITE(HDMI_VID_CTL,
1318 VC4_HD_VID_CTL_ENABLE |
1319 VC4_HD_VID_CTL_CLRRGB |
1320 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1321 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1322 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1323 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1325 HDMI_WRITE(HDMI_VID_CTL,
1326 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1328 if (display->is_hdmi) {
1329 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1330 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1331 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1333 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1335 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1336 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1337 WARN_ONCE(ret, "Timeout waiting for "
1338 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1340 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1341 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1342 ~(VC4_HDMI_RAM_PACKET_ENABLE));
1343 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1344 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1345 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1347 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1349 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1350 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1351 WARN_ONCE(ret, "Timeout waiting for "
1352 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1355 if (display->is_hdmi) {
1356 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1358 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1359 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1361 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1362 VC4_HDMI_RAM_PACKET_ENABLE);
1364 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1365 vc4_hdmi->packet_ram_enabled = true;
1367 vc4_hdmi_set_infoframes(encoder);
1370 vc4_hdmi_recenter_fifo(vc4_hdmi);
1371 vc4_hdmi_enable_scrambling(encoder);
1373 mutex_unlock(&vc4_hdmi->mutex);
1376 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1377 struct drm_crtc_state *crtc_state,
1378 struct drm_connector_state *conn_state)
1380 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1381 struct vc4_hdmi_connector_state *vc4_state =
1382 conn_state_to_vc4_hdmi_conn_state(conn_state);
1384 mutex_lock(&vc4_hdmi->mutex);
1385 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1386 &crtc_state->adjusted_mode);
1387 vc4_hdmi->output_bpc = vc4_state->output_bpc;
1388 vc4_hdmi->output_format = vc4_state->output_format;
1389 mutex_unlock(&vc4_hdmi->mutex);
1393 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi,
1394 const struct drm_display_info *info,
1395 const struct drm_display_mode *mode,
1396 unsigned int format, unsigned int bpc)
1398 struct drm_device *dev = vc4_hdmi->connector.dev;
1399 u8 vic = drm_match_cea_mode(mode);
1401 if (vic == 1 && bpc != 8) {
1402 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc);
1406 if (!info->is_hdmi &&
1407 (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) {
1408 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n");
1413 case VC4_HDMI_OUTPUT_RGB:
1414 drm_dbg(dev, "RGB Format, checking the constraints.\n");
1416 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444))
1419 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1420 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1424 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1425 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1429 drm_dbg(dev, "RGB format supported in that configuration.\n");
1433 case VC4_HDMI_OUTPUT_YUV422:
1434 drm_dbg(dev, "YUV422 format, checking the constraints.\n");
1436 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) {
1437 drm_dbg(dev, "Sink doesn't support YUV422.\n");
1442 drm_dbg(dev, "YUV422 only supports 12 bpc.\n");
1446 drm_dbg(dev, "YUV422 format supported in that configuration.\n");
1450 case VC4_HDMI_OUTPUT_YUV444:
1451 drm_dbg(dev, "YUV444 format, checking the constraints.\n");
1453 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) {
1454 drm_dbg(dev, "Sink doesn't support YUV444.\n");
1458 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1459 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1463 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1464 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1468 drm_dbg(dev, "YUV444 format supported in that configuration.\n");
1476 static enum drm_mode_status
1477 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
1478 unsigned long long clock)
1480 const struct drm_connector *connector = &vc4_hdmi->connector;
1481 const struct drm_display_info *info = &connector->display_info;
1483 if (clock > vc4_hdmi->variant->max_pixel_clock)
1484 return MODE_CLOCK_HIGH;
1486 if (vc4_hdmi->disable_4kp60 && clock > HDMI_14_MAX_TMDS_CLK)
1487 return MODE_CLOCK_HIGH;
1489 if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000))
1490 return MODE_CLOCK_HIGH;
1495 static unsigned long long
1496 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
1498 enum vc4_hdmi_output_format fmt)
1500 unsigned long long clock = mode->clock * 1000ULL;
1502 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1505 if (fmt == VC4_HDMI_OUTPUT_YUV422)
1508 clock = clock * bpc;
1515 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
1516 struct vc4_hdmi_connector_state *vc4_state,
1517 const struct drm_display_mode *mode,
1518 unsigned int bpc, unsigned int fmt)
1520 unsigned long long clock;
1522 clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
1523 if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, clock) != MODE_OK)
1526 vc4_state->tmds_char_rate = clock;
1532 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi,
1533 struct vc4_hdmi_connector_state *vc4_state,
1534 const struct drm_display_mode *mode,
1537 struct drm_device *dev = vc4_hdmi->connector.dev;
1538 const struct drm_connector *connector = &vc4_hdmi->connector;
1539 const struct drm_display_info *info = &connector->display_info;
1540 unsigned int format;
1542 drm_dbg(dev, "Trying with an RGB output\n");
1544 format = VC4_HDMI_OUTPUT_RGB;
1545 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1548 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1551 vc4_state->output_format = format;
1556 drm_dbg(dev, "Failed, Trying with an YUV422 output\n");
1558 format = VC4_HDMI_OUTPUT_YUV422;
1559 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1562 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1565 vc4_state->output_format = format;
1570 drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n");
1576 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi,
1577 struct vc4_hdmi_connector_state *vc4_state,
1578 const struct drm_display_mode *mode)
1580 struct drm_device *dev = vc4_hdmi->connector.dev;
1581 struct drm_connector_state *conn_state = &vc4_state->base;
1582 unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12);
1586 for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
1587 drm_dbg(dev, "Trying with a %d bpc output\n", bpc);
1589 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state,
1594 vc4_state->output_bpc = bpc;
1597 "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n",
1598 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
1599 vc4_state->output_bpc,
1600 vc4_hdmi_output_fmt_str(vc4_state->output_format),
1601 vc4_state->tmds_char_rate);
1609 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
1610 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
1612 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1613 struct drm_crtc_state *crtc_state,
1614 struct drm_connector_state *conn_state)
1616 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1617 struct drm_connector *connector = &vc4_hdmi->connector;
1618 struct drm_connector_state *old_conn_state =
1619 drm_atomic_get_old_connector_state(conn_state->state, connector);
1620 struct vc4_hdmi_connector_state *old_vc4_state =
1621 conn_state_to_vc4_hdmi_conn_state(old_conn_state);
1622 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1623 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1624 unsigned long long tmds_char_rate = mode->clock * 1000;
1625 unsigned long long tmds_bit_rate;
1628 if (vc4_hdmi->variant->unsupported_odd_h_timings) {
1629 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1630 /* Only try to fixup DBLCLK modes to get 480i and 576i
1632 * A generic solution for all modes with odd horizontal
1633 * timing values seems impossible based on trying to
1634 * solve it for 1366x768 monitors.
1636 if ((mode->hsync_start - mode->hdisplay) & 1)
1637 mode->hsync_start--;
1638 if ((mode->hsync_end - mode->hsync_start) & 1)
1642 /* Now check whether we still have odd values remaining */
1643 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1644 (mode->hsync_end % 2) || (mode->htotal % 2))
1649 * The 1440p@60 pixel rate is in the same range than the first
1650 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1651 * bandwidth). Slightly lower the frequency to bring it out of
1654 tmds_bit_rate = tmds_char_rate * 10;
1655 if (vc4_hdmi->disable_wifi_frequencies &&
1656 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1657 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1658 mode->clock = 238560;
1659 tmds_char_rate = mode->clock * 1000;
1662 ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode);
1666 /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */
1667 if (vc4_state->output_bpc != old_vc4_state->output_bpc ||
1668 vc4_state->output_format != old_vc4_state->output_format)
1669 crtc_state->mode_changed = true;
1674 static enum drm_mode_status
1675 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1676 const struct drm_display_mode *mode)
1678 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1680 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1681 !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1682 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1683 (mode->hsync_end % 2) || (mode->htotal % 2)))
1684 return MODE_H_ILLEGAL;
1686 return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode->clock * 1000);
1689 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1690 .atomic_check = vc4_hdmi_encoder_atomic_check,
1691 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1692 .mode_valid = vc4_hdmi_encoder_mode_valid,
1695 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1698 u32 channel_map = 0;
1700 for (i = 0; i < 8; i++) {
1701 if (channel_mask & BIT(i))
1702 channel_map |= i << (3 * i);
1707 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1710 u32 channel_map = 0;
1712 for (i = 0; i < 8; i++) {
1713 if (channel_mask & BIT(i))
1714 channel_map |= i << (4 * i);
1719 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
1721 unsigned long flags;
1724 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1725 hotplug = HDMI_READ(HDMI_HOTPLUG);
1726 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1728 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
1731 /* HDMI audio codec callbacks */
1732 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1733 unsigned int samplerate)
1735 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1736 unsigned long flags;
1739 rational_best_approximation(hsm_clock, samplerate,
1740 VC4_HD_MAI_SMP_N_MASK >>
1741 VC4_HD_MAI_SMP_N_SHIFT,
1742 (VC4_HD_MAI_SMP_M_MASK >>
1743 VC4_HD_MAI_SMP_M_SHIFT) + 1,
1746 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1747 HDMI_WRITE(HDMI_MAI_SMP,
1748 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1749 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1750 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1753 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1755 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1759 lockdep_assert_held(&vc4_hdmi->mutex);
1760 lockdep_assert_held(&vc4_hdmi->hw_lock);
1762 n = 128 * samplerate / 1000;
1763 tmp = (u64)(mode->clock * 1000) * n;
1764 do_div(tmp, 128 * samplerate);
1767 HDMI_WRITE(HDMI_CRP_CFG,
1768 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1769 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1772 * We could get slightly more accurate clocks in some cases by
1773 * providing a CTS_1 value. The two CTS values are alternated
1774 * between based on the period fields
1776 HDMI_WRITE(HDMI_CTS_0, cts);
1777 HDMI_WRITE(HDMI_CTS_1, cts);
1780 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1782 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1784 return snd_soc_card_get_drvdata(card);
1787 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
1789 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1791 lockdep_assert_held(&vc4_hdmi->mutex);
1794 * If the encoder is currently in DVI mode, treat the codec DAI
1797 if (!display->is_hdmi)
1803 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1805 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1806 unsigned long flags;
1808 mutex_lock(&vc4_hdmi->mutex);
1810 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1811 mutex_unlock(&vc4_hdmi->mutex);
1815 vc4_hdmi->audio.streaming = true;
1817 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1818 HDMI_WRITE(HDMI_MAI_CTL,
1819 VC4_HD_MAI_CTL_RESET |
1820 VC4_HD_MAI_CTL_FLUSH |
1821 VC4_HD_MAI_CTL_DLATE |
1822 VC4_HD_MAI_CTL_ERRORE |
1823 VC4_HD_MAI_CTL_ERRORF);
1824 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1826 if (vc4_hdmi->variant->phy_rng_enable)
1827 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1829 mutex_unlock(&vc4_hdmi->mutex);
1834 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1836 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
1837 struct device *dev = &vc4_hdmi->pdev->dev;
1838 unsigned long flags;
1841 lockdep_assert_held(&vc4_hdmi->mutex);
1843 vc4_hdmi->audio.streaming = false;
1844 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1846 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1848 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1850 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1851 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1852 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1854 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1857 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1859 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1860 unsigned long flags;
1862 mutex_lock(&vc4_hdmi->mutex);
1864 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1866 HDMI_WRITE(HDMI_MAI_CTL,
1867 VC4_HD_MAI_CTL_DLATE |
1868 VC4_HD_MAI_CTL_ERRORE |
1869 VC4_HD_MAI_CTL_ERRORF);
1871 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1873 if (vc4_hdmi->variant->phy_rng_disable)
1874 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1876 vc4_hdmi->audio.streaming = false;
1877 vc4_hdmi_audio_reset(vc4_hdmi);
1879 mutex_unlock(&vc4_hdmi->mutex);
1882 static int sample_rate_to_mai_fmt(int samplerate)
1884 switch (samplerate) {
1886 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1888 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1890 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1892 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1894 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1896 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1898 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1900 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1902 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1904 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
1906 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
1908 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
1910 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
1912 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
1914 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
1916 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
1920 /* HDMI audio codec callbacks */
1921 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
1922 struct hdmi_codec_daifmt *daifmt,
1923 struct hdmi_codec_params *params)
1925 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1926 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
1927 unsigned int sample_rate = params->sample_rate;
1928 unsigned int channels = params->channels;
1929 unsigned long flags;
1930 u32 audio_packet_config, channel_mask;
1932 u32 mai_audio_format;
1933 u32 mai_sample_rate;
1935 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1936 sample_rate, params->sample_width, channels);
1938 mutex_lock(&vc4_hdmi->mutex);
1940 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1941 mutex_unlock(&vc4_hdmi->mutex);
1945 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
1947 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1948 HDMI_WRITE(HDMI_MAI_CTL,
1949 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
1950 VC4_HD_MAI_CTL_WHOLSMP |
1951 VC4_HD_MAI_CTL_CHALIGN |
1952 VC4_HD_MAI_CTL_ENABLE);
1954 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
1955 if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
1956 params->channels == 8)
1957 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
1959 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
1960 HDMI_WRITE(HDMI_MAI_FMT,
1961 VC4_SET_FIELD(mai_sample_rate,
1962 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
1963 VC4_SET_FIELD(mai_audio_format,
1964 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
1966 /* The B frame identifier should match the value used by alsa-lib (8) */
1967 audio_packet_config =
1968 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1969 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1970 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1972 channel_mask = GENMASK(channels - 1, 0);
1973 audio_packet_config |= VC4_SET_FIELD(channel_mask,
1974 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1976 /* Set the MAI threshold */
1977 HDMI_WRITE(HDMI_MAI_THR,
1978 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
1979 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
1980 VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
1981 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
1983 HDMI_WRITE(HDMI_MAI_CONFIG,
1984 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1985 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
1986 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1988 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1989 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1990 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1992 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
1994 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1996 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea));
1997 vc4_hdmi_set_audio_infoframe(encoder);
1999 mutex_unlock(&vc4_hdmi->mutex);
2004 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2005 .name = "vc4-hdmi-cpu-dai-component",
2006 .legacy_dai_naming = 1,
2009 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2011 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2013 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2018 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2019 .name = "vc4-hdmi-cpu-dai",
2020 .probe = vc4_hdmi_audio_cpu_dai_probe,
2022 .stream_name = "Playback",
2025 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2026 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2027 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2028 SNDRV_PCM_RATE_192000,
2029 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2033 static const struct snd_dmaengine_pcm_config pcm_conf = {
2034 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2035 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2038 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
2039 uint8_t *buf, size_t len)
2041 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2042 struct drm_connector *connector = &vc4_hdmi->connector;
2044 mutex_lock(&vc4_hdmi->mutex);
2045 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2046 mutex_unlock(&vc4_hdmi->mutex);
2051 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
2052 .get_eld = vc4_hdmi_audio_get_eld,
2053 .prepare = vc4_hdmi_audio_prepare,
2054 .audio_shutdown = vc4_hdmi_audio_shutdown,
2055 .audio_startup = vc4_hdmi_audio_startup,
2058 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
2059 .ops = &vc4_hdmi_codec_ops,
2060 .max_i2s_channels = 8,
2064 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2066 const struct vc4_hdmi_register *mai_data =
2067 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2068 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2069 struct snd_soc_card *card = &vc4_hdmi->audio.card;
2070 struct device *dev = &vc4_hdmi->pdev->dev;
2071 struct platform_device *codec_pdev;
2076 if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
2078 "'dmas' DT property is missing or empty, no HDMI audio\n");
2082 if (mai_data->reg != VC4_HD) {
2083 WARN_ONCE(true, "MAI isn't in the HD block\n");
2088 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2089 * the bus address specified in the DT, because the physical address
2090 * (the one returned by platform_get_resource()) is not appropriate
2091 * for DMA transfers.
2092 * This VC/MMU should probably be exposed to avoid this kind of hacks.
2094 index = of_property_match_string(dev->of_node, "reg-names", "hd");
2095 /* Before BCM2711, we don't have a named register range */
2099 addr = of_get_address(dev->of_node, index, NULL, NULL);
2101 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2102 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2103 vc4_hdmi->audio.dma_data.maxburst = 2;
2105 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2107 dev_err(dev, "Could not register PCM component: %d\n", ret);
2111 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2112 &vc4_hdmi_audio_cpu_dai_drv, 1);
2114 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2118 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
2119 PLATFORM_DEVID_AUTO,
2120 &vc4_hdmi_codec_pdata,
2121 sizeof(vc4_hdmi_codec_pdata));
2122 if (IS_ERR(codec_pdev)) {
2123 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
2124 return PTR_ERR(codec_pdev);
2126 vc4_hdmi->audio.codec_pdev = codec_pdev;
2128 dai_link->cpus = &vc4_hdmi->audio.cpu;
2129 dai_link->codecs = &vc4_hdmi->audio.codec;
2130 dai_link->platforms = &vc4_hdmi->audio.platform;
2132 dai_link->num_cpus = 1;
2133 dai_link->num_codecs = 1;
2134 dai_link->num_platforms = 1;
2136 dai_link->name = "MAI";
2137 dai_link->stream_name = "MAI PCM";
2138 dai_link->codecs->dai_name = "i2s-hifi";
2139 dai_link->cpus->dai_name = dev_name(dev);
2140 dai_link->codecs->name = dev_name(&codec_pdev->dev);
2141 dai_link->platforms->name = dev_name(dev);
2143 card->dai_link = dai_link;
2144 card->num_links = 1;
2145 card->name = vc4_hdmi->variant->card_name;
2146 card->driver_name = "vc4-hdmi";
2148 card->owner = THIS_MODULE;
2151 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2152 * stores a pointer to the snd card object in dev->driver_data. This
2153 * means we cannot use it for something else. The hdmi back-pointer is
2154 * now stored in card->drvdata and should be retrieved with
2155 * snd_soc_card_get_drvdata() if needed.
2157 snd_soc_card_set_drvdata(card, vc4_hdmi);
2158 ret = devm_snd_soc_register_card(dev, card);
2160 dev_err_probe(dev, ret, "Could not register sound card\n");
2166 static void vc4_hdmi_audio_exit(struct vc4_hdmi *vc4_hdmi)
2168 platform_device_unregister(vc4_hdmi->audio.codec_pdev);
2169 vc4_hdmi->audio.codec_pdev = NULL;
2172 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2174 struct vc4_hdmi *vc4_hdmi = priv;
2175 struct drm_connector *connector = &vc4_hdmi->connector;
2176 struct drm_device *dev = connector->dev;
2178 if (dev && dev->registered)
2179 drm_connector_helper_hpd_irq_event(connector);
2184 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2186 struct drm_connector *connector = &vc4_hdmi->connector;
2187 struct platform_device *pdev = vc4_hdmi->pdev;
2190 if (vc4_hdmi->variant->external_irq_controller) {
2191 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2192 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2194 ret = request_threaded_irq(hpd_con,
2196 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2197 "vc4 hdmi hpd connected", vc4_hdmi);
2201 ret = request_threaded_irq(hpd_rm,
2203 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2204 "vc4 hdmi hpd disconnected", vc4_hdmi);
2206 free_irq(hpd_con, vc4_hdmi);
2210 connector->polled = DRM_CONNECTOR_POLL_HPD;
2216 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi)
2218 struct platform_device *pdev = vc4_hdmi->pdev;
2220 if (vc4_hdmi->variant->external_irq_controller) {
2221 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi);
2222 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi);
2226 #ifdef CONFIG_DRM_VC4_HDMI_CEC
2227 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2229 struct vc4_hdmi *vc4_hdmi = priv;
2231 if (vc4_hdmi->cec_rx_msg.len)
2232 cec_received_msg(vc4_hdmi->cec_adap,
2233 &vc4_hdmi->cec_rx_msg);
2238 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2240 struct vc4_hdmi *vc4_hdmi = priv;
2242 if (vc4_hdmi->cec_tx_ok) {
2243 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2247 * This CEC implementation makes 1 retry, so if we
2248 * get a NACK, then that means it made 2 attempts.
2250 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2256 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2258 struct vc4_hdmi *vc4_hdmi = priv;
2261 if (vc4_hdmi->cec_irq_was_rx)
2262 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2264 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2269 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2271 struct drm_device *dev = vc4_hdmi->connector.dev;
2272 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2275 lockdep_assert_held(&vc4_hdmi->hw_lock);
2277 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2278 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2280 if (msg->len > 16) {
2281 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2285 for (i = 0; i < msg->len; i += 4) {
2286 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2288 msg->msg[i] = val & 0xff;
2289 msg->msg[i + 1] = (val >> 8) & 0xff;
2290 msg->msg[i + 2] = (val >> 16) & 0xff;
2291 msg->msg[i + 3] = (val >> 24) & 0xff;
2295 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2299 lockdep_assert_held(&vc4_hdmi->hw_lock);
2301 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2302 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2303 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2304 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2306 return IRQ_WAKE_THREAD;
2309 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2311 struct vc4_hdmi *vc4_hdmi = priv;
2314 spin_lock(&vc4_hdmi->hw_lock);
2315 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2316 spin_unlock(&vc4_hdmi->hw_lock);
2321 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2325 lockdep_assert_held(&vc4_hdmi->hw_lock);
2327 vc4_hdmi->cec_rx_msg.len = 0;
2328 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2329 vc4_cec_read_msg(vc4_hdmi, cntrl1);
2330 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2331 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2332 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2334 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2336 return IRQ_WAKE_THREAD;
2339 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
2341 struct vc4_hdmi *vc4_hdmi = priv;
2344 spin_lock(&vc4_hdmi->hw_lock);
2345 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2346 spin_unlock(&vc4_hdmi->hw_lock);
2351 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2353 struct vc4_hdmi *vc4_hdmi = priv;
2354 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2358 if (!(stat & VC4_HDMI_CPU_CEC))
2361 spin_lock(&vc4_hdmi->hw_lock);
2362 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2363 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2364 if (vc4_hdmi->cec_irq_was_rx)
2365 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2367 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2369 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2370 spin_unlock(&vc4_hdmi->hw_lock);
2375 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2377 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2378 /* clock period in microseconds */
2379 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2380 unsigned long flags;
2385 * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2386 * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2387 * .detect or .get_modes might call .adap_enable, which leads to this
2388 * function being called with that mutex held.
2390 * Concurrency is not an issue for the moment since we don't share any
2391 * state with KMS, so we can ignore the lock for now, but we need to
2392 * keep it in mind if we were to change that assumption.
2395 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2399 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2401 val = HDMI_READ(HDMI_CEC_CNTRL_5);
2402 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2403 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2404 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2405 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2406 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2408 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2409 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2410 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2411 HDMI_WRITE(HDMI_CEC_CNTRL_2,
2412 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2413 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2414 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2415 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2416 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2417 HDMI_WRITE(HDMI_CEC_CNTRL_3,
2418 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2419 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2420 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2421 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2422 HDMI_WRITE(HDMI_CEC_CNTRL_4,
2423 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2424 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2425 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2426 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2428 if (!vc4_hdmi->variant->external_irq_controller)
2429 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2431 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2436 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2438 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2439 unsigned long flags;
2442 * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2443 * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2444 * .detect or .get_modes might call .adap_enable, which leads to this
2445 * function being called with that mutex held.
2447 * Concurrency is not an issue for the moment since we don't share any
2448 * state with KMS, so we can ignore the lock for now, but we need to
2449 * keep it in mind if we were to change that assumption.
2452 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2454 if (!vc4_hdmi->variant->external_irq_controller)
2455 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2457 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2458 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2460 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2462 pm_runtime_put(&vc4_hdmi->pdev->dev);
2467 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2470 return vc4_hdmi_cec_enable(adap);
2472 return vc4_hdmi_cec_disable(adap);
2475 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2477 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2478 unsigned long flags;
2481 * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2482 * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2483 * .detect or .get_modes might call .adap_enable, which leads to this
2484 * function being called with that mutex held.
2486 * Concurrency is not an issue for the moment since we don't share any
2487 * state with KMS, so we can ignore the lock for now, but we need to
2488 * keep it in mind if we were to change that assumption.
2491 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2492 HDMI_WRITE(HDMI_CEC_CNTRL_1,
2493 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2494 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2495 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2500 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2501 u32 signal_free_time, struct cec_msg *msg)
2503 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2504 struct drm_device *dev = vc4_hdmi->connector.dev;
2505 unsigned long flags;
2510 * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2511 * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2512 * .detect or .get_modes might call .adap_enable, which leads to this
2513 * function being called with that mutex held.
2515 * Concurrency is not an issue for the moment since we don't share any
2516 * state with KMS, so we can ignore the lock for now, but we need to
2517 * keep it in mind if we were to change that assumption.
2520 if (msg->len > 16) {
2521 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2525 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2527 for (i = 0; i < msg->len; i += 4)
2528 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2530 (msg->msg[i + 1] << 8) |
2531 (msg->msg[i + 2] << 16) |
2532 (msg->msg[i + 3] << 24));
2534 val = HDMI_READ(HDMI_CEC_CNTRL_1);
2535 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2536 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2537 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2538 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2539 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2541 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2543 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2548 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2549 .adap_enable = vc4_hdmi_cec_adap_enable,
2550 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2551 .adap_transmit = vc4_hdmi_cec_adap_transmit,
2554 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2556 struct cec_connector_info conn_info;
2557 struct platform_device *pdev = vc4_hdmi->pdev;
2558 struct device *dev = &pdev->dev;
2561 if (!of_find_property(dev->of_node, "interrupts", NULL)) {
2562 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
2566 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
2569 CEC_CAP_CONNECTOR_INFO, 1);
2570 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
2574 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
2575 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
2577 if (vc4_hdmi->variant->external_irq_controller) {
2578 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"),
2579 vc4_cec_irq_handler_rx_bare,
2580 vc4_cec_irq_handler_rx_thread, 0,
2581 "vc4 hdmi cec rx", vc4_hdmi);
2583 goto err_delete_cec_adap;
2585 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"),
2586 vc4_cec_irq_handler_tx_bare,
2587 vc4_cec_irq_handler_tx_thread, 0,
2588 "vc4 hdmi cec tx", vc4_hdmi);
2590 goto err_remove_cec_rx_handler;
2592 ret = request_threaded_irq(platform_get_irq(pdev, 0),
2593 vc4_cec_irq_handler,
2594 vc4_cec_irq_handler_thread, 0,
2595 "vc4 hdmi cec", vc4_hdmi);
2597 goto err_delete_cec_adap;
2600 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
2602 goto err_remove_handlers;
2606 err_remove_handlers:
2607 if (vc4_hdmi->variant->external_irq_controller)
2608 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
2610 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
2612 err_remove_cec_rx_handler:
2613 if (vc4_hdmi->variant->external_irq_controller)
2614 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
2616 err_delete_cec_adap:
2617 cec_delete_adapter(vc4_hdmi->cec_adap);
2622 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
2624 struct platform_device *pdev = vc4_hdmi->pdev;
2626 if (vc4_hdmi->variant->external_irq_controller) {
2627 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
2628 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
2630 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
2633 cec_unregister_adapter(vc4_hdmi->cec_adap);
2636 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2641 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
2644 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
2645 struct debugfs_regset32 *regset,
2646 enum vc4_hdmi_regs reg)
2648 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2649 struct debugfs_reg32 *regs, *new_regs;
2650 unsigned int count = 0;
2653 regs = kcalloc(variant->num_registers, sizeof(*regs),
2658 for (i = 0; i < variant->num_registers; i++) {
2659 const struct vc4_hdmi_register *field = &variant->registers[i];
2661 if (field->reg != reg)
2664 regs[count].name = field->name;
2665 regs[count].offset = field->offset;
2669 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
2673 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
2674 regset->regs = new_regs;
2675 regset->nregs = count;
2680 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2682 struct platform_device *pdev = vc4_hdmi->pdev;
2683 struct device *dev = &pdev->dev;
2686 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
2687 if (IS_ERR(vc4_hdmi->hdmicore_regs))
2688 return PTR_ERR(vc4_hdmi->hdmicore_regs);
2690 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
2691 if (IS_ERR(vc4_hdmi->hd_regs))
2692 return PTR_ERR(vc4_hdmi->hd_regs);
2694 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2698 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2702 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
2703 if (IS_ERR(vc4_hdmi->pixel_clock)) {
2704 ret = PTR_ERR(vc4_hdmi->pixel_clock);
2705 if (ret != -EPROBE_DEFER)
2706 DRM_ERROR("Failed to get pixel clock\n");
2710 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2711 if (IS_ERR(vc4_hdmi->hsm_clock)) {
2712 DRM_ERROR("Failed to get HDMI state machine clock\n");
2713 return PTR_ERR(vc4_hdmi->hsm_clock);
2715 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2716 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2721 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2723 struct platform_device *pdev = vc4_hdmi->pdev;
2724 struct device *dev = &pdev->dev;
2725 struct resource *res;
2728 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2732 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2733 resource_size(res));
2734 if (!vc4_hdmi->hdmicore_regs)
2737 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2741 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2742 if (!vc4_hdmi->hd_regs)
2745 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2749 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2750 if (!vc4_hdmi->cec_regs)
2753 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2757 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2758 if (!vc4_hdmi->csc_regs)
2761 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2765 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2766 if (!vc4_hdmi->dvp_regs)
2769 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2773 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2774 if (!vc4_hdmi->phy_regs)
2777 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2781 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2782 if (!vc4_hdmi->ram_regs)
2785 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2789 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2790 if (!vc4_hdmi->rm_regs)
2793 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2794 if (IS_ERR(vc4_hdmi->hsm_clock)) {
2795 DRM_ERROR("Failed to get HDMI state machine clock\n");
2796 return PTR_ERR(vc4_hdmi->hsm_clock);
2799 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2800 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2801 DRM_ERROR("Failed to get pixel bvb clock\n");
2802 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2805 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2806 if (IS_ERR(vc4_hdmi->audio_clock)) {
2807 DRM_ERROR("Failed to get audio clock\n");
2808 return PTR_ERR(vc4_hdmi->audio_clock);
2811 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2812 if (IS_ERR(vc4_hdmi->cec_clock)) {
2813 DRM_ERROR("Failed to get CEC clock\n");
2814 return PTR_ERR(vc4_hdmi->cec_clock);
2817 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2818 if (IS_ERR(vc4_hdmi->reset)) {
2819 DRM_ERROR("Failed to get HDMI reset line\n");
2820 return PTR_ERR(vc4_hdmi->reset);
2823 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2827 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2831 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
2835 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
2839 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
2843 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
2847 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
2851 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
2858 static int vc4_hdmi_runtime_suspend(struct device *dev)
2860 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2862 clk_disable_unprepare(vc4_hdmi->hsm_clock);
2867 static int vc4_hdmi_runtime_resume(struct device *dev)
2869 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2870 unsigned long __maybe_unused flags;
2871 u32 __maybe_unused value;
2876 * The HSM clock is in the HDMI power domain, so we need to set
2877 * its frequency while the power domain is active so that it
2880 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
2884 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
2889 * Whenever the RaspberryPi boots without an HDMI monitor
2890 * plugged in, the firmware won't have initialized the HSM clock
2891 * rate and it will be reported as 0.
2893 * If we try to access a register of the controller in such a
2894 * case, it will lead to a silent CPU stall. Let's make sure we
2895 * prevent such a case.
2897 rate = clk_get_rate(vc4_hdmi->hsm_clock);
2900 goto err_disable_clk;
2903 if (vc4_hdmi->variant->reset)
2904 vc4_hdmi->variant->reset(vc4_hdmi);
2906 #ifdef CONFIG_DRM_VC4_HDMI_CEC
2907 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2908 value = HDMI_READ(HDMI_CEC_CNTRL_1);
2909 /* Set the logical address to Unregistered */
2910 value |= VC4_HDMI_CEC_ADDR_MASK;
2911 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
2912 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2914 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
2916 if (!vc4_hdmi->variant->external_irq_controller) {
2917 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2918 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
2919 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2926 clk_disable_unprepare(vc4_hdmi->hsm_clock);
2930 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2932 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2933 struct platform_device *pdev = to_platform_device(dev);
2934 struct drm_device *drm = dev_get_drvdata(master);
2935 struct vc4_hdmi *vc4_hdmi;
2936 struct drm_encoder *encoder;
2937 struct device_node *ddc_node;
2940 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2943 mutex_init(&vc4_hdmi->mutex);
2944 spin_lock_init(&vc4_hdmi->hw_lock);
2945 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2947 dev_set_drvdata(dev, vc4_hdmi);
2948 encoder = &vc4_hdmi->encoder.base;
2949 vc4_hdmi->encoder.type = variant->encoder_type;
2950 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2951 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2952 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2953 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2954 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2955 vc4_hdmi->pdev = pdev;
2956 vc4_hdmi->variant = variant;
2959 * Since we don't know the state of the controller and its
2960 * display (if any), let's assume it's always enabled.
2961 * vc4_hdmi_disable_scrambling() will thus run at boot, make
2962 * sure it's disabled, and avoid any inconsistency.
2964 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
2965 vc4_hdmi->scdc_enabled = true;
2967 ret = variant->init_resources(vc4_hdmi);
2971 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2973 DRM_ERROR("Failed to find ddc node in device tree\n");
2977 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2978 of_node_put(ddc_node);
2979 if (!vc4_hdmi->ddc) {
2980 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2981 return -EPROBE_DEFER;
2984 /* Only use the GPIO HPD pin if present in the DT, otherwise
2985 * we'll use the HDMI core's register.
2987 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2988 if (IS_ERR(vc4_hdmi->hpd_gpio)) {
2989 ret = PTR_ERR(vc4_hdmi->hpd_gpio);
2993 vc4_hdmi->disable_wifi_frequencies =
2994 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2996 if (variant->max_pixel_clock == 600000000) {
2997 struct vc4_dev *vc4 = to_vc4_dev(drm);
2998 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
3000 if (max_rate < 550000000)
3001 vc4_hdmi->disable_4kp60 = true;
3004 pm_runtime_enable(dev);
3007 * We need to have the device powered up at this point to call
3008 * our reset hook and for the CEC init.
3010 ret = pm_runtime_resume_and_get(dev);
3012 goto err_disable_runtime_pm;
3014 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3015 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
3016 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3017 clk_prepare_enable(vc4_hdmi->pixel_clock);
3018 clk_prepare_enable(vc4_hdmi->hsm_clock);
3019 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3022 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
3023 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3025 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3027 goto err_destroy_encoder;
3029 ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3031 goto err_destroy_conn;
3033 ret = vc4_hdmi_cec_init(vc4_hdmi);
3035 goto err_free_hotplug;
3037 ret = vc4_hdmi_audio_init(vc4_hdmi);
3041 vc4_debugfs_add_file(drm, variant->debugfs_name,
3042 vc4_hdmi_debugfs_regs,
3045 pm_runtime_put_sync(dev);
3050 vc4_hdmi_cec_exit(vc4_hdmi);
3052 vc4_hdmi_hotplug_exit(vc4_hdmi);
3054 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
3055 err_destroy_encoder:
3056 drm_encoder_cleanup(encoder);
3057 pm_runtime_put_sync(dev);
3058 err_disable_runtime_pm:
3059 pm_runtime_disable(dev);
3061 put_device(&vc4_hdmi->ddc->dev);
3066 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
3069 struct vc4_hdmi *vc4_hdmi;
3072 * ASoC makes it a bit hard to retrieve a pointer to the
3073 * vc4_hdmi structure. Registering the card will overwrite our
3074 * device drvdata with a pointer to the snd_soc_card structure,
3075 * which can then be used to retrieve whatever drvdata we want
3078 * However, that doesn't fly in the case where we wouldn't
3079 * register an ASoC card (because of an old DT that is missing
3080 * the dmas properties for example), then the card isn't
3081 * registered and the device drvdata wouldn't be set.
3083 * We can deal with both cases by making sure a snd_soc_card
3084 * pointer and a vc4_hdmi structure are pointing to the same
3085 * memory address, so we can treat them indistinctly without any
3088 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
3089 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
3090 vc4_hdmi = dev_get_drvdata(dev);
3092 kfree(vc4_hdmi->hdmi_regset.regs);
3093 kfree(vc4_hdmi->hd_regset.regs);
3095 vc4_hdmi_audio_exit(vc4_hdmi);
3096 vc4_hdmi_cec_exit(vc4_hdmi);
3097 vc4_hdmi_hotplug_exit(vc4_hdmi);
3098 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
3099 drm_encoder_cleanup(&vc4_hdmi->encoder.base);
3101 pm_runtime_disable(dev);
3103 put_device(&vc4_hdmi->ddc->dev);
3106 static const struct component_ops vc4_hdmi_ops = {
3107 .bind = vc4_hdmi_bind,
3108 .unbind = vc4_hdmi_unbind,
3111 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3113 return component_add(&pdev->dev, &vc4_hdmi_ops);
3116 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
3118 component_del(&pdev->dev, &vc4_hdmi_ops);
3122 static const struct vc4_hdmi_variant bcm2835_variant = {
3123 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3124 .debugfs_name = "hdmi_regs",
3125 .card_name = "vc4-hdmi",
3126 .max_pixel_clock = 162000000,
3127 .registers = vc4_hdmi_fields,
3128 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
3130 .init_resources = vc4_hdmi_init_resources,
3131 .csc_setup = vc4_hdmi_csc_setup,
3132 .reset = vc4_hdmi_reset,
3133 .set_timings = vc4_hdmi_set_timings,
3134 .phy_init = vc4_hdmi_phy_init,
3135 .phy_disable = vc4_hdmi_phy_disable,
3136 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
3137 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
3138 .channel_map = vc4_hdmi_channel_map,
3139 .supports_hdr = false,
3142 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3143 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3144 .debugfs_name = "hdmi0_regs",
3145 .card_name = "vc4-hdmi-0",
3146 .max_pixel_clock = 600000000,
3147 .registers = vc5_hdmi_hdmi0_fields,
3148 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3149 .phy_lane_mapping = {
3155 .unsupported_odd_h_timings = true,
3156 .external_irq_controller = true,
3158 .init_resources = vc5_hdmi_init_resources,
3159 .csc_setup = vc5_hdmi_csc_setup,
3160 .reset = vc5_hdmi_reset,
3161 .set_timings = vc5_hdmi_set_timings,
3162 .phy_init = vc5_hdmi_phy_init,
3163 .phy_disable = vc5_hdmi_phy_disable,
3164 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3165 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3166 .channel_map = vc5_hdmi_channel_map,
3167 .supports_hdr = true,
3168 .hp_detect = vc5_hdmi_hp_detect,
3171 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3172 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
3173 .debugfs_name = "hdmi1_regs",
3174 .card_name = "vc4-hdmi-1",
3175 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
3176 .registers = vc5_hdmi_hdmi1_fields,
3177 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3178 .phy_lane_mapping = {
3184 .unsupported_odd_h_timings = true,
3185 .external_irq_controller = true,
3187 .init_resources = vc5_hdmi_init_resources,
3188 .csc_setup = vc5_hdmi_csc_setup,
3189 .reset = vc5_hdmi_reset,
3190 .set_timings = vc5_hdmi_set_timings,
3191 .phy_init = vc5_hdmi_phy_init,
3192 .phy_disable = vc5_hdmi_phy_disable,
3193 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3194 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3195 .channel_map = vc5_hdmi_channel_map,
3196 .supports_hdr = true,
3197 .hp_detect = vc5_hdmi_hp_detect,
3200 static const struct of_device_id vc4_hdmi_dt_match[] = {
3201 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3202 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3203 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3207 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3208 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3209 vc4_hdmi_runtime_resume,
3213 struct platform_driver vc4_hdmi_driver = {
3214 .probe = vc4_hdmi_dev_probe,
3215 .remove = vc4_hdmi_dev_remove,
3218 .of_match_table = vc4_hdmi_dt_match,
3219 .pm = &vc4_hdmi_pm_ops,