drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_drv.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_probe_helper.h>
  38 #include <drm/drm_simple_kms_helper.h>
  39 #include <drm/drm_scdc_helper.h>
  40 #include <linux/clk.h>
  41 #include <linux/component.h>
  42 #include <linux/gpio/consumer.h>
  43 #include <linux/extcon-provider.h>
  44 #include <linux/i2c.h>
  45 #include <linux/module.h>
  46 #include <linux/moduleparam.h>
  47 #include <linux/of_address.h>
  48 #include <linux/of_gpio.h>
  49 #include <linux/of_platform.h>
  50 #include <linux/pm_runtime.h>
  51 #include <linux/rational.h>
  52 #include <linux/reset.h>
  53 #include <sound/dmaengine_pcm.h>
  54 #include <sound/hdmi-codec.h>
  55 #include <sound/pcm_drm_eld.h>
  56 #include <sound/pcm_params.h>
  57 #include <sound/soc.h>
  58 #include "media/cec.h"
  59 #include "vc4_drv.h"
  60 #include "vc4_hdmi.h"
  61 #include "vc4_hdmi_regs.h"
  62 #include "vc4_regs.h"
  63
  64 /*
  65  * "Broadcast RGB" property.
  66  * Allows overriding of HDMI full or limited range RGB
  67  */
  68 #define VC4_BROADCAST_RGB_AUTO 0
  69 #define VC4_BROADCAST_RGB_FULL 1
  70 #define VC4_BROADCAST_RGB_LIMITED 2
  71
  72 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  73 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  74 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  75 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  76 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  77 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  78
  79 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  80 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  81 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  82 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  83
  84 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  85 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  86 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  87 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  88 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  89 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  90
  91 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  92 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  93
  94 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  95 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  96 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  97 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  98
  99 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
 100
 101 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
 102 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
 103
 104 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
 105 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
 106
 107 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
 108
 109 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
 110 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
 111
 112 # define VC4_HD_M_SW_RST                        BIT(2)
 113 # define VC4_HD_M_ENABLE                        BIT(0)
 114
 115 #define HSM_MIN_CLOCK_FREQ      120000000
 116 #define CEC_CLOCK_FREQ 40000
 117
 118 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 119
 120 /* bit field to force hotplug detection. bit0 = HDMI0 */
 121 static int force_hotplug = 0;
 122 module_param(force_hotplug, int, 0644);
 123
 124 static const char * const output_format_str[] = {
 125         [VC4_HDMI_OUTPUT_RGB]           = "RGB",
 126         [VC4_HDMI_OUTPUT_YUV420]        = "YUV 4:2:0",
 127         [VC4_HDMI_OUTPUT_YUV422]        = "YUV 4:2:2",
 128         [VC4_HDMI_OUTPUT_YUV444]        = "YUV 4:4:4",
 129 };
 130
 131 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt)
 132 {
 133         if (fmt >= ARRAY_SIZE(output_format_str))
 134                 return "invalid";
 135
 136         return output_format_str[fmt];
 137 }
 138
 139 static unsigned long long
 140 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
 141                                     unsigned int bpc, enum vc4_hdmi_output_format fmt);
 142
 143 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder)
 144 {
 145         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 146         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 147
 148         lockdep_assert_held(&vc4_hdmi->mutex);
 149
 150         if (!display->is_hdmi)
 151                 return false;
 152
 153         if (!display->hdmi.scdc.supported ||
 154             !display->hdmi.scdc.scrambling.supported)
 155                 return false;
 156
 157         return true;
 158 }
 159
 160 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
 161                                            unsigned int bpc,
 162                                            enum vc4_hdmi_output_format fmt)
 163 {
 164         unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
 165
 166         return clock > HDMI_14_MAX_TMDS_CLK;
 167 }
 168
 169 static bool vc4_hdmi_is_full_range(struct vc4_hdmi *vc4_hdmi,
 170                                    const struct drm_display_mode *mode)
 171 {
 172         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 173
 174         if (vc4_hdmi->broadcast_rgb == VC4_BROADCAST_RGB_LIMITED)
 175                 return false;
 176         else if (vc4_hdmi->broadcast_rgb == VC4_BROADCAST_RGB_FULL)
 177                 return true;
 178         return !display->is_hdmi ||
 179                 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
 180 }
 181
 182 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 183 {
 184         struct drm_info_node *node = (struct drm_info_node *)m->private;
 185         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
 186         struct drm_device *drm = vc4_hdmi->connector.dev;
 187         struct drm_printer p = drm_seq_file_printer(m);
 188         int idx;
 189
 190         if (!drm_dev_enter(drm, &idx))
 191                 return -ENODEV;
 192
 193         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 194         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 195         drm_print_regset32(&p, &vc4_hdmi->cec_regset);
 196         drm_print_regset32(&p, &vc4_hdmi->csc_regset);
 197         drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
 198         drm_print_regset32(&p, &vc4_hdmi->phy_regset);
 199         drm_print_regset32(&p, &vc4_hdmi->ram_regset);
 200         drm_print_regset32(&p, &vc4_hdmi->rm_regset);
 201
 202         drm_dev_exit(idx);
 203
 204         return 0;
 205 }
 206
 207 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 208 {
 209         struct drm_device *drm = vc4_hdmi->connector.dev;
 210         unsigned long flags;
 211         int idx;
 212
 213         /*
 214          * We can be called by our bind callback, when the
 215          * connector->dev pointer might not be initialised yet.
 216          */
 217         if (drm && !drm_dev_enter(drm, &idx))
 218                 return;
 219
 220         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 221
 222         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 223         udelay(1);
 224         HDMI_WRITE(HDMI_M_CTL, 0);
 225
 226         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 227
 228         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 229                    VC4_HDMI_SW_RESET_HDMI |
 230                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 231
 232         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 233
 234         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 235
 236         if (drm)
 237                 drm_dev_exit(idx);
 238 }
 239
 240 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 241 {
 242         struct drm_device *drm = vc4_hdmi->connector.dev;
 243         unsigned long flags;
 244         int idx;
 245
 246         /*
 247          * We can be called by our bind callback, when the
 248          * connector->dev pointer might not be initialised yet.
 249          */
 250         if (drm && !drm_dev_enter(drm, &idx))
 251                 return;
 252
 253         reset_control_reset(vc4_hdmi->reset);
 254
 255         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 256
 257         HDMI_WRITE(HDMI_DVP_CTL, 0);
 258
 259         HDMI_WRITE(HDMI_CLOCK_STOP,
 260                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 261
 262         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 263
 264         if (drm)
 265                 drm_dev_exit(idx);
 266 }
 267
 268 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 269 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 270 {
 271         struct drm_device *drm = vc4_hdmi->connector.dev;
 272         unsigned long cec_rate;
 273         unsigned long flags;
 274         u16 clk_cnt;
 275         u32 value;
 276         int idx;
 277
 278         /*
 279          * This function is called by our runtime_resume implementation
 280          * and thus at bind time, when we haven't registered our
 281          * connector yet and thus don't have a pointer to the DRM
 282          * device.
 283          */
 284         if (drm && !drm_dev_enter(drm, &idx))
 285                 return;
 286
 287         cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
 288
 289         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 290
 291         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 292         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 293
 294         /*
 295          * Set the clock divider: the hsm_clock rate and this divider
 296          * setting will give a 40 kHz CEC clock.
 297          */
 298         clk_cnt = cec_rate / CEC_CLOCK_FREQ;
 299         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 300         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 301
 302         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 303
 304         if (drm)
 305                 drm_dev_exit(idx);
 306 }
 307 #else
 308 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 309 #endif
 310
 311 static int reset_pipe(struct drm_crtc *crtc,
 312                         struct drm_modeset_acquire_ctx *ctx)
 313 {
 314         struct drm_atomic_state *state;
 315         struct drm_crtc_state *crtc_state;
 316         int ret;
 317
 318         state = drm_atomic_state_alloc(crtc->dev);
 319         if (!state)
 320                 return -ENOMEM;
 321
 322         state->acquire_ctx = ctx;
 323
 324         crtc_state = drm_atomic_get_crtc_state(state, crtc);
 325         if (IS_ERR(crtc_state)) {
 326                 ret = PTR_ERR(crtc_state);
 327                 goto out;
 328         }
 329
 330         crtc_state->connectors_changed = true;
 331
 332         ret = drm_atomic_commit(state);
 333 out:
 334         drm_atomic_state_put(state);
 335
 336         return ret;
 337 }
 338
 339 static int vc4_hdmi_reset_link(struct drm_connector *connector,
 340                                struct drm_modeset_acquire_ctx *ctx)
 341 {
 342         struct drm_device *drm = connector->dev;
 343         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 344         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
 345         struct drm_connector_state *conn_state;
 346         struct drm_crtc_state *crtc_state;
 347         struct drm_crtc *crtc;
 348         bool scrambling_needed;
 349         u8 config;
 350         int ret;
 351
 352         if (!connector)
 353                 return 0;
 354
 355         ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx);
 356         if (ret)
 357                 return ret;
 358
 359         conn_state = connector->state;
 360         crtc = conn_state->crtc;
 361         if (!crtc)
 362                 return 0;
 363
 364         ret = drm_modeset_lock(&crtc->mutex, ctx);
 365         if (ret)
 366                 return ret;
 367
 368         crtc_state = crtc->state;
 369         if (!crtc_state->active)
 370                 return 0;
 371
 372         if (!vc4_hdmi_supports_scrambling(encoder))
 373                 return 0;
 374
 375         scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
 376                                                            vc4_hdmi->output_bpc,
 377                                                            vc4_hdmi->output_format);
 378         if (!scrambling_needed)
 379                 return 0;
 380
 381         if (conn_state->commit &&
 382             !try_wait_for_completion(&conn_state->commit->hw_done))
 383                 return 0;
 384
 385         ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
 386         if (ret < 0) {
 387                 drm_err(drm, "Failed to read TMDS config: %d\n", ret);
 388                 return 0;
 389         }
 390
 391         if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed)
 392                 return 0;
 393
 394         /*
 395          * HDMI 2.0 says that one should not send scrambled data
 396          * prior to configuring the sink scrambling, and that
 397          * TMDS clock/data transmission should be suspended when
 398          * changing the TMDS clock rate in the sink. So let's
 399          * just do a full modeset here, even though some sinks
 400          * would be perfectly happy if were to just reconfigure
 401          * the SCDC settings on the fly.
 402          */
 403         return reset_pipe(crtc, ctx);
 404 }
 405
 406 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi,
 407                                     struct drm_modeset_acquire_ctx *ctx,
 408                                     enum drm_connector_status status)
 409 {
 410         struct drm_connector *connector = &vc4_hdmi->connector;
 411         struct edid *edid;
 412
 413         /*
 414          * NOTE: This function should really be called with
 415          * vc4_hdmi->mutex held, but doing so results in reentrancy
 416          * issues since cec_s_phys_addr_from_edid might call
 417          * .adap_enable, which leads to that funtion being called with
 418          * our mutex held.
 419          *
 420          * A similar situation occurs with
 421          * drm_atomic_helper_connector_hdmi_reset_link() that will call
 422          * into our KMS hooks if the scrambling was enabled.
 423          *
 424          * Concurrency isn't an issue at the moment since we don't share
 425          * any state with any of the other frameworks so we can ignore
 426          * the lock for now.
 427          */
 428
 429         if (status == connector->status)
 430                 return;
 431
 432         if (status == connector_status_disconnected) {
 433                 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 434                 return;
 435         }
 436
 437         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 438         if (!edid)
 439                 return;
 440
 441         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 442         kfree(edid);
 443
 444         vc4_hdmi_reset_link(connector, ctx);
 445 }
 446
 447 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
 448                                          struct drm_modeset_acquire_ctx *ctx,
 449                                          bool force)
 450 {
 451         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 452         enum drm_connector_status status = connector_status_disconnected;
 453
 454         /*
 455          * NOTE: This function should really take vc4_hdmi->mutex, but
 456          * doing so results in reentrancy issues since
 457          * vc4_hdmi_handle_hotplug() can call into other functions that
 458          * would take the mutex while it's held here.
 459          *
 460          * Concurrency isn't an issue at the moment since we don't share
 461          * any state with any of the other frameworks so we can ignore
 462          * the lock for now.
 463          */
 464
 465         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 466
 467         if (force_hotplug & BIT(vc4_hdmi->encoder.type - VC4_ENCODER_TYPE_HDMI0))
 468                 status = connector_status_connected;
 469         else if (vc4_hdmi->hpd_gpio) {
 470                 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
 471                         status = connector_status_connected;
 472         } else {
 473                 if (vc4_hdmi->variant->hp_detect &&
 474                     vc4_hdmi->variant->hp_detect(vc4_hdmi))
 475                         status = connector_status_connected;
 476         }
 477
 478         vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status);
 479         pm_runtime_put(&vc4_hdmi->pdev->dev);
 480
 481 #ifdef CONFIG_EXTCON
 482         if (status != vc4_hdmi->status) {
 483                 extcon_set_state_sync(vc4_hdmi->edev, EXTCON_DISP_HDMI,
 484                                       (status == connector_status_connected ?
 485                                       true : false));
 486                 vc4_hdmi->status = status;
 487         }
 488 #endif
 489
 490         return status;
 491 }
 492
 493 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 494 {
 495         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 496         struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
 497         int ret = 0;
 498         struct edid *edid;
 499
 500         /*
 501          * NOTE: This function should really take vc4_hdmi->mutex, but
 502          * doing so results in reentrancy issues since
 503          * cec_s_phys_addr_from_edid might call .adap_enable, which
 504          * leads to that funtion being called with our mutex held.
 505          *
 506          * Concurrency isn't an issue at the moment since we don't share
 507          * any state with any of the other frameworks so we can ignore
 508          * the lock for now.
 509          */
 510
 511         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 512         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 513         if (!edid)
 514                 return -ENODEV;
 515
 516         drm_connector_update_edid_property(connector, edid);
 517         ret = drm_add_edid_modes(connector, edid);
 518         kfree(edid);
 519
 520         if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) {
 521                 struct drm_device *drm = connector->dev;
 522                 const struct drm_display_mode *mode;
 523
 524                 list_for_each_entry(mode, &connector->probed_modes, head) {
 525                         if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) {
 526                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 527                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 528                         }
 529                 }
 530         }
 531
 532         return ret;
 533 }
 534
 535 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 536                                            struct drm_atomic_state *state)
 537 {
 538         struct drm_connector_state *old_state =
 539                 drm_atomic_get_old_connector_state(state, connector);
 540         struct vc4_hdmi_connector_state *old_vc4_state = conn_state_to_vc4_hdmi_conn_state(old_state);
 541         struct drm_connector_state *new_state =
 542                 drm_atomic_get_new_connector_state(state, connector);
 543         struct vc4_hdmi_connector_state *new_vc4_state = conn_state_to_vc4_hdmi_conn_state(new_state);
 544         struct drm_crtc *crtc = new_state->crtc;
 545
 546         if (!crtc)
 547                 return 0;
 548
 549         if (old_state->colorspace != new_state->colorspace ||
 550             old_vc4_state->broadcast_rgb != new_vc4_state->broadcast_rgb ||
 551             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 552                 struct drm_crtc_state *crtc_state;
 553
 554                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 555                 if (IS_ERR(crtc_state))
 556                         return PTR_ERR(crtc_state);
 557
 558                 crtc_state->mode_changed = true;
 559         }
 560
 561         return 0;
 562 }
 563
 564 /**
 565  * vc4_hdmi_connector_atomic_get_property - hook for
 566  *                                              connector->atomic_get_property.
 567  * @connector: Connector to get the property for.
 568  * @state: Connector state to retrieve the property from.
 569  * @property: Property to retrieve.
 570  * @val: Return value for the property.
 571  *
 572  * Returns the atomic property value for a digital connector.
 573  */
 574 int vc4_hdmi_connector_get_property(struct drm_connector *connector,
 575                                     const struct drm_connector_state *state,
 576                                     struct drm_property *property,
 577                                     uint64_t *val)
 578 {
 579         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 580         const struct vc4_hdmi_connector_state *vc4_conn_state =
 581                                 const_conn_state_to_vc4_hdmi_conn_state(state);
 582
 583         if (property == vc4_hdmi->broadcast_rgb_property) {
 584                 *val = vc4_conn_state->broadcast_rgb;
 585         } else {
 586                 DRM_DEBUG_ATOMIC("Unknown property [PROP:%d:%s]\n",
 587                                  property->base.id, property->name);
 588                 return -EINVAL;
 589         }
 590
 591         return 0;
 592 }
 593
 594 /**
 595  * vc4_hdmi_connector_atomic_set_property - hook for
 596  *                                              connector->atomic_set_property.
 597  * @connector: Connector to set the property for.
 598  * @state: Connector state to set the property on.
 599  * @property: Property to set.
 600  * @val: New value for the property.
 601  *
 602  * Sets the atomic property value for a digital connector.
 603  */
 604 int vc4_hdmi_connector_set_property(struct drm_connector *connector,
 605                                     struct drm_connector_state *state,
 606                                     struct drm_property *property,
 607                                     uint64_t val)
 608 {
 609         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 610         struct vc4_hdmi_connector_state *vc4_conn_state =
 611                                 conn_state_to_vc4_hdmi_conn_state(state);
 612
 613         if (property == vc4_hdmi->broadcast_rgb_property) {
 614                 vc4_conn_state->broadcast_rgb = val;
 615                 return 0;
 616         }
 617
 618         DRM_DEBUG_ATOMIC("Unknown property [PROP:%d:%s]\n",
 619                          property->base.id, property->name);
 620         return -EINVAL;
 621 }
 622
 623 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 624 {
 625         struct vc4_hdmi_connector_state *old_state =
 626                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 627         struct vc4_hdmi_connector_state *new_state =
 628                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 629
 630         if (connector->state)
 631                 __drm_atomic_helper_connector_destroy_state(connector->state);
 632
 633         kfree(old_state);
 634         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 635
 636         if (!new_state)
 637                 return;
 638
 639         new_state->base.max_bpc = 8;
 640         new_state->base.max_requested_bpc = 8;
 641         new_state->output_format = VC4_HDMI_OUTPUT_RGB;
 642         drm_atomic_helper_connector_tv_reset(connector);
 643 }
 644
 645 static struct drm_connector_state *
 646 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 647 {
 648         struct drm_connector_state *conn_state = connector->state;
 649         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 650         struct vc4_hdmi_connector_state *new_state;
 651
 652         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 653         if (!new_state)
 654                 return NULL;
 655
 656         new_state->pixel_rate = vc4_state->pixel_rate;
 657         new_state->output_bpc = vc4_state->output_bpc;
 658         new_state->output_format = vc4_state->output_format;
 659         new_state->broadcast_rgb = vc4_state->broadcast_rgb;
 660         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 661
 662         return &new_state->base;
 663 }
 664
 665 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 666         .fill_modes = drm_helper_probe_single_connector_modes,
 667         .reset = vc4_hdmi_connector_reset,
 668         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 669         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 670         .atomic_get_property = vc4_hdmi_connector_get_property,
 671         .atomic_set_property = vc4_hdmi_connector_set_property,
 672 };
 673
 674 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 675         .detect_ctx = vc4_hdmi_connector_detect_ctx,
 676         .get_modes = vc4_hdmi_connector_get_modes,
 677         .atomic_check = vc4_hdmi_connector_atomic_check,
 678 };
 679
 680 static const struct drm_prop_enum_list broadcast_rgb_names[] = {
 681         { VC4_BROADCAST_RGB_AUTO, "Automatic" },
 682         { VC4_BROADCAST_RGB_FULL, "Full" },
 683         { VC4_BROADCAST_RGB_LIMITED, "Limited 16:235" },
 684 };
 685
 686 static void
 687 vc4_hdmi_attach_broadcast_rgb_property(struct drm_device *dev,
 688                                        struct vc4_hdmi *vc4_hdmi)
 689 {
 690         struct drm_property *prop = vc4_hdmi->broadcast_rgb_property;
 691
 692         if (!prop) {
 693                 prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
 694                                                 "Broadcast RGB",
 695                                                 broadcast_rgb_names,
 696                                                 ARRAY_SIZE(broadcast_rgb_names));
 697                 if (!prop)
 698                         return;
 699
 700                 vc4_hdmi->broadcast_rgb_property = prop;
 701         }
 702
 703         drm_object_attach_property(&vc4_hdmi->connector.base, prop, 0);
 704 }
 705
 706 static int vc4_hdmi_connector_init(struct drm_device *dev,
 707                                    struct vc4_hdmi *vc4_hdmi)
 708 {
 709         struct drm_connector *connector = &vc4_hdmi->connector;
 710         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
 711         int ret;
 712
 713         ret = drmm_connector_init(dev, connector,
 714                                   &vc4_hdmi_connector_funcs,
 715                                   DRM_MODE_CONNECTOR_HDMIA,
 716                                   vc4_hdmi->ddc);
 717         if (ret)
 718                 return ret;
 719
 720         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 721
 722         /*
 723          * Some of the properties below require access to state, like bpc.
 724          * Allocate some default initial connector state with our reset helper.
 725          */
 726         if (connector->funcs->reset)
 727                 connector->funcs->reset(connector);
 728
 729         /* Create and attach TV margin props to this connector. */
 730         ret = drm_mode_create_tv_margin_properties(dev);
 731         if (ret)
 732                 return ret;
 733
 734         ret = drm_mode_create_hdmi_colorspace_property(connector);
 735         if (ret)
 736                 return ret;
 737
 738         drm_connector_attach_colorspace_property(connector);
 739         drm_connector_attach_tv_margin_properties(connector);
 740         drm_connector_attach_max_bpc_property(connector, 8, 12);
 741
 742         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 743                              DRM_CONNECTOR_POLL_DISCONNECT);
 744
 745         connector->interlace_allowed = 1;
 746         connector->doublescan_allowed = 0;
 747         connector->stereo_allowed = 1;
 748
 749         if (vc4_hdmi->variant->supports_hdr)
 750                 drm_connector_attach_hdr_output_metadata_property(connector);
 751
 752         vc4_hdmi_attach_broadcast_rgb_property(dev, vc4_hdmi);
 753
 754         drm_connector_attach_encoder(connector, encoder);
 755
 756         return 0;
 757 }
 758
 759 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 760                                 enum hdmi_infoframe_type type,
 761                                 bool poll)
 762 {
 763         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 764         struct drm_device *drm = vc4_hdmi->connector.dev;
 765         u32 packet_id = type - 0x80;
 766         unsigned long flags;
 767         int ret = 0;
 768         int idx;
 769
 770         if (!drm_dev_enter(drm, &idx))
 771                 return -ENODEV;
 772
 773         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 774         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 775                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 776         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 777
 778         if (poll) {
 779                 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 780                                  BIT(packet_id)), 100);
 781         }
 782
 783         drm_dev_exit(idx);
 784         return ret;
 785 }
 786
 787 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 788                                      union hdmi_infoframe *frame)
 789 {
 790         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 791         struct drm_device *drm = vc4_hdmi->connector.dev;
 792         u32 packet_id = frame->any.type - 0x80;
 793         const struct vc4_hdmi_register *ram_packet_start =
 794                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 795         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 796         u32 packet_reg_next = ram_packet_start->offset +
 797                 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
 798         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 799                                                        ram_packet_start->reg);
 800         uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
 801         unsigned long flags;
 802         ssize_t len, i;
 803         int ret;
 804         int idx;
 805
 806         if (!drm_dev_enter(drm, &idx))
 807                 return;
 808
 809         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 810                     VC4_HDMI_RAM_PACKET_ENABLE),
 811                   "Packet RAM has to be on to store the packet.");
 812
 813         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 814         if (len < 0)
 815                 goto out;
 816
 817         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 818         if (ret) {
 819                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 820                 goto out;
 821         }
 822
 823         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 824
 825         for (i = 0; i < len; i += 7) {
 826                 writel(buffer[i + 0] << 0 |
 827                        buffer[i + 1] << 8 |
 828                        buffer[i + 2] << 16,
 829                        base + packet_reg);
 830                 packet_reg += 4;
 831
 832                 writel(buffer[i + 3] << 0 |
 833                        buffer[i + 4] << 8 |
 834                        buffer[i + 5] << 16 |
 835                        buffer[i + 6] << 24,
 836                        base + packet_reg);
 837                 packet_reg += 4;
 838         }
 839
 840         /*
 841          * clear remainder of packet ram as it's included in the
 842          * infoframe and triggers a checksum error on hdmi analyser
 843          */
 844         for (; packet_reg < packet_reg_next; packet_reg += 4)
 845                 writel(0, base + packet_reg);
 846
 847         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 848                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 849
 850         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 851
 852         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 853                         BIT(packet_id)), 100);
 854         if (ret)
 855                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 856
 857 out:
 858         drm_dev_exit(idx);
 859 }
 860
 861 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
 862                                               enum vc4_hdmi_output_format fmt)
 863 {
 864         switch (fmt) {
 865         case VC4_HDMI_OUTPUT_RGB:
 866                 frame->colorspace = HDMI_COLORSPACE_RGB;
 867                 break;
 868
 869         case VC4_HDMI_OUTPUT_YUV420:
 870                 frame->colorspace = HDMI_COLORSPACE_YUV420;
 871                 break;
 872
 873         case VC4_HDMI_OUTPUT_YUV422:
 874                 frame->colorspace = HDMI_COLORSPACE_YUV422;
 875                 break;
 876
 877         case VC4_HDMI_OUTPUT_YUV444:
 878                 frame->colorspace = HDMI_COLORSPACE_YUV444;
 879                 break;
 880
 881         default:
 882                 break;
 883         }
 884 }
 885
 886 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 887 {
 888         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 889         struct drm_connector *connector = &vc4_hdmi->connector;
 890         struct drm_connector_state *cstate = connector->state;
 891         struct vc4_hdmi_connector_state *vc4_state =
 892                 conn_state_to_vc4_hdmi_conn_state(cstate);
 893         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 894         union hdmi_infoframe frame;
 895         int ret;
 896
 897         lockdep_assert_held(&vc4_hdmi->mutex);
 898
 899         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 900                                                        connector, mode);
 901         if (ret < 0) {
 902                 DRM_ERROR("couldn't fill AVI infoframe\n");
 903                 return;
 904         }
 905
 906         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 907                                            connector, mode,
 908                                            vc4_hdmi_is_full_range(vc4_hdmi, mode) ?
 909                                            HDMI_QUANTIZATION_RANGE_FULL :
 910                                            HDMI_QUANTIZATION_RANGE_LIMITED);
 911         drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
 912         vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format);
 913         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 914
 915         vc4_hdmi_write_infoframe(encoder, &frame);
 916 }
 917
 918 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 919 {
 920         union hdmi_infoframe frame;
 921         int ret;
 922
 923         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 924         if (ret < 0) {
 925                 DRM_ERROR("couldn't fill SPD infoframe\n");
 926                 return;
 927         }
 928
 929         frame.spd.sdi = HDMI_SPD_SDI_PC;
 930
 931         vc4_hdmi_write_infoframe(encoder, &frame);
 932 }
 933
 934 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 935 {
 936         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 937         struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
 938         union hdmi_infoframe frame;
 939
 940         memcpy(&frame.audio, audio, sizeof(*audio));
 941         vc4_hdmi_write_infoframe(encoder, &frame);
 942 }
 943
 944 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 945 {
 946         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 947         struct drm_connector *connector = &vc4_hdmi->connector;
 948         struct drm_connector_state *conn_state = connector->state;
 949         union hdmi_infoframe frame;
 950
 951         lockdep_assert_held(&vc4_hdmi->mutex);
 952
 953         if (!vc4_hdmi->variant->supports_hdr)
 954                 return;
 955
 956         if (!conn_state->hdr_output_metadata)
 957                 return;
 958
 959         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 960                 return;
 961
 962         vc4_hdmi_write_infoframe(encoder, &frame);
 963 }
 964
 965 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 966 {
 967         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 968
 969         lockdep_assert_held(&vc4_hdmi->mutex);
 970
 971         vc4_hdmi_set_avi_infoframe(encoder);
 972         vc4_hdmi_set_spd_infoframe(encoder);
 973         /*
 974          * If audio was streaming, then we need to reenabled the audio
 975          * infoframe here during encoder_enable.
 976          */
 977         if (vc4_hdmi->audio.streaming)
 978                 vc4_hdmi_set_audio_infoframe(encoder);
 979
 980         vc4_hdmi_set_hdr_infoframe(encoder);
 981 }
 982
 983 #define SCRAMBLING_POLLING_DELAY_MS     1000
 984
 985 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 986 {
 987         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 988         struct drm_device *drm = vc4_hdmi->connector.dev;
 989         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 990         unsigned long flags;
 991         int idx;
 992
 993         lockdep_assert_held(&vc4_hdmi->mutex);
 994
 995         if (!vc4_hdmi_supports_scrambling(encoder))
 996                 return;
 997
 998         if (!vc4_hdmi_mode_needs_scrambling(mode,
 999                                             vc4_hdmi->output_bpc,
1000                                             vc4_hdmi->output_format))
1001                 return;
1002
1003         if (!drm_dev_enter(drm, &idx))
1004                 return;
1005
1006         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
1007         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
1008
1009         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1010         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
1011                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
1012         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1013
1014         drm_dev_exit(idx);
1015
1016         vc4_hdmi->scdc_enabled = true;
1017
1018         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
1019                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
1020 }
1021
1022 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
1023 {
1024         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1025         struct drm_device *drm = vc4_hdmi->connector.dev;
1026         unsigned long flags;
1027         int idx;
1028
1029         lockdep_assert_held(&vc4_hdmi->mutex);
1030
1031         if (!vc4_hdmi->scdc_enabled)
1032                 return;
1033
1034         vc4_hdmi->scdc_enabled = false;
1035
1036         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
1037                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
1038
1039         if (!drm_dev_enter(drm, &idx))
1040                 return;
1041
1042         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1043         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
1044                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
1045         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1046
1047         drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
1048         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
1049
1050         drm_dev_exit(idx);
1051 }
1052
1053 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
1054 {
1055         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
1056                                                  struct vc4_hdmi,
1057                                                  scrambling_work);
1058
1059         if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
1060                 return;
1061
1062         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
1063         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
1064
1065         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
1066                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
1067 }
1068
1069 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
1070                                                struct drm_atomic_state *state)
1071 {
1072         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1073         struct drm_device *drm = vc4_hdmi->connector.dev;
1074         unsigned long flags;
1075         int idx;
1076
1077         mutex_lock(&vc4_hdmi->mutex);
1078
1079         vc4_hdmi->output_enabled = false;
1080
1081         if (!drm_dev_enter(drm, &idx))
1082                 goto out;
1083
1084         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1085
1086         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
1087
1088         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
1089
1090         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1091
1092         mdelay(1);
1093
1094         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1095         HDMI_WRITE(HDMI_VID_CTL,
1096                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
1097         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1098
1099         vc4_hdmi_disable_scrambling(encoder);
1100
1101         drm_dev_exit(idx);
1102
1103 out:
1104         mutex_unlock(&vc4_hdmi->mutex);
1105 }
1106
1107 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
1108                                                  struct drm_atomic_state *state)
1109 {
1110         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1111         struct drm_device *drm = vc4_hdmi->connector.dev;
1112         unsigned long flags;
1113         int ret;
1114         int idx;
1115
1116         mutex_lock(&vc4_hdmi->mutex);
1117
1118         if (!drm_dev_enter(drm, &idx))
1119                 goto out;
1120
1121         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1122         HDMI_WRITE(HDMI_VID_CTL,
1123                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
1124         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1125
1126         if (vc4_hdmi->variant->phy_disable)
1127                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
1128
1129         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
1130         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1131
1132         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
1133         if (ret < 0)
1134                 DRM_ERROR("Failed to release power domain: %d\n", ret);
1135
1136         drm_dev_exit(idx);
1137
1138 out:
1139         mutex_unlock(&vc4_hdmi->mutex);
1140 }
1141
1142 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1143                                struct drm_connector_state *state,
1144                                const struct drm_display_mode *mode)
1145 {
1146         struct drm_device *drm = vc4_hdmi->connector.dev;
1147         unsigned long flags;
1148         u32 csc_ctl;
1149         int idx;
1150
1151         if (!drm_dev_enter(drm, &idx))
1152                 return;
1153
1154         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1155
1156         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
1157                                 VC4_HD_CSC_CTL_ORDER);
1158
1159         if (!vc4_hdmi_is_full_range(vc4_hdmi, mode)) {
1160                 /* CEA VICs other than #1 requre limited range RGB
1161                  * output unless overridden by an AVI infoframe.
1162                  * Apply a colorspace conversion to squash 0-255 down
1163                  * to 16-235.  The matrix here is:
1164                  *
1165                  * [ 0      0      0.8594 16]
1166                  * [ 0      0.8594 0      16]
1167                  * [ 0.8594 0      0      16]
1168                  * [ 0      0      0       1]
1169                  */
1170                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
1171                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
1172                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1173                                          VC4_HD_CSC_CTL_MODE);
1174
1175                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
1176                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
1177                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
1178                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
1179                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
1180                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
1181         }
1182
1183         /* The RGB order applies even when CSC is disabled. */
1184         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1185
1186         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1187
1188         drm_dev_exit(idx);
1189 }
1190
1191 /*
1192  * If we need to output Full Range RGB, then use the unity matrix
1193  *
1194  * [ 1      0      0      0]
1195  * [ 0      1      0      0]
1196  * [ 0      0      1      0]
1197  *
1198  * CEA VICs other than #1 require limited range RGB output unless
1199  * overridden by an AVI infoframe. Apply a colorspace conversion to
1200  * squash 0-255 down to 16-235. The matrix here is:
1201  *
1202  * [ 0.8594 0      0      16]
1203  * [ 0      0.8594 0      16]
1204  * [ 0      0      0.8594 16]
1205  *
1206  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1207  */
1208 static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = {
1209         {
1210                 /* Full range - unity */
1211                 { 0x2000, 0x0000, 0x0000, 0x0000 },
1212                 { 0x0000, 0x2000, 0x0000, 0x0000 },
1213                 { 0x0000, 0x0000, 0x2000, 0x0000 },
1214         }, {
1215                 /* Limited range */
1216                 { 0x1b80, 0x0000, 0x0000, 0x0400 },
1217                 { 0x0000, 0x1b80, 0x0000, 0x0400 },
1218                 { 0x0000, 0x0000, 0x1b80, 0x0400 },
1219         }
1220 };
1221
1222 /*
1223  * Conversion between Full Range RGB and YUV using the BT.601 Colorspace
1224  *
1225  * Full range
1226  * [    0.299000   0.587000   0.114000   0.000000 ]
1227  * [   -0.168736  -0.331264   0.500000 128.000000 ]
1228  * [    0.500000  -0.418688  -0.081312 128.000000 ]
1229  *
1230  * Limited range
1231  * [    0.255785   0.502160   0.097523  16.000000 ]
1232  * [   -0.147644  -0.289856   0.437500 128.000000 ]
1233  * [    0.437500  -0.366352  -0.071148 128.000000 ]
1234  *
1235  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1236  */
1237 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = {
1238         {
1239                 /* Full range */
1240                 { 0x0991, 0x12c9, 0x03a6, 0x0000 },
1241                 { 0xfa9b, 0xf567, 0x1000, 0x2000 },
1242                 { 0x1000, 0xf29b, 0xfd67, 0x2000 },
1243         }, {
1244                 /* Limited range */
1245                 { 0x082f, 0x1012, 0x031f, 0x0400 },
1246                 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1247                 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1248         }
1249 };
1250
1251 /*
1252  * Conversion between Full Range RGB and YUV using the BT.709 Colorspace
1253  *
1254  * Full range
1255  * [    0.212600   0.715200   0.072200   0.000000 ]
1256  * [   -0.114572  -0.385428   0.500000 128.000000 ]
1257  * [    0.500000  -0.454153  -0.045847 128.000000 ]
1258  *
1259  * Limited range
1260  * [    0.181873   0.611831   0.061765  16.000000 ]
1261  * [   -0.100251  -0.337249   0.437500 128.000000 ]
1262  * [    0.437500  -0.397384  -0.040116 128.000000 ]
1263  *
1264  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1265  */
1266 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = {
1267         {
1268                 /* Full range */
1269                 { 0x06ce, 0x16e3, 0x024f, 0x0000 },
1270                 { 0xfc56, 0xf3ac, 0x1000, 0x2000 },
1271                 { 0x1000, 0xf179, 0xfe89, 0x2000 },
1272         }, {
1273                 /* Limited range        */
1274                 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1275                 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1276                 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1277         }
1278 };
1279
1280 /*
1281  * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace
1282  *
1283  * Full range
1284  * [    0.262700   0.678000   0.059300   0.000000 ]
1285  * [   -0.139630  -0.360370   0.500000 128.000000 ]
1286  * [    0.500000  -0.459786  -0.040214 128.000000 ]
1287  *
1288  * Limited range
1289  * [    0.224732   0.580008   0.050729  16.000000 ]
1290  * [   -0.122176  -0.315324   0.437500 128.000000 ]
1291  * [    0.437500  -0.402312  -0.035188 128.000000 ]
1292  *
1293  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
1294  */
1295 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = {
1296         {
1297                 /* Full range */
1298                 { 0x0868, 0x15b2, 0x01e6, 0x0000 },
1299                 { 0xfb89, 0xf479, 0x1000, 0x2000 },
1300                 { 0x1000, 0xf14a, 0xfeb8, 0x2000 },
1301         }, {
1302                 /* Limited range */
1303                 { 0x0731, 0x128f, 0x01a0, 0x0400 },
1304                 { 0xfc18, 0xf5ea, 0x0e00, 0x2000 },
1305                 { 0x0e00, 0xf321, 0xfee1, 0x2000 },
1306         }
1307 };
1308
1309 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1310                                     const u16 coeffs[3][4])
1311 {
1312         lockdep_assert_held(&vc4_hdmi->hw_lock);
1313
1314         HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1315         HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1316         HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1317         HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1318         HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1319         HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1320 }
1321
1322 static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi,
1323                                          const u16 coeffs[3][4])
1324 {
1325         lockdep_assert_held(&vc4_hdmi->hw_lock);
1326
1327         /* YUV444 needs the CSC matrices using the channels in a different order */
1328         HDMI_WRITE(HDMI_CSC_12_11, (coeffs[2][1] << 16) | coeffs[2][0]);
1329         HDMI_WRITE(HDMI_CSC_14_13, (coeffs[2][3] << 16) | coeffs[2][2]);
1330         HDMI_WRITE(HDMI_CSC_22_21, (coeffs[0][1] << 16) | coeffs[0][0]);
1331         HDMI_WRITE(HDMI_CSC_24_23, (coeffs[0][3] << 16) | coeffs[0][2]);
1332         HDMI_WRITE(HDMI_CSC_32_31, (coeffs[1][1] << 16) | coeffs[1][0]);
1333         HDMI_WRITE(HDMI_CSC_34_33, (coeffs[1][3] << 16) | coeffs[1][2]);
1334 }
1335
1336 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1337                                struct drm_connector_state *state,
1338                                const struct drm_display_mode *mode)
1339 {
1340         struct drm_device *drm = vc4_hdmi->connector.dev;
1341         struct vc4_hdmi_connector_state *vc4_state =
1342                 conn_state_to_vc4_hdmi_conn_state(state);
1343         unsigned int lim_range = vc4_hdmi_is_full_range(vc4_hdmi, mode) ? 0 : 1;
1344         const u16 (*csc)[4];
1345         unsigned long flags;
1346         u32 if_cfg = 0;
1347         u32 if_xbar = 0x543210;
1348         u32 csc_chan_ctl = 0;
1349         u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1350                                                                VC5_MT_CP_CSC_CTL_MODE);
1351         int idx;
1352
1353         if (!drm_dev_enter(drm, &idx))
1354                 return;
1355
1356         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1357
1358         switch (vc4_state->output_format) {
1359         case VC4_HDMI_OUTPUT_YUV444:
1360         case VC4_HDMI_OUTPUT_YUV422:
1361                 switch (state->colorspace) {
1362                 default:
1363                 case DRM_MODE_COLORIMETRY_NO_DATA:
1364                 case DRM_MODE_COLORIMETRY_BT709_YCC:
1365                 case DRM_MODE_COLORIMETRY_XVYCC_709:
1366                 case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED:
1367                 case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT:
1368                         csc = vc5_hdmi_csc_full_rgb_to_yuv_bt709[lim_range];
1369                         break;
1370                 case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC:
1371                 case DRM_MODE_COLORIMETRY_XVYCC_601:
1372                 case DRM_MODE_COLORIMETRY_SYCC_601:
1373                 case DRM_MODE_COLORIMETRY_OPYCC_601:
1374                 case DRM_MODE_COLORIMETRY_BT601_YCC:
1375                         csc = vc5_hdmi_csc_full_rgb_to_yuv_bt601[lim_range];
1376                         break;
1377                 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1378                 case DRM_MODE_COLORIMETRY_BT2020_YCC:
1379                 case DRM_MODE_COLORIMETRY_BT2020_RGB:
1380                 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1381                 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1382                         csc = vc5_hdmi_csc_full_rgb_to_yuv_bt2020[lim_range];
1383                         break;
1384                 }
1385
1386                 if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {
1387                         csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1388                                                  VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1389                                 VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1390                                 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1391
1392                         csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1393                                                       VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1394
1395                         if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1396                                                 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1397
1398                         vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc);
1399                 } else {
1400                         vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc);
1401                 }
1402
1403                 break;
1404
1405         case VC4_HDMI_OUTPUT_RGB:
1406                 if_xbar = 0x354021;
1407
1408                 vc5_hdmi_set_csc_coeffs(vc4_hdmi,
1409                                         vc5_hdmi_csc_full_rgb_to_rgb[lim_range]);
1410                 break;
1411
1412         default:
1413                 break;
1414         }
1415
1416         HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1417         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1418         HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1419         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1420
1421         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1422
1423         drm_dev_exit(idx);
1424 }
1425
1426 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1427                                  struct drm_connector_state *state,
1428                                  const struct drm_display_mode *mode)
1429 {
1430         struct drm_device *drm = vc4_hdmi->connector.dev;
1431         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1432         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1433         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1434         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1435         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1436                                    VC4_HDMI_VERTA_VSP) |
1437                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1438                                    VC4_HDMI_VERTA_VFP) |
1439                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1440         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1441                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1442                                    interlaced,
1443                                    VC4_HDMI_VERTB_VBP));
1444         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1445                           VC4_SET_FIELD(mode->crtc_vtotal -
1446                                         mode->crtc_vsync_end,
1447                                         VC4_HDMI_VERTB_VBP));
1448         unsigned long flags;
1449         u32 reg;
1450         int idx;
1451
1452         if (!drm_dev_enter(drm, &idx))
1453                 return;
1454
1455         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1456
1457         HDMI_WRITE(HDMI_HORZA,
1458                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1459                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1460                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1461                                  VC4_HDMI_HORZA_HAP));
1462
1463         HDMI_WRITE(HDMI_HORZB,
1464                    VC4_SET_FIELD((mode->htotal -
1465                                   mode->hsync_end) * pixel_rep,
1466                                  VC4_HDMI_HORZB_HBP) |
1467                    VC4_SET_FIELD((mode->hsync_end -
1468                                   mode->hsync_start) * pixel_rep,
1469                                  VC4_HDMI_HORZB_HSP) |
1470                    VC4_SET_FIELD((mode->hsync_start -
1471                                   mode->hdisplay) * pixel_rep,
1472                                  VC4_HDMI_HORZB_HFP));
1473
1474         HDMI_WRITE(HDMI_VERTA0, verta);
1475         HDMI_WRITE(HDMI_VERTA1, verta);
1476
1477         HDMI_WRITE(HDMI_VERTB0, vertb_even);
1478         HDMI_WRITE(HDMI_VERTB1, vertb);
1479
1480         reg = HDMI_READ(HDMI_MISC_CONTROL);
1481         reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1482         reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1483         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1484
1485         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1486
1487         drm_dev_exit(idx);
1488 }
1489
1490 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1491                                  struct drm_connector_state *state,
1492                                  const struct drm_display_mode *mode)
1493 {
1494         struct drm_device *drm = vc4_hdmi->connector.dev;
1495         const struct vc4_hdmi_connector_state *vc4_state =
1496                 conn_state_to_vc4_hdmi_conn_state(state);
1497         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1498         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1499         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1500         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1501         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1502                                    VC5_HDMI_VERTA_VSP) |
1503                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1504                                    VC5_HDMI_VERTA_VFP) |
1505                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1506         u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1507                                    VC5_HDMI_VERTB_VSPO) |
1508                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1509                                    interlaced,
1510                                    VC4_HDMI_VERTB_VBP));
1511         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1512                           VC4_SET_FIELD(mode->crtc_vtotal -
1513                                         mode->crtc_vsync_end,
1514                                         VC4_HDMI_VERTB_VBP));
1515         unsigned long flags;
1516         unsigned char gcp;
1517         bool gcp_en;
1518         u32 reg;
1519         int idx;
1520
1521         if (!drm_dev_enter(drm, &idx))
1522                 return;
1523
1524         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1525
1526         HDMI_WRITE(HDMI_HORZA,
1527                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1528                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1529                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1530                                  VC5_HDMI_HORZA_HAP) |
1531                    VC4_SET_FIELD((mode->hsync_start -
1532                                   mode->hdisplay) * pixel_rep,
1533                                  VC5_HDMI_HORZA_HFP));
1534
1535         HDMI_WRITE(HDMI_HORZB,
1536                    VC4_SET_FIELD((mode->htotal -
1537                                   mode->hsync_end) * pixel_rep,
1538                                  VC5_HDMI_HORZB_HBP) |
1539                    VC4_SET_FIELD((mode->hsync_end -
1540                                   mode->hsync_start) * pixel_rep,
1541                                  VC5_HDMI_HORZB_HSP));
1542
1543         HDMI_WRITE(HDMI_VERTA0, verta);
1544         HDMI_WRITE(HDMI_VERTA1, verta);
1545
1546         HDMI_WRITE(HDMI_VERTB0, vertb_even);
1547         HDMI_WRITE(HDMI_VERTB1, vertb);
1548
1549         switch (vc4_state->output_bpc) {
1550         case 12:
1551                 gcp = 6;
1552                 gcp_en = true;
1553                 break;
1554         case 10:
1555                 gcp = 5;
1556                 gcp_en = true;
1557                 break;
1558         case 8:
1559         default:
1560                 gcp = 4;
1561                 gcp_en = false;
1562                 break;
1563         }
1564
1565         /*
1566          * YCC422 is always 36-bit and not considered deep colour so
1567          * doesn't signal in GCP
1568          */
1569         if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {
1570                 gcp = 4;
1571                 gcp_en = false;
1572         }
1573
1574         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1575         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1576                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1577         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1578                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1579         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1580
1581         reg = HDMI_READ(HDMI_GCP_WORD_1);
1582         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1583         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1584         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1585
1586         reg = HDMI_READ(HDMI_GCP_CONFIG);
1587         reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1588         reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
1589         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1590
1591         reg = HDMI_READ(HDMI_MISC_CONTROL);
1592         reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1593         reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1594         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1595
1596         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1597
1598         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1599
1600         drm_dev_exit(idx);
1601 }
1602
1603 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1604 {
1605         struct drm_device *drm = vc4_hdmi->connector.dev;
1606         unsigned long flags;
1607         u32 drift;
1608         int ret;
1609         int idx;
1610
1611         if (!drm_dev_enter(drm, &idx))
1612                 return;
1613
1614         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1615
1616         drift = HDMI_READ(HDMI_FIFO_CTL);
1617         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1618
1619         HDMI_WRITE(HDMI_FIFO_CTL,
1620                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1621         HDMI_WRITE(HDMI_FIFO_CTL,
1622                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1623
1624         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1625
1626         usleep_range(1000, 1100);
1627
1628         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1629
1630         HDMI_WRITE(HDMI_FIFO_CTL,
1631                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1632         HDMI_WRITE(HDMI_FIFO_CTL,
1633                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1634
1635         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1636
1637         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1638                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1639         WARN_ONCE(ret, "Timeout waiting for "
1640                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1641
1642         drm_dev_exit(idx);
1643 }
1644
1645 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1646                                                 struct drm_atomic_state *state)
1647 {
1648         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1649         struct drm_device *drm = vc4_hdmi->connector.dev;
1650         struct drm_connector *connector = &vc4_hdmi->connector;
1651         struct drm_connector_state *conn_state =
1652                 drm_atomic_get_new_connector_state(state, connector);
1653         struct vc4_hdmi_connector_state *vc4_conn_state =
1654                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1655         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1656         unsigned long pixel_rate = vc4_conn_state->pixel_rate;
1657         unsigned long bvb_rate, hsm_rate;
1658         unsigned long flags;
1659         int ret;
1660         int idx;
1661
1662         mutex_lock(&vc4_hdmi->mutex);
1663
1664         if (!drm_dev_enter(drm, &idx))
1665                 goto out;
1666
1667         /*
1668          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1669          * be faster than pixel clock, infinitesimally faster, tested in
1670          * simulation. Otherwise, exact value is unimportant for HDMI
1671          * operation." This conflicts with bcm2835's vc4 documentation, which
1672          * states HSM's clock has to be at least 108% of the pixel clock.
1673          *
1674          * Real life tests reveal that vc4's firmware statement holds up, and
1675          * users are able to use pixel clocks closer to HSM's, namely for
1676          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1677          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1678          * 162MHz.
1679          *
1680          * Additionally, the AXI clock needs to be at least 25% of
1681          * pixel clock, but HSM ends up being the limiting factor.
1682          */
1683         hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
1684         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1685         if (ret) {
1686                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1687                 goto err_dev_exit;
1688         }
1689
1690         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1691         if (ret < 0) {
1692                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1693                 goto err_dev_exit;
1694         }
1695
1696         ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
1697         if (ret) {
1698                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1699                 goto err_put_runtime_pm;
1700         }
1701
1702         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1703         if (ret) {
1704                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1705                 goto err_put_runtime_pm;
1706         }
1707
1708
1709         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1710
1711         if (pixel_rate > 297000000)
1712                 bvb_rate = 300000000;
1713         else if (pixel_rate > 148500000)
1714                 bvb_rate = 150000000;
1715         else
1716                 bvb_rate = 75000000;
1717
1718         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1719         if (ret) {
1720                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1721                 goto err_disable_pixel_clock;
1722         }
1723
1724         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1725         if (ret) {
1726                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1727                 goto err_disable_pixel_clock;
1728         }
1729
1730         if (vc4_hdmi->variant->phy_init)
1731                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1732
1733         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1734
1735         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1736                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1737                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1738                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1739
1740         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1741
1742         if (vc4_hdmi->variant->set_timings)
1743                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1744
1745         drm_dev_exit(idx);
1746
1747         mutex_unlock(&vc4_hdmi->mutex);
1748
1749         return;
1750
1751 err_disable_pixel_clock:
1752         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1753 err_put_runtime_pm:
1754         pm_runtime_put(&vc4_hdmi->pdev->dev);
1755 err_dev_exit:
1756         drm_dev_exit(idx);
1757 out:
1758         mutex_unlock(&vc4_hdmi->mutex);
1759         return;
1760 }
1761
1762 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1763                                              struct drm_atomic_state *state)
1764 {
1765         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1766         struct drm_device *drm = vc4_hdmi->connector.dev;
1767         struct drm_connector *connector = &vc4_hdmi->connector;
1768         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1769         struct drm_connector_state *conn_state =
1770                 drm_atomic_get_new_connector_state(state, connector);
1771         unsigned long flags;
1772         int idx;
1773
1774         mutex_lock(&vc4_hdmi->mutex);
1775
1776         if (!drm_dev_enter(drm, &idx))
1777                 return;
1778
1779         if (vc4_hdmi->variant->csc_setup)
1780                 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1781
1782         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1783         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1784         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1785
1786         drm_dev_exit(idx);
1787
1788         mutex_unlock(&vc4_hdmi->mutex);
1789 }
1790
1791 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1792                                               struct drm_atomic_state *state)
1793 {
1794         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1795         struct drm_device *drm = vc4_hdmi->connector.dev;
1796         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1797         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1798         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1799         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1800         unsigned long flags;
1801         int ret;
1802         int idx;
1803
1804         mutex_lock(&vc4_hdmi->mutex);
1805
1806         if (!drm_dev_enter(drm, &idx))
1807                 return;
1808
1809         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1810
1811         HDMI_WRITE(HDMI_VID_CTL,
1812                    VC4_HD_VID_CTL_ENABLE |
1813                    VC4_HD_VID_CTL_CLRRGB |
1814                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1815                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1816                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1817                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1818
1819         HDMI_WRITE(HDMI_VID_CTL,
1820                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1821
1822         if (display->is_hdmi) {
1823                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1824                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1825                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1826
1827                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1828
1829                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1830                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1831                 WARN_ONCE(ret, "Timeout waiting for "
1832                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1833         } else {
1834                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1835                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1836                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1837                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1838                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1839                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1840
1841                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1842
1843                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1844                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1845                 WARN_ONCE(ret, "Timeout waiting for "
1846                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1847         }
1848
1849         if (display->is_hdmi) {
1850                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1851
1852                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1853                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1854
1855                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1856                            VC4_HDMI_RAM_PACKET_ENABLE);
1857
1858                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1859                 vc4_hdmi->output_enabled = true;
1860
1861                 vc4_hdmi_set_infoframes(encoder);
1862         }
1863
1864         vc4_hdmi_recenter_fifo(vc4_hdmi);
1865         vc4_hdmi_enable_scrambling(encoder);
1866
1867         drm_dev_exit(idx);
1868         mutex_unlock(&vc4_hdmi->mutex);
1869 }
1870
1871 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1872                                              struct drm_crtc_state *crtc_state,
1873                                              struct drm_connector_state *conn_state)
1874 {
1875         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1876         struct vc4_hdmi_connector_state *vc4_state =
1877                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1878
1879         mutex_lock(&vc4_hdmi->mutex);
1880         vc4_hdmi->output_bpc = vc4_state->output_bpc;
1881         vc4_hdmi->output_format = vc4_state->output_format;
1882         vc4_hdmi->broadcast_rgb = vc4_state->broadcast_rgb;
1883         memcpy(&vc4_hdmi->saved_adjusted_mode,
1884                &crtc_state->adjusted_mode,
1885                sizeof(vc4_hdmi->saved_adjusted_mode));
1886         mutex_unlock(&vc4_hdmi->mutex);
1887 }
1888
1889 static bool
1890 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi,
1891                                   const struct drm_display_info *info,
1892                                   const struct drm_display_mode *mode,
1893                                   unsigned int format, unsigned int bpc)
1894 {
1895         struct drm_device *dev = vc4_hdmi->connector.dev;
1896         u8 vic = drm_match_cea_mode(mode);
1897
1898         if (vic == 1 && bpc != 8) {
1899                 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc);
1900                 return false;
1901         }
1902
1903         if (!info->is_hdmi &&
1904             (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) {
1905                 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n");
1906                 return false;
1907         }
1908
1909         switch (format) {
1910         case VC4_HDMI_OUTPUT_RGB:
1911                 drm_dbg(dev, "RGB Format, checking the constraints.\n");
1912
1913                 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1914                         drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1915                         return false;
1916                 }
1917
1918                 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1919                         drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1920                         return false;
1921                 }
1922
1923                 drm_dbg(dev, "RGB format supported in that configuration.\n");
1924
1925                 return true;
1926
1927         case VC4_HDMI_OUTPUT_YUV422:
1928                 drm_dbg(dev, "YUV422 format, checking the constraints.\n");
1929
1930                 if (!(info->color_formats & DRM_COLOR_FORMAT_YCRCB422)) {
1931                         drm_dbg(dev, "Sink doesn't support YUV422.\n");
1932                         return false;
1933                 }
1934
1935                 if (bpc != 12) {
1936                         drm_dbg(dev, "YUV422 only supports 12 bpc.\n");
1937                         return false;
1938                 }
1939
1940                 drm_dbg(dev, "YUV422 format supported in that configuration.\n");
1941
1942                 return true;
1943
1944         case VC4_HDMI_OUTPUT_YUV444:
1945                 drm_dbg(dev, "YUV444 format, checking the constraints.\n");
1946
1947                 if (!(info->color_formats & DRM_COLOR_FORMAT_YCRCB444)) {
1948                         drm_dbg(dev, "Sink doesn't support YUV444.\n");
1949                         return false;
1950                 }
1951
1952                 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1953                         drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1954                         return false;
1955                 }
1956
1957                 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1958                         drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1959                         return false;
1960                 }
1961
1962                 drm_dbg(dev, "YUV444 format supported in that configuration.\n");
1963
1964                 return true;
1965         }
1966
1967         return false;
1968 }
1969
1970 static enum drm_mode_status
1971 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
1972                              const struct drm_display_mode *mode,
1973                              unsigned long long clock)
1974 {
1975         const struct drm_connector *connector = &vc4_hdmi->connector;
1976         const struct drm_display_info *info = &connector->display_info;
1977         struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
1978
1979         if (clock > vc4_hdmi->variant->max_pixel_clock)
1980                 return MODE_CLOCK_HIGH;
1981
1982         if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK)
1983                 return MODE_CLOCK_HIGH;
1984
1985         /* 4096x2160@60 is not reliable without overclocking core */
1986         if (!vc4->hvs->vc5_hdmi_enable_4096by2160 &&
1987             mode->hdisplay > 3840 && mode->vdisplay >= 2160 &&
1988             drm_mode_vrefresh(mode) >= 50)
1989                 return MODE_CLOCK_HIGH;
1990
1991         if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000))
1992                 return MODE_CLOCK_HIGH;
1993
1994         return MODE_OK;
1995 }
1996
1997 static unsigned long long
1998 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
1999                                     unsigned int bpc,
2000                                     enum vc4_hdmi_output_format fmt)
2001 {
2002         unsigned long long clock = mode->clock * 1000;
2003
2004         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2005                 clock = clock * 2;
2006
2007         if (fmt == VC4_HDMI_OUTPUT_YUV422)
2008                 bpc = 8;
2009
2010         return clock * bpc / 8;
2011 }
2012
2013 static int
2014 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
2015                                struct vc4_hdmi_connector_state *vc4_state,
2016                                const struct drm_display_mode *mode,
2017                                unsigned int bpc, unsigned int fmt)
2018 {
2019         unsigned long long clock;
2020
2021         clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
2022         if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, clock) != MODE_OK)
2023                 return -EINVAL;
2024
2025         vc4_state->pixel_rate = clock;
2026
2027         return 0;
2028 }
2029
2030 static int
2031 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi,
2032                                 struct vc4_hdmi_connector_state *vc4_state,
2033                                 const struct drm_display_mode *mode,
2034                                 unsigned int bpc)
2035 {
2036         struct drm_device *dev = vc4_hdmi->connector.dev;
2037         const struct drm_connector *connector = &vc4_hdmi->connector;
2038         const struct drm_display_info *info = &connector->display_info;
2039         unsigned int format;
2040
2041         drm_dbg(dev, "Trying with an RGB output\n");
2042
2043         format = VC4_HDMI_OUTPUT_RGB;
2044         if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
2045                 int ret;
2046
2047                 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
2048                                                      mode, bpc, format);
2049                 if (!ret) {
2050                         vc4_state->output_format = format;
2051                         return 0;
2052                 }
2053         }
2054
2055         drm_dbg(dev, "Failed, Trying with an YUV422 output\n");
2056
2057         format = VC4_HDMI_OUTPUT_YUV422;
2058         if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
2059                 int ret;
2060
2061                 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
2062                                                      mode, bpc, format);
2063                 if (!ret) {
2064                         vc4_state->output_format = format;
2065                         return 0;
2066                 }
2067         }
2068
2069         drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n");
2070
2071         return -EINVAL;
2072 }
2073
2074 static int
2075 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi,
2076                                 struct vc4_hdmi_connector_state *vc4_state,
2077                                 const struct drm_display_mode *mode)
2078 {
2079         struct drm_device *dev = vc4_hdmi->connector.dev;
2080         struct drm_connector_state *conn_state = &vc4_state->base;
2081         unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12);
2082         unsigned int bpc;
2083         int ret;
2084
2085         for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
2086                 drm_dbg(dev, "Trying with a %d bpc output\n", bpc);
2087
2088                 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state,
2089                                                       mode, bpc);
2090                 if (ret)
2091                         continue;
2092
2093                 vc4_state->output_bpc = bpc;
2094
2095                 drm_dbg(dev,
2096                         "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n",
2097                         mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
2098                         vc4_state->output_bpc,
2099                         vc4_hdmi_output_fmt_str(vc4_state->output_format),
2100                         vc4_state->pixel_rate);
2101
2102                 break;
2103         }
2104
2105         return ret;
2106 }
2107
2108 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
2109 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
2110
2111 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
2112                                          struct drm_crtc_state *crtc_state,
2113                                          struct drm_connector_state *conn_state)
2114 {
2115         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
2116         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
2117         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
2118         struct drm_connector *connector = &vc4_hdmi->connector;
2119         struct drm_connector_state *old_conn_state = drm_atomic_get_old_connector_state(conn_state->state, connector);
2120         struct vc4_hdmi_connector_state *old_vc4_state = conn_state_to_vc4_hdmi_conn_state(old_conn_state);
2121         unsigned long long pixel_rate = mode->clock * 1000;
2122         unsigned long long tmds_rate;
2123         int ret;
2124
2125         if (vc4_hdmi->variant->unsupported_odd_h_timings) {
2126                 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2127                         /* Only try to fixup DBLCLK modes to get 480i and 576i
2128                          * working.
2129                          * A generic solution for all modes with odd horizontal
2130                          * timing values seems impossible based on trying to
2131                          * solve it for 1366x768 monitors.
2132                          */
2133                         if ((mode->hsync_start - mode->hdisplay) & 1)
2134                                 mode->hsync_start--;
2135                         if ((mode->hsync_end - mode->hsync_start) & 1)
2136                                 mode->hsync_end--;
2137                 }
2138
2139                 /* Now check whether we still have odd values remaining */
2140                 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
2141                     (mode->hsync_end % 2) || (mode->htotal % 2))
2142                         return -EINVAL;
2143         }
2144
2145         /*
2146          * The 1440p@60 pixel rate is in the same range than the first
2147          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
2148          * bandwidth). Slightly lower the frequency to bring it out of
2149          * the WiFi range.
2150          */
2151         tmds_rate = pixel_rate * 10;
2152         if (vc4_hdmi->disable_wifi_frequencies &&
2153             (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
2154              tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
2155                 mode->clock = 238560;
2156                 pixel_rate = mode->clock * 1000;
2157         }
2158
2159         ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode);
2160         if (ret)
2161                 return ret;
2162
2163         /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */
2164         if (vc4_state->output_bpc != old_vc4_state->output_bpc ||
2165             vc4_state->output_format != old_vc4_state->output_format)
2166                 crtc_state->mode_changed = true;
2167
2168         return 0;
2169 }
2170
2171 static enum drm_mode_status
2172 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
2173                             const struct drm_display_mode *mode)
2174 {
2175         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
2176
2177         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
2178             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
2179             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
2180              (mode->hsync_end % 2) || (mode->htotal % 2)))
2181                 return MODE_H_ILLEGAL;
2182
2183         return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, mode->clock * 1000);
2184 }
2185
2186 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
2187         .atomic_check = vc4_hdmi_encoder_atomic_check,
2188         .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
2189         .mode_valid = vc4_hdmi_encoder_mode_valid,
2190 };
2191
2192 static int vc4_hdmi_late_register(struct drm_encoder *encoder)
2193 {
2194         struct drm_device *drm = encoder->dev;
2195         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
2196         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2197         int ret;
2198
2199         ret = vc4_debugfs_add_file(drm->primary, variant->debugfs_name,
2200                                    vc4_hdmi_debugfs_regs,
2201                                    vc4_hdmi);
2202         if (ret)
2203                 return ret;
2204
2205         return 0;
2206 }
2207
2208 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
2209         .late_register = vc4_hdmi_late_register,
2210 };
2211
2212 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2213 {
2214         int i;
2215         u32 channel_map = 0;
2216
2217         for (i = 0; i < 8; i++) {
2218                 if (channel_mask & BIT(i))
2219                         channel_map |= i << (3 * i);
2220         }
2221         return channel_map;
2222 }
2223
2224 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2225 {
2226         int i;
2227         u32 channel_map = 0;
2228
2229         for (i = 0; i < 8; i++) {
2230                 if (channel_mask & BIT(i))
2231                         channel_map |= i << (4 * i);
2232         }
2233         return channel_map;
2234 }
2235
2236 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
2237 {
2238         struct drm_device *drm = vc4_hdmi->connector.dev;
2239         unsigned long flags;
2240         u32 hotplug;
2241         int idx;
2242
2243         if (!drm_dev_enter(drm, &idx))
2244                 return false;
2245
2246         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2247         hotplug = HDMI_READ(HDMI_HOTPLUG);
2248         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2249
2250         drm_dev_exit(idx);
2251
2252         return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
2253 }
2254
2255 /* HDMI audio codec callbacks */
2256 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
2257                                          unsigned int samplerate)
2258 {
2259         struct drm_device *drm = vc4_hdmi->connector.dev;
2260         u32 hsm_clock;
2261         unsigned long flags;
2262         unsigned long n, m;
2263         int idx;
2264
2265         if (!drm_dev_enter(drm, &idx))
2266                 return;
2267
2268         hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
2269         rational_best_approximation(hsm_clock, samplerate,
2270                                     VC4_HD_MAI_SMP_N_MASK >>
2271                                     VC4_HD_MAI_SMP_N_SHIFT,
2272                                     (VC4_HD_MAI_SMP_M_MASK >>
2273                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
2274                                     &n, &m);
2275
2276         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2277         HDMI_WRITE(HDMI_MAI_SMP,
2278                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
2279                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
2280         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2281
2282         drm_dev_exit(idx);
2283 }
2284
2285 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
2286 {
2287         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
2288         u32 n, cts;
2289         u64 tmp;
2290
2291         lockdep_assert_held(&vc4_hdmi->mutex);
2292         lockdep_assert_held(&vc4_hdmi->hw_lock);
2293
2294         n = 128 * samplerate / 1000;
2295         tmp = (u64)(mode->clock * 1000) * n;
2296         do_div(tmp, 128 * samplerate);
2297         cts = tmp;
2298
2299         HDMI_WRITE(HDMI_CRP_CFG,
2300                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
2301                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
2302
2303         /*
2304          * We could get slightly more accurate clocks in some cases by
2305          * providing a CTS_1 value.  The two CTS values are alternated
2306          * between based on the period fields
2307          */
2308         HDMI_WRITE(HDMI_CTS_0, cts);
2309         HDMI_WRITE(HDMI_CTS_1, cts);
2310 }
2311
2312 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
2313 {
2314         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
2315
2316         return snd_soc_card_get_drvdata(card);
2317 }
2318
2319 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
2320 {
2321         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
2322
2323         lockdep_assert_held(&vc4_hdmi->mutex);
2324
2325         /*
2326          * If the encoder is currently in DVI mode, treat the codec DAI
2327          * as missing.
2328          */
2329         if (!display->is_hdmi)
2330                 return false;
2331
2332         return true;
2333 }
2334
2335 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
2336 {
2337         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2338         struct drm_device *drm = vc4_hdmi->connector.dev;
2339         unsigned long flags;
2340         int ret = 0;
2341         int idx;
2342
2343         mutex_lock(&vc4_hdmi->mutex);
2344
2345         if (!drm_dev_enter(drm, &idx)) {
2346                 ret = -ENODEV;
2347                 goto out;
2348         }
2349
2350         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2351                 ret = -ENODEV;
2352                 goto out_dev_exit;
2353         }
2354
2355         vc4_hdmi->audio.streaming = true;
2356
2357         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2358         HDMI_WRITE(HDMI_MAI_CTL,
2359                    VC4_HD_MAI_CTL_RESET |
2360                    VC4_HD_MAI_CTL_FLUSH |
2361                    VC4_HD_MAI_CTL_DLATE |
2362                    VC4_HD_MAI_CTL_ERRORE |
2363                    VC4_HD_MAI_CTL_ERRORF);
2364         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2365
2366         if (vc4_hdmi->variant->phy_rng_enable)
2367                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
2368
2369 out_dev_exit:
2370         drm_dev_exit(idx);
2371 out:
2372         mutex_unlock(&vc4_hdmi->mutex);
2373
2374         return ret;
2375 }
2376
2377 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
2378 {
2379         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2380         struct device *dev = &vc4_hdmi->pdev->dev;
2381         unsigned long flags;
2382         int ret;
2383
2384         lockdep_assert_held(&vc4_hdmi->mutex);
2385
2386         vc4_hdmi->audio.streaming = false;
2387         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
2388         if (ret)
2389                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
2390
2391         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2392
2393         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
2394         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
2395         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
2396
2397         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2398 }
2399
2400 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
2401 {
2402         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2403         struct drm_device *drm = vc4_hdmi->connector.dev;
2404         unsigned long flags;
2405         int idx;
2406
2407         mutex_lock(&vc4_hdmi->mutex);
2408
2409         if (!drm_dev_enter(drm, &idx))
2410                 goto out;
2411
2412         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2413
2414         HDMI_WRITE(HDMI_MAI_CTL,
2415                    VC4_HD_MAI_CTL_DLATE |
2416                    VC4_HD_MAI_CTL_ERRORE |
2417                    VC4_HD_MAI_CTL_ERRORF);
2418
2419         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2420
2421         if (vc4_hdmi->variant->phy_rng_disable)
2422                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
2423
2424         vc4_hdmi->audio.streaming = false;
2425         vc4_hdmi_audio_reset(vc4_hdmi);
2426
2427         drm_dev_exit(idx);
2428
2429 out:
2430         mutex_unlock(&vc4_hdmi->mutex);
2431 }
2432
2433 static int sample_rate_to_mai_fmt(int samplerate)
2434 {
2435         switch (samplerate) {
2436         case 8000:
2437                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
2438         case 11025:
2439                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
2440         case 12000:
2441                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
2442         case 16000:
2443                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
2444         case 22050:
2445                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
2446         case 24000:
2447                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
2448         case 32000:
2449                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
2450         case 44100:
2451                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
2452         case 48000:
2453                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
2454         case 64000:
2455                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
2456         case 88200:
2457                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
2458         case 96000:
2459                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
2460         case 128000:
2461                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2462         case 176400:
2463                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2464         case 192000:
2465                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2466         default:
2467                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2468         }
2469 }
2470
2471 /* HDMI audio codec callbacks */
2472 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
2473                                   struct hdmi_codec_daifmt *daifmt,
2474                                   struct hdmi_codec_params *params)
2475 {
2476         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2477         struct drm_device *drm = vc4_hdmi->connector.dev;
2478         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2479         unsigned int sample_rate = params->sample_rate;
2480         unsigned int channels = params->channels;
2481         unsigned long flags;
2482         u32 audio_packet_config, channel_mask;
2483         u32 channel_map;
2484         u32 mai_audio_format;
2485         u32 mai_sample_rate;
2486         int ret = 0;
2487         int idx;
2488
2489         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2490                 sample_rate, params->sample_width, channels);
2491
2492         mutex_lock(&vc4_hdmi->mutex);
2493
2494         if (!drm_dev_enter(drm, &idx)) {
2495                 ret = -ENODEV;
2496                 goto out;
2497         }
2498
2499         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2500                 ret = -EINVAL;
2501                 goto out_dev_exit;
2502         }
2503
2504         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2505
2506         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2507         HDMI_WRITE(HDMI_MAI_CTL,
2508                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2509                    VC4_HD_MAI_CTL_WHOLSMP |
2510                    VC4_HD_MAI_CTL_CHALIGN |
2511                    VC4_HD_MAI_CTL_ENABLE);
2512
2513         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2514         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2515             params->channels == 8)
2516                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2517         else
2518                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2519         HDMI_WRITE(HDMI_MAI_FMT,
2520                    VC4_SET_FIELD(mai_sample_rate,
2521                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2522                    VC4_SET_FIELD(mai_audio_format,
2523                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2524
2525         /* The B frame identifier should match the value used by alsa-lib (8) */
2526         audio_packet_config =
2527                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2528                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2529                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2530
2531         channel_mask = GENMASK(channels - 1, 0);
2532         audio_packet_config |= VC4_SET_FIELD(channel_mask,
2533                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2534
2535         /* Set the MAI threshold */
2536         HDMI_WRITE(HDMI_MAI_THR,
2537                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
2538                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
2539                    VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
2540                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
2541
2542         HDMI_WRITE(HDMI_MAI_CONFIG,
2543                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2544                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2545                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2546
2547         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2548         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2549         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2550
2551         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2552
2553         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2554
2555         memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
2556         if (vc4_hdmi->output_enabled)
2557                 vc4_hdmi_set_audio_infoframe(encoder);
2558
2559 out_dev_exit:
2560         drm_dev_exit(idx);
2561 out:
2562         mutex_unlock(&vc4_hdmi->mutex);
2563
2564         return ret;
2565 }
2566
2567 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2568         .name = "vc4-hdmi-cpu-dai-component",
2569 };
2570
2571 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2572 {
2573         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2574
2575         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2576
2577         return 0;
2578 }
2579
2580 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2581         .name = "vc4-hdmi-cpu-dai",
2582         .probe  = vc4_hdmi_audio_cpu_dai_probe,
2583         .playback = {
2584                 .stream_name = "Playback",
2585                 .channels_min = 1,
2586                 .channels_max = 8,
2587                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2588                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2589                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2590                          SNDRV_PCM_RATE_192000,
2591                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2592         },
2593 };
2594
2595 static const struct snd_dmaengine_pcm_config pcm_conf = {
2596         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2597         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2598 };
2599
2600 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
2601                                   uint8_t *buf, size_t len)
2602 {
2603         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2604         struct drm_connector *connector = &vc4_hdmi->connector;
2605
2606         mutex_lock(&vc4_hdmi->mutex);
2607         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2608         mutex_unlock(&vc4_hdmi->mutex);
2609
2610         return 0;
2611 }
2612
2613 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
2614         .get_eld = vc4_hdmi_audio_get_eld,
2615         .prepare = vc4_hdmi_audio_prepare,
2616         .audio_shutdown = vc4_hdmi_audio_shutdown,
2617         .audio_startup = vc4_hdmi_audio_startup,
2618 };
2619
2620 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
2621         .ops = &vc4_hdmi_codec_ops,
2622         .max_i2s_channels = 8,
2623         .i2s = 1,
2624 };
2625
2626 static void vc4_hdmi_audio_codec_release(void *ptr)
2627 {
2628         struct vc4_hdmi *vc4_hdmi = ptr;
2629
2630         platform_device_unregister(vc4_hdmi->audio.codec_pdev);
2631         vc4_hdmi->audio.codec_pdev = NULL;
2632 }
2633
2634 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2635 {
2636         const struct vc4_hdmi_register *mai_data =
2637                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2638         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2639         struct snd_soc_card *card = &vc4_hdmi->audio.card;
2640         struct device *dev = &vc4_hdmi->pdev->dev;
2641         struct platform_device *codec_pdev;
2642         const __be32 *addr;
2643         int index;
2644         int ret;
2645         int len;
2646
2647         /*
2648          * ASoC makes it a bit hard to retrieve a pointer to the
2649          * vc4_hdmi structure. Registering the card will overwrite our
2650          * device drvdata with a pointer to the snd_soc_card structure,
2651          * which can then be used to retrieve whatever drvdata we want
2652          * to associate.
2653          *
2654          * However, that doesn't fly in the case where we wouldn't
2655          * register an ASoC card (because of an old DT that is missing
2656          * the dmas properties for example), then the card isn't
2657          * registered and the device drvdata wouldn't be set.
2658          *
2659          * We can deal with both cases by making sure a snd_soc_card
2660          * pointer and a vc4_hdmi structure are pointing to the same
2661          * memory address, so we can treat them indistinctly without any
2662          * issue.
2663          */
2664         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2665         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2666
2667         if (!of_find_property(dev->of_node, "dmas", &len) ||
2668             len == 0) {
2669                 dev_warn(dev,
2670                          "'dmas' DT property is missing or empty, no HDMI audio\n");
2671                 return 0;
2672         }
2673
2674         if (mai_data->reg != VC4_HD) {
2675                 WARN_ONCE(true, "MAI isn't in the HD block\n");
2676                 return -EINVAL;
2677         }
2678
2679         /*
2680          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2681          * the bus address specified in the DT, because the physical address
2682          * (the one returned by platform_get_resource()) is not appropriate
2683          * for DMA transfers.
2684          * This VC/MMU should probably be exposed to avoid this kind of hacks.
2685          */
2686         index = of_property_match_string(dev->of_node, "reg-names", "hd");
2687         /* Before BCM2711, we don't have a named register range */
2688         if (index < 0)
2689                 index = 1;
2690
2691         addr = of_get_address(dev->of_node, index, NULL, NULL);
2692
2693         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2694         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2695         vc4_hdmi->audio.dma_data.maxburst = 2;
2696
2697         /*
2698          * NOTE: Strictly speaking, we should probably use a DRM-managed
2699          * registration there to avoid removing all the audio components
2700          * by the time the driver doesn't have any user anymore.
2701          *
2702          * However, the ASoC core uses a number of devm_kzalloc calls
2703          * when registering, even when using non-device-managed
2704          * functions (such as in snd_soc_register_component()).
2705          *
2706          * If we call snd_soc_unregister_component() in a DRM-managed
2707          * action, the device-managed actions have already been executed
2708          * and thus we would access memory that has been freed.
2709          *
2710          * Using device-managed hooks here probably leaves us open to a
2711          * bunch of issues if userspace still has a handle on the ALSA
2712          * device when the device is removed. However, this is mitigated
2713          * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2714          * path to prevent the access to the device resources if it
2715          * isn't there anymore.
2716          *
2717          * Then, the vc4_hdmi structure is DRM-managed and thus only
2718          * freed whenever the last user has closed the DRM device file.
2719          * It should thus outlive ALSA in most situations.
2720          */
2721         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2722         if (ret) {
2723                 dev_err(dev, "Could not register PCM component: %d\n", ret);
2724                 return ret;
2725         }
2726
2727         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2728                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
2729         if (ret) {
2730                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2731                 return ret;
2732         }
2733
2734         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
2735                                                    PLATFORM_DEVID_AUTO,
2736                                                    &vc4_hdmi_codec_pdata,
2737                                                    sizeof(vc4_hdmi_codec_pdata));
2738         if (IS_ERR(codec_pdev)) {
2739                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
2740                 return PTR_ERR(codec_pdev);
2741         }
2742         vc4_hdmi->audio.codec_pdev = codec_pdev;
2743
2744         ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi);
2745         if (ret)
2746                 return ret;
2747
2748         dai_link->cpus          = &vc4_hdmi->audio.cpu;
2749         dai_link->codecs        = &vc4_hdmi->audio.codec;
2750         dai_link->platforms     = &vc4_hdmi->audio.platform;
2751
2752         dai_link->num_cpus      = 1;
2753         dai_link->num_codecs    = 1;
2754         dai_link->num_platforms = 1;
2755
2756         dai_link->name = "MAI";
2757         dai_link->stream_name = "MAI PCM";
2758         dai_link->codecs->dai_name = "i2s-hifi";
2759         dai_link->cpus->dai_name = dev_name(dev);
2760         dai_link->codecs->name = dev_name(&codec_pdev->dev);
2761         dai_link->platforms->name = dev_name(dev);
2762
2763         card->dai_link = dai_link;
2764         card->num_links = 1;
2765         card->name = vc4_hdmi->variant->card_name;
2766         card->driver_name = "vc4-hdmi";
2767         card->dev = dev;
2768         card->owner = THIS_MODULE;
2769
2770         /*
2771          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2772          * stores a pointer to the snd card object in dev->driver_data. This
2773          * means we cannot use it for something else. The hdmi back-pointer is
2774          * now stored in card->drvdata and should be retrieved with
2775          * snd_soc_card_get_drvdata() if needed.
2776          */
2777         snd_soc_card_set_drvdata(card, vc4_hdmi);
2778         ret = devm_snd_soc_register_card(dev, card);
2779         if (ret)
2780                 dev_err_probe(dev, ret, "Could not register sound card\n");
2781
2782         return ret;
2783
2784 }
2785
2786 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2787 {
2788         struct vc4_hdmi *vc4_hdmi = priv;
2789         struct drm_connector *connector = &vc4_hdmi->connector;
2790         struct drm_device *dev = connector->dev;
2791
2792         if (dev && dev->registered)
2793                 drm_connector_helper_hpd_irq_event(connector);
2794
2795         return IRQ_HANDLED;
2796 }
2797
2798 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2799 {
2800         struct drm_connector *connector = &vc4_hdmi->connector;
2801         struct platform_device *pdev = vc4_hdmi->pdev;
2802         int ret;
2803
2804         if (vc4_hdmi->variant->external_irq_controller) {
2805                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2806                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2807
2808                 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2809                                                 NULL,
2810                                                 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2811                                                 "vc4 hdmi hpd connected", vc4_hdmi);
2812                 if (ret)
2813                         return ret;
2814
2815                 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2816                                                 NULL,
2817                                                 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2818                                                 "vc4 hdmi hpd disconnected", vc4_hdmi);
2819                 if (ret)
2820                         return ret;
2821
2822                 connector->polled = DRM_CONNECTOR_POLL_HPD;
2823         }
2824
2825         return 0;
2826 }
2827
2828 #ifdef CONFIG_DRM_VC4_HDMI_CEC
2829 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2830 {
2831         struct vc4_hdmi *vc4_hdmi = priv;
2832
2833         if (vc4_hdmi->cec_rx_msg.len)
2834                 cec_received_msg(vc4_hdmi->cec_adap,
2835                                  &vc4_hdmi->cec_rx_msg);
2836
2837         return IRQ_HANDLED;
2838 }
2839
2840 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2841 {
2842         struct vc4_hdmi *vc4_hdmi = priv;
2843
2844         if (vc4_hdmi->cec_tx_ok) {
2845                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2846                                   0, 0, 0, 0);
2847         } else {
2848                 /*
2849                  * This CEC implementation makes 1 retry, so if we
2850                  * get a NACK, then that means it made 2 attempts.
2851                  */
2852                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2853                                   0, 2, 0, 0);
2854         }
2855         return IRQ_HANDLED;
2856 }
2857
2858 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2859 {
2860         struct vc4_hdmi *vc4_hdmi = priv;
2861         irqreturn_t ret;
2862
2863         if (vc4_hdmi->cec_irq_was_rx)
2864                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2865         else
2866                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2867
2868         return ret;
2869 }
2870
2871 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2872 {
2873         struct drm_device *dev = vc4_hdmi->connector.dev;
2874         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2875         unsigned int i;
2876
2877         lockdep_assert_held(&vc4_hdmi->hw_lock);
2878
2879         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2880                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2881
2882         if (msg->len > 16) {
2883                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2884                 return;
2885         }
2886
2887         for (i = 0; i < msg->len; i += 4) {
2888                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2889
2890                 msg->msg[i] = val & 0xff;
2891                 msg->msg[i + 1] = (val >> 8) & 0xff;
2892                 msg->msg[i + 2] = (val >> 16) & 0xff;
2893                 msg->msg[i + 3] = (val >> 24) & 0xff;
2894         }
2895 }
2896
2897 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2898 {
2899         u32 cntrl1;
2900
2901         /*
2902          * We don't need to protect the register access using
2903          * drm_dev_enter() there because the interrupt handler lifetime
2904          * is tied to the device itself, and not to the DRM device.
2905          *
2906          * So when the device will be gone, one of the first thing we
2907          * will be doing will be to unregister the interrupt handler,
2908          * and then unregister the DRM device. drm_dev_enter() would
2909          * thus always succeed if we are here.
2910          */
2911
2912         lockdep_assert_held(&vc4_hdmi->hw_lock);
2913
2914         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2915         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2916         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2917         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2918
2919         return IRQ_WAKE_THREAD;
2920 }
2921
2922 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2923 {
2924         struct vc4_hdmi *vc4_hdmi = priv;
2925         irqreturn_t ret;
2926
2927         spin_lock(&vc4_hdmi->hw_lock);
2928         ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2929         spin_unlock(&vc4_hdmi->hw_lock);
2930
2931         return ret;
2932 }
2933
2934 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2935 {
2936         u32 cntrl1;
2937
2938         lockdep_assert_held(&vc4_hdmi->hw_lock);
2939
2940         /*
2941          * We don't need to protect the register access using
2942          * drm_dev_enter() there because the interrupt handler lifetime
2943          * is tied to the device itself, and not to the DRM device.
2944          *
2945          * So when the device will be gone, one of the first thing we
2946          * will be doing will be to unregister the interrupt handler,
2947          * and then unregister the DRM device. drm_dev_enter() would
2948          * thus always succeed if we are here.
2949          */
2950
2951         vc4_hdmi->cec_rx_msg.len = 0;
2952         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2953         vc4_cec_read_msg(vc4_hdmi, cntrl1);
2954         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2955         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2956         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2957
2958         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2959
2960         return IRQ_WAKE_THREAD;
2961 }
2962
2963 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
2964 {
2965         struct vc4_hdmi *vc4_hdmi = priv;
2966         irqreturn_t ret;
2967
2968         spin_lock(&vc4_hdmi->hw_lock);
2969         ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2970         spin_unlock(&vc4_hdmi->hw_lock);
2971
2972         return ret;
2973 }
2974
2975 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2976 {
2977         struct vc4_hdmi *vc4_hdmi = priv;
2978         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2979         irqreturn_t ret;
2980         u32 cntrl5;
2981
2982         /*
2983          * We don't need to protect the register access using
2984          * drm_dev_enter() there because the interrupt handler lifetime
2985          * is tied to the device itself, and not to the DRM device.
2986          *
2987          * So when the device will be gone, one of the first thing we
2988          * will be doing will be to unregister the interrupt handler,
2989          * and then unregister the DRM device. drm_dev_enter() would
2990          * thus always succeed if we are here.
2991          */
2992
2993         if (!(stat & VC4_HDMI_CPU_CEC))
2994                 return IRQ_NONE;
2995
2996         spin_lock(&vc4_hdmi->hw_lock);
2997         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2998         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2999         if (vc4_hdmi->cec_irq_was_rx)
3000                 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
3001         else
3002                 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
3003
3004         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
3005         spin_unlock(&vc4_hdmi->hw_lock);
3006
3007         return ret;
3008 }
3009
3010 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
3011 {
3012         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
3013         struct drm_device *drm = vc4_hdmi->connector.dev;
3014         /* clock period in microseconds */
3015         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
3016         unsigned long flags;
3017         u32 val;
3018         int ret;
3019         int idx;
3020
3021         if (!drm_dev_enter(drm, &idx))
3022                 /*
3023                  * We can't return an error code, because the CEC
3024                  * framework will emit WARN_ON messages at unbind
3025                  * otherwise.
3026                  */
3027                 return 0;
3028
3029         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
3030         if (ret) {
3031                 drm_dev_exit(idx);
3032                 return ret;
3033         }
3034
3035         mutex_lock(&vc4_hdmi->mutex);
3036
3037         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3038
3039         val = HDMI_READ(HDMI_CEC_CNTRL_5);
3040         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
3041                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
3042                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
3043         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
3044                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
3045
3046         HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
3047                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
3048         HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
3049         HDMI_WRITE(HDMI_CEC_CNTRL_2,
3050                    ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
3051                    ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
3052                    ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
3053                    ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
3054                    ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
3055         HDMI_WRITE(HDMI_CEC_CNTRL_3,
3056                    ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
3057                    ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
3058                    ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
3059                    ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
3060         HDMI_WRITE(HDMI_CEC_CNTRL_4,
3061                    ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
3062                    ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
3063                    ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
3064                    ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
3065
3066         if (!vc4_hdmi->variant->external_irq_controller)
3067                 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
3068
3069         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3070
3071         mutex_unlock(&vc4_hdmi->mutex);
3072         drm_dev_exit(idx);
3073
3074         return 0;
3075 }
3076
3077 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
3078 {
3079         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
3080         struct drm_device *drm = vc4_hdmi->connector.dev;
3081         unsigned long flags;
3082         int idx;
3083
3084         if (!drm_dev_enter(drm, &idx))
3085                 /*
3086                  * We can't return an error code, because the CEC
3087                  * framework will emit WARN_ON messages at unbind
3088                  * otherwise.
3089                  */
3090                 return 0;
3091
3092         mutex_lock(&vc4_hdmi->mutex);
3093
3094         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3095
3096         if (!vc4_hdmi->variant->external_irq_controller)
3097                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
3098
3099         HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
3100                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
3101
3102         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3103
3104         mutex_unlock(&vc4_hdmi->mutex);
3105
3106         pm_runtime_put(&vc4_hdmi->pdev->dev);
3107
3108         drm_dev_exit(idx);
3109
3110         return 0;
3111 }
3112
3113 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
3114 {
3115         if (enable)
3116                 return vc4_hdmi_cec_enable(adap);
3117         else
3118                 return vc4_hdmi_cec_disable(adap);
3119 }
3120
3121 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
3122 {
3123         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
3124         struct drm_device *drm = vc4_hdmi->connector.dev;
3125         unsigned long flags;
3126         int idx;
3127
3128         if (!drm_dev_enter(drm, &idx))
3129                 /*
3130                  * We can't return an error code, because the CEC
3131                  * framework will emit WARN_ON messages at unbind
3132                  * otherwise.
3133                  */
3134                 return 0;
3135
3136         mutex_lock(&vc4_hdmi->mutex);
3137         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3138         HDMI_WRITE(HDMI_CEC_CNTRL_1,
3139                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
3140                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
3141         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3142         mutex_unlock(&vc4_hdmi->mutex);
3143
3144         drm_dev_exit(idx);
3145
3146         return 0;
3147 }
3148
3149 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
3150                                       u32 signal_free_time, struct cec_msg *msg)
3151 {
3152         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
3153         struct drm_device *dev = vc4_hdmi->connector.dev;
3154         unsigned long flags;
3155         u32 val;
3156         unsigned int i;
3157         int idx;
3158
3159         if (!drm_dev_enter(dev, &idx))
3160                 return -ENODEV;
3161
3162         if (msg->len > 16) {
3163                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
3164                 drm_dev_exit(idx);
3165                 return -ENOMEM;
3166         }
3167
3168         mutex_lock(&vc4_hdmi->mutex);
3169
3170         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3171
3172         for (i = 0; i < msg->len; i += 4)
3173                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
3174                            (msg->msg[i]) |
3175                            (msg->msg[i + 1] << 8) |
3176                            (msg->msg[i + 2] << 16) |
3177                            (msg->msg[i + 3] << 24));
3178
3179         val = HDMI_READ(HDMI_CEC_CNTRL_1);
3180         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
3181         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
3182         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
3183         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
3184         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
3185
3186         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
3187
3188         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3189         mutex_unlock(&vc4_hdmi->mutex);
3190         drm_dev_exit(idx);
3191
3192         return 0;
3193 }
3194
3195 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
3196         .adap_enable = vc4_hdmi_cec_adap_enable,
3197         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
3198         .adap_transmit = vc4_hdmi_cec_adap_transmit,
3199 };
3200
3201 static void vc4_hdmi_cec_release(void *ptr)
3202 {
3203         struct vc4_hdmi *vc4_hdmi = ptr;
3204
3205         cec_unregister_adapter(vc4_hdmi->cec_adap);
3206         vc4_hdmi->cec_adap = NULL;
3207 }
3208
3209 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3210 {
3211         struct cec_connector_info conn_info;
3212         struct platform_device *pdev = vc4_hdmi->pdev;
3213         struct device *dev = &pdev->dev;
3214         unsigned long flags;
3215         int ret;
3216
3217         if (!of_find_property(dev->of_node, "interrupts", NULL)) {
3218                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
3219                 return 0;
3220         }
3221
3222         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
3223                                                   vc4_hdmi, "vc4",
3224                                                   CEC_CAP_DEFAULTS |
3225                                                   CEC_CAP_CONNECTOR_INFO, 1);
3226         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
3227         if (ret < 0)
3228                 return ret;
3229
3230         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
3231         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
3232
3233         if (vc4_hdmi->variant->external_irq_controller) {
3234                 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
3235                                                 vc4_cec_irq_handler_rx_bare,
3236                                                 vc4_cec_irq_handler_rx_thread, 0,
3237                                                 "vc4 hdmi cec rx", vc4_hdmi);
3238                 if (ret)
3239                         goto err_delete_cec_adap;
3240
3241                 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
3242                                                 vc4_cec_irq_handler_tx_bare,
3243                                                 vc4_cec_irq_handler_tx_thread, 0,
3244                                                 "vc4 hdmi cec tx", vc4_hdmi);
3245                 if (ret)
3246                         goto err_delete_cec_adap;
3247         } else {
3248                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3249                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3250                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3251
3252                 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
3253                                                 vc4_cec_irq_handler,
3254                                                 vc4_cec_irq_handler_thread, 0,
3255                                                 "vc4 hdmi cec", vc4_hdmi);
3256                 if (ret)
3257                         goto err_delete_cec_adap;
3258         }
3259
3260         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
3261         if (ret < 0)
3262                 goto err_delete_cec_adap;
3263
3264         /*
3265          * NOTE: Strictly speaking, we should probably use a DRM-managed
3266          * registration there to avoid removing the CEC adapter by the
3267          * time the DRM driver doesn't have any user anymore.
3268          *
3269          * However, the CEC framework already cleans up the CEC adapter
3270          * only when the last user has closed its file descriptor, so we
3271          * don't need to handle it in DRM.
3272          *
3273          * By the time the device-managed hook is executed, we will give
3274          * up our reference to the CEC adapter and therefore don't
3275          * really care when it's actually freed.
3276          *
3277          * There's still a problematic sequence: if we unregister our
3278          * CEC adapter, but the userspace keeps a handle on the CEC
3279          * adapter but not the DRM device for some reason. In such a
3280          * case, our vc4_hdmi structure will be freed, but the
3281          * cec_adapter structure will have a dangling pointer to what
3282          * used to be our HDMI controller. If we get a CEC call at that
3283          * moment, we could end up with a use-after-free. Fortunately,
3284          * the CEC framework already handles this too, by calling
3285          * cec_is_registered() in cec_ioctl() and cec_poll().
3286          */
3287         ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
3288         if (ret)
3289                 return ret;
3290
3291         return 0;
3292
3293 err_delete_cec_adap:
3294         cec_delete_adapter(vc4_hdmi->cec_adap);
3295
3296         return ret;
3297 }
3298
3299 static int vc4_hdmi_cec_resume(struct vc4_hdmi *vc4_hdmi)
3300 {
3301         unsigned long flags;
3302         u32 value;
3303
3304         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3305         value = HDMI_READ(HDMI_CEC_CNTRL_1);
3306         /* Set the logical address to Unregistered */
3307         value |= VC4_HDMI_CEC_ADDR_MASK;
3308         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3309         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3310
3311         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3312
3313         if (!vc4_hdmi->variant->external_irq_controller) {
3314                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3315                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3316                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3317         }
3318
3319         return 0;
3320 }
3321 #else
3322 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3323 {
3324         return 0;
3325 }
3326
3327 static int vc4_hdmi_cec_resume(struct vc4_hdmi *vc4_hdmi)
3328 {
3329         return 0;
3330 }
3331 #endif
3332
3333 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
3334 {
3335         struct debugfs_reg32 *regs = ptr;
3336
3337         kfree(regs);
3338 }
3339
3340 static int vc4_hdmi_build_regset(struct drm_device *drm,
3341                                  struct vc4_hdmi *vc4_hdmi,
3342                                  struct debugfs_regset32 *regset,
3343                                  enum vc4_hdmi_regs reg)
3344 {
3345         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
3346         struct debugfs_reg32 *regs, *new_regs;
3347         unsigned int count = 0;
3348         unsigned int i;
3349         int ret;
3350
3351         regs = kcalloc(variant->num_registers, sizeof(*regs),
3352                        GFP_KERNEL);
3353         if (!regs)
3354                 return -ENOMEM;
3355
3356         for (i = 0; i < variant->num_registers; i++) {
3357                 const struct vc4_hdmi_register *field = &variant->registers[i];
3358
3359                 if (field->reg != reg)
3360                         continue;
3361
3362                 regs[count].name = field->name;
3363                 regs[count].offset = field->offset;
3364                 count++;
3365         }
3366
3367         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
3368         if (!new_regs)
3369                 return -ENOMEM;
3370
3371         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
3372         regset->regs = new_regs;
3373         regset->nregs = count;
3374
3375         ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
3376         if (ret)
3377                 return ret;
3378
3379         return 0;
3380 }
3381
3382 static int vc4_hdmi_init_resources(struct drm_device *drm,
3383                                    struct vc4_hdmi *vc4_hdmi)
3384 {
3385         struct platform_device *pdev = vc4_hdmi->pdev;
3386         struct device *dev = &pdev->dev;
3387         int ret;
3388
3389         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
3390         if (IS_ERR(vc4_hdmi->hdmicore_regs))
3391                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
3392
3393         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
3394         if (IS_ERR(vc4_hdmi->hd_regs))
3395                 return PTR_ERR(vc4_hdmi->hd_regs);
3396
3397         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3398         if (ret)
3399                 return ret;
3400
3401         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3402         if (ret)
3403                 return ret;
3404
3405         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
3406         if (IS_ERR(vc4_hdmi->pixel_clock)) {
3407                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
3408                 if (ret != -EPROBE_DEFER)
3409                         DRM_ERROR("Failed to get pixel clock\n");
3410                 return ret;
3411         }
3412
3413         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3414         if (IS_ERR(vc4_hdmi->hsm_clock)) {
3415                 DRM_ERROR("Failed to get HDMI state machine clock\n");
3416                 return PTR_ERR(vc4_hdmi->hsm_clock);
3417         }
3418         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
3419         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
3420
3421         return 0;
3422 }
3423
3424 static int vc5_hdmi_init_resources(struct drm_device *drm,
3425                                    struct vc4_hdmi *vc4_hdmi)
3426 {
3427         struct platform_device *pdev = vc4_hdmi->pdev;
3428         struct device *dev = &pdev->dev;
3429         struct resource *res;
3430         int ret;
3431
3432         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
3433         if (!res)
3434                 return -ENODEV;
3435
3436         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
3437                                                resource_size(res));
3438         if (!vc4_hdmi->hdmicore_regs)
3439                 return -ENOMEM;
3440
3441         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
3442         if (!res)
3443                 return -ENODEV;
3444
3445         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
3446         if (!vc4_hdmi->hd_regs)
3447                 return -ENOMEM;
3448
3449         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
3450         if (!res)
3451                 return -ENODEV;
3452
3453         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
3454         if (!vc4_hdmi->cec_regs)
3455                 return -ENOMEM;
3456
3457         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
3458         if (!res)
3459                 return -ENODEV;
3460
3461         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
3462         if (!vc4_hdmi->csc_regs)
3463                 return -ENOMEM;
3464
3465         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
3466         if (!res)
3467                 return -ENODEV;
3468
3469         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
3470         if (!vc4_hdmi->dvp_regs)
3471                 return -ENOMEM;
3472
3473         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
3474         if (!res)
3475                 return -ENODEV;
3476
3477         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
3478         if (!vc4_hdmi->phy_regs)
3479                 return -ENOMEM;
3480
3481         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
3482         if (!res)
3483                 return -ENODEV;
3484
3485         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
3486         if (!vc4_hdmi->ram_regs)
3487                 return -ENOMEM;
3488
3489         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
3490         if (!res)
3491                 return -ENODEV;
3492
3493         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
3494         if (!vc4_hdmi->rm_regs)
3495                 return -ENOMEM;
3496
3497         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3498         if (IS_ERR(vc4_hdmi->hsm_clock)) {
3499                 DRM_ERROR("Failed to get HDMI state machine clock\n");
3500                 return PTR_ERR(vc4_hdmi->hsm_clock);
3501         }
3502
3503         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3504         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3505                 DRM_ERROR("Failed to get pixel bvb clock\n");
3506                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3507         }
3508
3509         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3510         if (IS_ERR(vc4_hdmi->audio_clock)) {
3511                 DRM_ERROR("Failed to get audio clock\n");
3512                 return PTR_ERR(vc4_hdmi->audio_clock);
3513         }
3514
3515         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3516         if (IS_ERR(vc4_hdmi->cec_clock)) {
3517                 DRM_ERROR("Failed to get CEC clock\n");
3518                 return PTR_ERR(vc4_hdmi->cec_clock);
3519         }
3520
3521         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3522         if (IS_ERR(vc4_hdmi->reset)) {
3523                 DRM_ERROR("Failed to get HDMI reset line\n");
3524                 return PTR_ERR(vc4_hdmi->reset);
3525         }
3526
3527         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3528         if (ret)
3529                 return ret;
3530
3531         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3532         if (ret)
3533                 return ret;
3534
3535         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3536         if (ret)
3537                 return ret;
3538
3539         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3540         if (ret)
3541                 return ret;
3542
3543         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3544         if (ret)
3545                 return ret;
3546
3547         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3548         if (ret)
3549                 return ret;
3550
3551         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3552         if (ret)
3553                 return ret;
3554
3555         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3556         if (ret)
3557                 return ret;
3558
3559         return 0;
3560 }
3561
3562 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev)
3563 {
3564         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3565
3566         clk_disable_unprepare(vc4_hdmi->hsm_clock);
3567
3568         return 0;
3569 }
3570
3571 static int vc4_hdmi_runtime_resume(struct device *dev)
3572 {
3573         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3574         int ret;
3575
3576         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
3577         if (ret)
3578                 return ret;
3579
3580         if (vc4_hdmi->variant->reset)
3581                 vc4_hdmi->variant->reset(vc4_hdmi);
3582
3583         ret = vc4_hdmi_cec_resume(vc4_hdmi);
3584         if (ret) {
3585                 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3586                 return ret;
3587         }
3588
3589         return 0;
3590 }
3591
3592 static void vc4_hdmi_put_ddc_device(void *ptr)
3593 {
3594         struct vc4_hdmi *vc4_hdmi = ptr;
3595
3596         put_device(&vc4_hdmi->ddc->dev);
3597 }
3598
3599 #ifdef CONFIG_EXTCON
3600 static const unsigned int vc4_hdmi_extcon_cable[] = {
3601         EXTCON_DISP_HDMI,
3602         EXTCON_NONE,
3603 };
3604 #endif
3605
3606 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3607 {
3608         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3609         struct platform_device *pdev = to_platform_device(dev);
3610         struct drm_device *drm = dev_get_drvdata(master);
3611         struct vc4_hdmi *vc4_hdmi;
3612         struct drm_encoder *encoder;
3613         struct device_node *ddc_node;
3614         int ret;
3615
3616         vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3617         if (!vc4_hdmi)
3618                 return -ENOMEM;
3619
3620         ret = drmm_mutex_init(drm, &vc4_hdmi->mutex);
3621         if (ret)
3622                 return ret;
3623
3624         spin_lock_init(&vc4_hdmi->hw_lock);
3625         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3626
3627         dev_set_drvdata(dev, vc4_hdmi);
3628         encoder = &vc4_hdmi->encoder.base;
3629         vc4_hdmi->encoder.type = variant->encoder_type;
3630         vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3631         vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3632         vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3633         vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3634         vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3635         vc4_hdmi->pdev = pdev;
3636         vc4_hdmi->variant = variant;
3637
3638         /*
3639          * Since we don't know the state of the controller and its
3640          * display (if any), let's assume it's always enabled.
3641          * vc4_hdmi_disable_scrambling() will thus run at boot, make
3642          * sure it's disabled, and avoid any inconsistency.
3643          */
3644         if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3645                 vc4_hdmi->scdc_enabled = true;
3646
3647         ret = variant->init_resources(drm, vc4_hdmi);
3648         if (ret)
3649                 return ret;
3650
3651         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3652         if (!ddc_node) {
3653                 DRM_ERROR("Failed to find ddc node in device tree\n");
3654                 return -ENODEV;
3655         }
3656
3657         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3658         of_node_put(ddc_node);
3659         if (!vc4_hdmi->ddc) {
3660                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
3661                 return -EPROBE_DEFER;
3662         }
3663
3664         ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3665         if (ret)
3666                 return ret;
3667
3668 #ifdef CONFIG_EXTCON
3669         vc4_hdmi->status = connector_status_disconnected;
3670
3671         /* Initialize extcon device */
3672         vc4_hdmi->edev = devm_extcon_dev_allocate(dev, vc4_hdmi_extcon_cable);
3673         if (IS_ERR(vc4_hdmi->edev)) {
3674                 dev_err(dev, "failed to allocate memory for extcon\n");
3675                 return PTR_ERR(vc4_hdmi->edev);
3676         }
3677
3678         ret = devm_extcon_dev_register(dev, vc4_hdmi->edev);
3679         if (ret) {
3680                 dev_err(dev, "failed to register extcon device\n");
3681                 return ret;
3682         }
3683 #endif
3684
3685         /* Only use the GPIO HPD pin if present in the DT, otherwise
3686          * we'll use the HDMI core's register.
3687          */
3688         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3689         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3690                 return PTR_ERR(vc4_hdmi->hpd_gpio);
3691         }
3692
3693         vc4_hdmi->disable_wifi_frequencies =
3694                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3695
3696         /*
3697          * If we boot without any cable connected to the HDMI connector,
3698          * the firmware will skip the HSM initialization and leave it
3699          * with a rate of 0, resulting in a bus lockup when we're
3700          * accessing the registers even if it's enabled.
3701          *
3702          * Let's put a sensible default at runtime_resume so that we
3703          * don't end up in this situation.
3704          */
3705         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
3706         if (ret)
3707                 return ret;
3708
3709         ret = devm_pm_runtime_enable(dev);
3710         if (ret)
3711                 return ret;
3712
3713         ret = pm_runtime_resume_and_get(dev);
3714         if (ret)
3715                 return ret;
3716
3717         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3718              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
3719             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3720                 clk_prepare_enable(vc4_hdmi->pixel_clock);
3721                 clk_prepare_enable(vc4_hdmi->hsm_clock);
3722                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3723         }
3724
3725         ret = drmm_encoder_init(drm, encoder,
3726                                 &vc4_hdmi_encoder_funcs,
3727                                 DRM_MODE_ENCODER_TMDS,
3728                                 NULL);
3729         if (ret)
3730                 goto err_put_runtime_pm;
3731
3732         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3733
3734         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3735         if (ret)
3736                 goto err_put_runtime_pm;
3737
3738         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3739         if (ret)
3740                 goto err_put_runtime_pm;
3741
3742         ret = vc4_hdmi_cec_init(vc4_hdmi);
3743         if (ret)
3744                 goto err_put_runtime_pm;
3745
3746         ret = vc4_hdmi_audio_init(vc4_hdmi);
3747         if (ret)
3748                 goto err_put_runtime_pm;
3749
3750         pm_runtime_put_sync(dev);
3751
3752         return 0;
3753
3754 err_put_runtime_pm:
3755         pm_runtime_put_sync(dev);
3756
3757         return ret;
3758 }
3759
3760 static const struct component_ops vc4_hdmi_ops = {
3761         .bind   = vc4_hdmi_bind,
3762 };
3763
3764 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3765 {
3766         return component_add(&pdev->dev, &vc4_hdmi_ops);
3767 }
3768
3769 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
3770 {
3771         component_del(&pdev->dev, &vc4_hdmi_ops);
3772         return 0;
3773 }
3774
3775 static const struct vc4_hdmi_variant bcm2835_variant = {
3776         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3777         .debugfs_name           = "hdmi_regs",
3778         .card_name              = "vc4-hdmi",
3779         .max_pixel_clock        = 162000000,
3780         .registers              = vc4_hdmi_fields,
3781         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
3782
3783         .init_resources         = vc4_hdmi_init_resources,
3784         .csc_setup              = vc4_hdmi_csc_setup,
3785         .reset                  = vc4_hdmi_reset,
3786         .set_timings            = vc4_hdmi_set_timings,
3787         .phy_init               = vc4_hdmi_phy_init,
3788         .phy_disable            = vc4_hdmi_phy_disable,
3789         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
3790         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
3791         .channel_map            = vc4_hdmi_channel_map,
3792         .supports_hdr           = false,
3793 };
3794
3795 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3796         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3797         .debugfs_name           = "hdmi0_regs",
3798         .card_name              = "vc4-hdmi-0",
3799         .max_pixel_clock        = 600000000,
3800         .registers              = vc5_hdmi_hdmi0_fields,
3801         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3802         .phy_lane_mapping       = {
3803                 PHY_LANE_0,
3804                 PHY_LANE_1,
3805                 PHY_LANE_2,
3806                 PHY_LANE_CK,
3807         },
3808         .unsupported_odd_h_timings      = true,
3809         .external_irq_controller        = true,
3810
3811         .init_resources         = vc5_hdmi_init_resources,
3812         .csc_setup              = vc5_hdmi_csc_setup,
3813         .reset                  = vc5_hdmi_reset,
3814         .set_timings            = vc5_hdmi_set_timings,
3815         .phy_init               = vc5_hdmi_phy_init,
3816         .phy_disable            = vc5_hdmi_phy_disable,
3817         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
3818         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
3819         .channel_map            = vc5_hdmi_channel_map,
3820         .supports_hdr           = true,
3821         .hp_detect              = vc5_hdmi_hp_detect,
3822 };
3823
3824 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3825         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
3826         .debugfs_name           = "hdmi1_regs",
3827         .card_name              = "vc4-hdmi-1",
3828         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
3829         .registers              = vc5_hdmi_hdmi1_fields,
3830         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3831         .phy_lane_mapping       = {
3832                 PHY_LANE_1,
3833                 PHY_LANE_0,
3834                 PHY_LANE_CK,
3835                 PHY_LANE_2,
3836         },
3837         .unsupported_odd_h_timings      = true,
3838         .external_irq_controller        = true,
3839
3840         .init_resources         = vc5_hdmi_init_resources,
3841         .csc_setup              = vc5_hdmi_csc_setup,
3842         .reset                  = vc5_hdmi_reset,
3843         .set_timings            = vc5_hdmi_set_timings,
3844         .phy_init               = vc5_hdmi_phy_init,
3845         .phy_disable            = vc5_hdmi_phy_disable,
3846         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
3847         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
3848         .channel_map            = vc5_hdmi_channel_map,
3849         .supports_hdr           = true,
3850         .hp_detect              = vc5_hdmi_hp_detect,
3851 };
3852
3853 static const struct of_device_id vc4_hdmi_dt_match[] = {
3854         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3855         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3856         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3857         {}
3858 };
3859
3860 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3861         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3862                            vc4_hdmi_runtime_resume,
3863                            NULL)
3864 };
3865
3866 struct platform_driver vc4_hdmi_driver = {
3867         .probe = vc4_hdmi_dev_probe,
3868         .remove = vc4_hdmi_dev_remove,
3869         .driver = {
3870                 .name = "vc4_hdmi",
3871                 .of_match_table = vc4_hdmi_dt_match,
3872                 .pm = &vc4_hdmi_pm_ops,
3873         },
3874 };