drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <drm/drm_simple_kms_helper.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include <linux/clk.h>
  40 #include <linux/component.h>
  41 #include <linux/i2c.h>
  42 #include <linux/of_address.h>
  43 #include <linux/of_gpio.h>
  44 #include <linux/of_platform.h>
  45 #include <linux/pm_runtime.h>
  46 #include <linux/rational.h>
  47 #include <linux/reset.h>
  48 #include <sound/dmaengine_pcm.h>
  49 #include <sound/hdmi-codec.h>
  50 #include <sound/pcm_drm_eld.h>
  51 #include <sound/pcm_params.h>
  52 #include <sound/soc.h>
  53 #include "media/cec.h"
  54 #include "vc4_drv.h"
  55 #include "vc4_hdmi.h"
  56 #include "vc4_hdmi_regs.h"
  57 #include "vc4_regs.h"
  58
  59 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  60 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  61 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  62 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  63 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  64 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  65
  66 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  67 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  68 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  69 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  70
  71 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  72 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  73 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  74 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  75 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  76 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  77
  78 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  79 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  80
  81 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  82 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  83
  84 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  85
  86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  88
  89 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  90 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  91
  92 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  93
  94 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
  95 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
  96
  97 # define VC4_HD_M_SW_RST                        BIT(2)
  98 # define VC4_HD_M_ENABLE                        BIT(0)
  99
 100 #define HSM_MIN_CLOCK_FREQ      120000000
 101 #define CEC_CLOCK_FREQ 40000
 102
 103 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 104
 105 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode)
 106 {
 107         return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK;
 108 }
 109
 110 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi,
 111                                        const struct drm_display_mode *mode)
 112 {
 113         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 114
 115         return !vc4_encoder->hdmi_monitor ||
 116                 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
 117 }
 118
 119 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 120 {
 121         struct drm_info_node *node = (struct drm_info_node *)m->private;
 122         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
 123         struct drm_printer p = drm_seq_file_printer(m);
 124
 125         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 126         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 127         drm_print_regset32(&p, &vc4_hdmi->cec_regset);
 128         drm_print_regset32(&p, &vc4_hdmi->csc_regset);
 129         drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
 130         drm_print_regset32(&p, &vc4_hdmi->phy_regset);
 131         drm_print_regset32(&p, &vc4_hdmi->ram_regset);
 132         drm_print_regset32(&p, &vc4_hdmi->rm_regset);
 133
 134         return 0;
 135 }
 136
 137 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 138 {
 139         unsigned long flags;
 140
 141         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 142
 143         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 144         udelay(1);
 145         HDMI_WRITE(HDMI_M_CTL, 0);
 146
 147         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 148
 149         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 150                    VC4_HDMI_SW_RESET_HDMI |
 151                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 152
 153         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 154
 155         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 156 }
 157
 158 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 159 {
 160         unsigned long flags;
 161
 162         reset_control_reset(vc4_hdmi->reset);
 163
 164         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 165
 166         HDMI_WRITE(HDMI_DVP_CTL, 0);
 167
 168         HDMI_WRITE(HDMI_CLOCK_STOP,
 169                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 170
 171         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 172 }
 173
 174 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 175 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 176 {
 177         unsigned long cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
 178         unsigned long flags;
 179         u16 clk_cnt;
 180         u32 value;
 181
 182         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 183
 184         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 185         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 186
 187         /*
 188          * Set the clock divider: the hsm_clock rate and this divider
 189          * setting will give a 40 kHz CEC clock.
 190          */
 191         clk_cnt = cec_rate / CEC_CLOCK_FREQ;
 192         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 193         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 194
 195         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 196 }
 197 #else
 198 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 199 #endif
 200
 201 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder);
 202
 203 static enum drm_connector_status
 204 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 205 {
 206         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 207         bool connected = false;
 208
 209         mutex_lock(&vc4_hdmi->mutex);
 210
 211         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 212
 213         if (vc4_hdmi->hpd_gpio) {
 214                 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
 215                         connected = true;
 216         } else {
 217                 if (vc4_hdmi->variant->hp_detect &&
 218                     vc4_hdmi->variant->hp_detect(vc4_hdmi))
 219                         connected = true;
 220         }
 221
 222         vc4_hdmi->encoder.hdmi_monitor = false;
 223         if (connected) {
 224                 if (connector->status != connector_status_connected) {
 225                         struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
 226
 227                         if (edid) {
 228                                 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 229                                 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
 230                                 kfree(edid);
 231                         }
 232                 }
 233
 234                 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base);
 235                 pm_runtime_put(&vc4_hdmi->pdev->dev);
 236                 mutex_unlock(&vc4_hdmi->mutex);
 237                 return connector_status_connected;
 238         }
 239
 240         cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 241         pm_runtime_put(&vc4_hdmi->pdev->dev);
 242         mutex_unlock(&vc4_hdmi->mutex);
 243         return connector_status_disconnected;
 244 }
 245
 246 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 247 {
 248         drm_connector_unregister(connector);
 249         drm_connector_cleanup(connector);
 250 }
 251
 252 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 253 {
 254         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 255         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 256         int ret = 0;
 257         struct edid *edid;
 258
 259         mutex_lock(&vc4_hdmi->mutex);
 260
 261         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 262         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 263         if (!edid) {
 264                 ret = -ENODEV;
 265                 goto out;
 266         }
 267
 268         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 269
 270         drm_connector_update_edid_property(connector, edid);
 271         ret = drm_add_edid_modes(connector, edid);
 272         kfree(edid);
 273
 274         if (vc4_hdmi->disable_4kp60) {
 275                 struct drm_device *drm = connector->dev;
 276                 struct drm_display_mode *mode;
 277
 278                 list_for_each_entry(mode, &connector->probed_modes, head) {
 279                         if (vc4_hdmi_mode_needs_scrambling(mode)) {
 280                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 281                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 282                         }
 283                 }
 284         }
 285
 286 out:
 287         mutex_unlock(&vc4_hdmi->mutex);
 288
 289         return ret;
 290 }
 291
 292 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 293                                            struct drm_atomic_state *state)
 294 {
 295         struct drm_connector_state *old_state =
 296                 drm_atomic_get_old_connector_state(state, connector);
 297         struct drm_connector_state *new_state =
 298                 drm_atomic_get_new_connector_state(state, connector);
 299         struct drm_crtc *crtc = new_state->crtc;
 300
 301         if (!crtc)
 302                 return 0;
 303
 304         if (old_state->colorspace != new_state->colorspace ||
 305             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 306                 struct drm_crtc_state *crtc_state;
 307
 308                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 309                 if (IS_ERR(crtc_state))
 310                         return PTR_ERR(crtc_state);
 311
 312                 crtc_state->mode_changed = true;
 313         }
 314
 315         return 0;
 316 }
 317
 318 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 319 {
 320         struct vc4_hdmi_connector_state *old_state =
 321                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 322         struct vc4_hdmi_connector_state *new_state =
 323                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 324
 325         if (connector->state)
 326                 __drm_atomic_helper_connector_destroy_state(connector->state);
 327
 328         kfree(old_state);
 329         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 330
 331         if (!new_state)
 332                 return;
 333
 334         new_state->base.max_bpc = 8;
 335         new_state->base.max_requested_bpc = 8;
 336         drm_atomic_helper_connector_tv_reset(connector);
 337 }
 338
 339 static struct drm_connector_state *
 340 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 341 {
 342         struct drm_connector_state *conn_state = connector->state;
 343         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 344         struct vc4_hdmi_connector_state *new_state;
 345
 346         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 347         if (!new_state)
 348                 return NULL;
 349
 350         new_state->pixel_rate = vc4_state->pixel_rate;
 351         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 352
 353         return &new_state->base;
 354 }
 355
 356 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 357         .detect = vc4_hdmi_connector_detect,
 358         .fill_modes = drm_helper_probe_single_connector_modes,
 359         .destroy = vc4_hdmi_connector_destroy,
 360         .reset = vc4_hdmi_connector_reset,
 361         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 362         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 363 };
 364
 365 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 366         .get_modes = vc4_hdmi_connector_get_modes,
 367         .atomic_check = vc4_hdmi_connector_atomic_check,
 368 };
 369
 370 static int vc4_hdmi_connector_init(struct drm_device *dev,
 371                                    struct vc4_hdmi *vc4_hdmi)
 372 {
 373         struct drm_connector *connector = &vc4_hdmi->connector;
 374         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 375         int ret;
 376
 377         drm_connector_init_with_ddc(dev, connector,
 378                                     &vc4_hdmi_connector_funcs,
 379                                     DRM_MODE_CONNECTOR_HDMIA,
 380                                     vc4_hdmi->ddc);
 381         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 382
 383         /*
 384          * Some of the properties below require access to state, like bpc.
 385          * Allocate some default initial connector state with our reset helper.
 386          */
 387         if (connector->funcs->reset)
 388                 connector->funcs->reset(connector);
 389
 390         /* Create and attach TV margin props to this connector. */
 391         ret = drm_mode_create_tv_margin_properties(dev);
 392         if (ret)
 393                 return ret;
 394
 395         ret = drm_mode_create_hdmi_colorspace_property(connector);
 396         if (ret)
 397                 return ret;
 398
 399         drm_connector_attach_colorspace_property(connector);
 400         drm_connector_attach_tv_margin_properties(connector);
 401         drm_connector_attach_max_bpc_property(connector, 8, 12);
 402
 403         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 404                              DRM_CONNECTOR_POLL_DISCONNECT);
 405
 406         connector->interlace_allowed = 1;
 407         connector->doublescan_allowed = 0;
 408         connector->stereo_allowed = 1;
 409
 410         if (vc4_hdmi->variant->supports_hdr)
 411                 drm_connector_attach_hdr_output_metadata_property(connector);
 412
 413         drm_connector_attach_encoder(connector, encoder);
 414
 415         return 0;
 416 }
 417
 418 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 419                                 enum hdmi_infoframe_type type,
 420                                 bool poll)
 421 {
 422         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 423         u32 packet_id = type - 0x80;
 424         unsigned long flags;
 425
 426         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 427         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 428                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 429         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 430
 431         if (!poll)
 432                 return 0;
 433
 434         return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 435                           BIT(packet_id)), 100);
 436 }
 437
 438 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 439                                      union hdmi_infoframe *frame)
 440 {
 441         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 442         u32 packet_id = frame->any.type - 0x80;
 443         const struct vc4_hdmi_register *ram_packet_start =
 444                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 445         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 446         u32 packet_reg_next = ram_packet_start->offset +
 447                 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
 448         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 449                                                        ram_packet_start->reg);
 450         uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
 451         unsigned long flags;
 452         ssize_t len, i;
 453         int ret;
 454
 455         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 456                     VC4_HDMI_RAM_PACKET_ENABLE),
 457                   "Packet RAM has to be on to store the packet.");
 458
 459         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 460         if (len < 0)
 461                 return;
 462
 463         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 464         if (ret) {
 465                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 466                 return;
 467         }
 468
 469         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 470
 471         for (i = 0; i < len; i += 7) {
 472                 writel(buffer[i + 0] << 0 |
 473                        buffer[i + 1] << 8 |
 474                        buffer[i + 2] << 16,
 475                        base + packet_reg);
 476                 packet_reg += 4;
 477
 478                 writel(buffer[i + 3] << 0 |
 479                        buffer[i + 4] << 8 |
 480                        buffer[i + 5] << 16 |
 481                        buffer[i + 6] << 24,
 482                        base + packet_reg);
 483                 packet_reg += 4;
 484         }
 485
 486         /*
 487          * clear remainder of packet ram as it's included in the
 488          * infoframe and triggers a checksum error on hdmi analyser
 489          */
 490         for (; packet_reg < packet_reg_next; packet_reg += 4)
 491                 writel(0, base + packet_reg);
 492
 493         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 494                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 495
 496         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 497
 498         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 499                         BIT(packet_id)), 100);
 500         if (ret)
 501                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 502 }
 503
 504 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 505 {
 506         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 507         struct drm_connector *connector = &vc4_hdmi->connector;
 508         struct drm_connector_state *cstate = connector->state;
 509         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 510         union hdmi_infoframe frame;
 511         int ret;
 512
 513         lockdep_assert_held(&vc4_hdmi->mutex);
 514
 515         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 516                                                        connector, mode);
 517         if (ret < 0) {
 518                 DRM_ERROR("couldn't fill AVI infoframe\n");
 519                 return;
 520         }
 521
 522         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 523                                            connector, mode,
 524                                            vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ?
 525                                            HDMI_QUANTIZATION_RANGE_FULL :
 526                                            HDMI_QUANTIZATION_RANGE_LIMITED);
 527         drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
 528         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 529
 530         vc4_hdmi_write_infoframe(encoder, &frame);
 531 }
 532
 533 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 534 {
 535         union hdmi_infoframe frame;
 536         int ret;
 537
 538         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 539         if (ret < 0) {
 540                 DRM_ERROR("couldn't fill SPD infoframe\n");
 541                 return;
 542         }
 543
 544         frame.spd.sdi = HDMI_SPD_SDI_PC;
 545
 546         vc4_hdmi_write_infoframe(encoder, &frame);
 547 }
 548
 549 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 550 {
 551         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 552         struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
 553         union hdmi_infoframe frame;
 554
 555         memcpy(&frame.audio, audio, sizeof(*audio));
 556         vc4_hdmi_write_infoframe(encoder, &frame);
 557 }
 558
 559 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 560 {
 561         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 562         struct drm_connector *connector = &vc4_hdmi->connector;
 563         struct drm_connector_state *conn_state = connector->state;
 564         union hdmi_infoframe frame;
 565
 566         lockdep_assert_held(&vc4_hdmi->mutex);
 567
 568         if (!vc4_hdmi->variant->supports_hdr)
 569                 return;
 570
 571         if (!conn_state->hdr_output_metadata)
 572                 return;
 573
 574         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 575                 return;
 576
 577         vc4_hdmi_write_infoframe(encoder, &frame);
 578 }
 579
 580 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 581 {
 582         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 583
 584         lockdep_assert_held(&vc4_hdmi->mutex);
 585
 586         vc4_hdmi_set_avi_infoframe(encoder);
 587         vc4_hdmi_set_spd_infoframe(encoder);
 588         /*
 589          * If audio was streaming, then we need to reenabled the audio
 590          * infoframe here during encoder_enable.
 591          */
 592         if (vc4_hdmi->audio.streaming)
 593                 vc4_hdmi_set_audio_infoframe(encoder);
 594
 595         vc4_hdmi_set_hdr_infoframe(encoder);
 596 }
 597
 598 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
 599                                          struct drm_display_mode *mode)
 600 {
 601         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 602         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 603         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 604
 605         lockdep_assert_held(&vc4_hdmi->mutex);
 606
 607         if (!vc4_encoder->hdmi_monitor)
 608                 return false;
 609
 610         if (!display->hdmi.scdc.supported ||
 611             !display->hdmi.scdc.scrambling.supported)
 612                 return false;
 613
 614         return true;
 615 }
 616
 617 #define SCRAMBLING_POLLING_DELAY_MS     1000
 618
 619 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 620 {
 621         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 622         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 623         unsigned long flags;
 624
 625         lockdep_assert_held(&vc4_hdmi->mutex);
 626
 627         if (!vc4_hdmi_supports_scrambling(encoder, mode))
 628                 return;
 629
 630         if (!vc4_hdmi_mode_needs_scrambling(mode))
 631                 return;
 632
 633         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 634         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 635
 636         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 637         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
 638                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 639         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 640
 641         vc4_hdmi->scdc_enabled = true;
 642
 643         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 644                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 645 }
 646
 647 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
 648 {
 649         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 650         unsigned long flags;
 651
 652         lockdep_assert_held(&vc4_hdmi->mutex);
 653
 654         if (!vc4_hdmi->scdc_enabled)
 655                 return;
 656
 657         vc4_hdmi->scdc_enabled = false;
 658
 659         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
 660                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
 661
 662         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 663         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
 664                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 665         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 666
 667         drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
 668         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
 669 }
 670
 671 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
 672 {
 673         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
 674                                                  struct vc4_hdmi,
 675                                                  scrambling_work);
 676
 677         if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
 678                 return;
 679
 680         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 681         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 682
 683         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 684                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 685 }
 686
 687 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 688                                                struct drm_atomic_state *state)
 689 {
 690         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 691         unsigned long flags;
 692
 693         mutex_lock(&vc4_hdmi->mutex);
 694
 695         vc4_hdmi->output_enabled = false;
 696         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 697
 698         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 699
 700         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
 701
 702         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 703
 704         mdelay(1);
 705
 706         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 707         HDMI_WRITE(HDMI_VID_CTL,
 708                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 709         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 710
 711         vc4_hdmi_disable_scrambling(encoder);
 712
 713         mutex_unlock(&vc4_hdmi->mutex);
 714 }
 715
 716 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
 717                                                  struct drm_atomic_state *state)
 718 {
 719         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 720         unsigned long flags;
 721         int ret;
 722
 723         mutex_lock(&vc4_hdmi->mutex);
 724
 725         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 726         HDMI_WRITE(HDMI_VID_CTL,
 727                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 728         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 729
 730         if (vc4_hdmi->variant->phy_disable)
 731                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 732
 733         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 734         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 735
 736         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 737         if (ret < 0)
 738                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 739
 740         mutex_unlock(&vc4_hdmi->mutex);
 741 }
 742
 743 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
 744                                const struct drm_display_mode *mode)
 745 {
 746         unsigned long flags;
 747         u32 csc_ctl;
 748
 749         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 750
 751         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 752                                 VC4_HD_CSC_CTL_ORDER);
 753
 754         if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) {
 755                 /* CEA VICs other than #1 requre limited range RGB
 756                  * output unless overridden by an AVI infoframe.
 757                  * Apply a colorspace conversion to squash 0-255 down
 758                  * to 16-235.  The matrix here is:
 759                  *
 760                  * [ 0      0      0.8594 16]
 761                  * [ 0      0.8594 0      16]
 762                  * [ 0.8594 0      0      16]
 763                  * [ 0      0      0       1]
 764                  */
 765                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 766                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 767                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 768                                          VC4_HD_CSC_CTL_MODE);
 769
 770                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 771                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 772                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 773                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 774                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 775                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 776         }
 777
 778         /* The RGB order applies even when CSC is disabled. */
 779         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 780
 781         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 782 }
 783
 784 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
 785                                const struct drm_display_mode *mode)
 786 {
 787         unsigned long flags;
 788         u32 csc_ctl;
 789
 790         csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
 791
 792         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 793
 794         if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) {
 795                 /* CEA VICs other than #1 requre limited range RGB
 796                  * output unless overridden by an AVI infoframe.
 797                  * Apply a colorspace conversion to squash 0-255 down
 798                  * to 16-235.  The matrix here is:
 799                  *
 800                  * [ 0.8594 0      0      16]
 801                  * [ 0      0.8594 0      16]
 802                  * [ 0      0      0.8594 16]
 803                  * [ 0      0      0       1]
 804                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 805                  */
 806                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
 807                 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
 808                 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
 809                 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
 810                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 811                 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
 812         } else {
 813                 /* Still use the matrix for full range, but make it unity.
 814                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 815                  */
 816                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
 817                 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
 818                 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
 819                 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
 820                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 821                 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
 822         }
 823
 824         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 825
 826         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 827 }
 828
 829 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 830                                  struct drm_connector_state *state,
 831                                  struct drm_display_mode *mode)
 832 {
 833         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 834         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 835         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 836         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 837         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 838                                    VC4_HDMI_VERTA_VSP) |
 839                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 840                                    VC4_HDMI_VERTA_VFP) |
 841                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 842         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 843                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
 844                                    interlaced,
 845                                    VC4_HDMI_VERTB_VBP));
 846         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 847                           VC4_SET_FIELD(mode->crtc_vtotal -
 848                                         mode->crtc_vsync_end,
 849                                         VC4_HDMI_VERTB_VBP));
 850         unsigned long flags;
 851
 852         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 853
 854         HDMI_WRITE(HDMI_HORZA,
 855                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 856                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 857                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 858                                  VC4_HDMI_HORZA_HAP));
 859
 860         HDMI_WRITE(HDMI_HORZB,
 861                    VC4_SET_FIELD((mode->htotal -
 862                                   mode->hsync_end) * pixel_rep,
 863                                  VC4_HDMI_HORZB_HBP) |
 864                    VC4_SET_FIELD((mode->hsync_end -
 865                                   mode->hsync_start) * pixel_rep,
 866                                  VC4_HDMI_HORZB_HSP) |
 867                    VC4_SET_FIELD((mode->hsync_start -
 868                                   mode->hdisplay) * pixel_rep,
 869                                  VC4_HDMI_HORZB_HFP));
 870
 871         HDMI_WRITE(HDMI_VERTA0, verta);
 872         HDMI_WRITE(HDMI_VERTA1, verta);
 873
 874         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 875         HDMI_WRITE(HDMI_VERTB1, vertb);
 876
 877         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 878 }
 879
 880 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 881                                  struct drm_connector_state *state,
 882                                  struct drm_display_mode *mode)
 883 {
 884         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 885         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 886         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 887         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 888         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 889                                    VC5_HDMI_VERTA_VSP) |
 890                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 891                                    VC5_HDMI_VERTA_VFP) |
 892                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
 893         u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 894                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
 895                                    interlaced,
 896                                    VC4_HDMI_VERTB_VBP));
 897         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 898                           VC4_SET_FIELD(mode->crtc_vtotal -
 899                                         mode->crtc_vsync_end,
 900                                         VC4_HDMI_VERTB_VBP));
 901         unsigned long flags;
 902         unsigned char gcp;
 903         bool gcp_en;
 904         u32 reg;
 905
 906         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 907
 908         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
 909         HDMI_WRITE(HDMI_HORZA,
 910                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
 911                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
 912                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 913                                  VC5_HDMI_HORZA_HAP) |
 914                    VC4_SET_FIELD((mode->hsync_start -
 915                                   mode->hdisplay) * pixel_rep,
 916                                  VC5_HDMI_HORZA_HFP));
 917
 918         HDMI_WRITE(HDMI_HORZB,
 919                    VC4_SET_FIELD((mode->htotal -
 920                                   mode->hsync_end) * pixel_rep,
 921                                  VC5_HDMI_HORZB_HBP) |
 922                    VC4_SET_FIELD((mode->hsync_end -
 923                                   mode->hsync_start) * pixel_rep,
 924                                  VC5_HDMI_HORZB_HSP));
 925
 926         HDMI_WRITE(HDMI_VERTA0, verta);
 927         HDMI_WRITE(HDMI_VERTA1, verta);
 928
 929         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 930         HDMI_WRITE(HDMI_VERTB1, vertb);
 931
 932         switch (state->max_bpc) {
 933         case 12:
 934                 gcp = 6;
 935                 gcp_en = true;
 936                 break;
 937         case 10:
 938                 gcp = 5;
 939                 gcp_en = true;
 940                 break;
 941         case 8:
 942         default:
 943                 gcp = 4;
 944                 gcp_en = false;
 945                 break;
 946         }
 947
 948         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
 949         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
 950                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
 951         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
 952                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
 953         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
 954
 955         reg = HDMI_READ(HDMI_GCP_WORD_1);
 956         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
 957         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
 958         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
 959
 960         reg = HDMI_READ(HDMI_GCP_CONFIG);
 961         reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
 962         reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
 963         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
 964
 965         reg = HDMI_READ(HDMI_MISC_CONTROL);
 966         reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
 967         reg |= VC4_SET_FIELD(0, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
 968         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
 969
 970         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
 971
 972         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 973 }
 974
 975 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
 976 {
 977         unsigned long flags;
 978         u32 drift;
 979         int ret;
 980
 981         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 982
 983         drift = HDMI_READ(HDMI_FIFO_CTL);
 984         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 985
 986         HDMI_WRITE(HDMI_FIFO_CTL,
 987                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 988         HDMI_WRITE(HDMI_FIFO_CTL,
 989                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 990
 991         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 992
 993         usleep_range(1000, 1100);
 994
 995         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 996
 997         HDMI_WRITE(HDMI_FIFO_CTL,
 998                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 999         HDMI_WRITE(HDMI_FIFO_CTL,
1000                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1001
1002         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1003
1004         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1005                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1006         WARN_ONCE(ret, "Timeout waiting for "
1007                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1008 }
1009
1010 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1011                                                 struct drm_atomic_state *state)
1012 {
1013         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1014         struct drm_connector *connector = &vc4_hdmi->connector;
1015         struct drm_connector_state *conn_state =
1016                 drm_atomic_get_new_connector_state(state, connector);
1017         struct vc4_hdmi_connector_state *vc4_conn_state =
1018                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1019         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1020         unsigned long pixel_rate = vc4_conn_state->pixel_rate;
1021         unsigned long bvb_rate, hsm_rate;
1022         unsigned long flags;
1023         int ret;
1024
1025         mutex_lock(&vc4_hdmi->mutex);
1026
1027         /*
1028          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1029          * be faster than pixel clock, infinitesimally faster, tested in
1030          * simulation. Otherwise, exact value is unimportant for HDMI
1031          * operation." This conflicts with bcm2835's vc4 documentation, which
1032          * states HSM's clock has to be at least 108% of the pixel clock.
1033          *
1034          * Real life tests reveal that vc4's firmware statement holds up, and
1035          * users are able to use pixel clocks closer to HSM's, namely for
1036          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1037          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1038          * 162MHz.
1039          *
1040          * Additionally, the AXI clock needs to be at least 25% of
1041          * pixel clock, but HSM ends up being the limiting factor.
1042          */
1043         hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
1044         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1045         if (ret) {
1046                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1047                 goto out;
1048         }
1049
1050         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1051         if (ret < 0) {
1052                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1053                 goto out;
1054         }
1055
1056         ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
1057         if (ret) {
1058                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1059                 goto err_put_runtime_pm;
1060         }
1061
1062         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1063         if (ret) {
1064                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1065                 goto err_put_runtime_pm;
1066         }
1067
1068
1069         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1070
1071         if (pixel_rate > 297000000)
1072                 bvb_rate = 300000000;
1073         else if (pixel_rate > 148500000)
1074                 bvb_rate = 150000000;
1075         else
1076                 bvb_rate = 75000000;
1077
1078         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1079         if (ret) {
1080                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1081                 goto err_disable_pixel_clock;
1082         }
1083
1084         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1085         if (ret) {
1086                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1087                 goto err_disable_pixel_clock;
1088         }
1089
1090         if (vc4_hdmi->variant->phy_init)
1091                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1092
1093         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1094
1095         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1096                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1097                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1098                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1099
1100         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1101
1102         if (vc4_hdmi->variant->set_timings)
1103                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1104
1105         mutex_unlock(&vc4_hdmi->mutex);
1106
1107         return;
1108
1109 err_disable_pixel_clock:
1110         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1111 err_put_runtime_pm:
1112         pm_runtime_put(&vc4_hdmi->pdev->dev);
1113 out:
1114         mutex_unlock(&vc4_hdmi->mutex);
1115         return;
1116 }
1117
1118 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1119                                              struct drm_atomic_state *state)
1120 {
1121         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1122         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1123         unsigned long flags;
1124
1125         mutex_lock(&vc4_hdmi->mutex);
1126
1127         if (vc4_hdmi->variant->csc_setup)
1128                 vc4_hdmi->variant->csc_setup(vc4_hdmi, mode);
1129
1130         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1131         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1132         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1133
1134         mutex_unlock(&vc4_hdmi->mutex);
1135 }
1136
1137 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1138                                               struct drm_atomic_state *state)
1139 {
1140         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1141         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1142         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1143         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1144         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1145         unsigned long flags;
1146         int ret;
1147
1148         mutex_lock(&vc4_hdmi->mutex);
1149
1150         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1151
1152         HDMI_WRITE(HDMI_VID_CTL,
1153                    VC4_HD_VID_CTL_ENABLE |
1154                    VC4_HD_VID_CTL_CLRRGB |
1155                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1156                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1157                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1158                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1159
1160         HDMI_WRITE(HDMI_VID_CTL,
1161                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1162
1163         if (vc4_encoder->hdmi_monitor) {
1164                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1165                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1166                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1167
1168                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1169
1170                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1171                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1172                 WARN_ONCE(ret, "Timeout waiting for "
1173                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1174         } else {
1175                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1176                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1177                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1178                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1179                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1180                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1181
1182                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1183
1184                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1185                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1186                 WARN_ONCE(ret, "Timeout waiting for "
1187                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1188         }
1189
1190         if (vc4_encoder->hdmi_monitor) {
1191                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1192
1193                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1194                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1195                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1196                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1197                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
1198
1199                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1200                            VC4_HDMI_RAM_PACKET_ENABLE);
1201
1202                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1203                 vc4_hdmi->output_enabled = true;
1204
1205                 vc4_hdmi_set_infoframes(encoder);
1206         }
1207
1208         vc4_hdmi_recenter_fifo(vc4_hdmi);
1209         vc4_hdmi_enable_scrambling(encoder);
1210
1211         mutex_unlock(&vc4_hdmi->mutex);
1212 }
1213
1214 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1215                                              struct drm_crtc_state *crtc_state,
1216                                              struct drm_connector_state *conn_state)
1217 {
1218         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1219
1220         mutex_lock(&vc4_hdmi->mutex);
1221         memcpy(&vc4_hdmi->saved_adjusted_mode,
1222                &crtc_state->adjusted_mode,
1223                sizeof(vc4_hdmi->saved_adjusted_mode));
1224         mutex_unlock(&vc4_hdmi->mutex);
1225 }
1226
1227 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
1228 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
1229
1230 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1231                                          struct drm_crtc_state *crtc_state,
1232                                          struct drm_connector_state *conn_state)
1233 {
1234         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1235         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1236         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1237         unsigned long long pixel_rate = mode->clock * 1000;
1238         unsigned long long tmds_rate;
1239
1240         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1241             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1242             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1243              (mode->hsync_end % 2) || (mode->htotal % 2)))
1244                 return -EINVAL;
1245
1246         /*
1247          * The 1440p@60 pixel rate is in the same range than the first
1248          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1249          * bandwidth). Slightly lower the frequency to bring it out of
1250          * the WiFi range.
1251          */
1252         tmds_rate = pixel_rate * 10;
1253         if (vc4_hdmi->disable_wifi_frequencies &&
1254             (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1255              tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1256                 mode->clock = 238560;
1257                 pixel_rate = mode->clock * 1000;
1258         }
1259
1260         if (conn_state->max_bpc == 12) {
1261                 pixel_rate = pixel_rate * 150;
1262                 do_div(pixel_rate, 100);
1263         } else if (conn_state->max_bpc == 10) {
1264                 pixel_rate = pixel_rate * 125;
1265                 do_div(pixel_rate, 100);
1266         }
1267
1268         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1269                 pixel_rate = pixel_rate * 2;
1270
1271         if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
1272                 return -EINVAL;
1273
1274         if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK))
1275                 return -EINVAL;
1276
1277         vc4_state->pixel_rate = pixel_rate;
1278
1279         return 0;
1280 }
1281
1282 static enum drm_mode_status
1283 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1284                             const struct drm_display_mode *mode)
1285 {
1286         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1287
1288         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1289             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1290             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1291              (mode->hsync_end % 2) || (mode->htotal % 2)))
1292                 return MODE_H_ILLEGAL;
1293
1294         if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
1295                 return MODE_CLOCK_HIGH;
1296
1297         if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode))
1298                 return MODE_CLOCK_HIGH;
1299
1300         return MODE_OK;
1301 }
1302
1303 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1304         .atomic_check = vc4_hdmi_encoder_atomic_check,
1305         .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1306         .mode_valid = vc4_hdmi_encoder_mode_valid,
1307 };
1308
1309 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1310 {
1311         int i;
1312         u32 channel_map = 0;
1313
1314         for (i = 0; i < 8; i++) {
1315                 if (channel_mask & BIT(i))
1316                         channel_map |= i << (3 * i);
1317         }
1318         return channel_map;
1319 }
1320
1321 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1322 {
1323         int i;
1324         u32 channel_map = 0;
1325
1326         for (i = 0; i < 8; i++) {
1327                 if (channel_mask & BIT(i))
1328                         channel_map |= i << (4 * i);
1329         }
1330         return channel_map;
1331 }
1332
1333 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
1334 {
1335         unsigned long flags;
1336         u32 hotplug;
1337
1338         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1339         hotplug = HDMI_READ(HDMI_HOTPLUG);
1340         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1341
1342         return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
1343 }
1344
1345 /* HDMI audio codec callbacks */
1346 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1347                                          unsigned int samplerate)
1348 {
1349         u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1350         unsigned long flags;
1351         unsigned long n, m;
1352
1353         rational_best_approximation(hsm_clock, samplerate,
1354                                     VC4_HD_MAI_SMP_N_MASK >>
1355                                     VC4_HD_MAI_SMP_N_SHIFT,
1356                                     (VC4_HD_MAI_SMP_M_MASK >>
1357                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
1358                                     &n, &m);
1359
1360         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1361         HDMI_WRITE(HDMI_MAI_SMP,
1362                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1363                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1364         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1365 }
1366
1367 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1368 {
1369         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1370         u32 n, cts;
1371         u64 tmp;
1372
1373         lockdep_assert_held(&vc4_hdmi->mutex);
1374         lockdep_assert_held(&vc4_hdmi->hw_lock);
1375
1376         n = 128 * samplerate / 1000;
1377         tmp = (u64)(mode->clock * 1000) * n;
1378         do_div(tmp, 128 * samplerate);
1379         cts = tmp;
1380
1381         HDMI_WRITE(HDMI_CRP_CFG,
1382                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1383                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1384
1385         /*
1386          * We could get slightly more accurate clocks in some cases by
1387          * providing a CTS_1 value.  The two CTS values are alternated
1388          * between based on the period fields
1389          */
1390         HDMI_WRITE(HDMI_CTS_0, cts);
1391         HDMI_WRITE(HDMI_CTS_1, cts);
1392 }
1393
1394 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1395 {
1396         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1397
1398         return snd_soc_card_get_drvdata(card);
1399 }
1400
1401 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
1402 {
1403         lockdep_assert_held(&vc4_hdmi->mutex);
1404
1405         /*
1406          * If the encoder is currently in DVI mode, treat the codec DAI
1407          * as missing.
1408          */
1409         if (!vc4_hdmi->encoder.hdmi_monitor)
1410                 return false;
1411
1412         return true;
1413 }
1414
1415 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1416 {
1417         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1418         unsigned long flags;
1419
1420         mutex_lock(&vc4_hdmi->mutex);
1421
1422         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1423                 mutex_unlock(&vc4_hdmi->mutex);
1424                 return -ENODEV;
1425         }
1426
1427         vc4_hdmi->audio.streaming = true;
1428
1429         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1430         HDMI_WRITE(HDMI_MAI_CTL,
1431                    VC4_HD_MAI_CTL_RESET |
1432                    VC4_HD_MAI_CTL_FLUSH |
1433                    VC4_HD_MAI_CTL_DLATE |
1434                    VC4_HD_MAI_CTL_ERRORE |
1435                    VC4_HD_MAI_CTL_ERRORF);
1436         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1437
1438         if (vc4_hdmi->variant->phy_rng_enable)
1439                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1440
1441         mutex_unlock(&vc4_hdmi->mutex);
1442
1443         return 0;
1444 }
1445
1446 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1447 {
1448         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1449         struct device *dev = &vc4_hdmi->pdev->dev;
1450         unsigned long flags;
1451         int ret;
1452
1453         lockdep_assert_held(&vc4_hdmi->mutex);
1454
1455         vc4_hdmi->audio.streaming = false;
1456         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1457         if (ret)
1458                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1459
1460         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1461
1462         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1463         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1464         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1465
1466         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1467 }
1468
1469 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1470 {
1471         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1472         unsigned long flags;
1473
1474         mutex_lock(&vc4_hdmi->mutex);
1475
1476         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1477
1478         HDMI_WRITE(HDMI_MAI_CTL,
1479                    VC4_HD_MAI_CTL_DLATE |
1480                    VC4_HD_MAI_CTL_ERRORE |
1481                    VC4_HD_MAI_CTL_ERRORF);
1482
1483         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1484
1485         if (vc4_hdmi->variant->phy_rng_disable)
1486                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1487
1488         vc4_hdmi->audio.streaming = false;
1489         vc4_hdmi_audio_reset(vc4_hdmi);
1490
1491         mutex_unlock(&vc4_hdmi->mutex);
1492 }
1493
1494 static int sample_rate_to_mai_fmt(int samplerate)
1495 {
1496         switch (samplerate) {
1497         case 8000:
1498                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1499         case 11025:
1500                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1501         case 12000:
1502                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1503         case 16000:
1504                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1505         case 22050:
1506                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1507         case 24000:
1508                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1509         case 32000:
1510                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1511         case 44100:
1512                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1513         case 48000:
1514                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1515         case 64000:
1516                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
1517         case 88200:
1518                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
1519         case 96000:
1520                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
1521         case 128000:
1522                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
1523         case 176400:
1524                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
1525         case 192000:
1526                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
1527         default:
1528                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
1529         }
1530 }
1531
1532 /* HDMI audio codec callbacks */
1533 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
1534                                   struct hdmi_codec_daifmt *daifmt,
1535                                   struct hdmi_codec_params *params)
1536 {
1537         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1538         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1539         unsigned int sample_rate = params->sample_rate;
1540         unsigned int channels = params->channels;
1541         unsigned long flags;
1542         u32 audio_packet_config, channel_mask;
1543         u32 channel_map;
1544         u32 mai_audio_format;
1545         u32 mai_sample_rate;
1546
1547         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1548                 sample_rate, params->sample_width, channels);
1549
1550         mutex_lock(&vc4_hdmi->mutex);
1551
1552         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1553                 mutex_unlock(&vc4_hdmi->mutex);
1554                 return -EINVAL;
1555         }
1556
1557         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
1558
1559         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1560         HDMI_WRITE(HDMI_MAI_CTL,
1561                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
1562                    VC4_HD_MAI_CTL_WHOLSMP |
1563                    VC4_HD_MAI_CTL_CHALIGN |
1564                    VC4_HD_MAI_CTL_ENABLE);
1565
1566         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
1567         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
1568             params->channels == 8)
1569                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
1570         else
1571                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
1572         HDMI_WRITE(HDMI_MAI_FMT,
1573                    VC4_SET_FIELD(mai_sample_rate,
1574                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
1575                    VC4_SET_FIELD(mai_audio_format,
1576                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
1577
1578         /* The B frame identifier should match the value used by alsa-lib (8) */
1579         audio_packet_config =
1580                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1581                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1582                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1583
1584         channel_mask = GENMASK(channels - 1, 0);
1585         audio_packet_config |= VC4_SET_FIELD(channel_mask,
1586                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1587
1588         /* Set the MAI threshold */
1589         HDMI_WRITE(HDMI_MAI_THR,
1590                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
1591                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
1592                    VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
1593                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
1594
1595         HDMI_WRITE(HDMI_MAI_CONFIG,
1596                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1597                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
1598                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1599
1600         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1601         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1602         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1603
1604         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
1605
1606         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1607
1608         memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
1609         if (vc4_hdmi->output_enabled)
1610                 vc4_hdmi_set_audio_infoframe(encoder);
1611
1612         mutex_unlock(&vc4_hdmi->mutex);
1613
1614         return 0;
1615 }
1616
1617 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1618         .name = "vc4-hdmi-cpu-dai-component",
1619 };
1620
1621 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1622 {
1623         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1624
1625         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1626
1627         return 0;
1628 }
1629
1630 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1631         .name = "vc4-hdmi-cpu-dai",
1632         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1633         .playback = {
1634                 .stream_name = "Playback",
1635                 .channels_min = 1,
1636                 .channels_max = 8,
1637                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1638                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1639                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1640                          SNDRV_PCM_RATE_192000,
1641                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1642         },
1643 };
1644
1645 static const struct snd_dmaengine_pcm_config pcm_conf = {
1646         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1647         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1648 };
1649
1650 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
1651                                   uint8_t *buf, size_t len)
1652 {
1653         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1654         struct drm_connector *connector = &vc4_hdmi->connector;
1655
1656         mutex_lock(&vc4_hdmi->mutex);
1657         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1658         mutex_unlock(&vc4_hdmi->mutex);
1659
1660         return 0;
1661 }
1662
1663 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
1664         .get_eld = vc4_hdmi_audio_get_eld,
1665         .prepare = vc4_hdmi_audio_prepare,
1666         .audio_shutdown = vc4_hdmi_audio_shutdown,
1667         .audio_startup = vc4_hdmi_audio_startup,
1668 };
1669
1670 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
1671         .ops = &vc4_hdmi_codec_ops,
1672         .max_i2s_channels = 8,
1673         .i2s = 1,
1674 };
1675
1676 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1677 {
1678         const struct vc4_hdmi_register *mai_data =
1679                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1680         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1681         struct snd_soc_card *card = &vc4_hdmi->audio.card;
1682         struct device *dev = &vc4_hdmi->pdev->dev;
1683         struct platform_device *codec_pdev;
1684         const __be32 *addr;
1685         int index;
1686         int ret;
1687         int len;
1688
1689         if (!of_find_property(dev->of_node, "dmas", &len) ||
1690             len == 0) {
1691                 dev_warn(dev,
1692                          "'dmas' DT property is missing or empty, no HDMI audio\n");
1693                 return 0;
1694         }
1695
1696         if (mai_data->reg != VC4_HD) {
1697                 WARN_ONCE(true, "MAI isn't in the HD block\n");
1698                 return -EINVAL;
1699         }
1700
1701         /*
1702          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1703          * the bus address specified in the DT, because the physical address
1704          * (the one returned by platform_get_resource()) is not appropriate
1705          * for DMA transfers.
1706          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1707          */
1708         index = of_property_match_string(dev->of_node, "reg-names", "hd");
1709         /* Before BCM2711, we don't have a named register range */
1710         if (index < 0)
1711                 index = 1;
1712
1713         addr = of_get_address(dev->of_node, index, NULL, NULL);
1714
1715         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1716         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1717         vc4_hdmi->audio.dma_data.maxburst = 2;
1718
1719         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1720         if (ret) {
1721                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1722                 return ret;
1723         }
1724
1725         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1726                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1727         if (ret) {
1728                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1729                 return ret;
1730         }
1731
1732         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1733                                                    PLATFORM_DEVID_AUTO,
1734                                                    &vc4_hdmi_codec_pdata,
1735                                                    sizeof(vc4_hdmi_codec_pdata));
1736         if (IS_ERR(codec_pdev)) {
1737                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
1738                 return PTR_ERR(codec_pdev);
1739         }
1740         vc4_hdmi->audio.codec_pdev = codec_pdev;
1741
1742         dai_link->cpus          = &vc4_hdmi->audio.cpu;
1743         dai_link->codecs        = &vc4_hdmi->audio.codec;
1744         dai_link->platforms     = &vc4_hdmi->audio.platform;
1745
1746         dai_link->num_cpus      = 1;
1747         dai_link->num_codecs    = 1;
1748         dai_link->num_platforms = 1;
1749
1750         dai_link->name = "MAI";
1751         dai_link->stream_name = "MAI PCM";
1752         dai_link->codecs->dai_name = "i2s-hifi";
1753         dai_link->cpus->dai_name = dev_name(dev);
1754         dai_link->codecs->name = dev_name(&codec_pdev->dev);
1755         dai_link->platforms->name = dev_name(dev);
1756
1757         card->dai_link = dai_link;
1758         card->num_links = 1;
1759         card->name = vc4_hdmi->variant->card_name;
1760         card->driver_name = "vc4-hdmi";
1761         card->dev = dev;
1762         card->owner = THIS_MODULE;
1763
1764         /*
1765          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1766          * stores a pointer to the snd card object in dev->driver_data. This
1767          * means we cannot use it for something else. The hdmi back-pointer is
1768          * now stored in card->drvdata and should be retrieved with
1769          * snd_soc_card_get_drvdata() if needed.
1770          */
1771         snd_soc_card_set_drvdata(card, vc4_hdmi);
1772         ret = devm_snd_soc_register_card(dev, card);
1773         if (ret)
1774                 dev_err_probe(dev, ret, "Could not register sound card\n");
1775
1776         return ret;
1777
1778 }
1779
1780 static void vc4_hdmi_audio_exit(struct vc4_hdmi *vc4_hdmi)
1781 {
1782         platform_device_unregister(vc4_hdmi->audio.codec_pdev);
1783         vc4_hdmi->audio.codec_pdev = NULL;
1784 }
1785
1786 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
1787 {
1788         struct vc4_hdmi *vc4_hdmi = priv;
1789         struct drm_connector *connector = &vc4_hdmi->connector;
1790         struct drm_device *dev = connector->dev;
1791
1792         if (dev && dev->registered)
1793                 drm_connector_helper_hpd_irq_event(connector);
1794
1795         return IRQ_HANDLED;
1796 }
1797
1798 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
1799 {
1800         struct drm_connector *connector = &vc4_hdmi->connector;
1801         struct platform_device *pdev = vc4_hdmi->pdev;
1802         int ret;
1803
1804         if (vc4_hdmi->variant->external_irq_controller) {
1805                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
1806                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
1807
1808                 ret = request_threaded_irq(hpd_con,
1809                                            NULL,
1810                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1811                                            "vc4 hdmi hpd connected", vc4_hdmi);
1812                 if (ret)
1813                         return ret;
1814
1815                 ret = request_threaded_irq(hpd_rm,
1816                                            NULL,
1817                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1818                                            "vc4 hdmi hpd disconnected", vc4_hdmi);
1819                 if (ret) {
1820                         free_irq(hpd_con, vc4_hdmi);
1821                         return ret;
1822                 }
1823
1824                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1825         }
1826
1827         return 0;
1828 }
1829
1830 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi)
1831 {
1832         struct platform_device *pdev = vc4_hdmi->pdev;
1833
1834         if (vc4_hdmi->variant->external_irq_controller) {
1835                 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi);
1836                 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi);
1837         }
1838 }
1839
1840 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1841 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1842 {
1843         struct vc4_hdmi *vc4_hdmi = priv;
1844
1845         if (vc4_hdmi->cec_rx_msg.len)
1846                 cec_received_msg(vc4_hdmi->cec_adap,
1847                                  &vc4_hdmi->cec_rx_msg);
1848
1849         return IRQ_HANDLED;
1850 }
1851
1852 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1853 {
1854         struct vc4_hdmi *vc4_hdmi = priv;
1855
1856         if (vc4_hdmi->cec_tx_ok) {
1857                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1858                                   0, 0, 0, 0);
1859         } else {
1860                 /*
1861                  * This CEC implementation makes 1 retry, so if we
1862                  * get a NACK, then that means it made 2 attempts.
1863                  */
1864                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1865                                   0, 2, 0, 0);
1866         }
1867         return IRQ_HANDLED;
1868 }
1869
1870 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1871 {
1872         struct vc4_hdmi *vc4_hdmi = priv;
1873         irqreturn_t ret;
1874
1875         if (vc4_hdmi->cec_irq_was_rx)
1876                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1877         else
1878                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1879
1880         return ret;
1881 }
1882
1883 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1884 {
1885         struct drm_device *dev = vc4_hdmi->connector.dev;
1886         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1887         unsigned int i;
1888
1889         lockdep_assert_held(&vc4_hdmi->hw_lock);
1890
1891         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1892                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1893
1894         if (msg->len > 16) {
1895                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1896                 return;
1897         }
1898
1899         for (i = 0; i < msg->len; i += 4) {
1900                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1901
1902                 msg->msg[i] = val & 0xff;
1903                 msg->msg[i + 1] = (val >> 8) & 0xff;
1904                 msg->msg[i + 2] = (val >> 16) & 0xff;
1905                 msg->msg[i + 3] = (val >> 24) & 0xff;
1906         }
1907 }
1908
1909 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
1910 {
1911         u32 cntrl1;
1912
1913         lockdep_assert_held(&vc4_hdmi->hw_lock);
1914
1915         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1916         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1917         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1918         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1919
1920         return IRQ_WAKE_THREAD;
1921 }
1922
1923 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1924 {
1925         struct vc4_hdmi *vc4_hdmi = priv;
1926         irqreturn_t ret;
1927
1928         spin_lock(&vc4_hdmi->hw_lock);
1929         ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
1930         spin_unlock(&vc4_hdmi->hw_lock);
1931
1932         return ret;
1933 }
1934
1935 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
1936 {
1937         u32 cntrl1;
1938
1939         lockdep_assert_held(&vc4_hdmi->hw_lock);
1940
1941         vc4_hdmi->cec_rx_msg.len = 0;
1942         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1943         vc4_cec_read_msg(vc4_hdmi, cntrl1);
1944         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1945         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1946         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1947
1948         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1949
1950         return IRQ_WAKE_THREAD;
1951 }
1952
1953 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1954 {
1955         struct vc4_hdmi *vc4_hdmi = priv;
1956         irqreturn_t ret;
1957
1958         spin_lock(&vc4_hdmi->hw_lock);
1959         ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
1960         spin_unlock(&vc4_hdmi->hw_lock);
1961
1962         return ret;
1963 }
1964
1965 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1966 {
1967         struct vc4_hdmi *vc4_hdmi = priv;
1968         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1969         irqreturn_t ret;
1970         u32 cntrl5;
1971
1972         if (!(stat & VC4_HDMI_CPU_CEC))
1973                 return IRQ_NONE;
1974
1975         spin_lock(&vc4_hdmi->hw_lock);
1976         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1977         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1978         if (vc4_hdmi->cec_irq_was_rx)
1979                 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
1980         else
1981                 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
1982
1983         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1984         spin_unlock(&vc4_hdmi->hw_lock);
1985
1986         return ret;
1987 }
1988
1989 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
1990 {
1991         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1992         /* clock period in microseconds */
1993         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1994         unsigned long flags;
1995         u32 val;
1996         int ret;
1997
1998         /*
1999          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2000          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2001          * .detect or .get_modes might call .adap_enable, which leads to this
2002          * function being called with that mutex held.
2003          *
2004          * Concurrency is not an issue for the moment since we don't share any
2005          * state with KMS, so we can ignore the lock for now, but we need to
2006          * keep it in mind if we were to change that assumption.
2007          */
2008
2009         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2010         if (ret)
2011                 return ret;
2012
2013         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2014
2015         val = HDMI_READ(HDMI_CEC_CNTRL_5);
2016         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2017                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2018                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2019         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2020                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2021
2022         HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2023                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2024         HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2025         HDMI_WRITE(HDMI_CEC_CNTRL_2,
2026                    ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2027                    ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2028                    ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2029                    ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2030                    ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2031         HDMI_WRITE(HDMI_CEC_CNTRL_3,
2032                    ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2033                    ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2034                    ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2035                    ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2036         HDMI_WRITE(HDMI_CEC_CNTRL_4,
2037                    ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2038                    ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2039                    ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2040                    ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2041
2042         if (!vc4_hdmi->variant->external_irq_controller)
2043                 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2044
2045         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2046
2047         return 0;
2048 }
2049
2050 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2051 {
2052         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2053         unsigned long flags;
2054
2055         /*
2056          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2057          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2058          * .detect or .get_modes might call .adap_enable, which leads to this
2059          * function being called with that mutex held.
2060          *
2061          * Concurrency is not an issue for the moment since we don't share any
2062          * state with KMS, so we can ignore the lock for now, but we need to
2063          * keep it in mind if we were to change that assumption.
2064          */
2065
2066         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2067
2068         if (!vc4_hdmi->variant->external_irq_controller)
2069                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2070
2071         HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2072                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2073
2074         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2075
2076         pm_runtime_put(&vc4_hdmi->pdev->dev);
2077
2078         return 0;
2079 }
2080
2081 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2082 {
2083         if (enable)
2084                 return vc4_hdmi_cec_enable(adap);
2085         else
2086                 return vc4_hdmi_cec_disable(adap);
2087 }
2088
2089 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2090 {
2091         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2092         unsigned long flags;
2093
2094         /*
2095          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2096          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2097          * .detect or .get_modes might call .adap_enable, which leads to this
2098          * function being called with that mutex held.
2099          *
2100          * Concurrency is not an issue for the moment since we don't share any
2101          * state with KMS, so we can ignore the lock for now, but we need to
2102          * keep it in mind if we were to change that assumption.
2103          */
2104
2105         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2106         HDMI_WRITE(HDMI_CEC_CNTRL_1,
2107                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2108                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2109         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2110
2111         return 0;
2112 }
2113
2114 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2115                                       u32 signal_free_time, struct cec_msg *msg)
2116 {
2117         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2118         struct drm_device *dev = vc4_hdmi->connector.dev;
2119         unsigned long flags;
2120         u32 val;
2121         unsigned int i;
2122
2123         /*
2124          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2125          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2126          * .detect or .get_modes might call .adap_enable, which leads to this
2127          * function being called with that mutex held.
2128          *
2129          * Concurrency is not an issue for the moment since we don't share any
2130          * state with KMS, so we can ignore the lock for now, but we need to
2131          * keep it in mind if we were to change that assumption.
2132          */
2133
2134         if (msg->len > 16) {
2135                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2136                 return -ENOMEM;
2137         }
2138
2139         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2140
2141         for (i = 0; i < msg->len; i += 4)
2142                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2143                            (msg->msg[i]) |
2144                            (msg->msg[i + 1] << 8) |
2145                            (msg->msg[i + 2] << 16) |
2146                            (msg->msg[i + 3] << 24));
2147
2148         val = HDMI_READ(HDMI_CEC_CNTRL_1);
2149         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2150         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2151         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2152         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2153         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2154
2155         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2156
2157         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2158
2159         return 0;
2160 }
2161
2162 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2163         .adap_enable = vc4_hdmi_cec_adap_enable,
2164         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2165         .adap_transmit = vc4_hdmi_cec_adap_transmit,
2166 };
2167
2168 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2169 {
2170         struct cec_connector_info conn_info;
2171         struct platform_device *pdev = vc4_hdmi->pdev;
2172         struct device *dev = &pdev->dev;
2173         unsigned long flags;
2174         int ret;
2175
2176         if (!of_find_property(dev->of_node, "interrupts", NULL)) {
2177                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
2178                 return 0;
2179         }
2180
2181         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
2182                                                   vc4_hdmi, "vc4",
2183                                                   CEC_CAP_DEFAULTS |
2184                                                   CEC_CAP_CONNECTOR_INFO, 1);
2185         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
2186         if (ret < 0)
2187                 return ret;
2188
2189         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
2190         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
2191
2192         if (vc4_hdmi->variant->external_irq_controller) {
2193                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"),
2194                                            vc4_cec_irq_handler_rx_bare,
2195                                            vc4_cec_irq_handler_rx_thread, 0,
2196                                            "vc4 hdmi cec rx", vc4_hdmi);
2197                 if (ret)
2198                         goto err_delete_cec_adap;
2199
2200                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"),
2201                                            vc4_cec_irq_handler_tx_bare,
2202                                            vc4_cec_irq_handler_tx_thread, 0,
2203                                            "vc4 hdmi cec tx", vc4_hdmi);
2204                 if (ret)
2205                         goto err_remove_cec_rx_handler;
2206         } else {
2207                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2208                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
2209                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2210
2211                 ret = request_threaded_irq(platform_get_irq(pdev, 0),
2212                                            vc4_cec_irq_handler,
2213                                            vc4_cec_irq_handler_thread, 0,
2214                                            "vc4 hdmi cec", vc4_hdmi);
2215                 if (ret)
2216                         goto err_delete_cec_adap;
2217         }
2218
2219         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
2220         if (ret < 0)
2221                 goto err_remove_handlers;
2222
2223         return 0;
2224
2225 err_remove_handlers:
2226         if (vc4_hdmi->variant->external_irq_controller)
2227                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
2228         else
2229                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
2230
2231 err_remove_cec_rx_handler:
2232         if (vc4_hdmi->variant->external_irq_controller)
2233                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
2234
2235 err_delete_cec_adap:
2236         cec_delete_adapter(vc4_hdmi->cec_adap);
2237
2238         return ret;
2239 }
2240
2241 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
2242 {
2243         struct platform_device *pdev = vc4_hdmi->pdev;
2244
2245         if (vc4_hdmi->variant->external_irq_controller) {
2246                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
2247                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
2248         } else {
2249                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
2250         }
2251
2252         cec_unregister_adapter(vc4_hdmi->cec_adap);
2253 }
2254
2255 static int vc4_hdmi_cec_resume(struct vc4_hdmi *vc4_hdmi)
2256 {
2257         unsigned long flags;
2258         u32 value;
2259
2260         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2261         value = HDMI_READ(HDMI_CEC_CNTRL_1);
2262         /* Set the logical address to Unregistered */
2263         value |= VC4_HDMI_CEC_ADDR_MASK;
2264         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
2265         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2266
2267         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
2268
2269         if (!vc4_hdmi->variant->external_irq_controller) {
2270                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2271                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
2272                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2273         }
2274
2275         return 0;
2276 }
2277 #else
2278 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2279 {
2280         return 0;
2281 }
2282
2283 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
2284
2285 static int vc4_hdmi_cec_resume(struct vc4_hdmi *vc4_hdmi)
2286 {
2287         return 0;
2288 }
2289 #endif
2290
2291 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
2292                                  struct debugfs_regset32 *regset,
2293                                  enum vc4_hdmi_regs reg)
2294 {
2295         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2296         struct debugfs_reg32 *regs, *new_regs;
2297         unsigned int count = 0;
2298         unsigned int i;
2299
2300         regs = kcalloc(variant->num_registers, sizeof(*regs),
2301                        GFP_KERNEL);
2302         if (!regs)
2303                 return -ENOMEM;
2304
2305         for (i = 0; i < variant->num_registers; i++) {
2306                 const struct vc4_hdmi_register *field = &variant->registers[i];
2307
2308                 if (field->reg != reg)
2309                         continue;
2310
2311                 regs[count].name = field->name;
2312                 regs[count].offset = field->offset;
2313                 count++;
2314         }
2315
2316         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
2317         if (!new_regs)
2318                 return -ENOMEM;
2319
2320         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
2321         regset->regs = new_regs;
2322         regset->nregs = count;
2323
2324         return 0;
2325 }
2326
2327 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2328 {
2329         struct platform_device *pdev = vc4_hdmi->pdev;
2330         struct device *dev = &pdev->dev;
2331         int ret;
2332
2333         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
2334         if (IS_ERR(vc4_hdmi->hdmicore_regs))
2335                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
2336
2337         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
2338         if (IS_ERR(vc4_hdmi->hd_regs))
2339                 return PTR_ERR(vc4_hdmi->hd_regs);
2340
2341         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2342         if (ret)
2343                 return ret;
2344
2345         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2346         if (ret)
2347                 return ret;
2348
2349         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
2350         if (IS_ERR(vc4_hdmi->pixel_clock)) {
2351                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
2352                 if (ret != -EPROBE_DEFER)
2353                         DRM_ERROR("Failed to get pixel clock\n");
2354                 return ret;
2355         }
2356
2357         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2358         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2359                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2360                 return PTR_ERR(vc4_hdmi->hsm_clock);
2361         }
2362         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2363         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2364
2365         return 0;
2366 }
2367
2368 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2369 {
2370         struct platform_device *pdev = vc4_hdmi->pdev;
2371         struct device *dev = &pdev->dev;
2372         struct resource *res;
2373         int ret;
2374
2375         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2376         if (!res)
2377                 return -ENODEV;
2378
2379         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2380                                                resource_size(res));
2381         if (!vc4_hdmi->hdmicore_regs)
2382                 return -ENOMEM;
2383
2384         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2385         if (!res)
2386                 return -ENODEV;
2387
2388         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2389         if (!vc4_hdmi->hd_regs)
2390                 return -ENOMEM;
2391
2392         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2393         if (!res)
2394                 return -ENODEV;
2395
2396         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2397         if (!vc4_hdmi->cec_regs)
2398                 return -ENOMEM;
2399
2400         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2401         if (!res)
2402                 return -ENODEV;
2403
2404         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2405         if (!vc4_hdmi->csc_regs)
2406                 return -ENOMEM;
2407
2408         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2409         if (!res)
2410                 return -ENODEV;
2411
2412         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2413         if (!vc4_hdmi->dvp_regs)
2414                 return -ENOMEM;
2415
2416         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2417         if (!res)
2418                 return -ENODEV;
2419
2420         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2421         if (!vc4_hdmi->phy_regs)
2422                 return -ENOMEM;
2423
2424         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2425         if (!res)
2426                 return -ENODEV;
2427
2428         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2429         if (!vc4_hdmi->ram_regs)
2430                 return -ENOMEM;
2431
2432         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2433         if (!res)
2434                 return -ENODEV;
2435
2436         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2437         if (!vc4_hdmi->rm_regs)
2438                 return -ENOMEM;
2439
2440         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2441         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2442                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2443                 return PTR_ERR(vc4_hdmi->hsm_clock);
2444         }
2445
2446         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2447         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2448                 DRM_ERROR("Failed to get pixel bvb clock\n");
2449                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2450         }
2451
2452         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2453         if (IS_ERR(vc4_hdmi->audio_clock)) {
2454                 DRM_ERROR("Failed to get audio clock\n");
2455                 return PTR_ERR(vc4_hdmi->audio_clock);
2456         }
2457
2458         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2459         if (IS_ERR(vc4_hdmi->cec_clock)) {
2460                 DRM_ERROR("Failed to get CEC clock\n");
2461                 return PTR_ERR(vc4_hdmi->cec_clock);
2462         }
2463
2464         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2465         if (IS_ERR(vc4_hdmi->reset)) {
2466                 DRM_ERROR("Failed to get HDMI reset line\n");
2467                 return PTR_ERR(vc4_hdmi->reset);
2468         }
2469
2470         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2471         if (ret)
2472                 return ret;
2473
2474         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2475         if (ret)
2476                 return ret;
2477
2478         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
2479         if (ret)
2480                 return ret;
2481
2482         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
2483         if (ret)
2484                 return ret;
2485
2486         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
2487         if (ret)
2488                 return ret;
2489
2490         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
2491         if (ret)
2492                 return ret;
2493
2494         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
2495         if (ret)
2496                 return ret;
2497
2498         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
2499         if (ret)
2500                 return ret;
2501
2502         return 0;
2503 }
2504
2505 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev)
2506 {
2507         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2508
2509         clk_disable_unprepare(vc4_hdmi->hsm_clock);
2510
2511         return 0;
2512 }
2513
2514 static int vc4_hdmi_runtime_resume(struct device *dev)
2515 {
2516         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2517         int ret;
2518
2519         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
2520         if (ret)
2521                 return ret;
2522
2523         if (vc4_hdmi->variant->reset)
2524                 vc4_hdmi->variant->reset(vc4_hdmi);
2525
2526         ret = vc4_hdmi_cec_resume(vc4_hdmi);
2527         if (ret) {
2528                 clk_disable_unprepare(vc4_hdmi->hsm_clock);
2529                 return ret;
2530         }
2531
2532         return 0;
2533 }
2534
2535 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2536 {
2537         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2538         struct platform_device *pdev = to_platform_device(dev);
2539         struct drm_device *drm = dev_get_drvdata(master);
2540         struct vc4_hdmi *vc4_hdmi;
2541         struct drm_encoder *encoder;
2542         struct device_node *ddc_node;
2543         int ret;
2544
2545         vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2546         if (!vc4_hdmi)
2547                 return -ENOMEM;
2548         mutex_init(&vc4_hdmi->mutex);
2549         spin_lock_init(&vc4_hdmi->hw_lock);
2550         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2551
2552         dev_set_drvdata(dev, vc4_hdmi);
2553         encoder = &vc4_hdmi->encoder.base.base;
2554         vc4_hdmi->encoder.base.type = variant->encoder_type;
2555         vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2556         vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2557         vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2558         vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2559         vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2560         vc4_hdmi->pdev = pdev;
2561         vc4_hdmi->variant = variant;
2562
2563         /*
2564          * Since we don't know the state of the controller and its
2565          * display (if any), let's assume it's always enabled.
2566          * vc4_hdmi_disable_scrambling() will thus run at boot, make
2567          * sure it's disabled, and avoid any inconsistency.
2568          */
2569         if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
2570                 vc4_hdmi->scdc_enabled = true;
2571
2572         ret = variant->init_resources(vc4_hdmi);
2573         if (ret)
2574                 return ret;
2575
2576         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2577         if (!ddc_node) {
2578                 DRM_ERROR("Failed to find ddc node in device tree\n");
2579                 return -ENODEV;
2580         }
2581
2582         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2583         of_node_put(ddc_node);
2584         if (!vc4_hdmi->ddc) {
2585                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2586                 return -EPROBE_DEFER;
2587         }
2588
2589         /* Only use the GPIO HPD pin if present in the DT, otherwise
2590          * we'll use the HDMI core's register.
2591          */
2592         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2593         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
2594                 ret = PTR_ERR(vc4_hdmi->hpd_gpio);
2595                 goto err_put_ddc;
2596         }
2597
2598         vc4_hdmi->disable_wifi_frequencies =
2599                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2600
2601         if (variant->max_pixel_clock == 600000000) {
2602                 struct vc4_dev *vc4 = to_vc4_dev(drm);
2603                 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
2604
2605                 if (max_rate < 550000000)
2606                         vc4_hdmi->disable_4kp60 = true;
2607         }
2608
2609         /*
2610          * If we boot without any cable connected to the HDMI connector,
2611          * the firmware will skip the HSM initialization and leave it
2612          * with a rate of 0, resulting in a bus lockup when we're
2613          * accessing the registers even if it's enabled.
2614          *
2615          * Let's put a sensible default at runtime_resume so that we
2616          * don't end up in this situation.
2617          */
2618         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
2619         if (ret)
2620                 goto err_put_ddc;
2621
2622         pm_runtime_enable(dev);
2623
2624         ret = pm_runtime_resume_and_get(dev);
2625         if (ret)
2626                 goto err_put_ddc;
2627
2628         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
2629              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
2630             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
2631                 clk_prepare_enable(vc4_hdmi->pixel_clock);
2632                 clk_prepare_enable(vc4_hdmi->hsm_clock);
2633                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
2634         }
2635
2636         drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2637         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2638
2639         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2640         if (ret)
2641                 goto err_destroy_encoder;
2642
2643         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
2644         if (ret)
2645                 goto err_destroy_conn;
2646
2647         ret = vc4_hdmi_cec_init(vc4_hdmi);
2648         if (ret)
2649                 goto err_free_hotplug;
2650
2651         ret = vc4_hdmi_audio_init(vc4_hdmi);
2652         if (ret)
2653                 goto err_free_cec;
2654
2655         vc4_debugfs_add_file(drm, variant->debugfs_name,
2656                              vc4_hdmi_debugfs_regs,
2657                              vc4_hdmi);
2658
2659         pm_runtime_put_sync(dev);
2660
2661         return 0;
2662
2663 err_free_cec:
2664         vc4_hdmi_cec_exit(vc4_hdmi);
2665 err_free_hotplug:
2666         vc4_hdmi_hotplug_exit(vc4_hdmi);
2667 err_destroy_conn:
2668         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2669 err_destroy_encoder:
2670         drm_encoder_cleanup(encoder);
2671         pm_runtime_put_sync(dev);
2672         pm_runtime_disable(dev);
2673 err_put_ddc:
2674         put_device(&vc4_hdmi->ddc->dev);
2675
2676         return ret;
2677 }
2678
2679 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2680                             void *data)
2681 {
2682         struct vc4_hdmi *vc4_hdmi;
2683
2684         /*
2685          * ASoC makes it a bit hard to retrieve a pointer to the
2686          * vc4_hdmi structure. Registering the card will overwrite our
2687          * device drvdata with a pointer to the snd_soc_card structure,
2688          * which can then be used to retrieve whatever drvdata we want
2689          * to associate.
2690          *
2691          * However, that doesn't fly in the case where we wouldn't
2692          * register an ASoC card (because of an old DT that is missing
2693          * the dmas properties for example), then the card isn't
2694          * registered and the device drvdata wouldn't be set.
2695          *
2696          * We can deal with both cases by making sure a snd_soc_card
2697          * pointer and a vc4_hdmi structure are pointing to the same
2698          * memory address, so we can treat them indistinctly without any
2699          * issue.
2700          */
2701         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2702         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2703         vc4_hdmi = dev_get_drvdata(dev);
2704
2705         kfree(vc4_hdmi->hdmi_regset.regs);
2706         kfree(vc4_hdmi->hd_regset.regs);
2707
2708         vc4_hdmi_audio_exit(vc4_hdmi);
2709         vc4_hdmi_cec_exit(vc4_hdmi);
2710         vc4_hdmi_hotplug_exit(vc4_hdmi);
2711         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2712         drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2713
2714         pm_runtime_disable(dev);
2715
2716         put_device(&vc4_hdmi->ddc->dev);
2717 }
2718
2719 static const struct component_ops vc4_hdmi_ops = {
2720         .bind   = vc4_hdmi_bind,
2721         .unbind = vc4_hdmi_unbind,
2722 };
2723
2724 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2725 {
2726         return component_add(&pdev->dev, &vc4_hdmi_ops);
2727 }
2728
2729 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2730 {
2731         component_del(&pdev->dev, &vc4_hdmi_ops);
2732         return 0;
2733 }
2734
2735 static const struct vc4_hdmi_variant bcm2835_variant = {
2736         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2737         .debugfs_name           = "hdmi_regs",
2738         .card_name              = "vc4-hdmi",
2739         .max_pixel_clock        = 162000000,
2740         .registers              = vc4_hdmi_fields,
2741         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
2742
2743         .init_resources         = vc4_hdmi_init_resources,
2744         .csc_setup              = vc4_hdmi_csc_setup,
2745         .reset                  = vc4_hdmi_reset,
2746         .set_timings            = vc4_hdmi_set_timings,
2747         .phy_init               = vc4_hdmi_phy_init,
2748         .phy_disable            = vc4_hdmi_phy_disable,
2749         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
2750         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
2751         .channel_map            = vc4_hdmi_channel_map,
2752         .supports_hdr           = false,
2753 };
2754
2755 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2756         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2757         .debugfs_name           = "hdmi0_regs",
2758         .card_name              = "vc4-hdmi-0",
2759         .max_pixel_clock        = 600000000,
2760         .registers              = vc5_hdmi_hdmi0_fields,
2761         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2762         .phy_lane_mapping       = {
2763                 PHY_LANE_0,
2764                 PHY_LANE_1,
2765                 PHY_LANE_2,
2766                 PHY_LANE_CK,
2767         },
2768         .unsupported_odd_h_timings      = true,
2769         .external_irq_controller        = true,
2770
2771         .init_resources         = vc5_hdmi_init_resources,
2772         .csc_setup              = vc5_hdmi_csc_setup,
2773         .reset                  = vc5_hdmi_reset,
2774         .set_timings            = vc5_hdmi_set_timings,
2775         .phy_init               = vc5_hdmi_phy_init,
2776         .phy_disable            = vc5_hdmi_phy_disable,
2777         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2778         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2779         .channel_map            = vc5_hdmi_channel_map,
2780         .supports_hdr           = true,
2781         .hp_detect              = vc5_hdmi_hp_detect,
2782 };
2783
2784 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2785         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
2786         .debugfs_name           = "hdmi1_regs",
2787         .card_name              = "vc4-hdmi-1",
2788         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2789         .registers              = vc5_hdmi_hdmi1_fields,
2790         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2791         .phy_lane_mapping       = {
2792                 PHY_LANE_1,
2793                 PHY_LANE_0,
2794                 PHY_LANE_CK,
2795                 PHY_LANE_2,
2796         },
2797         .unsupported_odd_h_timings      = true,
2798         .external_irq_controller        = true,
2799
2800         .init_resources         = vc5_hdmi_init_resources,
2801         .csc_setup              = vc5_hdmi_csc_setup,
2802         .reset                  = vc5_hdmi_reset,
2803         .set_timings            = vc5_hdmi_set_timings,
2804         .phy_init               = vc5_hdmi_phy_init,
2805         .phy_disable            = vc5_hdmi_phy_disable,
2806         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2807         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2808         .channel_map            = vc5_hdmi_channel_map,
2809         .supports_hdr           = true,
2810         .hp_detect              = vc5_hdmi_hp_detect,
2811 };
2812
2813 static const struct of_device_id vc4_hdmi_dt_match[] = {
2814         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2815         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2816         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2817         {}
2818 };
2819
2820 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
2821         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
2822                            vc4_hdmi_runtime_resume,
2823                            NULL)
2824 };
2825
2826 struct platform_driver vc4_hdmi_driver = {
2827         .probe = vc4_hdmi_dev_probe,
2828         .remove = vc4_hdmi_dev_remove,
2829         .driver = {
2830                 .name = "vc4_hdmi",
2831                 .of_match_table = vc4_hdmi_dt_match,
2832                 .pm = &vc4_hdmi_pm_ops,
2833         },
2834 };