drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <drm/drm_simple_kms_helper.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include <linux/clk.h>
  40 #include <linux/component.h>
  41 #include <linux/i2c.h>
  42 #include <linux/of_address.h>
  43 #include <linux/of_gpio.h>
  44 #include <linux/of_platform.h>
  45 #include <linux/pm_runtime.h>
  46 #include <linux/rational.h>
  47 #include <linux/reset.h>
  48 #include <sound/dmaengine_pcm.h>
  49 #include <sound/hdmi-codec.h>
  50 #include <sound/pcm_drm_eld.h>
  51 #include <sound/pcm_params.h>
  52 #include <sound/soc.h>
  53 #include "media/cec.h"
  54 #include "vc4_drv.h"
  55 #include "vc4_hdmi.h"
  56 #include "vc4_hdmi_regs.h"
  57 #include "vc4_regs.h"
  58
  59 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  60 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  61 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  62 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  63 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  64 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  65
  66 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  67 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  68 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  69 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  70
  71 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  72 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  73 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  74 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  75 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  76 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  77
  78 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  79 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  80
  81 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  82
  83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  85
  86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  88
  89 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  90
  91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
  92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
  93
  94 # define VC4_HD_M_SW_RST                        BIT(2)
  95 # define VC4_HD_M_ENABLE                        BIT(0)
  96
  97 #define HSM_MIN_CLOCK_FREQ      120000000
  98 #define CEC_CLOCK_FREQ 40000
  99
 100 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 101
 102 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode)
 103 {
 104         return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK;
 105 }
 106
 107 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 108 {
 109         struct drm_info_node *node = (struct drm_info_node *)m->private;
 110         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
 111         struct drm_printer p = drm_seq_file_printer(m);
 112
 113         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 114         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 115
 116         return 0;
 117 }
 118
 119 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 120 {
 121         unsigned long flags;
 122
 123         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 124
 125         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 126         udelay(1);
 127         HDMI_WRITE(HDMI_M_CTL, 0);
 128
 129         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 130
 131         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 132                    VC4_HDMI_SW_RESET_HDMI |
 133                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 134
 135         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 136
 137         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 138 }
 139
 140 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 141 {
 142         unsigned long flags;
 143
 144         reset_control_reset(vc4_hdmi->reset);
 145
 146         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 147
 148         HDMI_WRITE(HDMI_DVP_CTL, 0);
 149
 150         HDMI_WRITE(HDMI_CLOCK_STOP,
 151                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 152
 153         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 154 }
 155
 156 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 157 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 158 {
 159         unsigned long cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
 160         unsigned long flags;
 161         u16 clk_cnt;
 162         u32 value;
 163
 164         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 165
 166         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 167         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 168
 169         /*
 170          * Set the clock divider: the hsm_clock rate and this divider
 171          * setting will give a 40 kHz CEC clock.
 172          */
 173         clk_cnt = cec_rate / CEC_CLOCK_FREQ;
 174         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 175         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 176
 177         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 178 }
 179 #else
 180 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 181 #endif
 182
 183 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder);
 184
 185 static enum drm_connector_status
 186 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 187 {
 188         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 189         bool connected = false;
 190
 191         mutex_lock(&vc4_hdmi->mutex);
 192
 193         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 194
 195         if (vc4_hdmi->hpd_gpio) {
 196                 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
 197                         connected = true;
 198         } else {
 199                 unsigned long flags;
 200                 u32 hotplug;
 201
 202                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 203                 hotplug = HDMI_READ(HDMI_HOTPLUG);
 204                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 205
 206                 if (hotplug & VC4_HDMI_HOTPLUG_CONNECTED)
 207                         connected = true;
 208         }
 209
 210         if (connected) {
 211                 if (connector->status != connector_status_connected) {
 212                         struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
 213
 214                         if (edid) {
 215                                 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 216                                 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
 217                                 kfree(edid);
 218                         }
 219                 }
 220
 221                 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base);
 222                 pm_runtime_put(&vc4_hdmi->pdev->dev);
 223                 mutex_unlock(&vc4_hdmi->mutex);
 224                 return connector_status_connected;
 225         }
 226
 227         cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 228         pm_runtime_put(&vc4_hdmi->pdev->dev);
 229         mutex_unlock(&vc4_hdmi->mutex);
 230         return connector_status_disconnected;
 231 }
 232
 233 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 234 {
 235         drm_connector_unregister(connector);
 236         drm_connector_cleanup(connector);
 237 }
 238
 239 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 240 {
 241         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 242         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 243         int ret = 0;
 244         struct edid *edid;
 245
 246         mutex_lock(&vc4_hdmi->mutex);
 247
 248         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 249         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 250         if (!edid) {
 251                 ret = -ENODEV;
 252                 goto out;
 253         }
 254
 255         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 256
 257         drm_connector_update_edid_property(connector, edid);
 258         ret = drm_add_edid_modes(connector, edid);
 259         kfree(edid);
 260
 261         if (vc4_hdmi->disable_4kp60) {
 262                 struct drm_device *drm = connector->dev;
 263                 struct drm_display_mode *mode;
 264
 265                 list_for_each_entry(mode, &connector->probed_modes, head) {
 266                         if (vc4_hdmi_mode_needs_scrambling(mode)) {
 267                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 268                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 269                         }
 270                 }
 271         }
 272
 273 out:
 274         mutex_unlock(&vc4_hdmi->mutex);
 275
 276         return ret;
 277 }
 278
 279 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 280                                            struct drm_atomic_state *state)
 281 {
 282         struct drm_connector_state *old_state =
 283                 drm_atomic_get_old_connector_state(state, connector);
 284         struct drm_connector_state *new_state =
 285                 drm_atomic_get_new_connector_state(state, connector);
 286         struct drm_crtc *crtc = new_state->crtc;
 287
 288         if (!crtc)
 289                 return 0;
 290
 291         if (old_state->colorspace != new_state->colorspace ||
 292             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 293                 struct drm_crtc_state *crtc_state;
 294
 295                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 296                 if (IS_ERR(crtc_state))
 297                         return PTR_ERR(crtc_state);
 298
 299                 crtc_state->mode_changed = true;
 300         }
 301
 302         return 0;
 303 }
 304
 305 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 306 {
 307         struct vc4_hdmi_connector_state *old_state =
 308                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 309         struct vc4_hdmi_connector_state *new_state =
 310                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 311
 312         if (connector->state)
 313                 __drm_atomic_helper_connector_destroy_state(connector->state);
 314
 315         kfree(old_state);
 316         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 317
 318         if (!new_state)
 319                 return;
 320
 321         new_state->base.max_bpc = 8;
 322         new_state->base.max_requested_bpc = 8;
 323         drm_atomic_helper_connector_tv_reset(connector);
 324 }
 325
 326 static struct drm_connector_state *
 327 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 328 {
 329         struct drm_connector_state *conn_state = connector->state;
 330         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 331         struct vc4_hdmi_connector_state *new_state;
 332
 333         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 334         if (!new_state)
 335                 return NULL;
 336
 337         new_state->pixel_rate = vc4_state->pixel_rate;
 338         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 339
 340         return &new_state->base;
 341 }
 342
 343 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 344         .detect = vc4_hdmi_connector_detect,
 345         .fill_modes = drm_helper_probe_single_connector_modes,
 346         .destroy = vc4_hdmi_connector_destroy,
 347         .reset = vc4_hdmi_connector_reset,
 348         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 349         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 350 };
 351
 352 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 353         .get_modes = vc4_hdmi_connector_get_modes,
 354         .atomic_check = vc4_hdmi_connector_atomic_check,
 355 };
 356
 357 static int vc4_hdmi_connector_init(struct drm_device *dev,
 358                                    struct vc4_hdmi *vc4_hdmi)
 359 {
 360         struct drm_connector *connector = &vc4_hdmi->connector;
 361         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 362         int ret;
 363
 364         drm_connector_init_with_ddc(dev, connector,
 365                                     &vc4_hdmi_connector_funcs,
 366                                     DRM_MODE_CONNECTOR_HDMIA,
 367                                     vc4_hdmi->ddc);
 368         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 369
 370         /*
 371          * Some of the properties below require access to state, like bpc.
 372          * Allocate some default initial connector state with our reset helper.
 373          */
 374         if (connector->funcs->reset)
 375                 connector->funcs->reset(connector);
 376
 377         /* Create and attach TV margin props to this connector. */
 378         ret = drm_mode_create_tv_margin_properties(dev);
 379         if (ret)
 380                 return ret;
 381
 382         ret = drm_mode_create_hdmi_colorspace_property(connector);
 383         if (ret)
 384                 return ret;
 385
 386         drm_connector_attach_colorspace_property(connector);
 387         drm_connector_attach_tv_margin_properties(connector);
 388         drm_connector_attach_max_bpc_property(connector, 8, 12);
 389
 390         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 391                              DRM_CONNECTOR_POLL_DISCONNECT);
 392
 393         connector->interlace_allowed = 1;
 394         connector->doublescan_allowed = 0;
 395
 396         if (vc4_hdmi->variant->supports_hdr)
 397                 drm_connector_attach_hdr_output_metadata_property(connector);
 398
 399         drm_connector_attach_encoder(connector, encoder);
 400
 401         return 0;
 402 }
 403
 404 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 405                                 enum hdmi_infoframe_type type,
 406                                 bool poll)
 407 {
 408         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 409         u32 packet_id = type - 0x80;
 410         unsigned long flags;
 411
 412         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 413         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 414                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 415         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 416
 417         if (!poll)
 418                 return 0;
 419
 420         return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 421                           BIT(packet_id)), 100);
 422 }
 423
 424 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 425                                      union hdmi_infoframe *frame)
 426 {
 427         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 428         u32 packet_id = frame->any.type - 0x80;
 429         const struct vc4_hdmi_register *ram_packet_start =
 430                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 431         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 432         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 433                                                        ram_packet_start->reg);
 434         uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
 435         unsigned long flags;
 436         ssize_t len, i;
 437         int ret;
 438
 439         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 440                     VC4_HDMI_RAM_PACKET_ENABLE),
 441                   "Packet RAM has to be on to store the packet.");
 442
 443         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 444         if (len < 0)
 445                 return;
 446
 447         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 448         if (ret) {
 449                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 450                 return;
 451         }
 452
 453         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 454
 455         for (i = 0; i < len; i += 7) {
 456                 writel(buffer[i + 0] << 0 |
 457                        buffer[i + 1] << 8 |
 458                        buffer[i + 2] << 16,
 459                        base + packet_reg);
 460                 packet_reg += 4;
 461
 462                 writel(buffer[i + 3] << 0 |
 463                        buffer[i + 4] << 8 |
 464                        buffer[i + 5] << 16 |
 465                        buffer[i + 6] << 24,
 466                        base + packet_reg);
 467                 packet_reg += 4;
 468         }
 469
 470         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 471                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 472
 473         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 474
 475         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 476                         BIT(packet_id)), 100);
 477         if (ret)
 478                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 479 }
 480
 481 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 482 {
 483         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 484         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 485         struct drm_connector *connector = &vc4_hdmi->connector;
 486         struct drm_connector_state *cstate = connector->state;
 487         struct drm_crtc *crtc = encoder->crtc;
 488         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 489         union hdmi_infoframe frame;
 490         int ret;
 491
 492         lockdep_assert_held(&vc4_hdmi->mutex);
 493
 494         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 495                                                        connector, mode);
 496         if (ret < 0) {
 497                 DRM_ERROR("couldn't fill AVI infoframe\n");
 498                 return;
 499         }
 500
 501         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 502                                            connector, mode,
 503                                            vc4_encoder->limited_rgb_range ?
 504                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 505                                            HDMI_QUANTIZATION_RANGE_FULL);
 506         drm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate);
 507         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 508
 509         vc4_hdmi_write_infoframe(encoder, &frame);
 510 }
 511
 512 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 513 {
 514         union hdmi_infoframe frame;
 515         int ret;
 516
 517         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 518         if (ret < 0) {
 519                 DRM_ERROR("couldn't fill SPD infoframe\n");
 520                 return;
 521         }
 522
 523         frame.spd.sdi = HDMI_SPD_SDI_PC;
 524
 525         vc4_hdmi_write_infoframe(encoder, &frame);
 526 }
 527
 528 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 529 {
 530         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 531         struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
 532         union hdmi_infoframe frame;
 533
 534         memcpy(&frame.audio, audio, sizeof(*audio));
 535         vc4_hdmi_write_infoframe(encoder, &frame);
 536 }
 537
 538 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 539 {
 540         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 541         struct drm_connector *connector = &vc4_hdmi->connector;
 542         struct drm_connector_state *conn_state = connector->state;
 543         union hdmi_infoframe frame;
 544
 545         lockdep_assert_held(&vc4_hdmi->mutex);
 546
 547         if (!vc4_hdmi->variant->supports_hdr)
 548                 return;
 549
 550         if (!conn_state->hdr_output_metadata)
 551                 return;
 552
 553         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 554                 return;
 555
 556         vc4_hdmi_write_infoframe(encoder, &frame);
 557 }
 558
 559 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 560 {
 561         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 562
 563         lockdep_assert_held(&vc4_hdmi->mutex);
 564
 565         vc4_hdmi_set_avi_infoframe(encoder);
 566         vc4_hdmi_set_spd_infoframe(encoder);
 567         /*
 568          * If audio was streaming, then we need to reenabled the audio
 569          * infoframe here during encoder_enable.
 570          */
 571         if (vc4_hdmi->audio.streaming)
 572                 vc4_hdmi_set_audio_infoframe(encoder);
 573
 574         vc4_hdmi_set_hdr_infoframe(encoder);
 575 }
 576
 577 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
 578                                          struct drm_display_mode *mode)
 579 {
 580         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 581         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 582         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 583
 584         lockdep_assert_held(&vc4_hdmi->mutex);
 585
 586         if (!vc4_encoder->hdmi_monitor)
 587                 return false;
 588
 589         if (!display->hdmi.scdc.supported ||
 590             !display->hdmi.scdc.scrambling.supported)
 591                 return false;
 592
 593         return true;
 594 }
 595
 596 #define SCRAMBLING_POLLING_DELAY_MS     1000
 597
 598 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 599 {
 600         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 601         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 602         unsigned long flags;
 603
 604         lockdep_assert_held(&vc4_hdmi->mutex);
 605
 606         if (!vc4_hdmi_supports_scrambling(encoder, mode))
 607                 return;
 608
 609         if (!vc4_hdmi_mode_needs_scrambling(mode))
 610                 return;
 611
 612         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 613         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 614
 615         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 616         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
 617                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 618         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 619
 620         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 621                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 622 }
 623
 624 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
 625 {
 626         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 627         struct drm_crtc *crtc = encoder->crtc;
 628         unsigned long flags;
 629
 630         /*
 631          * At boot, encoder->crtc will be NULL. Since we don't know the
 632          * state of the scrambler and in order to avoid any
 633          * inconsistency, let's disable it all the time.
 634          */
 635         if (crtc && !vc4_hdmi_supports_scrambling(encoder, &crtc->mode))
 636                 return;
 637
 638         if (crtc && !vc4_hdmi_mode_needs_scrambling(&crtc->mode))
 639                 return;
 640
 641         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
 642                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
 643
 644         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 645         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
 646                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 647         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 648
 649         drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
 650         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
 651 }
 652
 653 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
 654 {
 655         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
 656                                                  struct vc4_hdmi,
 657                                                  scrambling_work);
 658
 659         if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
 660                 return;
 661
 662         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 663         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 664
 665         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 666                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 667 }
 668
 669 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 670                                                struct drm_atomic_state *state)
 671 {
 672         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 673         unsigned long flags;
 674
 675         mutex_lock(&vc4_hdmi->mutex);
 676
 677         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 678
 679         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 680
 681         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
 682
 683         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 684
 685         mdelay(1);
 686
 687         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 688         HDMI_WRITE(HDMI_VID_CTL,
 689                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 690         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 691
 692         vc4_hdmi_disable_scrambling(encoder);
 693
 694         mutex_unlock(&vc4_hdmi->mutex);
 695 }
 696
 697 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
 698                                                  struct drm_atomic_state *state)
 699 {
 700         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 701         unsigned long flags;
 702         int ret;
 703
 704         mutex_lock(&vc4_hdmi->mutex);
 705
 706         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 707         HDMI_WRITE(HDMI_VID_CTL,
 708                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 709         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 710
 711         if (vc4_hdmi->variant->phy_disable)
 712                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 713
 714         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 715         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 716
 717         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 718         if (ret < 0)
 719                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 720
 721         mutex_unlock(&vc4_hdmi->mutex);
 722 }
 723
 724 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 725 {
 726 }
 727
 728 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 729 {
 730         unsigned long flags;
 731         u32 csc_ctl;
 732
 733         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 734
 735         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 736                                 VC4_HD_CSC_CTL_ORDER);
 737
 738         if (enable) {
 739                 /* CEA VICs other than #1 requre limited range RGB
 740                  * output unless overridden by an AVI infoframe.
 741                  * Apply a colorspace conversion to squash 0-255 down
 742                  * to 16-235.  The matrix here is:
 743                  *
 744                  * [ 0      0      0.8594 16]
 745                  * [ 0      0.8594 0      16]
 746                  * [ 0.8594 0      0      16]
 747                  * [ 0      0      0       1]
 748                  */
 749                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 750                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 751                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 752                                          VC4_HD_CSC_CTL_MODE);
 753
 754                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 755                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 756                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 757                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 758                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 759                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 760         }
 761
 762         /* The RGB order applies even when CSC is disabled. */
 763         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 764
 765         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 766 }
 767
 768 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 769 {
 770         unsigned long flags;
 771         u32 csc_ctl;
 772
 773         csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
 774
 775         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 776
 777         if (enable) {
 778                 /* CEA VICs other than #1 requre limited range RGB
 779                  * output unless overridden by an AVI infoframe.
 780                  * Apply a colorspace conversion to squash 0-255 down
 781                  * to 16-235.  The matrix here is:
 782                  *
 783                  * [ 0.8594 0      0      16]
 784                  * [ 0      0.8594 0      16]
 785                  * [ 0      0      0.8594 16]
 786                  * [ 0      0      0       1]
 787                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 788                  */
 789                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
 790                 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
 791                 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
 792                 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
 793                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 794                 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
 795         } else {
 796                 /* Still use the matrix for full range, but make it unity.
 797                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 798                  */
 799                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
 800                 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
 801                 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
 802                 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
 803                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 804                 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
 805         }
 806
 807         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 808
 809         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 810 }
 811
 812 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 813                                  struct drm_connector_state *state,
 814                                  struct drm_display_mode *mode)
 815 {
 816         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 817         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 818         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 819         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 820         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 821                                    VC4_HDMI_VERTA_VSP) |
 822                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 823                                    VC4_HDMI_VERTA_VFP) |
 824                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 825         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 826                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 827                                    VC4_HDMI_VERTB_VBP));
 828         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 829                           VC4_SET_FIELD(mode->crtc_vtotal -
 830                                         mode->crtc_vsync_end -
 831                                         interlaced,
 832                                         VC4_HDMI_VERTB_VBP));
 833         unsigned long flags;
 834
 835         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 836
 837         HDMI_WRITE(HDMI_HORZA,
 838                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 839                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 840                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 841                                  VC4_HDMI_HORZA_HAP));
 842
 843         HDMI_WRITE(HDMI_HORZB,
 844                    VC4_SET_FIELD((mode->htotal -
 845                                   mode->hsync_end) * pixel_rep,
 846                                  VC4_HDMI_HORZB_HBP) |
 847                    VC4_SET_FIELD((mode->hsync_end -
 848                                   mode->hsync_start) * pixel_rep,
 849                                  VC4_HDMI_HORZB_HSP) |
 850                    VC4_SET_FIELD((mode->hsync_start -
 851                                   mode->hdisplay) * pixel_rep,
 852                                  VC4_HDMI_HORZB_HFP));
 853
 854         HDMI_WRITE(HDMI_VERTA0, verta);
 855         HDMI_WRITE(HDMI_VERTA1, verta);
 856
 857         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 858         HDMI_WRITE(HDMI_VERTB1, vertb);
 859
 860         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 861 }
 862
 863 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 864                                  struct drm_connector_state *state,
 865                                  struct drm_display_mode *mode)
 866 {
 867         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 868         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 869         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 870         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 871         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 872                                    VC5_HDMI_VERTA_VSP) |
 873                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 874                                    VC5_HDMI_VERTA_VFP) |
 875                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
 876         u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 877                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 878                                    VC4_HDMI_VERTB_VBP));
 879         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 880                           VC4_SET_FIELD(mode->crtc_vtotal -
 881                                         mode->crtc_vsync_end -
 882                                         interlaced,
 883                                         VC4_HDMI_VERTB_VBP));
 884         unsigned long flags;
 885         unsigned char gcp;
 886         bool gcp_en;
 887         u32 reg;
 888
 889         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 890
 891         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
 892         HDMI_WRITE(HDMI_HORZA,
 893                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
 894                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
 895                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 896                                  VC5_HDMI_HORZA_HAP) |
 897                    VC4_SET_FIELD((mode->hsync_start -
 898                                   mode->hdisplay) * pixel_rep,
 899                                  VC5_HDMI_HORZA_HFP));
 900
 901         HDMI_WRITE(HDMI_HORZB,
 902                    VC4_SET_FIELD((mode->htotal -
 903                                   mode->hsync_end) * pixel_rep,
 904                                  VC5_HDMI_HORZB_HBP) |
 905                    VC4_SET_FIELD((mode->hsync_end -
 906                                   mode->hsync_start) * pixel_rep,
 907                                  VC5_HDMI_HORZB_HSP));
 908
 909         HDMI_WRITE(HDMI_VERTA0, verta);
 910         HDMI_WRITE(HDMI_VERTA1, verta);
 911
 912         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 913         HDMI_WRITE(HDMI_VERTB1, vertb);
 914
 915         switch (state->max_bpc) {
 916         case 12:
 917                 gcp = 6;
 918                 gcp_en = true;
 919                 break;
 920         case 10:
 921                 gcp = 5;
 922                 gcp_en = true;
 923                 break;
 924         case 8:
 925         default:
 926                 gcp = 4;
 927                 gcp_en = false;
 928                 break;
 929         }
 930
 931         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
 932         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
 933                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
 934         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
 935                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
 936         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
 937
 938         reg = HDMI_READ(HDMI_GCP_WORD_1);
 939         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
 940         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
 941         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
 942
 943         reg = HDMI_READ(HDMI_GCP_CONFIG);
 944         reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
 945         reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
 946         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
 947
 948         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
 949
 950         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 951 }
 952
 953 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
 954 {
 955         unsigned long flags;
 956         u32 drift;
 957         int ret;
 958
 959         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 960
 961         drift = HDMI_READ(HDMI_FIFO_CTL);
 962         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 963
 964         HDMI_WRITE(HDMI_FIFO_CTL,
 965                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 966         HDMI_WRITE(HDMI_FIFO_CTL,
 967                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 968
 969         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 970
 971         usleep_range(1000, 1100);
 972
 973         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 974
 975         HDMI_WRITE(HDMI_FIFO_CTL,
 976                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 977         HDMI_WRITE(HDMI_FIFO_CTL,
 978                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 979
 980         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 981
 982         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
 983                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
 984         WARN_ONCE(ret, "Timeout waiting for "
 985                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
 986 }
 987
 988 static struct drm_connector_state *
 989 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder,
 990                                      struct drm_atomic_state *state)
 991 {
 992         struct drm_connector_state *conn_state;
 993         struct drm_connector *connector;
 994         unsigned int i;
 995
 996         for_each_new_connector_in_state(state, connector, conn_state, i) {
 997                 if (conn_state->best_encoder == encoder)
 998                         return conn_state;
 999         }
1000
1001         return NULL;
1002 }
1003
1004 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1005                                                 struct drm_atomic_state *state)
1006 {
1007         struct drm_connector_state *conn_state =
1008                 vc4_hdmi_encoder_get_connector_state(encoder, state);
1009         struct vc4_hdmi_connector_state *vc4_conn_state =
1010                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1011         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1012         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1013         unsigned long pixel_rate = vc4_conn_state->pixel_rate;
1014         unsigned long bvb_rate, hsm_rate;
1015         unsigned long flags;
1016         int ret;
1017
1018         mutex_lock(&vc4_hdmi->mutex);
1019
1020         /*
1021          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1022          * be faster than pixel clock, infinitesimally faster, tested in
1023          * simulation. Otherwise, exact value is unimportant for HDMI
1024          * operation." This conflicts with bcm2835's vc4 documentation, which
1025          * states HSM's clock has to be at least 108% of the pixel clock.
1026          *
1027          * Real life tests reveal that vc4's firmware statement holds up, and
1028          * users are able to use pixel clocks closer to HSM's, namely for
1029          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1030          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1031          * 162MHz.
1032          *
1033          * Additionally, the AXI clock needs to be at least 25% of
1034          * pixel clock, but HSM ends up being the limiting factor.
1035          */
1036         hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
1037         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1038         if (ret) {
1039                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1040                 goto out;
1041         }
1042
1043         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1044         if (ret < 0) {
1045                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1046                 goto out;
1047         }
1048
1049         ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
1050         if (ret) {
1051                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1052                 goto err_put_runtime_pm;
1053         }
1054
1055         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1056         if (ret) {
1057                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1058                 goto err_put_runtime_pm;
1059         }
1060
1061
1062         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1063
1064         if (pixel_rate > 297000000)
1065                 bvb_rate = 300000000;
1066         else if (pixel_rate > 148500000)
1067                 bvb_rate = 150000000;
1068         else
1069                 bvb_rate = 75000000;
1070
1071         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1072         if (ret) {
1073                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1074                 goto err_disable_pixel_clock;
1075         }
1076
1077         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1078         if (ret) {
1079                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1080                 goto err_disable_pixel_clock;
1081         }
1082
1083         if (vc4_hdmi->variant->phy_init)
1084                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1085
1086         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1087
1088         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1089                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1090                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1091                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1092
1093         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1094
1095         if (vc4_hdmi->variant->set_timings)
1096                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1097
1098         mutex_unlock(&vc4_hdmi->mutex);
1099
1100         return;
1101
1102 err_disable_pixel_clock:
1103         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1104 err_put_runtime_pm:
1105         pm_runtime_put(&vc4_hdmi->pdev->dev);
1106 out:
1107         mutex_unlock(&vc4_hdmi->mutex);
1108         return;
1109 }
1110
1111 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1112                                              struct drm_atomic_state *state)
1113 {
1114         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1115         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1116         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1117         unsigned long flags;
1118
1119         mutex_lock(&vc4_hdmi->mutex);
1120
1121         if (vc4_encoder->hdmi_monitor &&
1122             drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
1123                 if (vc4_hdmi->variant->csc_setup)
1124                         vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
1125
1126                 vc4_encoder->limited_rgb_range = true;
1127         } else {
1128                 if (vc4_hdmi->variant->csc_setup)
1129                         vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
1130
1131                 vc4_encoder->limited_rgb_range = false;
1132         }
1133
1134         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1135         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1136         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1137
1138         mutex_unlock(&vc4_hdmi->mutex);
1139 }
1140
1141 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1142                                               struct drm_atomic_state *state)
1143 {
1144         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1145         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1146         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1147         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1148         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1149         unsigned long flags;
1150         int ret;
1151
1152         mutex_lock(&vc4_hdmi->mutex);
1153
1154         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1155
1156         HDMI_WRITE(HDMI_VID_CTL,
1157                    VC4_HD_VID_CTL_ENABLE |
1158                    VC4_HD_VID_CTL_CLRRGB |
1159                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1160                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1161                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1162                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1163
1164         HDMI_WRITE(HDMI_VID_CTL,
1165                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1166
1167         if (vc4_encoder->hdmi_monitor) {
1168                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1169                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1170                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1171
1172                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1173
1174                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1175                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1176                 WARN_ONCE(ret, "Timeout waiting for "
1177                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1178         } else {
1179                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1180                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1181                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1182                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1183                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1184                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1185
1186                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1187
1188                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1189                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1190                 WARN_ONCE(ret, "Timeout waiting for "
1191                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1192         }
1193
1194         if (vc4_encoder->hdmi_monitor) {
1195                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1196
1197                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1198                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1199                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1200                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1201                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
1202
1203                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1204                            VC4_HDMI_RAM_PACKET_ENABLE);
1205
1206                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1207
1208                 vc4_hdmi_set_infoframes(encoder);
1209         }
1210
1211         vc4_hdmi_recenter_fifo(vc4_hdmi);
1212         vc4_hdmi_enable_scrambling(encoder);
1213
1214         mutex_unlock(&vc4_hdmi->mutex);
1215 }
1216
1217 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
1218 {
1219 }
1220
1221 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
1222 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
1223
1224 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1225                                          struct drm_crtc_state *crtc_state,
1226                                          struct drm_connector_state *conn_state)
1227 {
1228         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1229         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1230         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1231         unsigned long long pixel_rate = mode->clock * 1000;
1232         unsigned long long tmds_rate;
1233
1234         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1235             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1236             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1237              (mode->hsync_end % 2) || (mode->htotal % 2)))
1238                 return -EINVAL;
1239
1240         /*
1241          * The 1440p@60 pixel rate is in the same range than the first
1242          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1243          * bandwidth). Slightly lower the frequency to bring it out of
1244          * the WiFi range.
1245          */
1246         tmds_rate = pixel_rate * 10;
1247         if (vc4_hdmi->disable_wifi_frequencies &&
1248             (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1249              tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1250                 mode->clock = 238560;
1251                 pixel_rate = mode->clock * 1000;
1252         }
1253
1254         if (conn_state->max_bpc == 12) {
1255                 pixel_rate = pixel_rate * 150;
1256                 do_div(pixel_rate, 100);
1257         } else if (conn_state->max_bpc == 10) {
1258                 pixel_rate = pixel_rate * 125;
1259                 do_div(pixel_rate, 100);
1260         }
1261
1262         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1263                 pixel_rate = pixel_rate * 2;
1264
1265         if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
1266                 return -EINVAL;
1267
1268         if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK))
1269                 return -EINVAL;
1270
1271         vc4_state->pixel_rate = pixel_rate;
1272
1273         return 0;
1274 }
1275
1276 static enum drm_mode_status
1277 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1278                             const struct drm_display_mode *mode)
1279 {
1280         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1281
1282         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1283             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1284             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1285              (mode->hsync_end % 2) || (mode->htotal % 2)))
1286                 return MODE_H_ILLEGAL;
1287
1288         if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
1289                 return MODE_CLOCK_HIGH;
1290
1291         if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode))
1292                 return MODE_CLOCK_HIGH;
1293
1294         return MODE_OK;
1295 }
1296
1297 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1298         .atomic_check = vc4_hdmi_encoder_atomic_check,
1299         .mode_valid = vc4_hdmi_encoder_mode_valid,
1300         .disable = vc4_hdmi_encoder_disable,
1301         .enable = vc4_hdmi_encoder_enable,
1302 };
1303
1304 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1305 {
1306         int i;
1307         u32 channel_map = 0;
1308
1309         for (i = 0; i < 8; i++) {
1310                 if (channel_mask & BIT(i))
1311                         channel_map |= i << (3 * i);
1312         }
1313         return channel_map;
1314 }
1315
1316 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1317 {
1318         int i;
1319         u32 channel_map = 0;
1320
1321         for (i = 0; i < 8; i++) {
1322                 if (channel_mask & BIT(i))
1323                         channel_map |= i << (4 * i);
1324         }
1325         return channel_map;
1326 }
1327
1328 /* HDMI audio codec callbacks */
1329 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1330                                          unsigned int samplerate)
1331 {
1332         u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1333         unsigned long flags;
1334         unsigned long n, m;
1335
1336         rational_best_approximation(hsm_clock, samplerate,
1337                                     VC4_HD_MAI_SMP_N_MASK >>
1338                                     VC4_HD_MAI_SMP_N_SHIFT,
1339                                     (VC4_HD_MAI_SMP_M_MASK >>
1340                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
1341                                     &n, &m);
1342
1343         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1344         HDMI_WRITE(HDMI_MAI_SMP,
1345                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1346                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1347         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1348 }
1349
1350 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1351 {
1352         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1353         struct drm_crtc *crtc = encoder->crtc;
1354         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1355         u32 n, cts;
1356         u64 tmp;
1357
1358         lockdep_assert_held(&vc4_hdmi->mutex);
1359         lockdep_assert_held(&vc4_hdmi->hw_lock);
1360
1361         n = 128 * samplerate / 1000;
1362         tmp = (u64)(mode->clock * 1000) * n;
1363         do_div(tmp, 128 * samplerate);
1364         cts = tmp;
1365
1366         HDMI_WRITE(HDMI_CRP_CFG,
1367                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1368                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1369
1370         /*
1371          * We could get slightly more accurate clocks in some cases by
1372          * providing a CTS_1 value.  The two CTS values are alternated
1373          * between based on the period fields
1374          */
1375         HDMI_WRITE(HDMI_CTS_0, cts);
1376         HDMI_WRITE(HDMI_CTS_1, cts);
1377 }
1378
1379 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1380 {
1381         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1382
1383         return snd_soc_card_get_drvdata(card);
1384 }
1385
1386 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1387 {
1388         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1389         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1390         unsigned long flags;
1391
1392         mutex_lock(&vc4_hdmi->mutex);
1393
1394         /*
1395          * If the HDMI encoder hasn't probed, or the encoder is
1396          * currently in DVI mode, treat the codec dai as missing.
1397          */
1398         if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1399                                 VC4_HDMI_RAM_PACKET_ENABLE)) {
1400                 mutex_unlock(&vc4_hdmi->mutex);
1401                 return -ENODEV;
1402         }
1403
1404         vc4_hdmi->audio.streaming = true;
1405
1406         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1407         HDMI_WRITE(HDMI_MAI_CTL,
1408                    VC4_HD_MAI_CTL_RESET |
1409                    VC4_HD_MAI_CTL_FLUSH |
1410                    VC4_HD_MAI_CTL_DLATE |
1411                    VC4_HD_MAI_CTL_ERRORE |
1412                    VC4_HD_MAI_CTL_ERRORF);
1413         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1414
1415         if (vc4_hdmi->variant->phy_rng_enable)
1416                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1417
1418         mutex_unlock(&vc4_hdmi->mutex);
1419
1420         return 0;
1421 }
1422
1423 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1424 {
1425         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1426         struct device *dev = &vc4_hdmi->pdev->dev;
1427         unsigned long flags;
1428         int ret;
1429
1430         lockdep_assert_held(&vc4_hdmi->mutex);
1431
1432         vc4_hdmi->audio.streaming = false;
1433         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1434         if (ret)
1435                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1436
1437         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1438
1439         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1440         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1441         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1442
1443         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1444 }
1445
1446 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1447 {
1448         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1449         unsigned long flags;
1450
1451         mutex_lock(&vc4_hdmi->mutex);
1452
1453         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1454
1455         HDMI_WRITE(HDMI_MAI_CTL,
1456                    VC4_HD_MAI_CTL_DLATE |
1457                    VC4_HD_MAI_CTL_ERRORE |
1458                    VC4_HD_MAI_CTL_ERRORF);
1459
1460         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1461
1462         if (vc4_hdmi->variant->phy_rng_disable)
1463                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1464
1465         vc4_hdmi->audio.streaming = false;
1466         vc4_hdmi_audio_reset(vc4_hdmi);
1467
1468         mutex_unlock(&vc4_hdmi->mutex);
1469 }
1470
1471 static int sample_rate_to_mai_fmt(int samplerate)
1472 {
1473         switch (samplerate) {
1474         case 8000:
1475                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1476         case 11025:
1477                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1478         case 12000:
1479                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1480         case 16000:
1481                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1482         case 22050:
1483                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1484         case 24000:
1485                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1486         case 32000:
1487                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1488         case 44100:
1489                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1490         case 48000:
1491                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1492         case 64000:
1493                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
1494         case 88200:
1495                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
1496         case 96000:
1497                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
1498         case 128000:
1499                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
1500         case 176400:
1501                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
1502         case 192000:
1503                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
1504         default:
1505                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
1506         }
1507 }
1508
1509 /* HDMI audio codec callbacks */
1510 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
1511                                   struct hdmi_codec_daifmt *daifmt,
1512                                   struct hdmi_codec_params *params)
1513 {
1514         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1515         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1516         unsigned int sample_rate = params->sample_rate;
1517         unsigned int channels = params->channels;
1518         unsigned long flags;
1519         u32 audio_packet_config, channel_mask;
1520         u32 channel_map;
1521         u32 mai_audio_format;
1522         u32 mai_sample_rate;
1523
1524         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1525                 sample_rate, params->sample_width, channels);
1526
1527         mutex_lock(&vc4_hdmi->mutex);
1528
1529         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
1530
1531         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1532         HDMI_WRITE(HDMI_MAI_CTL,
1533                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
1534                    VC4_HD_MAI_CTL_WHOLSMP |
1535                    VC4_HD_MAI_CTL_CHALIGN |
1536                    VC4_HD_MAI_CTL_ENABLE);
1537
1538         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
1539         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
1540             params->channels == 8)
1541                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
1542         else
1543                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
1544         HDMI_WRITE(HDMI_MAI_FMT,
1545                    VC4_SET_FIELD(mai_sample_rate,
1546                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
1547                    VC4_SET_FIELD(mai_audio_format,
1548                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
1549
1550         /* The B frame identifier should match the value used by alsa-lib (8) */
1551         audio_packet_config =
1552                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1553                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1554                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1555
1556         channel_mask = GENMASK(channels - 1, 0);
1557         audio_packet_config |= VC4_SET_FIELD(channel_mask,
1558                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1559
1560         /* Set the MAI threshold */
1561         HDMI_WRITE(HDMI_MAI_THR,
1562                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1563                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1564                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1565                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1566
1567         HDMI_WRITE(HDMI_MAI_CONFIG,
1568                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1569                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
1570                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1571
1572         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1573         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1574         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1575
1576         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
1577
1578         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1579
1580         memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
1581         vc4_hdmi_set_audio_infoframe(encoder);
1582
1583         mutex_unlock(&vc4_hdmi->mutex);
1584
1585         return 0;
1586 }
1587
1588 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1589         .name = "vc4-hdmi-cpu-dai-component",
1590 };
1591
1592 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1593 {
1594         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1595
1596         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1597
1598         return 0;
1599 }
1600
1601 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1602         .name = "vc4-hdmi-cpu-dai",
1603         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1604         .playback = {
1605                 .stream_name = "Playback",
1606                 .channels_min = 1,
1607                 .channels_max = 8,
1608                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1609                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1610                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1611                          SNDRV_PCM_RATE_192000,
1612                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1613         },
1614 };
1615
1616 static const struct snd_dmaengine_pcm_config pcm_conf = {
1617         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1618         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1619 };
1620
1621 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
1622                                   uint8_t *buf, size_t len)
1623 {
1624         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1625         struct drm_connector *connector = &vc4_hdmi->connector;
1626
1627         mutex_lock(&vc4_hdmi->mutex);
1628         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1629         mutex_unlock(&vc4_hdmi->mutex);
1630
1631         return 0;
1632 }
1633
1634 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
1635         .get_eld = vc4_hdmi_audio_get_eld,
1636         .prepare = vc4_hdmi_audio_prepare,
1637         .audio_shutdown = vc4_hdmi_audio_shutdown,
1638         .audio_startup = vc4_hdmi_audio_startup,
1639 };
1640
1641 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
1642         .ops = &vc4_hdmi_codec_ops,
1643         .max_i2s_channels = 8,
1644         .i2s = 1,
1645 };
1646
1647 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1648 {
1649         const struct vc4_hdmi_register *mai_data =
1650                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1651         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1652         struct snd_soc_card *card = &vc4_hdmi->audio.card;
1653         struct device *dev = &vc4_hdmi->pdev->dev;
1654         struct platform_device *codec_pdev;
1655         const __be32 *addr;
1656         int index;
1657         int ret;
1658
1659         if (!of_find_property(dev->of_node, "dmas", NULL)) {
1660                 dev_warn(dev,
1661                          "'dmas' DT property is missing, no HDMI audio\n");
1662                 return 0;
1663         }
1664
1665         if (mai_data->reg != VC4_HD) {
1666                 WARN_ONCE(true, "MAI isn't in the HD block\n");
1667                 return -EINVAL;
1668         }
1669
1670         /*
1671          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1672          * the bus address specified in the DT, because the physical address
1673          * (the one returned by platform_get_resource()) is not appropriate
1674          * for DMA transfers.
1675          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1676          */
1677         index = of_property_match_string(dev->of_node, "reg-names", "hd");
1678         /* Before BCM2711, we don't have a named register range */
1679         if (index < 0)
1680                 index = 1;
1681
1682         addr = of_get_address(dev->of_node, index, NULL, NULL);
1683
1684         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1685         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1686         vc4_hdmi->audio.dma_data.maxburst = 2;
1687
1688         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1689         if (ret) {
1690                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1691                 return ret;
1692         }
1693
1694         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1695                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1696         if (ret) {
1697                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1698                 return ret;
1699         }
1700
1701         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1702                                                    PLATFORM_DEVID_AUTO,
1703                                                    &vc4_hdmi_codec_pdata,
1704                                                    sizeof(vc4_hdmi_codec_pdata));
1705         if (IS_ERR(codec_pdev)) {
1706                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
1707                 return PTR_ERR(codec_pdev);
1708         }
1709         vc4_hdmi->audio.codec_pdev = codec_pdev;
1710
1711         dai_link->cpus          = &vc4_hdmi->audio.cpu;
1712         dai_link->codecs        = &vc4_hdmi->audio.codec;
1713         dai_link->platforms     = &vc4_hdmi->audio.platform;
1714
1715         dai_link->num_cpus      = 1;
1716         dai_link->num_codecs    = 1;
1717         dai_link->num_platforms = 1;
1718
1719         dai_link->name = "MAI";
1720         dai_link->stream_name = "MAI PCM";
1721         dai_link->codecs->dai_name = "i2s-hifi";
1722         dai_link->cpus->dai_name = dev_name(dev);
1723         dai_link->codecs->name = dev_name(&codec_pdev->dev);
1724         dai_link->platforms->name = dev_name(dev);
1725
1726         card->dai_link = dai_link;
1727         card->num_links = 1;
1728         card->name = vc4_hdmi->variant->card_name;
1729         card->driver_name = "vc4-hdmi";
1730         card->dev = dev;
1731         card->owner = THIS_MODULE;
1732
1733         /*
1734          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1735          * stores a pointer to the snd card object in dev->driver_data. This
1736          * means we cannot use it for something else. The hdmi back-pointer is
1737          * now stored in card->drvdata and should be retrieved with
1738          * snd_soc_card_get_drvdata() if needed.
1739          */
1740         snd_soc_card_set_drvdata(card, vc4_hdmi);
1741         ret = devm_snd_soc_register_card(dev, card);
1742         if (ret)
1743                 dev_err_probe(dev, ret, "Could not register sound card\n");
1744
1745         return ret;
1746
1747 }
1748
1749 static void vc4_hdmi_audio_exit(struct vc4_hdmi *vc4_hdmi)
1750 {
1751         platform_device_unregister(vc4_hdmi->audio.codec_pdev);
1752         vc4_hdmi->audio.codec_pdev = NULL;
1753 }
1754
1755 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
1756 {
1757         struct vc4_hdmi *vc4_hdmi = priv;
1758         struct drm_device *dev = vc4_hdmi->connector.dev;
1759
1760         if (dev && dev->registered)
1761                 drm_kms_helper_hotplug_event(dev);
1762
1763         return IRQ_HANDLED;
1764 }
1765
1766 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
1767 {
1768         struct drm_connector *connector = &vc4_hdmi->connector;
1769         struct platform_device *pdev = vc4_hdmi->pdev;
1770         int ret;
1771
1772         if (vc4_hdmi->variant->external_irq_controller) {
1773                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
1774                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
1775
1776                 ret = request_threaded_irq(hpd_con,
1777                                            NULL,
1778                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1779                                            "vc4 hdmi hpd connected", vc4_hdmi);
1780                 if (ret)
1781                         return ret;
1782
1783                 ret = request_threaded_irq(hpd_rm,
1784                                            NULL,
1785                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1786                                            "vc4 hdmi hpd disconnected", vc4_hdmi);
1787                 if (ret) {
1788                         free_irq(hpd_con, vc4_hdmi);
1789                         return ret;
1790                 }
1791
1792                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1793         }
1794
1795         return 0;
1796 }
1797
1798 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi)
1799 {
1800         struct platform_device *pdev = vc4_hdmi->pdev;
1801
1802         if (vc4_hdmi->variant->external_irq_controller) {
1803                 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi);
1804                 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi);
1805         }
1806 }
1807
1808 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1809 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1810 {
1811         struct vc4_hdmi *vc4_hdmi = priv;
1812
1813         if (vc4_hdmi->cec_rx_msg.len)
1814                 cec_received_msg(vc4_hdmi->cec_adap,
1815                                  &vc4_hdmi->cec_rx_msg);
1816
1817         return IRQ_HANDLED;
1818 }
1819
1820 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1821 {
1822         struct vc4_hdmi *vc4_hdmi = priv;
1823
1824         if (vc4_hdmi->cec_tx_ok) {
1825                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1826                                   0, 0, 0, 0);
1827         } else {
1828                 /*
1829                  * This CEC implementation makes 1 retry, so if we
1830                  * get a NACK, then that means it made 2 attempts.
1831                  */
1832                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1833                                   0, 2, 0, 0);
1834         }
1835         return IRQ_HANDLED;
1836 }
1837
1838 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1839 {
1840         struct vc4_hdmi *vc4_hdmi = priv;
1841         irqreturn_t ret;
1842
1843         if (vc4_hdmi->cec_irq_was_rx)
1844                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1845         else
1846                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1847
1848         return ret;
1849 }
1850
1851 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1852 {
1853         struct drm_device *dev = vc4_hdmi->connector.dev;
1854         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1855         unsigned int i;
1856
1857         lockdep_assert_held(&vc4_hdmi->hw_lock);
1858
1859         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1860                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1861
1862         if (msg->len > 16) {
1863                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1864                 return;
1865         }
1866
1867         for (i = 0; i < msg->len; i += 4) {
1868                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1869
1870                 msg->msg[i] = val & 0xff;
1871                 msg->msg[i + 1] = (val >> 8) & 0xff;
1872                 msg->msg[i + 2] = (val >> 16) & 0xff;
1873                 msg->msg[i + 3] = (val >> 24) & 0xff;
1874         }
1875 }
1876
1877 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
1878 {
1879         u32 cntrl1;
1880
1881         lockdep_assert_held(&vc4_hdmi->hw_lock);
1882
1883         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1884         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1885         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1886         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1887
1888         return IRQ_WAKE_THREAD;
1889 }
1890
1891 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1892 {
1893         struct vc4_hdmi *vc4_hdmi = priv;
1894         irqreturn_t ret;
1895
1896         spin_lock(&vc4_hdmi->hw_lock);
1897         ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
1898         spin_unlock(&vc4_hdmi->hw_lock);
1899
1900         return ret;
1901 }
1902
1903 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
1904 {
1905         u32 cntrl1;
1906
1907         lockdep_assert_held(&vc4_hdmi->hw_lock);
1908
1909         vc4_hdmi->cec_rx_msg.len = 0;
1910         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1911         vc4_cec_read_msg(vc4_hdmi, cntrl1);
1912         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1913         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1914         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1915
1916         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1917
1918         return IRQ_WAKE_THREAD;
1919 }
1920
1921 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1922 {
1923         struct vc4_hdmi *vc4_hdmi = priv;
1924         irqreturn_t ret;
1925
1926         spin_lock(&vc4_hdmi->hw_lock);
1927         ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
1928         spin_unlock(&vc4_hdmi->hw_lock);
1929
1930         return ret;
1931 }
1932
1933 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1934 {
1935         struct vc4_hdmi *vc4_hdmi = priv;
1936         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1937         irqreturn_t ret;
1938         u32 cntrl5;
1939
1940         if (!(stat & VC4_HDMI_CPU_CEC))
1941                 return IRQ_NONE;
1942
1943         spin_lock(&vc4_hdmi->hw_lock);
1944         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1945         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1946         if (vc4_hdmi->cec_irq_was_rx)
1947                 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
1948         else
1949                 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
1950
1951         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1952         spin_unlock(&vc4_hdmi->hw_lock);
1953
1954         return ret;
1955 }
1956
1957 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
1958 {
1959         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1960         /* clock period in microseconds */
1961         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1962         unsigned long flags;
1963         u32 val;
1964         int ret;
1965
1966         /*
1967          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
1968          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
1969          * .detect or .get_modes might call .adap_enable, which leads to this
1970          * function being called with that mutex held.
1971          *
1972          * Concurrency is not an issue for the moment since we don't share any
1973          * state with KMS, so we can ignore the lock for now, but we need to
1974          * keep it in mind if we were to change that assumption.
1975          */
1976
1977         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1978         if (ret)
1979                 return ret;
1980
1981         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1982
1983         val = HDMI_READ(HDMI_CEC_CNTRL_5);
1984         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1985                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1986                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1987         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1988                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1989
1990         HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1991                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1992         HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1993         HDMI_WRITE(HDMI_CEC_CNTRL_2,
1994                    ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1995                    ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1996                    ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1997                    ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1998                    ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1999         HDMI_WRITE(HDMI_CEC_CNTRL_3,
2000                    ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2001                    ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2002                    ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2003                    ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2004         HDMI_WRITE(HDMI_CEC_CNTRL_4,
2005                    ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2006                    ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2007                    ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2008                    ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2009
2010         if (!vc4_hdmi->variant->external_irq_controller)
2011                 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2012
2013         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2014
2015         return 0;
2016 }
2017
2018 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2019 {
2020         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2021         unsigned long flags;
2022
2023         /*
2024          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2025          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2026          * .detect or .get_modes might call .adap_enable, which leads to this
2027          * function being called with that mutex held.
2028          *
2029          * Concurrency is not an issue for the moment since we don't share any
2030          * state with KMS, so we can ignore the lock for now, but we need to
2031          * keep it in mind if we were to change that assumption.
2032          */
2033
2034         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2035
2036         if (!vc4_hdmi->variant->external_irq_controller)
2037                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2038
2039         HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2040                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2041
2042         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2043
2044         pm_runtime_put(&vc4_hdmi->pdev->dev);
2045
2046         return 0;
2047 }
2048
2049 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2050 {
2051         if (enable)
2052                 return vc4_hdmi_cec_enable(adap);
2053         else
2054                 return vc4_hdmi_cec_disable(adap);
2055 }
2056
2057 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2058 {
2059         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2060         unsigned long flags;
2061
2062         /*
2063          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2064          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2065          * .detect or .get_modes might call .adap_enable, which leads to this
2066          * function being called with that mutex held.
2067          *
2068          * Concurrency is not an issue for the moment since we don't share any
2069          * state with KMS, so we can ignore the lock for now, but we need to
2070          * keep it in mind if we were to change that assumption.
2071          */
2072
2073         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2074         HDMI_WRITE(HDMI_CEC_CNTRL_1,
2075                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2076                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2077         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2078
2079         return 0;
2080 }
2081
2082 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2083                                       u32 signal_free_time, struct cec_msg *msg)
2084 {
2085         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2086         struct drm_device *dev = vc4_hdmi->connector.dev;
2087         unsigned long flags;
2088         u32 val;
2089         unsigned int i;
2090
2091         /*
2092          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2093          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2094          * .detect or .get_modes might call .adap_enable, which leads to this
2095          * function being called with that mutex held.
2096          *
2097          * Concurrency is not an issue for the moment since we don't share any
2098          * state with KMS, so we can ignore the lock for now, but we need to
2099          * keep it in mind if we were to change that assumption.
2100          */
2101
2102         if (msg->len > 16) {
2103                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2104                 return -ENOMEM;
2105         }
2106
2107         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2108
2109         for (i = 0; i < msg->len; i += 4)
2110                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2111                            (msg->msg[i]) |
2112                            (msg->msg[i + 1] << 8) |
2113                            (msg->msg[i + 2] << 16) |
2114                            (msg->msg[i + 3] << 24));
2115
2116         val = HDMI_READ(HDMI_CEC_CNTRL_1);
2117         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2118         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2119         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2120         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2121         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2122
2123         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2124
2125         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2126
2127         return 0;
2128 }
2129
2130 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2131         .adap_enable = vc4_hdmi_cec_adap_enable,
2132         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2133         .adap_transmit = vc4_hdmi_cec_adap_transmit,
2134 };
2135
2136 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2137 {
2138         struct cec_connector_info conn_info;
2139         struct platform_device *pdev = vc4_hdmi->pdev;
2140         struct device *dev = &pdev->dev;
2141         unsigned long flags;
2142         u32 value;
2143         int ret;
2144
2145         if (!of_find_property(dev->of_node, "interrupts", NULL)) {
2146                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
2147                 return 0;
2148         }
2149
2150         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
2151                                                   vc4_hdmi, "vc4",
2152                                                   CEC_CAP_DEFAULTS |
2153                                                   CEC_CAP_CONNECTOR_INFO, 1);
2154         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
2155         if (ret < 0)
2156                 return ret;
2157
2158         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
2159         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
2160
2161         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2162         value = HDMI_READ(HDMI_CEC_CNTRL_1);
2163         /* Set the logical address to Unregistered */
2164         value |= VC4_HDMI_CEC_ADDR_MASK;
2165         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
2166         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2167
2168         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
2169
2170         if (vc4_hdmi->variant->external_irq_controller) {
2171                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"),
2172                                            vc4_cec_irq_handler_rx_bare,
2173                                            vc4_cec_irq_handler_rx_thread, 0,
2174                                            "vc4 hdmi cec rx", vc4_hdmi);
2175                 if (ret)
2176                         goto err_delete_cec_adap;
2177
2178                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"),
2179                                            vc4_cec_irq_handler_tx_bare,
2180                                            vc4_cec_irq_handler_tx_thread, 0,
2181                                            "vc4 hdmi cec tx", vc4_hdmi);
2182                 if (ret)
2183                         goto err_remove_cec_rx_handler;
2184         } else {
2185                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2186                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
2187                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2188
2189                 ret = request_threaded_irq(platform_get_irq(pdev, 0),
2190                                            vc4_cec_irq_handler,
2191                                            vc4_cec_irq_handler_thread, 0,
2192                                            "vc4 hdmi cec", vc4_hdmi);
2193                 if (ret)
2194                         goto err_delete_cec_adap;
2195         }
2196
2197         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
2198         if (ret < 0)
2199                 goto err_remove_handlers;
2200
2201         return 0;
2202
2203 err_remove_handlers:
2204         if (vc4_hdmi->variant->external_irq_controller)
2205                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
2206         else
2207                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
2208
2209 err_remove_cec_rx_handler:
2210         if (vc4_hdmi->variant->external_irq_controller)
2211                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
2212
2213 err_delete_cec_adap:
2214         cec_delete_adapter(vc4_hdmi->cec_adap);
2215
2216         return ret;
2217 }
2218
2219 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
2220 {
2221         struct platform_device *pdev = vc4_hdmi->pdev;
2222
2223         if (vc4_hdmi->variant->external_irq_controller) {
2224                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
2225                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
2226         } else {
2227                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
2228         }
2229
2230         cec_unregister_adapter(vc4_hdmi->cec_adap);
2231 }
2232 #else
2233 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2234 {
2235         return 0;
2236 }
2237
2238 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
2239
2240 #endif
2241
2242 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
2243                                  struct debugfs_regset32 *regset,
2244                                  enum vc4_hdmi_regs reg)
2245 {
2246         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2247         struct debugfs_reg32 *regs, *new_regs;
2248         unsigned int count = 0;
2249         unsigned int i;
2250
2251         regs = kcalloc(variant->num_registers, sizeof(*regs),
2252                        GFP_KERNEL);
2253         if (!regs)
2254                 return -ENOMEM;
2255
2256         for (i = 0; i < variant->num_registers; i++) {
2257                 const struct vc4_hdmi_register *field = &variant->registers[i];
2258
2259                 if (field->reg != reg)
2260                         continue;
2261
2262                 regs[count].name = field->name;
2263                 regs[count].offset = field->offset;
2264                 count++;
2265         }
2266
2267         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
2268         if (!new_regs)
2269                 return -ENOMEM;
2270
2271         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
2272         regset->regs = new_regs;
2273         regset->nregs = count;
2274
2275         return 0;
2276 }
2277
2278 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2279 {
2280         struct platform_device *pdev = vc4_hdmi->pdev;
2281         struct device *dev = &pdev->dev;
2282         int ret;
2283
2284         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
2285         if (IS_ERR(vc4_hdmi->hdmicore_regs))
2286                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
2287
2288         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
2289         if (IS_ERR(vc4_hdmi->hd_regs))
2290                 return PTR_ERR(vc4_hdmi->hd_regs);
2291
2292         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2293         if (ret)
2294                 return ret;
2295
2296         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2297         if (ret)
2298                 return ret;
2299
2300         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
2301         if (IS_ERR(vc4_hdmi->pixel_clock)) {
2302                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
2303                 if (ret != -EPROBE_DEFER)
2304                         DRM_ERROR("Failed to get pixel clock\n");
2305                 return ret;
2306         }
2307
2308         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2309         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2310                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2311                 return PTR_ERR(vc4_hdmi->hsm_clock);
2312         }
2313         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2314         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2315
2316         return 0;
2317 }
2318
2319 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2320 {
2321         struct platform_device *pdev = vc4_hdmi->pdev;
2322         struct device *dev = &pdev->dev;
2323         struct resource *res;
2324
2325         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2326         if (!res)
2327                 return -ENODEV;
2328
2329         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2330                                                resource_size(res));
2331         if (!vc4_hdmi->hdmicore_regs)
2332                 return -ENOMEM;
2333
2334         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2335         if (!res)
2336                 return -ENODEV;
2337
2338         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2339         if (!vc4_hdmi->hd_regs)
2340                 return -ENOMEM;
2341
2342         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2343         if (!res)
2344                 return -ENODEV;
2345
2346         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2347         if (!vc4_hdmi->cec_regs)
2348                 return -ENOMEM;
2349
2350         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2351         if (!res)
2352                 return -ENODEV;
2353
2354         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2355         if (!vc4_hdmi->csc_regs)
2356                 return -ENOMEM;
2357
2358         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2359         if (!res)
2360                 return -ENODEV;
2361
2362         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2363         if (!vc4_hdmi->dvp_regs)
2364                 return -ENOMEM;
2365
2366         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2367         if (!res)
2368                 return -ENODEV;
2369
2370         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2371         if (!vc4_hdmi->phy_regs)
2372                 return -ENOMEM;
2373
2374         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2375         if (!res)
2376                 return -ENODEV;
2377
2378         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2379         if (!vc4_hdmi->ram_regs)
2380                 return -ENOMEM;
2381
2382         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2383         if (!res)
2384                 return -ENODEV;
2385
2386         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2387         if (!vc4_hdmi->rm_regs)
2388                 return -ENOMEM;
2389
2390         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2391         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2392                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2393                 return PTR_ERR(vc4_hdmi->hsm_clock);
2394         }
2395
2396         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2397         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2398                 DRM_ERROR("Failed to get pixel bvb clock\n");
2399                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2400         }
2401
2402         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2403         if (IS_ERR(vc4_hdmi->audio_clock)) {
2404                 DRM_ERROR("Failed to get audio clock\n");
2405                 return PTR_ERR(vc4_hdmi->audio_clock);
2406         }
2407
2408         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2409         if (IS_ERR(vc4_hdmi->cec_clock)) {
2410                 DRM_ERROR("Failed to get CEC clock\n");
2411                 return PTR_ERR(vc4_hdmi->cec_clock);
2412         }
2413
2414         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2415         if (IS_ERR(vc4_hdmi->reset)) {
2416                 DRM_ERROR("Failed to get HDMI reset line\n");
2417                 return PTR_ERR(vc4_hdmi->reset);
2418         }
2419
2420         return 0;
2421 }
2422
2423 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev)
2424 {
2425         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2426
2427         clk_disable_unprepare(vc4_hdmi->hsm_clock);
2428
2429         return 0;
2430 }
2431
2432 static int vc4_hdmi_runtime_resume(struct device *dev)
2433 {
2434         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2435         int ret;
2436
2437         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
2438         if (ret)
2439                 return ret;
2440
2441         return 0;
2442 }
2443
2444 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2445 {
2446         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2447         struct platform_device *pdev = to_platform_device(dev);
2448         struct drm_device *drm = dev_get_drvdata(master);
2449         struct vc4_hdmi *vc4_hdmi;
2450         struct drm_encoder *encoder;
2451         struct device_node *ddc_node;
2452         int ret;
2453
2454         vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2455         if (!vc4_hdmi)
2456                 return -ENOMEM;
2457         mutex_init(&vc4_hdmi->mutex);
2458         spin_lock_init(&vc4_hdmi->hw_lock);
2459         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2460
2461         dev_set_drvdata(dev, vc4_hdmi);
2462         encoder = &vc4_hdmi->encoder.base.base;
2463         vc4_hdmi->encoder.base.type = variant->encoder_type;
2464         vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2465         vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2466         vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2467         vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2468         vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2469         vc4_hdmi->pdev = pdev;
2470         vc4_hdmi->variant = variant;
2471
2472         ret = variant->init_resources(vc4_hdmi);
2473         if (ret)
2474                 return ret;
2475
2476         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2477         if (!ddc_node) {
2478                 DRM_ERROR("Failed to find ddc node in device tree\n");
2479                 return -ENODEV;
2480         }
2481
2482         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2483         of_node_put(ddc_node);
2484         if (!vc4_hdmi->ddc) {
2485                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2486                 return -EPROBE_DEFER;
2487         }
2488
2489         /* Only use the GPIO HPD pin if present in the DT, otherwise
2490          * we'll use the HDMI core's register.
2491          */
2492         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2493         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
2494                 ret = PTR_ERR(vc4_hdmi->hpd_gpio);
2495                 goto err_put_ddc;
2496         }
2497
2498         vc4_hdmi->disable_wifi_frequencies =
2499                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2500
2501         if (variant->max_pixel_clock == 600000000) {
2502                 struct vc4_dev *vc4 = to_vc4_dev(drm);
2503                 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
2504
2505                 if (max_rate < 550000000)
2506                         vc4_hdmi->disable_4kp60 = true;
2507         }
2508
2509         /*
2510          * If we boot without any cable connected to the HDMI connector,
2511          * the firmware will skip the HSM initialization and leave it
2512          * with a rate of 0, resulting in a bus lockup when we're
2513          * accessing the registers even if it's enabled.
2514          *
2515          * Let's put a sensible default at runtime_resume so that we
2516          * don't end up in this situation.
2517          */
2518         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
2519         if (ret)
2520                 goto err_put_ddc;
2521
2522         /*
2523          * We need to have the device powered up at this point to call
2524          * our reset hook and for the CEC init.
2525          */
2526         ret = vc4_hdmi_runtime_resume(dev);
2527         if (ret)
2528                 goto err_put_ddc;
2529
2530         pm_runtime_get_noresume(dev);
2531         pm_runtime_set_active(dev);
2532         pm_runtime_enable(dev);
2533
2534         if (vc4_hdmi->variant->reset)
2535                 vc4_hdmi->variant->reset(vc4_hdmi);
2536
2537         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
2538              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
2539             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
2540                 clk_prepare_enable(vc4_hdmi->pixel_clock);
2541                 clk_prepare_enable(vc4_hdmi->hsm_clock);
2542                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
2543         }
2544
2545         drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2546         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2547
2548         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2549         if (ret)
2550                 goto err_destroy_encoder;
2551
2552         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
2553         if (ret)
2554                 goto err_destroy_conn;
2555
2556         ret = vc4_hdmi_cec_init(vc4_hdmi);
2557         if (ret)
2558                 goto err_free_hotplug;
2559
2560         ret = vc4_hdmi_audio_init(vc4_hdmi);
2561         if (ret)
2562                 goto err_free_cec;
2563
2564         vc4_debugfs_add_file(drm, variant->debugfs_name,
2565                              vc4_hdmi_debugfs_regs,
2566                              vc4_hdmi);
2567
2568         pm_runtime_put_sync(dev);
2569
2570         return 0;
2571
2572 err_free_cec:
2573         vc4_hdmi_cec_exit(vc4_hdmi);
2574 err_free_hotplug:
2575         vc4_hdmi_hotplug_exit(vc4_hdmi);
2576 err_destroy_conn:
2577         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2578 err_destroy_encoder:
2579         drm_encoder_cleanup(encoder);
2580         pm_runtime_put_sync(dev);
2581         pm_runtime_disable(dev);
2582 err_put_ddc:
2583         put_device(&vc4_hdmi->ddc->dev);
2584
2585         return ret;
2586 }
2587
2588 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2589                             void *data)
2590 {
2591         struct vc4_hdmi *vc4_hdmi;
2592
2593         /*
2594          * ASoC makes it a bit hard to retrieve a pointer to the
2595          * vc4_hdmi structure. Registering the card will overwrite our
2596          * device drvdata with a pointer to the snd_soc_card structure,
2597          * which can then be used to retrieve whatever drvdata we want
2598          * to associate.
2599          *
2600          * However, that doesn't fly in the case where we wouldn't
2601          * register an ASoC card (because of an old DT that is missing
2602          * the dmas properties for example), then the card isn't
2603          * registered and the device drvdata wouldn't be set.
2604          *
2605          * We can deal with both cases by making sure a snd_soc_card
2606          * pointer and a vc4_hdmi structure are pointing to the same
2607          * memory address, so we can treat them indistinctly without any
2608          * issue.
2609          */
2610         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2611         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2612         vc4_hdmi = dev_get_drvdata(dev);
2613
2614         kfree(vc4_hdmi->hdmi_regset.regs);
2615         kfree(vc4_hdmi->hd_regset.regs);
2616
2617         vc4_hdmi_audio_exit(vc4_hdmi);
2618         vc4_hdmi_cec_exit(vc4_hdmi);
2619         vc4_hdmi_hotplug_exit(vc4_hdmi);
2620         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2621         drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2622
2623         pm_runtime_disable(dev);
2624
2625         put_device(&vc4_hdmi->ddc->dev);
2626 }
2627
2628 static const struct component_ops vc4_hdmi_ops = {
2629         .bind   = vc4_hdmi_bind,
2630         .unbind = vc4_hdmi_unbind,
2631 };
2632
2633 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2634 {
2635         return component_add(&pdev->dev, &vc4_hdmi_ops);
2636 }
2637
2638 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2639 {
2640         component_del(&pdev->dev, &vc4_hdmi_ops);
2641         return 0;
2642 }
2643
2644 static const struct vc4_hdmi_variant bcm2835_variant = {
2645         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2646         .debugfs_name           = "hdmi_regs",
2647         .card_name              = "vc4-hdmi",
2648         .max_pixel_clock        = 162000000,
2649         .registers              = vc4_hdmi_fields,
2650         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
2651
2652         .init_resources         = vc4_hdmi_init_resources,
2653         .csc_setup              = vc4_hdmi_csc_setup,
2654         .reset                  = vc4_hdmi_reset,
2655         .set_timings            = vc4_hdmi_set_timings,
2656         .phy_init               = vc4_hdmi_phy_init,
2657         .phy_disable            = vc4_hdmi_phy_disable,
2658         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
2659         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
2660         .channel_map            = vc4_hdmi_channel_map,
2661         .supports_hdr           = false,
2662 };
2663
2664 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2665         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2666         .debugfs_name           = "hdmi0_regs",
2667         .card_name              = "vc4-hdmi-0",
2668         .max_pixel_clock        = 600000000,
2669         .registers              = vc5_hdmi_hdmi0_fields,
2670         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2671         .phy_lane_mapping       = {
2672                 PHY_LANE_0,
2673                 PHY_LANE_1,
2674                 PHY_LANE_2,
2675                 PHY_LANE_CK,
2676         },
2677         .unsupported_odd_h_timings      = true,
2678         .external_irq_controller        = true,
2679
2680         .init_resources         = vc5_hdmi_init_resources,
2681         .csc_setup              = vc5_hdmi_csc_setup,
2682         .reset                  = vc5_hdmi_reset,
2683         .set_timings            = vc5_hdmi_set_timings,
2684         .phy_init               = vc5_hdmi_phy_init,
2685         .phy_disable            = vc5_hdmi_phy_disable,
2686         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2687         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2688         .channel_map            = vc5_hdmi_channel_map,
2689         .supports_hdr           = true,
2690 };
2691
2692 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2693         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
2694         .debugfs_name           = "hdmi1_regs",
2695         .card_name              = "vc4-hdmi-1",
2696         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2697         .registers              = vc5_hdmi_hdmi1_fields,
2698         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2699         .phy_lane_mapping       = {
2700                 PHY_LANE_1,
2701                 PHY_LANE_0,
2702                 PHY_LANE_CK,
2703                 PHY_LANE_2,
2704         },
2705         .unsupported_odd_h_timings      = true,
2706         .external_irq_controller        = true,
2707
2708         .init_resources         = vc5_hdmi_init_resources,
2709         .csc_setup              = vc5_hdmi_csc_setup,
2710         .reset                  = vc5_hdmi_reset,
2711         .set_timings            = vc5_hdmi_set_timings,
2712         .phy_init               = vc5_hdmi_phy_init,
2713         .phy_disable            = vc5_hdmi_phy_disable,
2714         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2715         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2716         .channel_map            = vc5_hdmi_channel_map,
2717         .supports_hdr           = true,
2718 };
2719
2720 static const struct of_device_id vc4_hdmi_dt_match[] = {
2721         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2722         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2723         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2724         {}
2725 };
2726
2727 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
2728         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
2729                            vc4_hdmi_runtime_resume,
2730                            NULL)
2731 };
2732
2733 struct platform_driver vc4_hdmi_driver = {
2734         .probe = vc4_hdmi_dev_probe,
2735         .remove = vc4_hdmi_dev_remove,
2736         .driver = {
2737                 .name = "vc4_hdmi",
2738                 .of_match_table = vc4_hdmi_dt_match,
2739                 .pm = &vc4_hdmi_pm_ops,
2740         },
2741 };