drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/display/drm_hdmi_helper.h>
  35 #include <drm/display/drm_scdc_helper.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_probe_helper.h>
  38 #include <drm/drm_simple_kms_helper.h>
  39 #include <linux/clk.h>
  40 #include <linux/component.h>
  41 #include <linux/gpio/consumer.h>
  42 #include <linux/i2c.h>
  43 #include <linux/of_address.h>
  44 #include <linux/of_gpio.h>
  45 #include <linux/of_platform.h>
  46 #include <linux/pm_runtime.h>
  47 #include <linux/rational.h>
  48 #include <linux/reset.h>
  49 #include <sound/dmaengine_pcm.h>
  50 #include <sound/hdmi-codec.h>
  51 #include <sound/pcm_drm_eld.h>
  52 #include <sound/pcm_params.h>
  53 #include <sound/soc.h>
  54 #include "media/cec.h"
  55 #include "vc4_drv.h"
  56 #include "vc4_hdmi.h"
  57 #include "vc4_hdmi_regs.h"
  58 #include "vc4_regs.h"
  59
  60 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  61 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  62 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  63 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  64 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  65 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  66
  67 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  68 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  69 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  70 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  71
  72 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  73 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  74 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  75 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  76 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  77 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  78
  79 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  80 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  81
  82 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  83 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  84 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  85 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  86
  87 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  88
  89 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  90 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  91
  92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  93 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  94
  95 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  96
  97 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
  98 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
  99
 100 # define VC4_HD_M_SW_RST                        BIT(2)
 101 # define VC4_HD_M_ENABLE                        BIT(0)
 102
 103 #define HSM_MIN_CLOCK_FREQ      120000000
 104 #define CEC_CLOCK_FREQ 40000
 105
 106 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 107
 108 static const char * const output_format_str[] = {
 109         [VC4_HDMI_OUTPUT_RGB]           = "RGB",
 110         [VC4_HDMI_OUTPUT_YUV420]        = "YUV 4:2:0",
 111         [VC4_HDMI_OUTPUT_YUV422]        = "YUV 4:2:2",
 112         [VC4_HDMI_OUTPUT_YUV444]        = "YUV 4:4:4",
 113 };
 114
 115 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt)
 116 {
 117         if (fmt >= ARRAY_SIZE(output_format_str))
 118                 return "invalid";
 119
 120         return output_format_str[fmt];
 121 }
 122
 123 static unsigned long long
 124 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
 125                                     unsigned int bpc, enum vc4_hdmi_output_format fmt);
 126
 127 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
 128                                            unsigned int bpc,
 129                                            enum vc4_hdmi_output_format fmt)
 130 {
 131         unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
 132
 133         return clock > HDMI_14_MAX_TMDS_CLK;
 134 }
 135
 136 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi,
 137                                        const struct drm_display_mode *mode)
 138 {
 139         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 140
 141         return !display->is_hdmi ||
 142                 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
 143 }
 144
 145 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 146 {
 147         struct drm_info_node *node = (struct drm_info_node *)m->private;
 148         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
 149         struct drm_printer p = drm_seq_file_printer(m);
 150
 151         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 152         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 153         drm_print_regset32(&p, &vc4_hdmi->cec_regset);
 154         drm_print_regset32(&p, &vc4_hdmi->csc_regset);
 155         drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
 156         drm_print_regset32(&p, &vc4_hdmi->phy_regset);
 157         drm_print_regset32(&p, &vc4_hdmi->ram_regset);
 158         drm_print_regset32(&p, &vc4_hdmi->rm_regset);
 159
 160         return 0;
 161 }
 162
 163 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 164 {
 165         unsigned long flags;
 166
 167         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 168
 169         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 170         udelay(1);
 171         HDMI_WRITE(HDMI_M_CTL, 0);
 172
 173         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 174
 175         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 176                    VC4_HDMI_SW_RESET_HDMI |
 177                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 178
 179         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 180
 181         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 182 }
 183
 184 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 185 {
 186         unsigned long flags;
 187
 188         reset_control_reset(vc4_hdmi->reset);
 189
 190         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 191
 192         HDMI_WRITE(HDMI_DVP_CTL, 0);
 193
 194         HDMI_WRITE(HDMI_CLOCK_STOP,
 195                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 196
 197         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 198 }
 199
 200 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 201 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 202 {
 203         unsigned long cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
 204         unsigned long flags;
 205         u16 clk_cnt;
 206         u32 value;
 207
 208         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 209
 210         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 211         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 212
 213         /*
 214          * Set the clock divider: the hsm_clock rate and this divider
 215          * setting will give a 40 kHz CEC clock.
 216          */
 217         clk_cnt = cec_rate / CEC_CLOCK_FREQ;
 218         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 219         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 220
 221         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 222 }
 223 #else
 224 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 225 #endif
 226
 227 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder);
 228
 229 static enum drm_connector_status
 230 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 231 {
 232         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 233         bool connected = false;
 234
 235         mutex_lock(&vc4_hdmi->mutex);
 236
 237         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 238
 239         if (vc4_hdmi->hpd_gpio) {
 240                 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
 241                         connected = true;
 242         } else {
 243                 if (vc4_hdmi->variant->hp_detect &&
 244                     vc4_hdmi->variant->hp_detect(vc4_hdmi))
 245                         connected = true;
 246         }
 247
 248         if (connected) {
 249                 if (connector->status != connector_status_connected) {
 250                         struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
 251
 252                         if (edid) {
 253                                 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 254                                 kfree(edid);
 255                         }
 256                 }
 257
 258                 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base);
 259                 pm_runtime_put(&vc4_hdmi->pdev->dev);
 260                 mutex_unlock(&vc4_hdmi->mutex);
 261                 return connector_status_connected;
 262         }
 263
 264         cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 265         pm_runtime_put(&vc4_hdmi->pdev->dev);
 266         mutex_unlock(&vc4_hdmi->mutex);
 267         return connector_status_disconnected;
 268 }
 269
 270 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 271 {
 272         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 273         int ret = 0;
 274         struct edid *edid;
 275
 276         mutex_lock(&vc4_hdmi->mutex);
 277
 278         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 279         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 280         if (!edid) {
 281                 ret = -ENODEV;
 282                 goto out;
 283         }
 284
 285         drm_connector_update_edid_property(connector, edid);
 286         ret = drm_add_edid_modes(connector, edid);
 287         kfree(edid);
 288
 289         if (vc4_hdmi->disable_4kp60) {
 290                 struct drm_device *drm = connector->dev;
 291                 struct drm_display_mode *mode;
 292
 293                 list_for_each_entry(mode, &connector->probed_modes, head) {
 294                         if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) {
 295                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 296                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 297                         }
 298                 }
 299         }
 300
 301 out:
 302         mutex_unlock(&vc4_hdmi->mutex);
 303
 304         return ret;
 305 }
 306
 307 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 308                                            struct drm_atomic_state *state)
 309 {
 310         struct drm_connector_state *old_state =
 311                 drm_atomic_get_old_connector_state(state, connector);
 312         struct drm_connector_state *new_state =
 313                 drm_atomic_get_new_connector_state(state, connector);
 314         struct drm_crtc *crtc = new_state->crtc;
 315
 316         if (!crtc)
 317                 return 0;
 318
 319         if (old_state->colorspace != new_state->colorspace ||
 320             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 321                 struct drm_crtc_state *crtc_state;
 322
 323                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 324                 if (IS_ERR(crtc_state))
 325                         return PTR_ERR(crtc_state);
 326
 327                 crtc_state->mode_changed = true;
 328         }
 329
 330         return 0;
 331 }
 332
 333 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 334 {
 335         struct vc4_hdmi_connector_state *old_state =
 336                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 337         struct vc4_hdmi_connector_state *new_state =
 338                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 339
 340         if (connector->state)
 341                 __drm_atomic_helper_connector_destroy_state(connector->state);
 342
 343         kfree(old_state);
 344         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 345
 346         if (!new_state)
 347                 return;
 348
 349         new_state->base.max_bpc = 8;
 350         new_state->base.max_requested_bpc = 8;
 351         new_state->output_format = VC4_HDMI_OUTPUT_RGB;
 352         drm_atomic_helper_connector_tv_reset(connector);
 353 }
 354
 355 static struct drm_connector_state *
 356 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 357 {
 358         struct drm_connector_state *conn_state = connector->state;
 359         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 360         struct vc4_hdmi_connector_state *new_state;
 361
 362         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 363         if (!new_state)
 364                 return NULL;
 365
 366         new_state->tmds_char_rate = vc4_state->tmds_char_rate;
 367         new_state->output_bpc = vc4_state->output_bpc;
 368         new_state->output_format = vc4_state->output_format;
 369         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 370
 371         return &new_state->base;
 372 }
 373
 374 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 375         .detect = vc4_hdmi_connector_detect,
 376         .fill_modes = drm_helper_probe_single_connector_modes,
 377         .reset = vc4_hdmi_connector_reset,
 378         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 379         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 380 };
 381
 382 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 383         .get_modes = vc4_hdmi_connector_get_modes,
 384         .atomic_check = vc4_hdmi_connector_atomic_check,
 385 };
 386
 387 static int vc4_hdmi_connector_init(struct drm_device *dev,
 388                                    struct vc4_hdmi *vc4_hdmi)
 389 {
 390         struct drm_connector *connector = &vc4_hdmi->connector;
 391         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
 392         int ret;
 393
 394         ret = drmm_connector_init(dev, connector,
 395                                   &vc4_hdmi_connector_funcs,
 396                                   DRM_MODE_CONNECTOR_HDMIA,
 397                                   vc4_hdmi->ddc);
 398         if (ret)
 399                 return ret;
 400
 401         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 402
 403         /*
 404          * Some of the properties below require access to state, like bpc.
 405          * Allocate some default initial connector state with our reset helper.
 406          */
 407         if (connector->funcs->reset)
 408                 connector->funcs->reset(connector);
 409
 410         /* Create and attach TV margin props to this connector. */
 411         ret = drm_mode_create_tv_margin_properties(dev);
 412         if (ret)
 413                 return ret;
 414
 415         ret = drm_mode_create_hdmi_colorspace_property(connector);
 416         if (ret)
 417                 return ret;
 418
 419         drm_connector_attach_colorspace_property(connector);
 420         drm_connector_attach_tv_margin_properties(connector);
 421         drm_connector_attach_max_bpc_property(connector, 8, 12);
 422
 423         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 424                              DRM_CONNECTOR_POLL_DISCONNECT);
 425
 426         connector->interlace_allowed = 1;
 427         connector->doublescan_allowed = 0;
 428         connector->stereo_allowed = 1;
 429
 430         if (vc4_hdmi->variant->supports_hdr)
 431                 drm_connector_attach_hdr_output_metadata_property(connector);
 432
 433         drm_connector_attach_encoder(connector, encoder);
 434
 435         return 0;
 436 }
 437
 438 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 439                                 enum hdmi_infoframe_type type,
 440                                 bool poll)
 441 {
 442         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 443         u32 packet_id = type - 0x80;
 444         unsigned long flags;
 445
 446         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 447         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 448                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 449         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 450
 451         if (!poll)
 452                 return 0;
 453
 454         return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 455                           BIT(packet_id)), 100);
 456 }
 457
 458 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 459                                      union hdmi_infoframe *frame)
 460 {
 461         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 462         u32 packet_id = frame->any.type - 0x80;
 463         const struct vc4_hdmi_register *ram_packet_start =
 464                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 465         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 466         u32 packet_reg_next = ram_packet_start->offset +
 467                 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
 468         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 469                                                        ram_packet_start->reg);
 470         uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
 471         unsigned long flags;
 472         ssize_t len, i;
 473         int ret;
 474
 475         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 476                     VC4_HDMI_RAM_PACKET_ENABLE),
 477                   "Packet RAM has to be on to store the packet.");
 478
 479         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 480         if (len < 0)
 481                 return;
 482
 483         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 484         if (ret) {
 485                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 486                 return;
 487         }
 488
 489         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 490
 491         for (i = 0; i < len; i += 7) {
 492                 writel(buffer[i + 0] << 0 |
 493                        buffer[i + 1] << 8 |
 494                        buffer[i + 2] << 16,
 495                        base + packet_reg);
 496                 packet_reg += 4;
 497
 498                 writel(buffer[i + 3] << 0 |
 499                        buffer[i + 4] << 8 |
 500                        buffer[i + 5] << 16 |
 501                        buffer[i + 6] << 24,
 502                        base + packet_reg);
 503                 packet_reg += 4;
 504         }
 505
 506         /*
 507          * clear remainder of packet ram as it's included in the
 508          * infoframe and triggers a checksum error on hdmi analyser
 509          */
 510         for (; packet_reg < packet_reg_next; packet_reg += 4)
 511                 writel(0, base + packet_reg);
 512
 513         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 514                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 515
 516         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 517
 518         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 519                         BIT(packet_id)), 100);
 520         if (ret)
 521                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 522 }
 523
 524 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
 525                                               enum vc4_hdmi_output_format fmt)
 526 {
 527         switch (fmt) {
 528         case VC4_HDMI_OUTPUT_RGB:
 529                 frame->colorspace = HDMI_COLORSPACE_RGB;
 530                 break;
 531
 532         case VC4_HDMI_OUTPUT_YUV420:
 533                 frame->colorspace = HDMI_COLORSPACE_YUV420;
 534                 break;
 535
 536         case VC4_HDMI_OUTPUT_YUV422:
 537                 frame->colorspace = HDMI_COLORSPACE_YUV422;
 538                 break;
 539
 540         case VC4_HDMI_OUTPUT_YUV444:
 541                 frame->colorspace = HDMI_COLORSPACE_YUV444;
 542                 break;
 543
 544         default:
 545                 break;
 546         }
 547 }
 548
 549 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 550 {
 551         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 552         struct drm_connector *connector = &vc4_hdmi->connector;
 553         struct drm_connector_state *cstate = connector->state;
 554         struct vc4_hdmi_connector_state *vc4_state =
 555                 conn_state_to_vc4_hdmi_conn_state(cstate);
 556         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 557         union hdmi_infoframe frame;
 558         int ret;
 559
 560         lockdep_assert_held(&vc4_hdmi->mutex);
 561
 562         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 563                                                        connector, mode);
 564         if (ret < 0) {
 565                 DRM_ERROR("couldn't fill AVI infoframe\n");
 566                 return;
 567         }
 568
 569         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 570                                            connector, mode,
 571                                            vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ?
 572                                            HDMI_QUANTIZATION_RANGE_FULL :
 573                                            HDMI_QUANTIZATION_RANGE_LIMITED);
 574         drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
 575         vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format);
 576         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 577
 578         vc4_hdmi_write_infoframe(encoder, &frame);
 579 }
 580
 581 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 582 {
 583         union hdmi_infoframe frame;
 584         int ret;
 585
 586         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 587         if (ret < 0) {
 588                 DRM_ERROR("couldn't fill SPD infoframe\n");
 589                 return;
 590         }
 591
 592         frame.spd.sdi = HDMI_SPD_SDI_PC;
 593
 594         vc4_hdmi_write_infoframe(encoder, &frame);
 595 }
 596
 597 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 598 {
 599         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 600         struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
 601         union hdmi_infoframe frame;
 602
 603         memcpy(&frame.audio, audio, sizeof(*audio));
 604
 605         if (vc4_hdmi->packet_ram_enabled)
 606                 vc4_hdmi_write_infoframe(encoder, &frame);
 607 }
 608
 609 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 610 {
 611         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 612         struct drm_connector *connector = &vc4_hdmi->connector;
 613         struct drm_connector_state *conn_state = connector->state;
 614         union hdmi_infoframe frame;
 615
 616         lockdep_assert_held(&vc4_hdmi->mutex);
 617
 618         if (!vc4_hdmi->variant->supports_hdr)
 619                 return;
 620
 621         if (!conn_state->hdr_output_metadata)
 622                 return;
 623
 624         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 625                 return;
 626
 627         vc4_hdmi_write_infoframe(encoder, &frame);
 628 }
 629
 630 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 631 {
 632         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 633
 634         lockdep_assert_held(&vc4_hdmi->mutex);
 635
 636         vc4_hdmi_set_avi_infoframe(encoder);
 637         vc4_hdmi_set_spd_infoframe(encoder);
 638         /*
 639          * If audio was streaming, then we need to reenabled the audio
 640          * infoframe here during encoder_enable.
 641          */
 642         if (vc4_hdmi->audio.streaming)
 643                 vc4_hdmi_set_audio_infoframe(encoder);
 644
 645         vc4_hdmi_set_hdr_infoframe(encoder);
 646 }
 647
 648 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
 649                                          struct drm_display_mode *mode)
 650 {
 651         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 652         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 653
 654         lockdep_assert_held(&vc4_hdmi->mutex);
 655
 656         if (!display->is_hdmi)
 657                 return false;
 658
 659         if (!display->hdmi.scdc.supported ||
 660             !display->hdmi.scdc.scrambling.supported)
 661                 return false;
 662
 663         return true;
 664 }
 665
 666 #define SCRAMBLING_POLLING_DELAY_MS     1000
 667
 668 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 669 {
 670         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 671         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 672         unsigned long flags;
 673
 674         lockdep_assert_held(&vc4_hdmi->mutex);
 675
 676         if (!vc4_hdmi_supports_scrambling(encoder, mode))
 677                 return;
 678
 679         if (!vc4_hdmi_mode_needs_scrambling(mode,
 680                                             vc4_hdmi->output_bpc,
 681                                             vc4_hdmi->output_format))
 682                 return;
 683
 684         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 685         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 686
 687         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 688         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
 689                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 690         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 691
 692         vc4_hdmi->scdc_enabled = true;
 693
 694         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 695                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 696 }
 697
 698 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
 699 {
 700         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 701         unsigned long flags;
 702
 703         lockdep_assert_held(&vc4_hdmi->mutex);
 704
 705         if (!vc4_hdmi->scdc_enabled)
 706                 return;
 707
 708         vc4_hdmi->scdc_enabled = false;
 709
 710         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
 711                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
 712
 713         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 714         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
 715                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 716         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 717
 718         drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
 719         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
 720 }
 721
 722 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
 723 {
 724         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
 725                                                  struct vc4_hdmi,
 726                                                  scrambling_work);
 727
 728         if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
 729                 return;
 730
 731         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 732         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 733
 734         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 735                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 736 }
 737
 738 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 739                                                struct drm_atomic_state *state)
 740 {
 741         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 742         unsigned long flags;
 743
 744         mutex_lock(&vc4_hdmi->mutex);
 745
 746         vc4_hdmi->packet_ram_enabled = false;
 747
 748         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 749
 750         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 751
 752         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
 753
 754         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 755
 756         mdelay(1);
 757
 758         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 759         HDMI_WRITE(HDMI_VID_CTL,
 760                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 761         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 762
 763         vc4_hdmi_disable_scrambling(encoder);
 764
 765         mutex_unlock(&vc4_hdmi->mutex);
 766 }
 767
 768 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
 769                                                  struct drm_atomic_state *state)
 770 {
 771         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 772         unsigned long flags;
 773         int ret;
 774
 775         mutex_lock(&vc4_hdmi->mutex);
 776
 777         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 778         HDMI_WRITE(HDMI_VID_CTL,
 779                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 780         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 781
 782         if (vc4_hdmi->variant->phy_disable)
 783                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 784
 785         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 786         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 787
 788         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 789         if (ret < 0)
 790                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 791
 792         mutex_unlock(&vc4_hdmi->mutex);
 793 }
 794
 795 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
 796                                struct drm_connector_state *state,
 797                                const struct drm_display_mode *mode)
 798 {
 799         unsigned long flags;
 800         u32 csc_ctl;
 801
 802         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 803
 804         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 805                                 VC4_HD_CSC_CTL_ORDER);
 806
 807         if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) {
 808                 /* CEA VICs other than #1 requre limited range RGB
 809                  * output unless overridden by an AVI infoframe.
 810                  * Apply a colorspace conversion to squash 0-255 down
 811                  * to 16-235.  The matrix here is:
 812                  *
 813                  * [ 0      0      0.8594 16]
 814                  * [ 0      0.8594 0      16]
 815                  * [ 0.8594 0      0      16]
 816                  * [ 0      0      0       1]
 817                  */
 818                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 819                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 820                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 821                                          VC4_HD_CSC_CTL_MODE);
 822
 823                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 824                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 825                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 826                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 827                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 828                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 829         }
 830
 831         /* The RGB order applies even when CSC is disabled. */
 832         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 833
 834         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 835 }
 836
 837 /*
 838  * If we need to output Full Range RGB, then use the unity matrix
 839  *
 840  * [ 1      0      0      0]
 841  * [ 0      1      0      0]
 842  * [ 0      0      1      0]
 843  *
 844  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 845  */
 846 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = {
 847         { 0x2000, 0x0000, 0x0000, 0x0000 },
 848         { 0x0000, 0x2000, 0x0000, 0x0000 },
 849         { 0x0000, 0x0000, 0x2000, 0x0000 },
 850 };
 851
 852 /*
 853  * CEA VICs other than #1 require limited range RGB output unless
 854  * overridden by an AVI infoframe. Apply a colorspace conversion to
 855  * squash 0-255 down to 16-235. The matrix here is:
 856  *
 857  * [ 0.8594 0      0      16]
 858  * [ 0      0.8594 0      16]
 859  * [ 0      0      0.8594 16]
 860  *
 861  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 862  */
 863 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = {
 864         { 0x1b80, 0x0000, 0x0000, 0x0400 },
 865         { 0x0000, 0x1b80, 0x0000, 0x0400 },
 866         { 0x0000, 0x0000, 0x1b80, 0x0400 },
 867 };
 868
 869 /*
 870  * Conversion between Full Range RGB and Full Range YUV422 using the
 871  * BT.709 Colorspace
 872  *
 873  *
 874  * [  0.181906  0.611804  0.061758  16  ]
 875  * [ -0.100268 -0.337232  0.437500  128 ]
 876  * [  0.437500 -0.397386 -0.040114  128 ]
 877  *
 878  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 879  */
 880 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709[3][4] = {
 881         { 0x05d2, 0x1394, 0x01fa, 0x0400 },
 882         { 0xfccc, 0xf536, 0x0e00, 0x2000 },
 883         { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
 884 };
 885
 886 /*
 887  * Conversion between Full Range RGB and Full Range YUV444 using the
 888  * BT.709 Colorspace
 889  *
 890  * [ -0.100268 -0.337232  0.437500  128 ]
 891  * [  0.437500 -0.397386 -0.040114  128 ]
 892  * [  0.181906  0.611804  0.061758  16  ]
 893  *
 894  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 895  */
 896 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709[3][4] = {
 897         { 0xfccc, 0xf536, 0x0e00, 0x2000 },
 898         { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
 899         { 0x05d2, 0x1394, 0x01fa, 0x0400 },
 900 };
 901
 902 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
 903                                     const u16 coeffs[3][4])
 904 {
 905         lockdep_assert_held(&vc4_hdmi->hw_lock);
 906
 907         HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
 908         HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
 909         HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
 910         HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
 911         HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
 912         HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
 913 }
 914
 915 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
 916                                struct drm_connector_state *state,
 917                                const struct drm_display_mode *mode)
 918 {
 919         struct vc4_hdmi_connector_state *vc4_state =
 920                 conn_state_to_vc4_hdmi_conn_state(state);
 921         unsigned long flags;
 922         u32 if_cfg = 0;
 923         u32 if_xbar = 0x543210;
 924         u32 csc_chan_ctl = 0;
 925         u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 926                                                                VC5_MT_CP_CSC_CTL_MODE);
 927
 928         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 929
 930         switch (vc4_state->output_format) {
 931         case VC4_HDMI_OUTPUT_YUV444:
 932                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709);
 933                 break;
 934
 935         case VC4_HDMI_OUTPUT_YUV422:
 936                 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
 937                                          VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
 938                         VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
 939                         VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
 940
 941                 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
 942                                               VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
 943
 944                 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
 945                                         VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
 946
 947                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709);
 948                 break;
 949
 950         case VC4_HDMI_OUTPUT_RGB:
 951                 if_xbar = 0x354021;
 952
 953                 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode))
 954                         vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb);
 955                 else
 956                         vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity);
 957                 break;
 958
 959         default:
 960                 break;
 961         }
 962
 963         HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
 964         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
 965         HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
 966         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 967
 968         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 969 }
 970
 971 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 972                                  struct drm_connector_state *state,
 973                                  struct drm_display_mode *mode)
 974 {
 975         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 976         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 977         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 978         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 979         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 980                                    VC4_HDMI_VERTA_VSP) |
 981                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 982                                    VC4_HDMI_VERTA_VFP) |
 983                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 984         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 985                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
 986                                    interlaced,
 987                                    VC4_HDMI_VERTB_VBP));
 988         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 989                           VC4_SET_FIELD(mode->crtc_vtotal -
 990                                         mode->crtc_vsync_end,
 991                                         VC4_HDMI_VERTB_VBP));
 992         unsigned long flags;
 993         u32 reg;
 994
 995         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 996
 997         HDMI_WRITE(HDMI_HORZA,
 998                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 999                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1000                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1001                                  VC4_HDMI_HORZA_HAP));
1002
1003         HDMI_WRITE(HDMI_HORZB,
1004                    VC4_SET_FIELD((mode->htotal -
1005                                   mode->hsync_end) * pixel_rep,
1006                                  VC4_HDMI_HORZB_HBP) |
1007                    VC4_SET_FIELD((mode->hsync_end -
1008                                   mode->hsync_start) * pixel_rep,
1009                                  VC4_HDMI_HORZB_HSP) |
1010                    VC4_SET_FIELD((mode->hsync_start -
1011                                   mode->hdisplay) * pixel_rep,
1012                                  VC4_HDMI_HORZB_HFP));
1013
1014         HDMI_WRITE(HDMI_VERTA0, verta);
1015         HDMI_WRITE(HDMI_VERTA1, verta);
1016
1017         HDMI_WRITE(HDMI_VERTB0, vertb_even);
1018         HDMI_WRITE(HDMI_VERTB1, vertb);
1019
1020         reg = HDMI_READ(HDMI_MISC_CONTROL);
1021         reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1022         reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1023         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1024
1025         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1026 }
1027
1028 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1029                                  struct drm_connector_state *state,
1030                                  struct drm_display_mode *mode)
1031 {
1032         const struct vc4_hdmi_connector_state *vc4_state =
1033                 conn_state_to_vc4_hdmi_conn_state(state);
1034         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1035         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1036         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1037         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1038         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1039                                    VC5_HDMI_VERTA_VSP) |
1040                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1041                                    VC5_HDMI_VERTA_VFP) |
1042                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1043         u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1044                                    VC5_HDMI_VERTB_VSPO) |
1045                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
1046                                    VC4_HDMI_VERTB_VBP));
1047         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1048                           VC4_SET_FIELD(mode->crtc_vtotal -
1049                                         mode->crtc_vsync_end - interlaced,
1050                                         VC4_HDMI_VERTB_VBP));
1051         unsigned long flags;
1052         unsigned char gcp;
1053         bool gcp_en;
1054         u32 reg;
1055
1056         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1057
1058         HDMI_WRITE(HDMI_HORZA,
1059                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1060                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1061                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1062                                  VC5_HDMI_HORZA_HAP) |
1063                    VC4_SET_FIELD((mode->hsync_start -
1064                                   mode->hdisplay) * pixel_rep,
1065                                  VC5_HDMI_HORZA_HFP));
1066
1067         HDMI_WRITE(HDMI_HORZB,
1068                    VC4_SET_FIELD((mode->htotal -
1069                                   mode->hsync_end) * pixel_rep,
1070                                  VC5_HDMI_HORZB_HBP) |
1071                    VC4_SET_FIELD((mode->hsync_end -
1072                                   mode->hsync_start) * pixel_rep,
1073                                  VC5_HDMI_HORZB_HSP));
1074
1075         HDMI_WRITE(HDMI_VERTA0, verta);
1076         HDMI_WRITE(HDMI_VERTA1, verta);
1077
1078         HDMI_WRITE(HDMI_VERTB0, vertb_even);
1079         HDMI_WRITE(HDMI_VERTB1, vertb);
1080
1081         switch (vc4_state->output_bpc) {
1082         case 12:
1083                 gcp = 6;
1084                 gcp_en = true;
1085                 break;
1086         case 10:
1087                 gcp = 5;
1088                 gcp_en = true;
1089                 break;
1090         case 8:
1091         default:
1092                 gcp = 4;
1093                 gcp_en = false;
1094                 break;
1095         }
1096
1097         /*
1098          * YCC422 is always 36-bit and not considered deep colour so
1099          * doesn't signal in GCP.
1100          */
1101         if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {
1102                 gcp = 4;
1103                 gcp_en = false;
1104         }
1105
1106         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1107         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1108                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1109         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1110                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1111         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1112
1113         reg = HDMI_READ(HDMI_GCP_WORD_1);
1114         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1115         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1116         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1117
1118         reg = HDMI_READ(HDMI_GCP_CONFIG);
1119         reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1120         reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
1121         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1122
1123         reg = HDMI_READ(HDMI_MISC_CONTROL);
1124         reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1125         reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1126         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1127
1128         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1129
1130         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1131 }
1132
1133 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1134 {
1135         unsigned long flags;
1136         u32 drift;
1137         int ret;
1138
1139         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1140
1141         drift = HDMI_READ(HDMI_FIFO_CTL);
1142         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1143
1144         HDMI_WRITE(HDMI_FIFO_CTL,
1145                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1146         HDMI_WRITE(HDMI_FIFO_CTL,
1147                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1148
1149         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1150
1151         usleep_range(1000, 1100);
1152
1153         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1154
1155         HDMI_WRITE(HDMI_FIFO_CTL,
1156                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1157         HDMI_WRITE(HDMI_FIFO_CTL,
1158                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1159
1160         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1161
1162         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1163                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1164         WARN_ONCE(ret, "Timeout waiting for "
1165                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1166 }
1167
1168 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1169                                                 struct drm_atomic_state *state)
1170 {
1171         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1172         struct drm_connector *connector = &vc4_hdmi->connector;
1173         struct drm_connector_state *conn_state =
1174                 drm_atomic_get_new_connector_state(state, connector);
1175         struct vc4_hdmi_connector_state *vc4_conn_state =
1176                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1177         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1178         unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate;
1179         unsigned long bvb_rate, hsm_rate;
1180         unsigned long flags;
1181         int ret;
1182
1183         mutex_lock(&vc4_hdmi->mutex);
1184
1185         /*
1186          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1187          * be faster than pixel clock, infinitesimally faster, tested in
1188          * simulation. Otherwise, exact value is unimportant for HDMI
1189          * operation." This conflicts with bcm2835's vc4 documentation, which
1190          * states HSM's clock has to be at least 108% of the pixel clock.
1191          *
1192          * Real life tests reveal that vc4's firmware statement holds up, and
1193          * users are able to use pixel clocks closer to HSM's, namely for
1194          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1195          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1196          * 162MHz.
1197          *
1198          * Additionally, the AXI clock needs to be at least 25% of
1199          * pixel clock, but HSM ends up being the limiting factor.
1200          */
1201         hsm_rate = max_t(unsigned long, 120000000, (tmds_char_rate / 100) * 101);
1202         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1203         if (ret) {
1204                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1205                 goto out;
1206         }
1207
1208         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1209         if (ret < 0) {
1210                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1211                 goto out;
1212         }
1213
1214         ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1215         if (ret) {
1216                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1217                 goto err_put_runtime_pm;
1218         }
1219
1220         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1221         if (ret) {
1222                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1223                 goto err_put_runtime_pm;
1224         }
1225
1226
1227         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1228
1229         if (tmds_char_rate > 297000000)
1230                 bvb_rate = 300000000;
1231         else if (tmds_char_rate > 148500000)
1232                 bvb_rate = 150000000;
1233         else
1234                 bvb_rate = 75000000;
1235
1236         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1237         if (ret) {
1238                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1239                 goto err_disable_pixel_clock;
1240         }
1241
1242         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1243         if (ret) {
1244                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1245                 goto err_disable_pixel_clock;
1246         }
1247
1248         if (vc4_hdmi->variant->phy_init)
1249                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1250
1251         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1252
1253         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1254                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1255                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1256                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1257
1258         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1259
1260         if (vc4_hdmi->variant->set_timings)
1261                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1262
1263         mutex_unlock(&vc4_hdmi->mutex);
1264
1265         return;
1266
1267 err_disable_pixel_clock:
1268         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1269 err_put_runtime_pm:
1270         pm_runtime_put(&vc4_hdmi->pdev->dev);
1271 out:
1272         mutex_unlock(&vc4_hdmi->mutex);
1273         return;
1274 }
1275
1276 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1277                                              struct drm_atomic_state *state)
1278 {
1279         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1280         struct drm_connector *connector = &vc4_hdmi->connector;
1281         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1282         struct drm_connector_state *conn_state =
1283                 drm_atomic_get_new_connector_state(state, connector);
1284         unsigned long flags;
1285
1286         mutex_lock(&vc4_hdmi->mutex);
1287
1288         if (vc4_hdmi->variant->csc_setup)
1289                 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1290
1291         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1292         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1293         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1294
1295         mutex_unlock(&vc4_hdmi->mutex);
1296 }
1297
1298 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1299                                               struct drm_atomic_state *state)
1300 {
1301         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1302         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1303         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1304         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1305         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1306         unsigned long flags;
1307         int ret;
1308
1309         mutex_lock(&vc4_hdmi->mutex);
1310
1311         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1312
1313         HDMI_WRITE(HDMI_VID_CTL,
1314                    VC4_HD_VID_CTL_ENABLE |
1315                    VC4_HD_VID_CTL_CLRRGB |
1316                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1317                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1318                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1319                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1320
1321         HDMI_WRITE(HDMI_VID_CTL,
1322                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1323
1324         if (display->is_hdmi) {
1325                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1326                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1327                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1328
1329                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1330
1331                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1332                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1333                 WARN_ONCE(ret, "Timeout waiting for "
1334                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1335         } else {
1336                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1337                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1338                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1339                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1340                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1341                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1342
1343                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1344
1345                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1346                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1347                 WARN_ONCE(ret, "Timeout waiting for "
1348                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1349         }
1350
1351         if (display->is_hdmi) {
1352                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1353
1354                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1355                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1356
1357                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1358                            VC4_HDMI_RAM_PACKET_ENABLE);
1359
1360                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1361                 vc4_hdmi->packet_ram_enabled = true;
1362
1363                 vc4_hdmi_set_infoframes(encoder);
1364         }
1365
1366         vc4_hdmi_recenter_fifo(vc4_hdmi);
1367         vc4_hdmi_enable_scrambling(encoder);
1368
1369         mutex_unlock(&vc4_hdmi->mutex);
1370 }
1371
1372 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1373                                              struct drm_crtc_state *crtc_state,
1374                                              struct drm_connector_state *conn_state)
1375 {
1376         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1377         struct vc4_hdmi_connector_state *vc4_state =
1378                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1379
1380         mutex_lock(&vc4_hdmi->mutex);
1381         drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1382                       &crtc_state->adjusted_mode);
1383         vc4_hdmi->output_bpc = vc4_state->output_bpc;
1384         vc4_hdmi->output_format = vc4_state->output_format;
1385         mutex_unlock(&vc4_hdmi->mutex);
1386 }
1387
1388 static bool
1389 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi,
1390                                   const struct drm_display_info *info,
1391                                   const struct drm_display_mode *mode,
1392                                   unsigned int format, unsigned int bpc)
1393 {
1394         struct drm_device *dev = vc4_hdmi->connector.dev;
1395         u8 vic = drm_match_cea_mode(mode);
1396
1397         if (vic == 1 && bpc != 8) {
1398                 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc);
1399                 return false;
1400         }
1401
1402         if (!info->is_hdmi &&
1403             (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) {
1404                 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n");
1405                 return false;
1406         }
1407
1408         switch (format) {
1409         case VC4_HDMI_OUTPUT_RGB:
1410                 drm_dbg(dev, "RGB Format, checking the constraints.\n");
1411
1412                 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444))
1413                         return false;
1414
1415                 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1416                         drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1417                         return false;
1418                 }
1419
1420                 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1421                         drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1422                         return false;
1423                 }
1424
1425                 drm_dbg(dev, "RGB format supported in that configuration.\n");
1426
1427                 return true;
1428
1429         case VC4_HDMI_OUTPUT_YUV422:
1430                 drm_dbg(dev, "YUV422 format, checking the constraints.\n");
1431
1432                 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) {
1433                         drm_dbg(dev, "Sink doesn't support YUV422.\n");
1434                         return false;
1435                 }
1436
1437                 if (bpc != 12) {
1438                         drm_dbg(dev, "YUV422 only supports 12 bpc.\n");
1439                         return false;
1440                 }
1441
1442                 drm_dbg(dev, "YUV422 format supported in that configuration.\n");
1443
1444                 return true;
1445
1446         case VC4_HDMI_OUTPUT_YUV444:
1447                 drm_dbg(dev, "YUV444 format, checking the constraints.\n");
1448
1449                 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) {
1450                         drm_dbg(dev, "Sink doesn't support YUV444.\n");
1451                         return false;
1452                 }
1453
1454                 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1455                         drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1456                         return false;
1457                 }
1458
1459                 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1460                         drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1461                         return false;
1462                 }
1463
1464                 drm_dbg(dev, "YUV444 format supported in that configuration.\n");
1465
1466                 return true;
1467         }
1468
1469         return false;
1470 }
1471
1472 static enum drm_mode_status
1473 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
1474                              unsigned long long clock)
1475 {
1476         const struct drm_connector *connector = &vc4_hdmi->connector;
1477         const struct drm_display_info *info = &connector->display_info;
1478
1479         if (clock > vc4_hdmi->variant->max_pixel_clock)
1480                 return MODE_CLOCK_HIGH;
1481
1482         if (vc4_hdmi->disable_4kp60 && clock > HDMI_14_MAX_TMDS_CLK)
1483                 return MODE_CLOCK_HIGH;
1484
1485         if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000))
1486                 return MODE_CLOCK_HIGH;
1487
1488         return MODE_OK;
1489 }
1490
1491 static unsigned long long
1492 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
1493                                     unsigned int bpc,
1494                                     enum vc4_hdmi_output_format fmt)
1495 {
1496         unsigned long long clock = mode->clock * 1000ULL;
1497
1498         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1499                 clock = clock * 2;
1500
1501         if (fmt == VC4_HDMI_OUTPUT_YUV422)
1502                 bpc = 8;
1503
1504         clock = clock * bpc;
1505         do_div(clock, 8);
1506
1507         return clock;
1508 }
1509
1510 static int
1511 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
1512                                struct vc4_hdmi_connector_state *vc4_state,
1513                                const struct drm_display_mode *mode,
1514                                unsigned int bpc, unsigned int fmt)
1515 {
1516         unsigned long long clock;
1517
1518         clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
1519         if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, clock) != MODE_OK)
1520                 return -EINVAL;
1521
1522         vc4_state->tmds_char_rate = clock;
1523
1524         return 0;
1525 }
1526
1527 static int
1528 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi,
1529                                 struct vc4_hdmi_connector_state *vc4_state,
1530                                 const struct drm_display_mode *mode,
1531                                 unsigned int bpc)
1532 {
1533         struct drm_device *dev = vc4_hdmi->connector.dev;
1534         const struct drm_connector *connector = &vc4_hdmi->connector;
1535         const struct drm_display_info *info = &connector->display_info;
1536         unsigned int format;
1537
1538         drm_dbg(dev, "Trying with an RGB output\n");
1539
1540         format = VC4_HDMI_OUTPUT_RGB;
1541         if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1542                 int ret;
1543
1544                 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1545                                                      mode, bpc, format);
1546                 if (!ret) {
1547                         vc4_state->output_format = format;
1548                         return 0;
1549                 }
1550         }
1551
1552         drm_dbg(dev, "Failed, Trying with an YUV422 output\n");
1553
1554         format = VC4_HDMI_OUTPUT_YUV422;
1555         if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1556                 int ret;
1557
1558                 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1559                                                      mode, bpc, format);
1560                 if (!ret) {
1561                         vc4_state->output_format = format;
1562                         return 0;
1563                 }
1564         }
1565
1566         drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n");
1567
1568         return -EINVAL;
1569 }
1570
1571 static int
1572 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi,
1573                                 struct vc4_hdmi_connector_state *vc4_state,
1574                                 const struct drm_display_mode *mode)
1575 {
1576         struct drm_device *dev = vc4_hdmi->connector.dev;
1577         struct drm_connector_state *conn_state = &vc4_state->base;
1578         unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12);
1579         unsigned int bpc;
1580         int ret;
1581
1582         for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
1583                 drm_dbg(dev, "Trying with a %d bpc output\n", bpc);
1584
1585                 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state,
1586                                                       mode, bpc);
1587                 if (ret)
1588                         continue;
1589
1590                 vc4_state->output_bpc = bpc;
1591
1592                 drm_dbg(dev,
1593                         "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n",
1594                         mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
1595                         vc4_state->output_bpc,
1596                         vc4_hdmi_output_fmt_str(vc4_state->output_format),
1597                         vc4_state->tmds_char_rate);
1598
1599                 break;
1600         }
1601
1602         return ret;
1603 }
1604
1605 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
1606 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
1607
1608 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1609                                          struct drm_crtc_state *crtc_state,
1610                                          struct drm_connector_state *conn_state)
1611 {
1612         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1613         struct drm_connector *connector = &vc4_hdmi->connector;
1614         struct drm_connector_state *old_conn_state =
1615                 drm_atomic_get_old_connector_state(conn_state->state, connector);
1616         struct vc4_hdmi_connector_state *old_vc4_state =
1617                 conn_state_to_vc4_hdmi_conn_state(old_conn_state);
1618         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1619         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1620         unsigned long long tmds_char_rate = mode->clock * 1000;
1621         unsigned long long tmds_bit_rate;
1622         int ret;
1623
1624         if (vc4_hdmi->variant->unsupported_odd_h_timings) {
1625                 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1626                         /* Only try to fixup DBLCLK modes to get 480i and 576i
1627                          * working.
1628                          * A generic solution for all modes with odd horizontal
1629                          * timing values seems impossible based on trying to
1630                          * solve it for 1366x768 monitors.
1631                          */
1632                         if ((mode->hsync_start - mode->hdisplay) & 1)
1633                                 mode->hsync_start--;
1634                         if ((mode->hsync_end - mode->hsync_start) & 1)
1635                                 mode->hsync_end--;
1636                 }
1637
1638                 /* Now check whether we still have odd values remaining */
1639                 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1640                     (mode->hsync_end % 2) || (mode->htotal % 2))
1641                         return -EINVAL;
1642         }
1643
1644         /*
1645          * The 1440p@60 pixel rate is in the same range than the first
1646          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1647          * bandwidth). Slightly lower the frequency to bring it out of
1648          * the WiFi range.
1649          */
1650         tmds_bit_rate = tmds_char_rate * 10;
1651         if (vc4_hdmi->disable_wifi_frequencies &&
1652             (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1653              tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1654                 mode->clock = 238560;
1655                 tmds_char_rate = mode->clock * 1000;
1656         }
1657
1658         ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode);
1659         if (ret)
1660                 return ret;
1661
1662         /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */
1663         if (vc4_state->output_bpc != old_vc4_state->output_bpc ||
1664             vc4_state->output_format != old_vc4_state->output_format)
1665                 crtc_state->mode_changed = true;
1666
1667         return 0;
1668 }
1669
1670 static enum drm_mode_status
1671 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1672                             const struct drm_display_mode *mode)
1673 {
1674         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1675
1676         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1677             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1678             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1679              (mode->hsync_end % 2) || (mode->htotal % 2)))
1680                 return MODE_H_ILLEGAL;
1681
1682         return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode->clock * 1000);
1683 }
1684
1685 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1686         .atomic_check = vc4_hdmi_encoder_atomic_check,
1687         .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1688         .mode_valid = vc4_hdmi_encoder_mode_valid,
1689 };
1690
1691 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1692 {
1693         int i;
1694         u32 channel_map = 0;
1695
1696         for (i = 0; i < 8; i++) {
1697                 if (channel_mask & BIT(i))
1698                         channel_map |= i << (3 * i);
1699         }
1700         return channel_map;
1701 }
1702
1703 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1704 {
1705         int i;
1706         u32 channel_map = 0;
1707
1708         for (i = 0; i < 8; i++) {
1709                 if (channel_mask & BIT(i))
1710                         channel_map |= i << (4 * i);
1711         }
1712         return channel_map;
1713 }
1714
1715 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
1716 {
1717         unsigned long flags;
1718         u32 hotplug;
1719
1720         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1721         hotplug = HDMI_READ(HDMI_HOTPLUG);
1722         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1723
1724         return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
1725 }
1726
1727 /* HDMI audio codec callbacks */
1728 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1729                                          unsigned int samplerate)
1730 {
1731         u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1732         unsigned long flags;
1733         unsigned long n, m;
1734
1735         rational_best_approximation(hsm_clock, samplerate,
1736                                     VC4_HD_MAI_SMP_N_MASK >>
1737                                     VC4_HD_MAI_SMP_N_SHIFT,
1738                                     (VC4_HD_MAI_SMP_M_MASK >>
1739                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
1740                                     &n, &m);
1741
1742         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1743         HDMI_WRITE(HDMI_MAI_SMP,
1744                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1745                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1746         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1747 }
1748
1749 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1750 {
1751         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1752         u32 n, cts;
1753         u64 tmp;
1754
1755         lockdep_assert_held(&vc4_hdmi->mutex);
1756         lockdep_assert_held(&vc4_hdmi->hw_lock);
1757
1758         n = 128 * samplerate / 1000;
1759         tmp = (u64)(mode->clock * 1000) * n;
1760         do_div(tmp, 128 * samplerate);
1761         cts = tmp;
1762
1763         HDMI_WRITE(HDMI_CRP_CFG,
1764                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1765                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1766
1767         /*
1768          * We could get slightly more accurate clocks in some cases by
1769          * providing a CTS_1 value.  The two CTS values are alternated
1770          * between based on the period fields
1771          */
1772         HDMI_WRITE(HDMI_CTS_0, cts);
1773         HDMI_WRITE(HDMI_CTS_1, cts);
1774 }
1775
1776 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1777 {
1778         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1779
1780         return snd_soc_card_get_drvdata(card);
1781 }
1782
1783 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
1784 {
1785         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1786
1787         lockdep_assert_held(&vc4_hdmi->mutex);
1788
1789         /*
1790          * If the encoder is currently in DVI mode, treat the codec DAI
1791          * as missing.
1792          */
1793         if (!display->is_hdmi)
1794                 return false;
1795
1796         return true;
1797 }
1798
1799 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1800 {
1801         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1802         unsigned long flags;
1803
1804         mutex_lock(&vc4_hdmi->mutex);
1805
1806         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1807                 mutex_unlock(&vc4_hdmi->mutex);
1808                 return -ENODEV;
1809         }
1810
1811         vc4_hdmi->audio.streaming = true;
1812
1813         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1814         HDMI_WRITE(HDMI_MAI_CTL,
1815                    VC4_HD_MAI_CTL_RESET |
1816                    VC4_HD_MAI_CTL_FLUSH |
1817                    VC4_HD_MAI_CTL_DLATE |
1818                    VC4_HD_MAI_CTL_ERRORE |
1819                    VC4_HD_MAI_CTL_ERRORF);
1820         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1821
1822         if (vc4_hdmi->variant->phy_rng_enable)
1823                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1824
1825         mutex_unlock(&vc4_hdmi->mutex);
1826
1827         return 0;
1828 }
1829
1830 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1831 {
1832         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
1833         struct device *dev = &vc4_hdmi->pdev->dev;
1834         unsigned long flags;
1835         int ret;
1836
1837         lockdep_assert_held(&vc4_hdmi->mutex);
1838
1839         vc4_hdmi->audio.streaming = false;
1840         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1841         if (ret)
1842                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1843
1844         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1845
1846         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1847         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1848         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1849
1850         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1851 }
1852
1853 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1854 {
1855         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1856         unsigned long flags;
1857
1858         mutex_lock(&vc4_hdmi->mutex);
1859
1860         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1861
1862         HDMI_WRITE(HDMI_MAI_CTL,
1863                    VC4_HD_MAI_CTL_DLATE |
1864                    VC4_HD_MAI_CTL_ERRORE |
1865                    VC4_HD_MAI_CTL_ERRORF);
1866
1867         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1868
1869         if (vc4_hdmi->variant->phy_rng_disable)
1870                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1871
1872         vc4_hdmi->audio.streaming = false;
1873         vc4_hdmi_audio_reset(vc4_hdmi);
1874
1875         mutex_unlock(&vc4_hdmi->mutex);
1876 }
1877
1878 static int sample_rate_to_mai_fmt(int samplerate)
1879 {
1880         switch (samplerate) {
1881         case 8000:
1882                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1883         case 11025:
1884                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1885         case 12000:
1886                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1887         case 16000:
1888                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1889         case 22050:
1890                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1891         case 24000:
1892                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1893         case 32000:
1894                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1895         case 44100:
1896                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1897         case 48000:
1898                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1899         case 64000:
1900                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
1901         case 88200:
1902                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
1903         case 96000:
1904                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
1905         case 128000:
1906                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
1907         case 176400:
1908                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
1909         case 192000:
1910                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
1911         default:
1912                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
1913         }
1914 }
1915
1916 /* HDMI audio codec callbacks */
1917 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
1918                                   struct hdmi_codec_daifmt *daifmt,
1919                                   struct hdmi_codec_params *params)
1920 {
1921         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1922         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
1923         unsigned int sample_rate = params->sample_rate;
1924         unsigned int channels = params->channels;
1925         unsigned long flags;
1926         u32 audio_packet_config, channel_mask;
1927         u32 channel_map;
1928         u32 mai_audio_format;
1929         u32 mai_sample_rate;
1930
1931         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1932                 sample_rate, params->sample_width, channels);
1933
1934         mutex_lock(&vc4_hdmi->mutex);
1935
1936         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1937                 mutex_unlock(&vc4_hdmi->mutex);
1938                 return -EINVAL;
1939         }
1940
1941         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
1942
1943         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1944         HDMI_WRITE(HDMI_MAI_CTL,
1945                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
1946                    VC4_HD_MAI_CTL_WHOLSMP |
1947                    VC4_HD_MAI_CTL_CHALIGN |
1948                    VC4_HD_MAI_CTL_ENABLE);
1949
1950         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
1951         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
1952             params->channels == 8)
1953                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
1954         else
1955                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
1956         HDMI_WRITE(HDMI_MAI_FMT,
1957                    VC4_SET_FIELD(mai_sample_rate,
1958                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
1959                    VC4_SET_FIELD(mai_audio_format,
1960                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
1961
1962         /* The B frame identifier should match the value used by alsa-lib (8) */
1963         audio_packet_config =
1964                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1965                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1966                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1967
1968         channel_mask = GENMASK(channels - 1, 0);
1969         audio_packet_config |= VC4_SET_FIELD(channel_mask,
1970                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1971
1972         /* Set the MAI threshold */
1973         HDMI_WRITE(HDMI_MAI_THR,
1974                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
1975                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
1976                    VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
1977                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
1978
1979         HDMI_WRITE(HDMI_MAI_CONFIG,
1980                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1981                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
1982                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1983
1984         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1985         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1986         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1987
1988         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
1989
1990         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1991
1992         memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
1993         vc4_hdmi_set_audio_infoframe(encoder);
1994
1995         mutex_unlock(&vc4_hdmi->mutex);
1996
1997         return 0;
1998 }
1999
2000 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2001         .name = "vc4-hdmi-cpu-dai-component",
2002 };
2003
2004 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2005 {
2006         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2007
2008         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2009
2010         return 0;
2011 }
2012
2013 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2014         .name = "vc4-hdmi-cpu-dai",
2015         .probe  = vc4_hdmi_audio_cpu_dai_probe,
2016         .playback = {
2017                 .stream_name = "Playback",
2018                 .channels_min = 1,
2019                 .channels_max = 8,
2020                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2021                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2022                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2023                          SNDRV_PCM_RATE_192000,
2024                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2025         },
2026 };
2027
2028 static const struct snd_dmaengine_pcm_config pcm_conf = {
2029         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2030         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2031 };
2032
2033 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
2034                                   uint8_t *buf, size_t len)
2035 {
2036         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2037         struct drm_connector *connector = &vc4_hdmi->connector;
2038
2039         mutex_lock(&vc4_hdmi->mutex);
2040         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2041         mutex_unlock(&vc4_hdmi->mutex);
2042
2043         return 0;
2044 }
2045
2046 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
2047         .get_eld = vc4_hdmi_audio_get_eld,
2048         .prepare = vc4_hdmi_audio_prepare,
2049         .audio_shutdown = vc4_hdmi_audio_shutdown,
2050         .audio_startup = vc4_hdmi_audio_startup,
2051 };
2052
2053 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
2054         .ops = &vc4_hdmi_codec_ops,
2055         .max_i2s_channels = 8,
2056         .i2s = 1,
2057 };
2058
2059 static void vc4_hdmi_audio_codec_release(void *ptr)
2060 {
2061         struct vc4_hdmi *vc4_hdmi = ptr;
2062
2063         platform_device_unregister(vc4_hdmi->audio.codec_pdev);
2064         vc4_hdmi->audio.codec_pdev = NULL;
2065 }
2066
2067 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2068 {
2069         const struct vc4_hdmi_register *mai_data =
2070                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2071         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2072         struct snd_soc_card *card = &vc4_hdmi->audio.card;
2073         struct device *dev = &vc4_hdmi->pdev->dev;
2074         struct platform_device *codec_pdev;
2075         const __be32 *addr;
2076         int index, len;
2077         int ret;
2078
2079         if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
2080                 dev_warn(dev,
2081                          "'dmas' DT property is missing or empty, no HDMI audio\n");
2082                 return 0;
2083         }
2084
2085         if (mai_data->reg != VC4_HD) {
2086                 WARN_ONCE(true, "MAI isn't in the HD block\n");
2087                 return -EINVAL;
2088         }
2089
2090         /*
2091          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2092          * the bus address specified in the DT, because the physical address
2093          * (the one returned by platform_get_resource()) is not appropriate
2094          * for DMA transfers.
2095          * This VC/MMU should probably be exposed to avoid this kind of hacks.
2096          */
2097         index = of_property_match_string(dev->of_node, "reg-names", "hd");
2098         /* Before BCM2711, we don't have a named register range */
2099         if (index < 0)
2100                 index = 1;
2101
2102         addr = of_get_address(dev->of_node, index, NULL, NULL);
2103
2104         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2105         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2106         vc4_hdmi->audio.dma_data.maxburst = 2;
2107
2108         /*
2109          * NOTE: Strictly speaking, we should probably use a DRM-managed
2110          * registration there to avoid removing all the audio components
2111          * by the time the driver doesn't have any user anymore.
2112          *
2113          * However, the ASoC core uses a number of devm_kzalloc calls
2114          * when registering, even when using non-device-managed
2115          * functions (such as in snd_soc_register_component()).
2116          *
2117          * If we call snd_soc_unregister_component() in a DRM-managed
2118          * action, the device-managed actions have already been executed
2119          * and thus we would access memory that has been freed.
2120          *
2121          * Using device-managed hooks here probably leaves us open to a
2122          * bunch of issues if userspace still has a handle on the ALSA
2123          * device when the device is removed. However, this is mitigated
2124          * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2125          * path to prevent the access to the device resources if it
2126          * isn't there anymore.
2127          *
2128          * Then, the vc4_hdmi structure is DRM-managed and thus only
2129          * freed whenever the last user has closed the DRM device file.
2130          * It should thus outlive ALSA in most situations.
2131          */
2132         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2133         if (ret) {
2134                 dev_err(dev, "Could not register PCM component: %d\n", ret);
2135                 return ret;
2136         }
2137
2138         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2139                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
2140         if (ret) {
2141                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2142                 return ret;
2143         }
2144
2145         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
2146                                                    PLATFORM_DEVID_AUTO,
2147                                                    &vc4_hdmi_codec_pdata,
2148                                                    sizeof(vc4_hdmi_codec_pdata));
2149         if (IS_ERR(codec_pdev)) {
2150                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
2151                 return PTR_ERR(codec_pdev);
2152         }
2153         vc4_hdmi->audio.codec_pdev = codec_pdev;
2154
2155         ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi);
2156         if (ret)
2157                 return ret;
2158
2159         dai_link->cpus          = &vc4_hdmi->audio.cpu;
2160         dai_link->codecs        = &vc4_hdmi->audio.codec;
2161         dai_link->platforms     = &vc4_hdmi->audio.platform;
2162
2163         dai_link->num_cpus      = 1;
2164         dai_link->num_codecs    = 1;
2165         dai_link->num_platforms = 1;
2166
2167         dai_link->name = "MAI";
2168         dai_link->stream_name = "MAI PCM";
2169         dai_link->codecs->dai_name = "i2s-hifi";
2170         dai_link->cpus->dai_name = dev_name(dev);
2171         dai_link->codecs->name = dev_name(&codec_pdev->dev);
2172         dai_link->platforms->name = dev_name(dev);
2173
2174         card->dai_link = dai_link;
2175         card->num_links = 1;
2176         card->name = vc4_hdmi->variant->card_name;
2177         card->driver_name = "vc4-hdmi";
2178         card->dev = dev;
2179         card->owner = THIS_MODULE;
2180
2181         /*
2182          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2183          * stores a pointer to the snd card object in dev->driver_data. This
2184          * means we cannot use it for something else. The hdmi back-pointer is
2185          * now stored in card->drvdata and should be retrieved with
2186          * snd_soc_card_get_drvdata() if needed.
2187          */
2188         snd_soc_card_set_drvdata(card, vc4_hdmi);
2189         ret = devm_snd_soc_register_card(dev, card);
2190         if (ret)
2191                 dev_err_probe(dev, ret, "Could not register sound card\n");
2192
2193         return ret;
2194
2195 }
2196
2197 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2198 {
2199         struct vc4_hdmi *vc4_hdmi = priv;
2200         struct drm_connector *connector = &vc4_hdmi->connector;
2201         struct drm_device *dev = connector->dev;
2202
2203         if (dev && dev->registered)
2204                 drm_connector_helper_hpd_irq_event(connector);
2205
2206         return IRQ_HANDLED;
2207 }
2208
2209 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2210 {
2211         struct drm_connector *connector = &vc4_hdmi->connector;
2212         struct platform_device *pdev = vc4_hdmi->pdev;
2213         int ret;
2214
2215         if (vc4_hdmi->variant->external_irq_controller) {
2216                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2217                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2218
2219                 ret = request_threaded_irq(hpd_con,
2220                                            NULL,
2221                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2222                                            "vc4 hdmi hpd connected", vc4_hdmi);
2223                 if (ret)
2224                         return ret;
2225
2226                 ret = request_threaded_irq(hpd_rm,
2227                                            NULL,
2228                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2229                                            "vc4 hdmi hpd disconnected", vc4_hdmi);
2230                 if (ret) {
2231                         free_irq(hpd_con, vc4_hdmi);
2232                         return ret;
2233                 }
2234
2235                 connector->polled = DRM_CONNECTOR_POLL_HPD;
2236         }
2237
2238         return 0;
2239 }
2240
2241 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi)
2242 {
2243         struct platform_device *pdev = vc4_hdmi->pdev;
2244
2245         if (vc4_hdmi->variant->external_irq_controller) {
2246                 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi);
2247                 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi);
2248         }
2249 }
2250
2251 #ifdef CONFIG_DRM_VC4_HDMI_CEC
2252 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2253 {
2254         struct vc4_hdmi *vc4_hdmi = priv;
2255
2256         if (vc4_hdmi->cec_rx_msg.len)
2257                 cec_received_msg(vc4_hdmi->cec_adap,
2258                                  &vc4_hdmi->cec_rx_msg);
2259
2260         return IRQ_HANDLED;
2261 }
2262
2263 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2264 {
2265         struct vc4_hdmi *vc4_hdmi = priv;
2266
2267         if (vc4_hdmi->cec_tx_ok) {
2268                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2269                                   0, 0, 0, 0);
2270         } else {
2271                 /*
2272                  * This CEC implementation makes 1 retry, so if we
2273                  * get a NACK, then that means it made 2 attempts.
2274                  */
2275                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2276                                   0, 2, 0, 0);
2277         }
2278         return IRQ_HANDLED;
2279 }
2280
2281 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2282 {
2283         struct vc4_hdmi *vc4_hdmi = priv;
2284         irqreturn_t ret;
2285
2286         if (vc4_hdmi->cec_irq_was_rx)
2287                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2288         else
2289                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2290
2291         return ret;
2292 }
2293
2294 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2295 {
2296         struct drm_device *dev = vc4_hdmi->connector.dev;
2297         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2298         unsigned int i;
2299
2300         lockdep_assert_held(&vc4_hdmi->hw_lock);
2301
2302         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2303                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2304
2305         if (msg->len > 16) {
2306                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2307                 return;
2308         }
2309
2310         for (i = 0; i < msg->len; i += 4) {
2311                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2312
2313                 msg->msg[i] = val & 0xff;
2314                 msg->msg[i + 1] = (val >> 8) & 0xff;
2315                 msg->msg[i + 2] = (val >> 16) & 0xff;
2316                 msg->msg[i + 3] = (val >> 24) & 0xff;
2317         }
2318 }
2319
2320 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2321 {
2322         u32 cntrl1;
2323
2324         lockdep_assert_held(&vc4_hdmi->hw_lock);
2325
2326         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2327         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2328         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2329         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2330
2331         return IRQ_WAKE_THREAD;
2332 }
2333
2334 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2335 {
2336         struct vc4_hdmi *vc4_hdmi = priv;
2337         irqreturn_t ret;
2338
2339         spin_lock(&vc4_hdmi->hw_lock);
2340         ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2341         spin_unlock(&vc4_hdmi->hw_lock);
2342
2343         return ret;
2344 }
2345
2346 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2347 {
2348         u32 cntrl1;
2349
2350         lockdep_assert_held(&vc4_hdmi->hw_lock);
2351
2352         vc4_hdmi->cec_rx_msg.len = 0;
2353         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2354         vc4_cec_read_msg(vc4_hdmi, cntrl1);
2355         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2356         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2357         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2358
2359         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2360
2361         return IRQ_WAKE_THREAD;
2362 }
2363
2364 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
2365 {
2366         struct vc4_hdmi *vc4_hdmi = priv;
2367         irqreturn_t ret;
2368
2369         spin_lock(&vc4_hdmi->hw_lock);
2370         ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2371         spin_unlock(&vc4_hdmi->hw_lock);
2372
2373         return ret;
2374 }
2375
2376 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2377 {
2378         struct vc4_hdmi *vc4_hdmi = priv;
2379         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2380         irqreturn_t ret;
2381         u32 cntrl5;
2382
2383         if (!(stat & VC4_HDMI_CPU_CEC))
2384                 return IRQ_NONE;
2385
2386         spin_lock(&vc4_hdmi->hw_lock);
2387         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2388         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2389         if (vc4_hdmi->cec_irq_was_rx)
2390                 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2391         else
2392                 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2393
2394         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2395         spin_unlock(&vc4_hdmi->hw_lock);
2396
2397         return ret;
2398 }
2399
2400 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2401 {
2402         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2403         /* clock period in microseconds */
2404         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2405         unsigned long flags;
2406         u32 val;
2407         int ret;
2408
2409         /*
2410          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2411          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2412          * .detect or .get_modes might call .adap_enable, which leads to this
2413          * function being called with that mutex held.
2414          *
2415          * Concurrency is not an issue for the moment since we don't share any
2416          * state with KMS, so we can ignore the lock for now, but we need to
2417          * keep it in mind if we were to change that assumption.
2418          */
2419
2420         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2421         if (ret)
2422                 return ret;
2423
2424         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2425
2426         val = HDMI_READ(HDMI_CEC_CNTRL_5);
2427         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2428                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2429                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2430         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2431                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2432
2433         HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2434                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2435         HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2436         HDMI_WRITE(HDMI_CEC_CNTRL_2,
2437                    ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2438                    ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2439                    ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2440                    ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2441                    ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2442         HDMI_WRITE(HDMI_CEC_CNTRL_3,
2443                    ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2444                    ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2445                    ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2446                    ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2447         HDMI_WRITE(HDMI_CEC_CNTRL_4,
2448                    ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2449                    ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2450                    ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2451                    ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2452
2453         if (!vc4_hdmi->variant->external_irq_controller)
2454                 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2455
2456         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2457
2458         return 0;
2459 }
2460
2461 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2462 {
2463         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2464         unsigned long flags;
2465
2466         /*
2467          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2468          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2469          * .detect or .get_modes might call .adap_enable, which leads to this
2470          * function being called with that mutex held.
2471          *
2472          * Concurrency is not an issue for the moment since we don't share any
2473          * state with KMS, so we can ignore the lock for now, but we need to
2474          * keep it in mind if we were to change that assumption.
2475          */
2476
2477         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2478
2479         if (!vc4_hdmi->variant->external_irq_controller)
2480                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2481
2482         HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2483                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2484
2485         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2486
2487         pm_runtime_put(&vc4_hdmi->pdev->dev);
2488
2489         return 0;
2490 }
2491
2492 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2493 {
2494         if (enable)
2495                 return vc4_hdmi_cec_enable(adap);
2496         else
2497                 return vc4_hdmi_cec_disable(adap);
2498 }
2499
2500 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2501 {
2502         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2503         unsigned long flags;
2504
2505         /*
2506          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2507          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2508          * .detect or .get_modes might call .adap_enable, which leads to this
2509          * function being called with that mutex held.
2510          *
2511          * Concurrency is not an issue for the moment since we don't share any
2512          * state with KMS, so we can ignore the lock for now, but we need to
2513          * keep it in mind if we were to change that assumption.
2514          */
2515
2516         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2517         HDMI_WRITE(HDMI_CEC_CNTRL_1,
2518                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2519                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2520         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2521
2522         return 0;
2523 }
2524
2525 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2526                                       u32 signal_free_time, struct cec_msg *msg)
2527 {
2528         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2529         struct drm_device *dev = vc4_hdmi->connector.dev;
2530         unsigned long flags;
2531         u32 val;
2532         unsigned int i;
2533
2534         /*
2535          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2536          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2537          * .detect or .get_modes might call .adap_enable, which leads to this
2538          * function being called with that mutex held.
2539          *
2540          * Concurrency is not an issue for the moment since we don't share any
2541          * state with KMS, so we can ignore the lock for now, but we need to
2542          * keep it in mind if we were to change that assumption.
2543          */
2544
2545         if (msg->len > 16) {
2546                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2547                 return -ENOMEM;
2548         }
2549
2550         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2551
2552         for (i = 0; i < msg->len; i += 4)
2553                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2554                            (msg->msg[i]) |
2555                            (msg->msg[i + 1] << 8) |
2556                            (msg->msg[i + 2] << 16) |
2557                            (msg->msg[i + 3] << 24));
2558
2559         val = HDMI_READ(HDMI_CEC_CNTRL_1);
2560         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2561         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2562         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2563         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2564         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2565
2566         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2567
2568         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2569
2570         return 0;
2571 }
2572
2573 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2574         .adap_enable = vc4_hdmi_cec_adap_enable,
2575         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2576         .adap_transmit = vc4_hdmi_cec_adap_transmit,
2577 };
2578
2579 static void vc4_hdmi_cec_release(void *ptr)
2580 {
2581         struct vc4_hdmi *vc4_hdmi = ptr;
2582
2583         cec_unregister_adapter(vc4_hdmi->cec_adap);
2584         vc4_hdmi->cec_adap = NULL;
2585 }
2586
2587 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2588 {
2589         struct cec_connector_info conn_info;
2590         struct platform_device *pdev = vc4_hdmi->pdev;
2591         struct device *dev = &pdev->dev;
2592         int ret;
2593
2594         if (!of_find_property(dev->of_node, "interrupts", NULL)) {
2595                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
2596                 return 0;
2597         }
2598
2599         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
2600                                                   vc4_hdmi, "vc4",
2601                                                   CEC_CAP_DEFAULTS |
2602                                                   CEC_CAP_CONNECTOR_INFO, 1);
2603         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
2604         if (ret < 0)
2605                 return ret;
2606
2607         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
2608         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
2609
2610         if (vc4_hdmi->variant->external_irq_controller) {
2611                 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
2612                                                 vc4_cec_irq_handler_rx_bare,
2613                                                 vc4_cec_irq_handler_rx_thread, 0,
2614                                                 "vc4 hdmi cec rx", vc4_hdmi);
2615                 if (ret)
2616                         goto err_delete_cec_adap;
2617
2618                 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
2619                                                 vc4_cec_irq_handler_tx_bare,
2620                                                 vc4_cec_irq_handler_tx_thread, 0,
2621                                                 "vc4 hdmi cec tx", vc4_hdmi);
2622                 if (ret)
2623                         goto err_delete_cec_adap;
2624         } else {
2625                 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
2626                                                 vc4_cec_irq_handler,
2627                                                 vc4_cec_irq_handler_thread, 0,
2628                                                 "vc4 hdmi cec", vc4_hdmi);
2629                 if (ret)
2630                         goto err_delete_cec_adap;
2631         }
2632
2633         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
2634         if (ret < 0)
2635                 goto err_delete_cec_adap;
2636
2637         /*
2638          * NOTE: Strictly speaking, we should probably use a DRM-managed
2639          * registration there to avoid removing the CEC adapter by the
2640          * time the DRM driver doesn't have any user anymore.
2641          *
2642          * However, the CEC framework already cleans up the CEC adapter
2643          * only when the last user has closed its file descriptor, so we
2644          * don't need to handle it in DRM.
2645          *
2646          * By the time the device-managed hook is executed, we will give
2647          * up our reference to the CEC adapter and therefore don't
2648          * really care when it's actually freed.
2649          *
2650          * There's still a problematic sequence: if we unregister our
2651          * CEC adapter, but the userspace keeps a handle on the CEC
2652          * adapter but not the DRM device for some reason. In such a
2653          * case, our vc4_hdmi structure will be freed, but the
2654          * cec_adapter structure will have a dangling pointer to what
2655          * used to be our HDMI controller. If we get a CEC call at that
2656          * moment, we could end up with a use-after-free. Fortunately,
2657          * the CEC framework already handles this too, by calling
2658          * cec_is_registered() in cec_ioctl() and cec_poll().
2659          */
2660         ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
2661         if (ret)
2662                 return ret;
2663
2664         return 0;
2665
2666 err_delete_cec_adap:
2667         cec_delete_adapter(vc4_hdmi->cec_adap);
2668
2669         return ret;
2670 }
2671 #else
2672 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2673 {
2674         return 0;
2675 }
2676 #endif
2677
2678 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
2679                                  struct debugfs_regset32 *regset,
2680                                  enum vc4_hdmi_regs reg)
2681 {
2682         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2683         struct debugfs_reg32 *regs, *new_regs;
2684         unsigned int count = 0;
2685         unsigned int i;
2686
2687         regs = kcalloc(variant->num_registers, sizeof(*regs),
2688                        GFP_KERNEL);
2689         if (!regs)
2690                 return -ENOMEM;
2691
2692         for (i = 0; i < variant->num_registers; i++) {
2693                 const struct vc4_hdmi_register *field = &variant->registers[i];
2694
2695                 if (field->reg != reg)
2696                         continue;
2697
2698                 regs[count].name = field->name;
2699                 regs[count].offset = field->offset;
2700                 count++;
2701         }
2702
2703         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
2704         if (!new_regs)
2705                 return -ENOMEM;
2706
2707         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
2708         regset->regs = new_regs;
2709         regset->nregs = count;
2710
2711         return 0;
2712 }
2713
2714 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2715 {
2716         struct platform_device *pdev = vc4_hdmi->pdev;
2717         struct device *dev = &pdev->dev;
2718         int ret;
2719
2720         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
2721         if (IS_ERR(vc4_hdmi->hdmicore_regs))
2722                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
2723
2724         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
2725         if (IS_ERR(vc4_hdmi->hd_regs))
2726                 return PTR_ERR(vc4_hdmi->hd_regs);
2727
2728         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2729         if (ret)
2730                 return ret;
2731
2732         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2733         if (ret)
2734                 return ret;
2735
2736         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
2737         if (IS_ERR(vc4_hdmi->pixel_clock)) {
2738                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
2739                 if (ret != -EPROBE_DEFER)
2740                         DRM_ERROR("Failed to get pixel clock\n");
2741                 return ret;
2742         }
2743
2744         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2745         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2746                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2747                 return PTR_ERR(vc4_hdmi->hsm_clock);
2748         }
2749         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2750         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2751
2752         return 0;
2753 }
2754
2755 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2756 {
2757         struct platform_device *pdev = vc4_hdmi->pdev;
2758         struct device *dev = &pdev->dev;
2759         struct resource *res;
2760         int ret;
2761
2762         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2763         if (!res)
2764                 return -ENODEV;
2765
2766         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2767                                                resource_size(res));
2768         if (!vc4_hdmi->hdmicore_regs)
2769                 return -ENOMEM;
2770
2771         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2772         if (!res)
2773                 return -ENODEV;
2774
2775         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2776         if (!vc4_hdmi->hd_regs)
2777                 return -ENOMEM;
2778
2779         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2780         if (!res)
2781                 return -ENODEV;
2782
2783         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2784         if (!vc4_hdmi->cec_regs)
2785                 return -ENOMEM;
2786
2787         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2788         if (!res)
2789                 return -ENODEV;
2790
2791         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2792         if (!vc4_hdmi->csc_regs)
2793                 return -ENOMEM;
2794
2795         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2796         if (!res)
2797                 return -ENODEV;
2798
2799         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2800         if (!vc4_hdmi->dvp_regs)
2801                 return -ENOMEM;
2802
2803         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2804         if (!res)
2805                 return -ENODEV;
2806
2807         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2808         if (!vc4_hdmi->phy_regs)
2809                 return -ENOMEM;
2810
2811         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2812         if (!res)
2813                 return -ENODEV;
2814
2815         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2816         if (!vc4_hdmi->ram_regs)
2817                 return -ENOMEM;
2818
2819         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2820         if (!res)
2821                 return -ENODEV;
2822
2823         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2824         if (!vc4_hdmi->rm_regs)
2825                 return -ENOMEM;
2826
2827         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2828         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2829                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2830                 return PTR_ERR(vc4_hdmi->hsm_clock);
2831         }
2832
2833         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2834         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2835                 DRM_ERROR("Failed to get pixel bvb clock\n");
2836                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2837         }
2838
2839         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2840         if (IS_ERR(vc4_hdmi->audio_clock)) {
2841                 DRM_ERROR("Failed to get audio clock\n");
2842                 return PTR_ERR(vc4_hdmi->audio_clock);
2843         }
2844
2845         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2846         if (IS_ERR(vc4_hdmi->cec_clock)) {
2847                 DRM_ERROR("Failed to get CEC clock\n");
2848                 return PTR_ERR(vc4_hdmi->cec_clock);
2849         }
2850
2851         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2852         if (IS_ERR(vc4_hdmi->reset)) {
2853                 DRM_ERROR("Failed to get HDMI reset line\n");
2854                 return PTR_ERR(vc4_hdmi->reset);
2855         }
2856
2857         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2858         if (ret)
2859                 return ret;
2860
2861         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2862         if (ret)
2863                 return ret;
2864
2865         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
2866         if (ret)
2867                 return ret;
2868
2869         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
2870         if (ret)
2871                 return ret;
2872
2873         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
2874         if (ret)
2875                 return ret;
2876
2877         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
2878         if (ret)
2879                 return ret;
2880
2881         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
2882         if (ret)
2883                 return ret;
2884
2885         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
2886         if (ret)
2887                 return ret;
2888
2889         return 0;
2890 }
2891
2892 static int vc4_hdmi_runtime_suspend(struct device *dev)
2893 {
2894         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2895
2896         clk_disable_unprepare(vc4_hdmi->hsm_clock);
2897
2898         return 0;
2899 }
2900
2901 static int vc4_hdmi_runtime_resume(struct device *dev)
2902 {
2903         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2904         unsigned long __maybe_unused flags;
2905         u32 __maybe_unused value;
2906         int ret;
2907
2908         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
2909         if (ret)
2910                 return ret;
2911
2912         if (vc4_hdmi->variant->reset)
2913                 vc4_hdmi->variant->reset(vc4_hdmi);
2914
2915 #ifdef CONFIG_DRM_VC4_HDMI_CEC
2916         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2917         value = HDMI_READ(HDMI_CEC_CNTRL_1);
2918         /* Set the logical address to Unregistered */
2919         value |= VC4_HDMI_CEC_ADDR_MASK;
2920         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
2921         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2922
2923         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
2924
2925         if (!vc4_hdmi->variant->external_irq_controller) {
2926                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2927                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
2928                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2929         }
2930 #endif
2931
2932         return 0;
2933 }
2934
2935 static void vc4_hdmi_put_ddc_device(void *ptr)
2936 {
2937         struct vc4_hdmi *vc4_hdmi = ptr;
2938
2939         put_device(&vc4_hdmi->ddc->dev);
2940 }
2941
2942 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2943 {
2944         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2945         struct platform_device *pdev = to_platform_device(dev);
2946         struct drm_device *drm = dev_get_drvdata(master);
2947         struct vc4_hdmi *vc4_hdmi;
2948         struct drm_encoder *encoder;
2949         struct device_node *ddc_node;
2950         int ret;
2951
2952         vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
2953         if (!vc4_hdmi)
2954                 return -ENOMEM;
2955
2956         mutex_init(&vc4_hdmi->mutex);
2957         spin_lock_init(&vc4_hdmi->hw_lock);
2958         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2959
2960         dev_set_drvdata(dev, vc4_hdmi);
2961         encoder = &vc4_hdmi->encoder.base;
2962         vc4_hdmi->encoder.type = variant->encoder_type;
2963         vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2964         vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2965         vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2966         vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2967         vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2968         vc4_hdmi->pdev = pdev;
2969         vc4_hdmi->variant = variant;
2970
2971         /*
2972          * Since we don't know the state of the controller and its
2973          * display (if any), let's assume it's always enabled.
2974          * vc4_hdmi_disable_scrambling() will thus run at boot, make
2975          * sure it's disabled, and avoid any inconsistency.
2976          */
2977         if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
2978                 vc4_hdmi->scdc_enabled = true;
2979
2980         ret = variant->init_resources(vc4_hdmi);
2981         if (ret)
2982                 return ret;
2983
2984         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2985         if (!ddc_node) {
2986                 DRM_ERROR("Failed to find ddc node in device tree\n");
2987                 return -ENODEV;
2988         }
2989
2990         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2991         of_node_put(ddc_node);
2992         if (!vc4_hdmi->ddc) {
2993                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2994                 return -EPROBE_DEFER;
2995         }
2996
2997         ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
2998         if (ret)
2999                 return ret;
3000
3001         /* Only use the GPIO HPD pin if present in the DT, otherwise
3002          * we'll use the HDMI core's register.
3003          */
3004         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3005         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3006                 return PTR_ERR(vc4_hdmi->hpd_gpio);
3007         }
3008
3009         vc4_hdmi->disable_wifi_frequencies =
3010                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3011
3012         if (variant->max_pixel_clock == 600000000) {
3013                 struct vc4_dev *vc4 = to_vc4_dev(drm);
3014                 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
3015
3016                 if (max_rate < 550000000)
3017                         vc4_hdmi->disable_4kp60 = true;
3018         }
3019
3020         pm_runtime_enable(dev);
3021
3022         /*
3023          *  We need to have the device powered up at this point to call
3024          *  our reset hook and for the CEC init.
3025          */
3026         ret = pm_runtime_resume_and_get(dev);
3027         if (ret)
3028                 goto err_disable_runtime_pm;
3029
3030         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3031              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
3032             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3033                 clk_prepare_enable(vc4_hdmi->pixel_clock);
3034                 clk_prepare_enable(vc4_hdmi->hsm_clock);
3035                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3036         }
3037
3038         ret = drmm_encoder_init(drm, encoder,
3039                                 NULL,
3040                                 DRM_MODE_ENCODER_TMDS,
3041                                 NULL);
3042         if (ret)
3043                 goto err_put_runtime_pm;
3044
3045         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3046
3047         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3048         if (ret)
3049                 goto err_put_runtime_pm;
3050
3051         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3052         if (ret)
3053                 goto err_put_runtime_pm;
3054
3055         ret = vc4_hdmi_cec_init(vc4_hdmi);
3056         if (ret)
3057                 goto err_free_hotplug;
3058
3059         ret = vc4_hdmi_audio_init(vc4_hdmi);
3060         if (ret)
3061                 goto err_free_hotplug;
3062
3063         vc4_debugfs_add_file(drm, variant->debugfs_name,
3064                              vc4_hdmi_debugfs_regs,
3065                              vc4_hdmi);
3066
3067         pm_runtime_put_sync(dev);
3068
3069         return 0;
3070
3071 err_free_hotplug:
3072         vc4_hdmi_hotplug_exit(vc4_hdmi);
3073 err_put_runtime_pm:
3074         pm_runtime_put_sync(dev);
3075 err_disable_runtime_pm:
3076         pm_runtime_disable(dev);
3077
3078         return ret;
3079 }
3080
3081 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
3082                             void *data)
3083 {
3084         struct vc4_hdmi *vc4_hdmi;
3085
3086         /*
3087          * ASoC makes it a bit hard to retrieve a pointer to the
3088          * vc4_hdmi structure. Registering the card will overwrite our
3089          * device drvdata with a pointer to the snd_soc_card structure,
3090          * which can then be used to retrieve whatever drvdata we want
3091          * to associate.
3092          *
3093          * However, that doesn't fly in the case where we wouldn't
3094          * register an ASoC card (because of an old DT that is missing
3095          * the dmas properties for example), then the card isn't
3096          * registered and the device drvdata wouldn't be set.
3097          *
3098          * We can deal with both cases by making sure a snd_soc_card
3099          * pointer and a vc4_hdmi structure are pointing to the same
3100          * memory address, so we can treat them indistinctly without any
3101          * issue.
3102          */
3103         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
3104         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
3105         vc4_hdmi = dev_get_drvdata(dev);
3106
3107         kfree(vc4_hdmi->hdmi_regset.regs);
3108         kfree(vc4_hdmi->hd_regset.regs);
3109
3110         vc4_hdmi_hotplug_exit(vc4_hdmi);
3111
3112         pm_runtime_disable(dev);
3113 }
3114
3115 static const struct component_ops vc4_hdmi_ops = {
3116         .bind   = vc4_hdmi_bind,
3117         .unbind = vc4_hdmi_unbind,
3118 };
3119
3120 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3121 {
3122         return component_add(&pdev->dev, &vc4_hdmi_ops);
3123 }
3124
3125 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
3126 {
3127         component_del(&pdev->dev, &vc4_hdmi_ops);
3128         return 0;
3129 }
3130
3131 static const struct vc4_hdmi_variant bcm2835_variant = {
3132         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3133         .debugfs_name           = "hdmi_regs",
3134         .card_name              = "vc4-hdmi",
3135         .max_pixel_clock        = 162000000,
3136         .registers              = vc4_hdmi_fields,
3137         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
3138
3139         .init_resources         = vc4_hdmi_init_resources,
3140         .csc_setup              = vc4_hdmi_csc_setup,
3141         .reset                  = vc4_hdmi_reset,
3142         .set_timings            = vc4_hdmi_set_timings,
3143         .phy_init               = vc4_hdmi_phy_init,
3144         .phy_disable            = vc4_hdmi_phy_disable,
3145         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
3146         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
3147         .channel_map            = vc4_hdmi_channel_map,
3148         .supports_hdr           = false,
3149 };
3150
3151 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3152         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3153         .debugfs_name           = "hdmi0_regs",
3154         .card_name              = "vc4-hdmi-0",
3155         .max_pixel_clock        = 600000000,
3156         .registers              = vc5_hdmi_hdmi0_fields,
3157         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3158         .phy_lane_mapping       = {
3159                 PHY_LANE_0,
3160                 PHY_LANE_1,
3161                 PHY_LANE_2,
3162                 PHY_LANE_CK,
3163         },
3164         .unsupported_odd_h_timings      = true,
3165         .external_irq_controller        = true,
3166
3167         .init_resources         = vc5_hdmi_init_resources,
3168         .csc_setup              = vc5_hdmi_csc_setup,
3169         .reset                  = vc5_hdmi_reset,
3170         .set_timings            = vc5_hdmi_set_timings,
3171         .phy_init               = vc5_hdmi_phy_init,
3172         .phy_disable            = vc5_hdmi_phy_disable,
3173         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
3174         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
3175         .channel_map            = vc5_hdmi_channel_map,
3176         .supports_hdr           = true,
3177         .hp_detect              = vc5_hdmi_hp_detect,
3178 };
3179
3180 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3181         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
3182         .debugfs_name           = "hdmi1_regs",
3183         .card_name              = "vc4-hdmi-1",
3184         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
3185         .registers              = vc5_hdmi_hdmi1_fields,
3186         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3187         .phy_lane_mapping       = {
3188                 PHY_LANE_1,
3189                 PHY_LANE_0,
3190                 PHY_LANE_CK,
3191                 PHY_LANE_2,
3192         },
3193         .unsupported_odd_h_timings      = true,
3194         .external_irq_controller        = true,
3195
3196         .init_resources         = vc5_hdmi_init_resources,
3197         .csc_setup              = vc5_hdmi_csc_setup,
3198         .reset                  = vc5_hdmi_reset,
3199         .set_timings            = vc5_hdmi_set_timings,
3200         .phy_init               = vc5_hdmi_phy_init,
3201         .phy_disable            = vc5_hdmi_phy_disable,
3202         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
3203         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
3204         .channel_map            = vc5_hdmi_channel_map,
3205         .supports_hdr           = true,
3206         .hp_detect              = vc5_hdmi_hp_detect,
3207 };
3208
3209 static const struct of_device_id vc4_hdmi_dt_match[] = {
3210         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3211         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3212         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3213         {}
3214 };
3215
3216 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3217         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3218                            vc4_hdmi_runtime_resume,
3219                            NULL)
3220 };
3221
3222 struct platform_driver vc4_hdmi_driver = {
3223         .probe = vc4_hdmi_dev_probe,
3224         .remove = vc4_hdmi_dev_remove,
3225         .driver = {
3226                 .name = "vc4_hdmi",
3227                 .of_match_table = vc4_hdmi_dt_match,
3228                 .pm = &vc4_hdmi_pm_ops,
3229         },
3230 };