drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/display/drm_hdmi_helper.h>
  35 #include <drm/display/drm_scdc_helper.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_drv.h>
  38 #include <drm/drm_probe_helper.h>
  39 #include <drm/drm_simple_kms_helper.h>
  40 #include <linux/clk.h>
  41 #include <linux/component.h>
  42 #include <linux/gpio/consumer.h>
  43 #include <linux/i2c.h>
  44 #include <linux/of_address.h>
  45 #include <linux/of_gpio.h>
  46 #include <linux/of_platform.h>
  47 #include <linux/pm_runtime.h>
  48 #include <linux/rational.h>
  49 #include <linux/reset.h>
  50 #include <sound/dmaengine_pcm.h>
  51 #include <sound/hdmi-codec.h>
  52 #include <sound/pcm_drm_eld.h>
  53 #include <sound/pcm_params.h>
  54 #include <sound/soc.h>
  55 #include "media/cec.h"
  56 #include "vc4_drv.h"
  57 #include "vc4_hdmi.h"
  58 #include "vc4_hdmi_regs.h"
  59 #include "vc4_regs.h"
  60
  61 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  62 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  63 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  64 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  65 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  66 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  67
  68 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  69 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  70 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  71 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  72
  73 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  74 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  75 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  76 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  77 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  78 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  79
  80 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  81 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  82
  83 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  84 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  85 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  86 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  87
  88 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  89
  90 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  91 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  92
  93 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  94 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  95
  96 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  97
  98 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
  99 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
 100
 101 # define VC4_HD_M_SW_RST                        BIT(2)
 102 # define VC4_HD_M_ENABLE                        BIT(0)
 103
 104 #define HSM_MIN_CLOCK_FREQ      120000000
 105 #define CEC_CLOCK_FREQ 40000
 106
 107 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 108
 109 static const char * const output_format_str[] = {
 110         [VC4_HDMI_OUTPUT_RGB]           = "RGB",
 111         [VC4_HDMI_OUTPUT_YUV420]        = "YUV 4:2:0",
 112         [VC4_HDMI_OUTPUT_YUV422]        = "YUV 4:2:2",
 113         [VC4_HDMI_OUTPUT_YUV444]        = "YUV 4:4:4",
 114 };
 115
 116 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt)
 117 {
 118         if (fmt >= ARRAY_SIZE(output_format_str))
 119                 return "invalid";
 120
 121         return output_format_str[fmt];
 122 }
 123
 124 static unsigned long long
 125 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
 126                                     unsigned int bpc, enum vc4_hdmi_output_format fmt);
 127
 128 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
 129                                            unsigned int bpc,
 130                                            enum vc4_hdmi_output_format fmt)
 131 {
 132         unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
 133
 134         return clock > HDMI_14_MAX_TMDS_CLK;
 135 }
 136
 137 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi,
 138                                        const struct drm_display_mode *mode)
 139 {
 140         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 141
 142         return !display->is_hdmi ||
 143                 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
 144 }
 145
 146 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 147 {
 148         struct drm_info_node *node = (struct drm_info_node *)m->private;
 149         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
 150         struct drm_device *drm = vc4_hdmi->connector.dev;
 151         struct drm_printer p = drm_seq_file_printer(m);
 152         int idx;
 153
 154         if (!drm_dev_enter(drm, &idx))
 155                 return -ENODEV;
 156
 157         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 158         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 159         drm_print_regset32(&p, &vc4_hdmi->cec_regset);
 160         drm_print_regset32(&p, &vc4_hdmi->csc_regset);
 161         drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
 162         drm_print_regset32(&p, &vc4_hdmi->phy_regset);
 163         drm_print_regset32(&p, &vc4_hdmi->ram_regset);
 164         drm_print_regset32(&p, &vc4_hdmi->rm_regset);
 165
 166         drm_dev_exit(idx);
 167
 168         return 0;
 169 }
 170
 171 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 172 {
 173         struct drm_device *drm = vc4_hdmi->connector.dev;
 174         unsigned long flags;
 175         int idx;
 176
 177         /*
 178          * We can be called by our bind callback, when the
 179          * connector->dev pointer might not be initialised yet.
 180          */
 181         if (drm && !drm_dev_enter(drm, &idx))
 182                 return;
 183
 184         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 185
 186         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 187         udelay(1);
 188         HDMI_WRITE(HDMI_M_CTL, 0);
 189
 190         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 191
 192         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 193                    VC4_HDMI_SW_RESET_HDMI |
 194                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 195
 196         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 197
 198         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 199
 200         if (drm)
 201                 drm_dev_exit(idx);
 202 }
 203
 204 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 205 {
 206         struct drm_device *drm = vc4_hdmi->connector.dev;
 207         unsigned long flags;
 208         int idx;
 209
 210         /*
 211          * We can be called by our bind callback, when the
 212          * connector->dev pointer might not be initialised yet.
 213          */
 214         if (drm && !drm_dev_enter(drm, &idx))
 215                 return;
 216
 217         reset_control_reset(vc4_hdmi->reset);
 218
 219         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 220
 221         HDMI_WRITE(HDMI_DVP_CTL, 0);
 222
 223         HDMI_WRITE(HDMI_CLOCK_STOP,
 224                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 225
 226         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 227
 228         if (drm)
 229                 drm_dev_exit(idx);
 230 }
 231
 232 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 233 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 234 {
 235         struct drm_device *drm = vc4_hdmi->connector.dev;
 236         unsigned long cec_rate;
 237         unsigned long flags;
 238         u16 clk_cnt;
 239         u32 value;
 240         int idx;
 241
 242         /*
 243          * This function is called by our runtime_resume implementation
 244          * and thus at bind time, when we haven't registered our
 245          * connector yet and thus don't have a pointer to the DRM
 246          * device.
 247          */
 248         if (drm && !drm_dev_enter(drm, &idx))
 249                 return;
 250
 251         cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
 252
 253         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 254
 255         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 256         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 257
 258         /*
 259          * Set the clock divider: the hsm_clock rate and this divider
 260          * setting will give a 40 kHz CEC clock.
 261          */
 262         clk_cnt = cec_rate / CEC_CLOCK_FREQ;
 263         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 264         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 265
 266         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 267
 268         if (drm)
 269                 drm_dev_exit(idx);
 270 }
 271 #else
 272 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 273 #endif
 274
 275 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder);
 276
 277 static enum drm_connector_status
 278 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 279 {
 280         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 281         bool connected = false;
 282
 283         mutex_lock(&vc4_hdmi->mutex);
 284
 285         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 286
 287         if (vc4_hdmi->hpd_gpio) {
 288                 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
 289                         connected = true;
 290         } else {
 291                 if (vc4_hdmi->variant->hp_detect &&
 292                     vc4_hdmi->variant->hp_detect(vc4_hdmi))
 293                         connected = true;
 294         }
 295
 296         if (connected) {
 297                 if (connector->status != connector_status_connected) {
 298                         struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
 299
 300                         if (edid) {
 301                                 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 302                                 kfree(edid);
 303                         }
 304                 }
 305
 306                 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base);
 307                 pm_runtime_put(&vc4_hdmi->pdev->dev);
 308                 mutex_unlock(&vc4_hdmi->mutex);
 309                 return connector_status_connected;
 310         }
 311
 312         cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 313         pm_runtime_put(&vc4_hdmi->pdev->dev);
 314         mutex_unlock(&vc4_hdmi->mutex);
 315         return connector_status_disconnected;
 316 }
 317
 318 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 319 {
 320         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 321         int ret = 0;
 322         struct edid *edid;
 323
 324         mutex_lock(&vc4_hdmi->mutex);
 325
 326         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 327         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 328         if (!edid) {
 329                 ret = -ENODEV;
 330                 goto out;
 331         }
 332
 333         drm_connector_update_edid_property(connector, edid);
 334         ret = drm_add_edid_modes(connector, edid);
 335         kfree(edid);
 336
 337         if (vc4_hdmi->disable_4kp60) {
 338                 struct drm_device *drm = connector->dev;
 339                 struct drm_display_mode *mode;
 340
 341                 list_for_each_entry(mode, &connector->probed_modes, head) {
 342                         if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) {
 343                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 344                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 345                         }
 346                 }
 347         }
 348
 349 out:
 350         mutex_unlock(&vc4_hdmi->mutex);
 351
 352         return ret;
 353 }
 354
 355 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 356                                            struct drm_atomic_state *state)
 357 {
 358         struct drm_connector_state *old_state =
 359                 drm_atomic_get_old_connector_state(state, connector);
 360         struct drm_connector_state *new_state =
 361                 drm_atomic_get_new_connector_state(state, connector);
 362         struct drm_crtc *crtc = new_state->crtc;
 363
 364         if (!crtc)
 365                 return 0;
 366
 367         if (old_state->colorspace != new_state->colorspace ||
 368             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 369                 struct drm_crtc_state *crtc_state;
 370
 371                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 372                 if (IS_ERR(crtc_state))
 373                         return PTR_ERR(crtc_state);
 374
 375                 crtc_state->mode_changed = true;
 376         }
 377
 378         return 0;
 379 }
 380
 381 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 382 {
 383         struct vc4_hdmi_connector_state *old_state =
 384                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 385         struct vc4_hdmi_connector_state *new_state =
 386                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 387
 388         if (connector->state)
 389                 __drm_atomic_helper_connector_destroy_state(connector->state);
 390
 391         kfree(old_state);
 392         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 393
 394         if (!new_state)
 395                 return;
 396
 397         new_state->base.max_bpc = 8;
 398         new_state->base.max_requested_bpc = 8;
 399         new_state->output_format = VC4_HDMI_OUTPUT_RGB;
 400         drm_atomic_helper_connector_tv_reset(connector);
 401 }
 402
 403 static struct drm_connector_state *
 404 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 405 {
 406         struct drm_connector_state *conn_state = connector->state;
 407         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 408         struct vc4_hdmi_connector_state *new_state;
 409
 410         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 411         if (!new_state)
 412                 return NULL;
 413
 414         new_state->tmds_char_rate = vc4_state->tmds_char_rate;
 415         new_state->output_bpc = vc4_state->output_bpc;
 416         new_state->output_format = vc4_state->output_format;
 417         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 418
 419         return &new_state->base;
 420 }
 421
 422 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 423         .detect = vc4_hdmi_connector_detect,
 424         .fill_modes = drm_helper_probe_single_connector_modes,
 425         .reset = vc4_hdmi_connector_reset,
 426         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 427         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 428 };
 429
 430 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 431         .get_modes = vc4_hdmi_connector_get_modes,
 432         .atomic_check = vc4_hdmi_connector_atomic_check,
 433 };
 434
 435 static int vc4_hdmi_connector_init(struct drm_device *dev,
 436                                    struct vc4_hdmi *vc4_hdmi)
 437 {
 438         struct drm_connector *connector = &vc4_hdmi->connector;
 439         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
 440         int ret;
 441
 442         ret = drmm_connector_init(dev, connector,
 443                                   &vc4_hdmi_connector_funcs,
 444                                   DRM_MODE_CONNECTOR_HDMIA,
 445                                   vc4_hdmi->ddc);
 446         if (ret)
 447                 return ret;
 448
 449         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 450
 451         /*
 452          * Some of the properties below require access to state, like bpc.
 453          * Allocate some default initial connector state with our reset helper.
 454          */
 455         if (connector->funcs->reset)
 456                 connector->funcs->reset(connector);
 457
 458         /* Create and attach TV margin props to this connector. */
 459         ret = drm_mode_create_tv_margin_properties(dev);
 460         if (ret)
 461                 return ret;
 462
 463         ret = drm_mode_create_hdmi_colorspace_property(connector);
 464         if (ret)
 465                 return ret;
 466
 467         drm_connector_attach_colorspace_property(connector);
 468         drm_connector_attach_tv_margin_properties(connector);
 469         drm_connector_attach_max_bpc_property(connector, 8, 12);
 470
 471         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 472                              DRM_CONNECTOR_POLL_DISCONNECT);
 473
 474         connector->interlace_allowed = 1;
 475         connector->doublescan_allowed = 0;
 476         connector->stereo_allowed = 1;
 477
 478         if (vc4_hdmi->variant->supports_hdr)
 479                 drm_connector_attach_hdr_output_metadata_property(connector);
 480
 481         drm_connector_attach_encoder(connector, encoder);
 482
 483         return 0;
 484 }
 485
 486 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 487                                 enum hdmi_infoframe_type type,
 488                                 bool poll)
 489 {
 490         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 491         struct drm_device *drm = vc4_hdmi->connector.dev;
 492         u32 packet_id = type - 0x80;
 493         unsigned long flags;
 494         int ret = 0;
 495         int idx;
 496
 497         if (!drm_dev_enter(drm, &idx))
 498                 return -ENODEV;
 499
 500         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 501         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 502                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 503         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 504
 505         if (poll) {
 506                 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 507                                  BIT(packet_id)), 100);
 508         }
 509
 510         drm_dev_exit(idx);
 511         return ret;
 512 }
 513
 514 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 515                                      union hdmi_infoframe *frame)
 516 {
 517         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 518         struct drm_device *drm = vc4_hdmi->connector.dev;
 519         u32 packet_id = frame->any.type - 0x80;
 520         const struct vc4_hdmi_register *ram_packet_start =
 521                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 522         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 523         u32 packet_reg_next = ram_packet_start->offset +
 524                 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
 525         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 526                                                        ram_packet_start->reg);
 527         uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
 528         unsigned long flags;
 529         ssize_t len, i;
 530         int ret;
 531         int idx;
 532
 533         if (!drm_dev_enter(drm, &idx))
 534                 return;
 535
 536         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 537                     VC4_HDMI_RAM_PACKET_ENABLE),
 538                   "Packet RAM has to be on to store the packet.");
 539
 540         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 541         if (len < 0)
 542                 goto out;
 543
 544         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 545         if (ret) {
 546                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 547                 goto out;
 548         }
 549
 550         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 551
 552         for (i = 0; i < len; i += 7) {
 553                 writel(buffer[i + 0] << 0 |
 554                        buffer[i + 1] << 8 |
 555                        buffer[i + 2] << 16,
 556                        base + packet_reg);
 557                 packet_reg += 4;
 558
 559                 writel(buffer[i + 3] << 0 |
 560                        buffer[i + 4] << 8 |
 561                        buffer[i + 5] << 16 |
 562                        buffer[i + 6] << 24,
 563                        base + packet_reg);
 564                 packet_reg += 4;
 565         }
 566
 567         /*
 568          * clear remainder of packet ram as it's included in the
 569          * infoframe and triggers a checksum error on hdmi analyser
 570          */
 571         for (; packet_reg < packet_reg_next; packet_reg += 4)
 572                 writel(0, base + packet_reg);
 573
 574         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 575                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 576
 577         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 578
 579         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 580                         BIT(packet_id)), 100);
 581         if (ret)
 582                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 583
 584 out:
 585         drm_dev_exit(idx);
 586 }
 587
 588 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
 589                                               enum vc4_hdmi_output_format fmt)
 590 {
 591         switch (fmt) {
 592         case VC4_HDMI_OUTPUT_RGB:
 593                 frame->colorspace = HDMI_COLORSPACE_RGB;
 594                 break;
 595
 596         case VC4_HDMI_OUTPUT_YUV420:
 597                 frame->colorspace = HDMI_COLORSPACE_YUV420;
 598                 break;
 599
 600         case VC4_HDMI_OUTPUT_YUV422:
 601                 frame->colorspace = HDMI_COLORSPACE_YUV422;
 602                 break;
 603
 604         case VC4_HDMI_OUTPUT_YUV444:
 605                 frame->colorspace = HDMI_COLORSPACE_YUV444;
 606                 break;
 607
 608         default:
 609                 break;
 610         }
 611 }
 612
 613 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 614 {
 615         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 616         struct drm_connector *connector = &vc4_hdmi->connector;
 617         struct drm_connector_state *cstate = connector->state;
 618         struct vc4_hdmi_connector_state *vc4_state =
 619                 conn_state_to_vc4_hdmi_conn_state(cstate);
 620         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 621         union hdmi_infoframe frame;
 622         int ret;
 623
 624         lockdep_assert_held(&vc4_hdmi->mutex);
 625
 626         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 627                                                        connector, mode);
 628         if (ret < 0) {
 629                 DRM_ERROR("couldn't fill AVI infoframe\n");
 630                 return;
 631         }
 632
 633         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 634                                            connector, mode,
 635                                            vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ?
 636                                            HDMI_QUANTIZATION_RANGE_FULL :
 637                                            HDMI_QUANTIZATION_RANGE_LIMITED);
 638         drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
 639         vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format);
 640         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 641
 642         vc4_hdmi_write_infoframe(encoder, &frame);
 643 }
 644
 645 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 646 {
 647         union hdmi_infoframe frame;
 648         int ret;
 649
 650         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 651         if (ret < 0) {
 652                 DRM_ERROR("couldn't fill SPD infoframe\n");
 653                 return;
 654         }
 655
 656         frame.spd.sdi = HDMI_SPD_SDI_PC;
 657
 658         vc4_hdmi_write_infoframe(encoder, &frame);
 659 }
 660
 661 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 662 {
 663         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 664         struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
 665         union hdmi_infoframe frame;
 666
 667         memcpy(&frame.audio, audio, sizeof(*audio));
 668
 669         if (vc4_hdmi->packet_ram_enabled)
 670                 vc4_hdmi_write_infoframe(encoder, &frame);
 671 }
 672
 673 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 674 {
 675         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 676         struct drm_connector *connector = &vc4_hdmi->connector;
 677         struct drm_connector_state *conn_state = connector->state;
 678         union hdmi_infoframe frame;
 679
 680         lockdep_assert_held(&vc4_hdmi->mutex);
 681
 682         if (!vc4_hdmi->variant->supports_hdr)
 683                 return;
 684
 685         if (!conn_state->hdr_output_metadata)
 686                 return;
 687
 688         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 689                 return;
 690
 691         vc4_hdmi_write_infoframe(encoder, &frame);
 692 }
 693
 694 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 695 {
 696         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 697
 698         lockdep_assert_held(&vc4_hdmi->mutex);
 699
 700         vc4_hdmi_set_avi_infoframe(encoder);
 701         vc4_hdmi_set_spd_infoframe(encoder);
 702         /*
 703          * If audio was streaming, then we need to reenabled the audio
 704          * infoframe here during encoder_enable.
 705          */
 706         if (vc4_hdmi->audio.streaming)
 707                 vc4_hdmi_set_audio_infoframe(encoder);
 708
 709         vc4_hdmi_set_hdr_infoframe(encoder);
 710 }
 711
 712 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
 713                                          struct drm_display_mode *mode)
 714 {
 715         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 716         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 717
 718         lockdep_assert_held(&vc4_hdmi->mutex);
 719
 720         if (!display->is_hdmi)
 721                 return false;
 722
 723         if (!display->hdmi.scdc.supported ||
 724             !display->hdmi.scdc.scrambling.supported)
 725                 return false;
 726
 727         return true;
 728 }
 729
 730 #define SCRAMBLING_POLLING_DELAY_MS     1000
 731
 732 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 733 {
 734         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 735         struct drm_device *drm = vc4_hdmi->connector.dev;
 736         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 737         unsigned long flags;
 738         int idx;
 739
 740         lockdep_assert_held(&vc4_hdmi->mutex);
 741
 742         if (!vc4_hdmi_supports_scrambling(encoder, mode))
 743                 return;
 744
 745         if (!vc4_hdmi_mode_needs_scrambling(mode,
 746                                             vc4_hdmi->output_bpc,
 747                                             vc4_hdmi->output_format))
 748                 return;
 749
 750         if (!drm_dev_enter(drm, &idx))
 751                 return;
 752
 753         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 754         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 755
 756         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 757         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
 758                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 759         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 760
 761         drm_dev_exit(idx);
 762
 763         vc4_hdmi->scdc_enabled = true;
 764
 765         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 766                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 767 }
 768
 769 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
 770 {
 771         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 772         struct drm_device *drm = vc4_hdmi->connector.dev;
 773         unsigned long flags;
 774         int idx;
 775
 776         lockdep_assert_held(&vc4_hdmi->mutex);
 777
 778         if (!vc4_hdmi->scdc_enabled)
 779                 return;
 780
 781         vc4_hdmi->scdc_enabled = false;
 782
 783         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
 784                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
 785
 786         if (!drm_dev_enter(drm, &idx))
 787                 return;
 788
 789         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 790         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
 791                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 792         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 793
 794         drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
 795         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
 796
 797         drm_dev_exit(idx);
 798 }
 799
 800 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
 801 {
 802         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
 803                                                  struct vc4_hdmi,
 804                                                  scrambling_work);
 805
 806         if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
 807                 return;
 808
 809         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 810         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 811
 812         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 813                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 814 }
 815
 816 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 817                                                struct drm_atomic_state *state)
 818 {
 819         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 820         struct drm_device *drm = vc4_hdmi->connector.dev;
 821         unsigned long flags;
 822         int idx;
 823
 824         mutex_lock(&vc4_hdmi->mutex);
 825
 826         vc4_hdmi->packet_ram_enabled = false;
 827
 828         if (!drm_dev_enter(drm, &idx))
 829                 goto out;
 830
 831         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 832
 833         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 834
 835         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
 836
 837         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 838
 839         mdelay(1);
 840
 841         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 842         HDMI_WRITE(HDMI_VID_CTL,
 843                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 844         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 845
 846         vc4_hdmi_disable_scrambling(encoder);
 847
 848         drm_dev_exit(idx);
 849
 850 out:
 851         mutex_unlock(&vc4_hdmi->mutex);
 852 }
 853
 854 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
 855                                                  struct drm_atomic_state *state)
 856 {
 857         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 858         struct drm_device *drm = vc4_hdmi->connector.dev;
 859         unsigned long flags;
 860         int ret;
 861         int idx;
 862
 863         mutex_lock(&vc4_hdmi->mutex);
 864
 865         if (!drm_dev_enter(drm, &idx))
 866                 goto out;
 867
 868         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 869         HDMI_WRITE(HDMI_VID_CTL,
 870                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 871         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 872
 873         if (vc4_hdmi->variant->phy_disable)
 874                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 875
 876         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 877         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 878
 879         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 880         if (ret < 0)
 881                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 882
 883         drm_dev_exit(idx);
 884
 885 out:
 886         mutex_unlock(&vc4_hdmi->mutex);
 887 }
 888
 889 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
 890                                struct drm_connector_state *state,
 891                                const struct drm_display_mode *mode)
 892 {
 893         struct drm_device *drm = vc4_hdmi->connector.dev;
 894         unsigned long flags;
 895         u32 csc_ctl;
 896         int idx;
 897
 898         if (!drm_dev_enter(drm, &idx))
 899                 return;
 900
 901         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 902
 903         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 904                                 VC4_HD_CSC_CTL_ORDER);
 905
 906         if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) {
 907                 /* CEA VICs other than #1 requre limited range RGB
 908                  * output unless overridden by an AVI infoframe.
 909                  * Apply a colorspace conversion to squash 0-255 down
 910                  * to 16-235.  The matrix here is:
 911                  *
 912                  * [ 0      0      0.8594 16]
 913                  * [ 0      0.8594 0      16]
 914                  * [ 0.8594 0      0      16]
 915                  * [ 0      0      0       1]
 916                  */
 917                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 918                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 919                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 920                                          VC4_HD_CSC_CTL_MODE);
 921
 922                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 923                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 924                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 925                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 926                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 927                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 928         }
 929
 930         /* The RGB order applies even when CSC is disabled. */
 931         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 932
 933         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 934
 935         drm_dev_exit(idx);
 936 }
 937
 938 /*
 939  * If we need to output Full Range RGB, then use the unity matrix
 940  *
 941  * [ 1      0      0      0]
 942  * [ 0      1      0      0]
 943  * [ 0      0      1      0]
 944  *
 945  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 946  */
 947 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = {
 948         { 0x2000, 0x0000, 0x0000, 0x0000 },
 949         { 0x0000, 0x2000, 0x0000, 0x0000 },
 950         { 0x0000, 0x0000, 0x2000, 0x0000 },
 951 };
 952
 953 /*
 954  * CEA VICs other than #1 require limited range RGB output unless
 955  * overridden by an AVI infoframe. Apply a colorspace conversion to
 956  * squash 0-255 down to 16-235. The matrix here is:
 957  *
 958  * [ 0.8594 0      0      16]
 959  * [ 0      0.8594 0      16]
 960  * [ 0      0      0.8594 16]
 961  *
 962  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 963  */
 964 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = {
 965         { 0x1b80, 0x0000, 0x0000, 0x0400 },
 966         { 0x0000, 0x1b80, 0x0000, 0x0400 },
 967         { 0x0000, 0x0000, 0x1b80, 0x0400 },
 968 };
 969
 970 /*
 971  * Conversion between Full Range RGB and Full Range YUV422 using the
 972  * BT.709 Colorspace
 973  *
 974  *
 975  * [  0.181906  0.611804  0.061758  16  ]
 976  * [ -0.100268 -0.337232  0.437500  128 ]
 977  * [  0.437500 -0.397386 -0.040114  128 ]
 978  *
 979  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 980  */
 981 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709[3][4] = {
 982         { 0x05d2, 0x1394, 0x01fa, 0x0400 },
 983         { 0xfccc, 0xf536, 0x0e00, 0x2000 },
 984         { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
 985 };
 986
 987 /*
 988  * Conversion between Full Range RGB and Full Range YUV444 using the
 989  * BT.709 Colorspace
 990  *
 991  * [ -0.100268 -0.337232  0.437500  128 ]
 992  * [  0.437500 -0.397386 -0.040114  128 ]
 993  * [  0.181906  0.611804  0.061758  16  ]
 994  *
 995  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 996  */
 997 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709[3][4] = {
 998         { 0xfccc, 0xf536, 0x0e00, 0x2000 },
 999         { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1000         { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1001 };
1002
1003 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1004                                     const u16 coeffs[3][4])
1005 {
1006         lockdep_assert_held(&vc4_hdmi->hw_lock);
1007
1008         HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1009         HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1010         HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1011         HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1012         HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1013         HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1014 }
1015
1016 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1017                                struct drm_connector_state *state,
1018                                const struct drm_display_mode *mode)
1019 {
1020         struct drm_device *drm = vc4_hdmi->connector.dev;
1021         struct vc4_hdmi_connector_state *vc4_state =
1022                 conn_state_to_vc4_hdmi_conn_state(state);
1023         unsigned long flags;
1024         u32 if_cfg = 0;
1025         u32 if_xbar = 0x543210;
1026         u32 csc_chan_ctl = 0;
1027         u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1028                                                                VC5_MT_CP_CSC_CTL_MODE);
1029         int idx;
1030
1031         if (!drm_dev_enter(drm, &idx))
1032                 return;
1033
1034         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1035
1036         switch (vc4_state->output_format) {
1037         case VC4_HDMI_OUTPUT_YUV444:
1038                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709);
1039                 break;
1040
1041         case VC4_HDMI_OUTPUT_YUV422:
1042                 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1043                                          VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1044                         VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1045                         VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1046
1047                 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1048                                               VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1049
1050                 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1051                                         VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1052
1053                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709);
1054                 break;
1055
1056         case VC4_HDMI_OUTPUT_RGB:
1057                 if_xbar = 0x354021;
1058
1059                 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode))
1060                         vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb);
1061                 else
1062                         vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity);
1063                 break;
1064
1065         default:
1066                 break;
1067         }
1068
1069         HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1070         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1071         HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1072         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1073
1074         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1075
1076         drm_dev_exit(idx);
1077 }
1078
1079 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1080                                  struct drm_connector_state *state,
1081                                  struct drm_display_mode *mode)
1082 {
1083         struct drm_device *drm = vc4_hdmi->connector.dev;
1084         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1085         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1086         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1087         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1088         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1089                                    VC4_HDMI_VERTA_VSP) |
1090                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1091                                    VC4_HDMI_VERTA_VFP) |
1092                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1093         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1094                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1095                                    interlaced,
1096                                    VC4_HDMI_VERTB_VBP));
1097         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1098                           VC4_SET_FIELD(mode->crtc_vtotal -
1099                                         mode->crtc_vsync_end,
1100                                         VC4_HDMI_VERTB_VBP));
1101         unsigned long flags;
1102         u32 reg;
1103         int idx;
1104
1105         if (!drm_dev_enter(drm, &idx))
1106                 return;
1107
1108         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1109
1110         HDMI_WRITE(HDMI_HORZA,
1111                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1112                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1113                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1114                                  VC4_HDMI_HORZA_HAP));
1115
1116         HDMI_WRITE(HDMI_HORZB,
1117                    VC4_SET_FIELD((mode->htotal -
1118                                   mode->hsync_end) * pixel_rep,
1119                                  VC4_HDMI_HORZB_HBP) |
1120                    VC4_SET_FIELD((mode->hsync_end -
1121                                   mode->hsync_start) * pixel_rep,
1122                                  VC4_HDMI_HORZB_HSP) |
1123                    VC4_SET_FIELD((mode->hsync_start -
1124                                   mode->hdisplay) * pixel_rep,
1125                                  VC4_HDMI_HORZB_HFP));
1126
1127         HDMI_WRITE(HDMI_VERTA0, verta);
1128         HDMI_WRITE(HDMI_VERTA1, verta);
1129
1130         HDMI_WRITE(HDMI_VERTB0, vertb_even);
1131         HDMI_WRITE(HDMI_VERTB1, vertb);
1132
1133         reg = HDMI_READ(HDMI_MISC_CONTROL);
1134         reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1135         reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1136         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1137
1138         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1139
1140         drm_dev_exit(idx);
1141 }
1142
1143 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1144                                  struct drm_connector_state *state,
1145                                  struct drm_display_mode *mode)
1146 {
1147         struct drm_device *drm = vc4_hdmi->connector.dev;
1148         const struct vc4_hdmi_connector_state *vc4_state =
1149                 conn_state_to_vc4_hdmi_conn_state(state);
1150         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1151         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1152         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1153         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1154         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1155                                    VC5_HDMI_VERTA_VSP) |
1156                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1157                                    VC5_HDMI_VERTA_VFP) |
1158                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1159         u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1160                                    VC5_HDMI_VERTB_VSPO) |
1161                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
1162                                    VC4_HDMI_VERTB_VBP));
1163         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1164                           VC4_SET_FIELD(mode->crtc_vtotal -
1165                                         mode->crtc_vsync_end - interlaced,
1166                                         VC4_HDMI_VERTB_VBP));
1167         unsigned long flags;
1168         unsigned char gcp;
1169         bool gcp_en;
1170         u32 reg;
1171         int idx;
1172
1173         if (!drm_dev_enter(drm, &idx))
1174                 return;
1175
1176         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1177
1178         HDMI_WRITE(HDMI_HORZA,
1179                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1180                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1181                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1182                                  VC5_HDMI_HORZA_HAP) |
1183                    VC4_SET_FIELD((mode->hsync_start -
1184                                   mode->hdisplay) * pixel_rep,
1185                                  VC5_HDMI_HORZA_HFP));
1186
1187         HDMI_WRITE(HDMI_HORZB,
1188                    VC4_SET_FIELD((mode->htotal -
1189                                   mode->hsync_end) * pixel_rep,
1190                                  VC5_HDMI_HORZB_HBP) |
1191                    VC4_SET_FIELD((mode->hsync_end -
1192                                   mode->hsync_start) * pixel_rep,
1193                                  VC5_HDMI_HORZB_HSP));
1194
1195         HDMI_WRITE(HDMI_VERTA0, verta);
1196         HDMI_WRITE(HDMI_VERTA1, verta);
1197
1198         HDMI_WRITE(HDMI_VERTB0, vertb_even);
1199         HDMI_WRITE(HDMI_VERTB1, vertb);
1200
1201         switch (vc4_state->output_bpc) {
1202         case 12:
1203                 gcp = 6;
1204                 gcp_en = true;
1205                 break;
1206         case 10:
1207                 gcp = 5;
1208                 gcp_en = true;
1209                 break;
1210         case 8:
1211         default:
1212                 gcp = 4;
1213                 gcp_en = false;
1214                 break;
1215         }
1216
1217         /*
1218          * YCC422 is always 36-bit and not considered deep colour so
1219          * doesn't signal in GCP.
1220          */
1221         if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {
1222                 gcp = 4;
1223                 gcp_en = false;
1224         }
1225
1226         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1227         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1228                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1229         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1230                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1231         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1232
1233         reg = HDMI_READ(HDMI_GCP_WORD_1);
1234         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1235         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1236         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1237
1238         reg = HDMI_READ(HDMI_GCP_CONFIG);
1239         reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1240         reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
1241         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1242
1243         reg = HDMI_READ(HDMI_MISC_CONTROL);
1244         reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1245         reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1246         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1247
1248         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1249
1250         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1251
1252         drm_dev_exit(idx);
1253 }
1254
1255 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1256 {
1257         struct drm_device *drm = vc4_hdmi->connector.dev;
1258         unsigned long flags;
1259         u32 drift;
1260         int ret;
1261         int idx;
1262
1263         if (!drm_dev_enter(drm, &idx))
1264                 return;
1265
1266         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1267
1268         drift = HDMI_READ(HDMI_FIFO_CTL);
1269         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1270
1271         HDMI_WRITE(HDMI_FIFO_CTL,
1272                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1273         HDMI_WRITE(HDMI_FIFO_CTL,
1274                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1275
1276         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1277
1278         usleep_range(1000, 1100);
1279
1280         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1281
1282         HDMI_WRITE(HDMI_FIFO_CTL,
1283                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1284         HDMI_WRITE(HDMI_FIFO_CTL,
1285                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1286
1287         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1288
1289         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1290                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1291         WARN_ONCE(ret, "Timeout waiting for "
1292                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1293
1294         drm_dev_exit(idx);
1295 }
1296
1297 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1298                                                 struct drm_atomic_state *state)
1299 {
1300         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1301         struct drm_device *drm = vc4_hdmi->connector.dev;
1302         struct drm_connector *connector = &vc4_hdmi->connector;
1303         struct drm_connector_state *conn_state =
1304                 drm_atomic_get_new_connector_state(state, connector);
1305         struct vc4_hdmi_connector_state *vc4_conn_state =
1306                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1307         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1308         unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate;
1309         unsigned long bvb_rate, hsm_rate;
1310         unsigned long flags;
1311         int ret;
1312         int idx;
1313
1314         mutex_lock(&vc4_hdmi->mutex);
1315
1316         if (!drm_dev_enter(drm, &idx))
1317                 goto out;
1318
1319         /*
1320          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1321          * be faster than pixel clock, infinitesimally faster, tested in
1322          * simulation. Otherwise, exact value is unimportant for HDMI
1323          * operation." This conflicts with bcm2835's vc4 documentation, which
1324          * states HSM's clock has to be at least 108% of the pixel clock.
1325          *
1326          * Real life tests reveal that vc4's firmware statement holds up, and
1327          * users are able to use pixel clocks closer to HSM's, namely for
1328          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1329          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1330          * 162MHz.
1331          *
1332          * Additionally, the AXI clock needs to be at least 25% of
1333          * pixel clock, but HSM ends up being the limiting factor.
1334          */
1335         hsm_rate = max_t(unsigned long, 120000000, (tmds_char_rate / 100) * 101);
1336         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1337         if (ret) {
1338                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1339                 goto err_dev_exit;
1340         }
1341
1342         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1343         if (ret < 0) {
1344                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1345                 goto err_dev_exit;
1346         }
1347
1348         ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1349         if (ret) {
1350                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1351                 goto err_put_runtime_pm;
1352         }
1353
1354         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1355         if (ret) {
1356                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1357                 goto err_put_runtime_pm;
1358         }
1359
1360
1361         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1362
1363         if (tmds_char_rate > 297000000)
1364                 bvb_rate = 300000000;
1365         else if (tmds_char_rate > 148500000)
1366                 bvb_rate = 150000000;
1367         else
1368                 bvb_rate = 75000000;
1369
1370         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1371         if (ret) {
1372                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1373                 goto err_disable_pixel_clock;
1374         }
1375
1376         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1377         if (ret) {
1378                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1379                 goto err_disable_pixel_clock;
1380         }
1381
1382         if (vc4_hdmi->variant->phy_init)
1383                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1384
1385         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1386
1387         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1388                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1389                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1390                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1391
1392         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1393
1394         if (vc4_hdmi->variant->set_timings)
1395                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1396
1397         drm_dev_exit(idx);
1398
1399         mutex_unlock(&vc4_hdmi->mutex);
1400
1401         return;
1402
1403 err_disable_pixel_clock:
1404         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1405 err_put_runtime_pm:
1406         pm_runtime_put(&vc4_hdmi->pdev->dev);
1407 err_dev_exit:
1408         drm_dev_exit(idx);
1409 out:
1410         mutex_unlock(&vc4_hdmi->mutex);
1411         return;
1412 }
1413
1414 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1415                                              struct drm_atomic_state *state)
1416 {
1417         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1418         struct drm_device *drm = vc4_hdmi->connector.dev;
1419         struct drm_connector *connector = &vc4_hdmi->connector;
1420         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1421         struct drm_connector_state *conn_state =
1422                 drm_atomic_get_new_connector_state(state, connector);
1423         unsigned long flags;
1424         int idx;
1425
1426         mutex_lock(&vc4_hdmi->mutex);
1427
1428         if (!drm_dev_enter(drm, &idx))
1429                 return;
1430
1431         if (vc4_hdmi->variant->csc_setup)
1432                 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1433
1434         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1435         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1436         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1437
1438         drm_dev_exit(idx);
1439
1440         mutex_unlock(&vc4_hdmi->mutex);
1441 }
1442
1443 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1444                                               struct drm_atomic_state *state)
1445 {
1446         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1447         struct drm_device *drm = vc4_hdmi->connector.dev;
1448         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1449         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1450         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1451         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1452         unsigned long flags;
1453         int ret;
1454         int idx;
1455
1456         mutex_lock(&vc4_hdmi->mutex);
1457
1458         if (!drm_dev_enter(drm, &idx))
1459                 return;
1460
1461         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1462
1463         HDMI_WRITE(HDMI_VID_CTL,
1464                    VC4_HD_VID_CTL_ENABLE |
1465                    VC4_HD_VID_CTL_CLRRGB |
1466                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1467                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1468                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1469                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1470
1471         HDMI_WRITE(HDMI_VID_CTL,
1472                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1473
1474         if (display->is_hdmi) {
1475                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1476                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1477                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1478
1479                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1480
1481                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1482                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1483                 WARN_ONCE(ret, "Timeout waiting for "
1484                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1485         } else {
1486                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1487                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1488                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1489                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1490                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1491                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1492
1493                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1494
1495                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1496                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1497                 WARN_ONCE(ret, "Timeout waiting for "
1498                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1499         }
1500
1501         if (display->is_hdmi) {
1502                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1503
1504                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1505                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1506
1507                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1508                            VC4_HDMI_RAM_PACKET_ENABLE);
1509
1510                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1511                 vc4_hdmi->packet_ram_enabled = true;
1512
1513                 vc4_hdmi_set_infoframes(encoder);
1514         }
1515
1516         vc4_hdmi_recenter_fifo(vc4_hdmi);
1517         vc4_hdmi_enable_scrambling(encoder);
1518
1519         drm_dev_exit(idx);
1520         mutex_unlock(&vc4_hdmi->mutex);
1521 }
1522
1523 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1524                                              struct drm_crtc_state *crtc_state,
1525                                              struct drm_connector_state *conn_state)
1526 {
1527         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1528         struct vc4_hdmi_connector_state *vc4_state =
1529                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1530
1531         mutex_lock(&vc4_hdmi->mutex);
1532         drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1533                       &crtc_state->adjusted_mode);
1534         vc4_hdmi->output_bpc = vc4_state->output_bpc;
1535         vc4_hdmi->output_format = vc4_state->output_format;
1536         mutex_unlock(&vc4_hdmi->mutex);
1537 }
1538
1539 static bool
1540 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi,
1541                                   const struct drm_display_info *info,
1542                                   const struct drm_display_mode *mode,
1543                                   unsigned int format, unsigned int bpc)
1544 {
1545         struct drm_device *dev = vc4_hdmi->connector.dev;
1546         u8 vic = drm_match_cea_mode(mode);
1547
1548         if (vic == 1 && bpc != 8) {
1549                 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc);
1550                 return false;
1551         }
1552
1553         if (!info->is_hdmi &&
1554             (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) {
1555                 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n");
1556                 return false;
1557         }
1558
1559         switch (format) {
1560         case VC4_HDMI_OUTPUT_RGB:
1561                 drm_dbg(dev, "RGB Format, checking the constraints.\n");
1562
1563                 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444))
1564                         return false;
1565
1566                 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1567                         drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1568                         return false;
1569                 }
1570
1571                 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1572                         drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1573                         return false;
1574                 }
1575
1576                 drm_dbg(dev, "RGB format supported in that configuration.\n");
1577
1578                 return true;
1579
1580         case VC4_HDMI_OUTPUT_YUV422:
1581                 drm_dbg(dev, "YUV422 format, checking the constraints.\n");
1582
1583                 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) {
1584                         drm_dbg(dev, "Sink doesn't support YUV422.\n");
1585                         return false;
1586                 }
1587
1588                 if (bpc != 12) {
1589                         drm_dbg(dev, "YUV422 only supports 12 bpc.\n");
1590                         return false;
1591                 }
1592
1593                 drm_dbg(dev, "YUV422 format supported in that configuration.\n");
1594
1595                 return true;
1596
1597         case VC4_HDMI_OUTPUT_YUV444:
1598                 drm_dbg(dev, "YUV444 format, checking the constraints.\n");
1599
1600                 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) {
1601                         drm_dbg(dev, "Sink doesn't support YUV444.\n");
1602                         return false;
1603                 }
1604
1605                 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1606                         drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1607                         return false;
1608                 }
1609
1610                 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1611                         drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1612                         return false;
1613                 }
1614
1615                 drm_dbg(dev, "YUV444 format supported in that configuration.\n");
1616
1617                 return true;
1618         }
1619
1620         return false;
1621 }
1622
1623 static enum drm_mode_status
1624 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
1625                              unsigned long long clock)
1626 {
1627         const struct drm_connector *connector = &vc4_hdmi->connector;
1628         const struct drm_display_info *info = &connector->display_info;
1629
1630         if (clock > vc4_hdmi->variant->max_pixel_clock)
1631                 return MODE_CLOCK_HIGH;
1632
1633         if (vc4_hdmi->disable_4kp60 && clock > HDMI_14_MAX_TMDS_CLK)
1634                 return MODE_CLOCK_HIGH;
1635
1636         if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000))
1637                 return MODE_CLOCK_HIGH;
1638
1639         return MODE_OK;
1640 }
1641
1642 static unsigned long long
1643 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
1644                                     unsigned int bpc,
1645                                     enum vc4_hdmi_output_format fmt)
1646 {
1647         unsigned long long clock = mode->clock * 1000ULL;
1648
1649         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1650                 clock = clock * 2;
1651
1652         if (fmt == VC4_HDMI_OUTPUT_YUV422)
1653                 bpc = 8;
1654
1655         clock = clock * bpc;
1656         do_div(clock, 8);
1657
1658         return clock;
1659 }
1660
1661 static int
1662 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
1663                                struct vc4_hdmi_connector_state *vc4_state,
1664                                const struct drm_display_mode *mode,
1665                                unsigned int bpc, unsigned int fmt)
1666 {
1667         unsigned long long clock;
1668
1669         clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
1670         if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, clock) != MODE_OK)
1671                 return -EINVAL;
1672
1673         vc4_state->tmds_char_rate = clock;
1674
1675         return 0;
1676 }
1677
1678 static int
1679 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi,
1680                                 struct vc4_hdmi_connector_state *vc4_state,
1681                                 const struct drm_display_mode *mode,
1682                                 unsigned int bpc)
1683 {
1684         struct drm_device *dev = vc4_hdmi->connector.dev;
1685         const struct drm_connector *connector = &vc4_hdmi->connector;
1686         const struct drm_display_info *info = &connector->display_info;
1687         unsigned int format;
1688
1689         drm_dbg(dev, "Trying with an RGB output\n");
1690
1691         format = VC4_HDMI_OUTPUT_RGB;
1692         if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1693                 int ret;
1694
1695                 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1696                                                      mode, bpc, format);
1697                 if (!ret) {
1698                         vc4_state->output_format = format;
1699                         return 0;
1700                 }
1701         }
1702
1703         drm_dbg(dev, "Failed, Trying with an YUV422 output\n");
1704
1705         format = VC4_HDMI_OUTPUT_YUV422;
1706         if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1707                 int ret;
1708
1709                 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1710                                                      mode, bpc, format);
1711                 if (!ret) {
1712                         vc4_state->output_format = format;
1713                         return 0;
1714                 }
1715         }
1716
1717         drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n");
1718
1719         return -EINVAL;
1720 }
1721
1722 static int
1723 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi,
1724                                 struct vc4_hdmi_connector_state *vc4_state,
1725                                 const struct drm_display_mode *mode)
1726 {
1727         struct drm_device *dev = vc4_hdmi->connector.dev;
1728         struct drm_connector_state *conn_state = &vc4_state->base;
1729         unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12);
1730         unsigned int bpc;
1731         int ret;
1732
1733         for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
1734                 drm_dbg(dev, "Trying with a %d bpc output\n", bpc);
1735
1736                 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state,
1737                                                       mode, bpc);
1738                 if (ret)
1739                         continue;
1740
1741                 vc4_state->output_bpc = bpc;
1742
1743                 drm_dbg(dev,
1744                         "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n",
1745                         mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
1746                         vc4_state->output_bpc,
1747                         vc4_hdmi_output_fmt_str(vc4_state->output_format),
1748                         vc4_state->tmds_char_rate);
1749
1750                 break;
1751         }
1752
1753         return ret;
1754 }
1755
1756 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
1757 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
1758
1759 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1760                                          struct drm_crtc_state *crtc_state,
1761                                          struct drm_connector_state *conn_state)
1762 {
1763         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1764         struct drm_connector *connector = &vc4_hdmi->connector;
1765         struct drm_connector_state *old_conn_state =
1766                 drm_atomic_get_old_connector_state(conn_state->state, connector);
1767         struct vc4_hdmi_connector_state *old_vc4_state =
1768                 conn_state_to_vc4_hdmi_conn_state(old_conn_state);
1769         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1770         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1771         unsigned long long tmds_char_rate = mode->clock * 1000;
1772         unsigned long long tmds_bit_rate;
1773         int ret;
1774
1775         if (vc4_hdmi->variant->unsupported_odd_h_timings) {
1776                 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1777                         /* Only try to fixup DBLCLK modes to get 480i and 576i
1778                          * working.
1779                          * A generic solution for all modes with odd horizontal
1780                          * timing values seems impossible based on trying to
1781                          * solve it for 1366x768 monitors.
1782                          */
1783                         if ((mode->hsync_start - mode->hdisplay) & 1)
1784                                 mode->hsync_start--;
1785                         if ((mode->hsync_end - mode->hsync_start) & 1)
1786                                 mode->hsync_end--;
1787                 }
1788
1789                 /* Now check whether we still have odd values remaining */
1790                 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1791                     (mode->hsync_end % 2) || (mode->htotal % 2))
1792                         return -EINVAL;
1793         }
1794
1795         /*
1796          * The 1440p@60 pixel rate is in the same range than the first
1797          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1798          * bandwidth). Slightly lower the frequency to bring it out of
1799          * the WiFi range.
1800          */
1801         tmds_bit_rate = tmds_char_rate * 10;
1802         if (vc4_hdmi->disable_wifi_frequencies &&
1803             (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1804              tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1805                 mode->clock = 238560;
1806                 tmds_char_rate = mode->clock * 1000;
1807         }
1808
1809         ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode);
1810         if (ret)
1811                 return ret;
1812
1813         /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */
1814         if (vc4_state->output_bpc != old_vc4_state->output_bpc ||
1815             vc4_state->output_format != old_vc4_state->output_format)
1816                 crtc_state->mode_changed = true;
1817
1818         return 0;
1819 }
1820
1821 static enum drm_mode_status
1822 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1823                             const struct drm_display_mode *mode)
1824 {
1825         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1826
1827         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1828             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1829             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1830              (mode->hsync_end % 2) || (mode->htotal % 2)))
1831                 return MODE_H_ILLEGAL;
1832
1833         return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode->clock * 1000);
1834 }
1835
1836 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1837         .atomic_check = vc4_hdmi_encoder_atomic_check,
1838         .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1839         .mode_valid = vc4_hdmi_encoder_mode_valid,
1840 };
1841
1842 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1843 {
1844         int i;
1845         u32 channel_map = 0;
1846
1847         for (i = 0; i < 8; i++) {
1848                 if (channel_mask & BIT(i))
1849                         channel_map |= i << (3 * i);
1850         }
1851         return channel_map;
1852 }
1853
1854 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1855 {
1856         int i;
1857         u32 channel_map = 0;
1858
1859         for (i = 0; i < 8; i++) {
1860                 if (channel_mask & BIT(i))
1861                         channel_map |= i << (4 * i);
1862         }
1863         return channel_map;
1864 }
1865
1866 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
1867 {
1868         struct drm_device *drm = vc4_hdmi->connector.dev;
1869         unsigned long flags;
1870         u32 hotplug;
1871         int idx;
1872
1873         if (!drm_dev_enter(drm, &idx))
1874                 return false;
1875
1876         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1877         hotplug = HDMI_READ(HDMI_HOTPLUG);
1878         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1879
1880         drm_dev_exit(idx);
1881
1882         return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
1883 }
1884
1885 /* HDMI audio codec callbacks */
1886 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1887                                          unsigned int samplerate)
1888 {
1889         struct drm_device *drm = vc4_hdmi->connector.dev;
1890         u32 hsm_clock;
1891         unsigned long flags;
1892         unsigned long n, m;
1893         int idx;
1894
1895         if (!drm_dev_enter(drm, &idx))
1896                 return;
1897
1898         hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1899         rational_best_approximation(hsm_clock, samplerate,
1900                                     VC4_HD_MAI_SMP_N_MASK >>
1901                                     VC4_HD_MAI_SMP_N_SHIFT,
1902                                     (VC4_HD_MAI_SMP_M_MASK >>
1903                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
1904                                     &n, &m);
1905
1906         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1907         HDMI_WRITE(HDMI_MAI_SMP,
1908                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1909                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1910         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1911
1912         drm_dev_exit(idx);
1913 }
1914
1915 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1916 {
1917         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1918         u32 n, cts;
1919         u64 tmp;
1920
1921         lockdep_assert_held(&vc4_hdmi->mutex);
1922         lockdep_assert_held(&vc4_hdmi->hw_lock);
1923
1924         n = 128 * samplerate / 1000;
1925         tmp = (u64)(mode->clock * 1000) * n;
1926         do_div(tmp, 128 * samplerate);
1927         cts = tmp;
1928
1929         HDMI_WRITE(HDMI_CRP_CFG,
1930                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1931                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1932
1933         /*
1934          * We could get slightly more accurate clocks in some cases by
1935          * providing a CTS_1 value.  The two CTS values are alternated
1936          * between based on the period fields
1937          */
1938         HDMI_WRITE(HDMI_CTS_0, cts);
1939         HDMI_WRITE(HDMI_CTS_1, cts);
1940 }
1941
1942 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1943 {
1944         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1945
1946         return snd_soc_card_get_drvdata(card);
1947 }
1948
1949 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
1950 {
1951         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1952
1953         lockdep_assert_held(&vc4_hdmi->mutex);
1954
1955         /*
1956          * If the encoder is currently in DVI mode, treat the codec DAI
1957          * as missing.
1958          */
1959         if (!display->is_hdmi)
1960                 return false;
1961
1962         return true;
1963 }
1964
1965 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1966 {
1967         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1968         struct drm_device *drm = vc4_hdmi->connector.dev;
1969         unsigned long flags;
1970         int ret = 0;
1971         int idx;
1972
1973         mutex_lock(&vc4_hdmi->mutex);
1974
1975         if (!drm_dev_enter(drm, &idx)) {
1976                 ret = -ENODEV;
1977                 goto out;
1978         }
1979
1980         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1981                 ret = -ENODEV;
1982                 goto out_dev_exit;
1983         }
1984
1985         vc4_hdmi->audio.streaming = true;
1986
1987         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1988         HDMI_WRITE(HDMI_MAI_CTL,
1989                    VC4_HD_MAI_CTL_RESET |
1990                    VC4_HD_MAI_CTL_FLUSH |
1991                    VC4_HD_MAI_CTL_DLATE |
1992                    VC4_HD_MAI_CTL_ERRORE |
1993                    VC4_HD_MAI_CTL_ERRORF);
1994         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1995
1996         if (vc4_hdmi->variant->phy_rng_enable)
1997                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1998
1999 out_dev_exit:
2000         drm_dev_exit(idx);
2001 out:
2002         mutex_unlock(&vc4_hdmi->mutex);
2003
2004         return ret;
2005 }
2006
2007 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
2008 {
2009         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2010         struct device *dev = &vc4_hdmi->pdev->dev;
2011         unsigned long flags;
2012         int ret;
2013
2014         lockdep_assert_held(&vc4_hdmi->mutex);
2015
2016         vc4_hdmi->audio.streaming = false;
2017         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
2018         if (ret)
2019                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
2020
2021         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2022
2023         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
2024         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
2025         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
2026
2027         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2028 }
2029
2030 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
2031 {
2032         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2033         struct drm_device *drm = vc4_hdmi->connector.dev;
2034         unsigned long flags;
2035         int idx;
2036
2037         mutex_lock(&vc4_hdmi->mutex);
2038
2039         if (!drm_dev_enter(drm, &idx))
2040                 goto out;
2041
2042         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2043
2044         HDMI_WRITE(HDMI_MAI_CTL,
2045                    VC4_HD_MAI_CTL_DLATE |
2046                    VC4_HD_MAI_CTL_ERRORE |
2047                    VC4_HD_MAI_CTL_ERRORF);
2048
2049         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2050
2051         if (vc4_hdmi->variant->phy_rng_disable)
2052                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
2053
2054         vc4_hdmi->audio.streaming = false;
2055         vc4_hdmi_audio_reset(vc4_hdmi);
2056
2057         drm_dev_exit(idx);
2058
2059 out:
2060         mutex_unlock(&vc4_hdmi->mutex);
2061 }
2062
2063 static int sample_rate_to_mai_fmt(int samplerate)
2064 {
2065         switch (samplerate) {
2066         case 8000:
2067                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
2068         case 11025:
2069                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
2070         case 12000:
2071                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
2072         case 16000:
2073                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
2074         case 22050:
2075                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
2076         case 24000:
2077                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
2078         case 32000:
2079                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
2080         case 44100:
2081                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
2082         case 48000:
2083                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
2084         case 64000:
2085                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
2086         case 88200:
2087                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
2088         case 96000:
2089                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
2090         case 128000:
2091                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2092         case 176400:
2093                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2094         case 192000:
2095                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2096         default:
2097                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2098         }
2099 }
2100
2101 /* HDMI audio codec callbacks */
2102 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
2103                                   struct hdmi_codec_daifmt *daifmt,
2104                                   struct hdmi_codec_params *params)
2105 {
2106         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2107         struct drm_device *drm = vc4_hdmi->connector.dev;
2108         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2109         unsigned int sample_rate = params->sample_rate;
2110         unsigned int channels = params->channels;
2111         unsigned long flags;
2112         u32 audio_packet_config, channel_mask;
2113         u32 channel_map;
2114         u32 mai_audio_format;
2115         u32 mai_sample_rate;
2116         int ret = 0;
2117         int idx;
2118
2119         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2120                 sample_rate, params->sample_width, channels);
2121
2122         mutex_lock(&vc4_hdmi->mutex);
2123
2124         if (!drm_dev_enter(drm, &idx)) {
2125                 ret = -ENODEV;
2126                 goto out;
2127         }
2128
2129         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2130                 ret = -EINVAL;
2131                 goto out_dev_exit;
2132         }
2133
2134         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2135
2136         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2137         HDMI_WRITE(HDMI_MAI_CTL,
2138                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2139                    VC4_HD_MAI_CTL_WHOLSMP |
2140                    VC4_HD_MAI_CTL_CHALIGN |
2141                    VC4_HD_MAI_CTL_ENABLE);
2142
2143         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2144         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2145             params->channels == 8)
2146                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2147         else
2148                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2149         HDMI_WRITE(HDMI_MAI_FMT,
2150                    VC4_SET_FIELD(mai_sample_rate,
2151                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2152                    VC4_SET_FIELD(mai_audio_format,
2153                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2154
2155         /* The B frame identifier should match the value used by alsa-lib (8) */
2156         audio_packet_config =
2157                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2158                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2159                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2160
2161         channel_mask = GENMASK(channels - 1, 0);
2162         audio_packet_config |= VC4_SET_FIELD(channel_mask,
2163                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2164
2165         /* Set the MAI threshold */
2166         HDMI_WRITE(HDMI_MAI_THR,
2167                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
2168                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
2169                    VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
2170                    VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
2171
2172         HDMI_WRITE(HDMI_MAI_CONFIG,
2173                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2174                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2175                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2176
2177         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2178         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2179         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2180
2181         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2182
2183         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2184
2185         memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
2186         vc4_hdmi_set_audio_infoframe(encoder);
2187
2188 out_dev_exit:
2189         drm_dev_exit(idx);
2190 out:
2191         mutex_unlock(&vc4_hdmi->mutex);
2192
2193         return ret;
2194 }
2195
2196 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2197         .name = "vc4-hdmi-cpu-dai-component",
2198 };
2199
2200 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2201 {
2202         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2203
2204         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2205
2206         return 0;
2207 }
2208
2209 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2210         .name = "vc4-hdmi-cpu-dai",
2211         .probe  = vc4_hdmi_audio_cpu_dai_probe,
2212         .playback = {
2213                 .stream_name = "Playback",
2214                 .channels_min = 1,
2215                 .channels_max = 8,
2216                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2217                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2218                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2219                          SNDRV_PCM_RATE_192000,
2220                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2221         },
2222 };
2223
2224 static const struct snd_dmaengine_pcm_config pcm_conf = {
2225         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2226         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2227 };
2228
2229 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
2230                                   uint8_t *buf, size_t len)
2231 {
2232         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2233         struct drm_connector *connector = &vc4_hdmi->connector;
2234
2235         mutex_lock(&vc4_hdmi->mutex);
2236         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2237         mutex_unlock(&vc4_hdmi->mutex);
2238
2239         return 0;
2240 }
2241
2242 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
2243         .get_eld = vc4_hdmi_audio_get_eld,
2244         .prepare = vc4_hdmi_audio_prepare,
2245         .audio_shutdown = vc4_hdmi_audio_shutdown,
2246         .audio_startup = vc4_hdmi_audio_startup,
2247 };
2248
2249 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
2250         .ops = &vc4_hdmi_codec_ops,
2251         .max_i2s_channels = 8,
2252         .i2s = 1,
2253 };
2254
2255 static void vc4_hdmi_audio_codec_release(void *ptr)
2256 {
2257         struct vc4_hdmi *vc4_hdmi = ptr;
2258
2259         platform_device_unregister(vc4_hdmi->audio.codec_pdev);
2260         vc4_hdmi->audio.codec_pdev = NULL;
2261 }
2262
2263 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2264 {
2265         const struct vc4_hdmi_register *mai_data =
2266                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2267         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2268         struct snd_soc_card *card = &vc4_hdmi->audio.card;
2269         struct device *dev = &vc4_hdmi->pdev->dev;
2270         struct platform_device *codec_pdev;
2271         const __be32 *addr;
2272         int index, len;
2273         int ret;
2274
2275         /*
2276          * ASoC makes it a bit hard to retrieve a pointer to the
2277          * vc4_hdmi structure. Registering the card will overwrite our
2278          * device drvdata with a pointer to the snd_soc_card structure,
2279          * which can then be used to retrieve whatever drvdata we want
2280          * to associate.
2281          *
2282          * However, that doesn't fly in the case where we wouldn't
2283          * register an ASoC card (because of an old DT that is missing
2284          * the dmas properties for example), then the card isn't
2285          * registered and the device drvdata wouldn't be set.
2286          *
2287          * We can deal with both cases by making sure a snd_soc_card
2288          * pointer and a vc4_hdmi structure are pointing to the same
2289          * memory address, so we can treat them indistinctly without any
2290          * issue.
2291          */
2292         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2293         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2294
2295         if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
2296                 dev_warn(dev,
2297                          "'dmas' DT property is missing or empty, no HDMI audio\n");
2298                 return 0;
2299         }
2300
2301         if (mai_data->reg != VC4_HD) {
2302                 WARN_ONCE(true, "MAI isn't in the HD block\n");
2303                 return -EINVAL;
2304         }
2305
2306         /*
2307          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2308          * the bus address specified in the DT, because the physical address
2309          * (the one returned by platform_get_resource()) is not appropriate
2310          * for DMA transfers.
2311          * This VC/MMU should probably be exposed to avoid this kind of hacks.
2312          */
2313         index = of_property_match_string(dev->of_node, "reg-names", "hd");
2314         /* Before BCM2711, we don't have a named register range */
2315         if (index < 0)
2316                 index = 1;
2317
2318         addr = of_get_address(dev->of_node, index, NULL, NULL);
2319
2320         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2321         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2322         vc4_hdmi->audio.dma_data.maxburst = 2;
2323
2324         /*
2325          * NOTE: Strictly speaking, we should probably use a DRM-managed
2326          * registration there to avoid removing all the audio components
2327          * by the time the driver doesn't have any user anymore.
2328          *
2329          * However, the ASoC core uses a number of devm_kzalloc calls
2330          * when registering, even when using non-device-managed
2331          * functions (such as in snd_soc_register_component()).
2332          *
2333          * If we call snd_soc_unregister_component() in a DRM-managed
2334          * action, the device-managed actions have already been executed
2335          * and thus we would access memory that has been freed.
2336          *
2337          * Using device-managed hooks here probably leaves us open to a
2338          * bunch of issues if userspace still has a handle on the ALSA
2339          * device when the device is removed. However, this is mitigated
2340          * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2341          * path to prevent the access to the device resources if it
2342          * isn't there anymore.
2343          *
2344          * Then, the vc4_hdmi structure is DRM-managed and thus only
2345          * freed whenever the last user has closed the DRM device file.
2346          * It should thus outlive ALSA in most situations.
2347          */
2348         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2349         if (ret) {
2350                 dev_err(dev, "Could not register PCM component: %d\n", ret);
2351                 return ret;
2352         }
2353
2354         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2355                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
2356         if (ret) {
2357                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2358                 return ret;
2359         }
2360
2361         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
2362                                                    PLATFORM_DEVID_AUTO,
2363                                                    &vc4_hdmi_codec_pdata,
2364                                                    sizeof(vc4_hdmi_codec_pdata));
2365         if (IS_ERR(codec_pdev)) {
2366                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
2367                 return PTR_ERR(codec_pdev);
2368         }
2369         vc4_hdmi->audio.codec_pdev = codec_pdev;
2370
2371         ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi);
2372         if (ret)
2373                 return ret;
2374
2375         dai_link->cpus          = &vc4_hdmi->audio.cpu;
2376         dai_link->codecs        = &vc4_hdmi->audio.codec;
2377         dai_link->platforms     = &vc4_hdmi->audio.platform;
2378
2379         dai_link->num_cpus      = 1;
2380         dai_link->num_codecs    = 1;
2381         dai_link->num_platforms = 1;
2382
2383         dai_link->name = "MAI";
2384         dai_link->stream_name = "MAI PCM";
2385         dai_link->codecs->dai_name = "i2s-hifi";
2386         dai_link->cpus->dai_name = dev_name(dev);
2387         dai_link->codecs->name = dev_name(&codec_pdev->dev);
2388         dai_link->platforms->name = dev_name(dev);
2389
2390         card->dai_link = dai_link;
2391         card->num_links = 1;
2392         card->name = vc4_hdmi->variant->card_name;
2393         card->driver_name = "vc4-hdmi";
2394         card->dev = dev;
2395         card->owner = THIS_MODULE;
2396
2397         /*
2398          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2399          * stores a pointer to the snd card object in dev->driver_data. This
2400          * means we cannot use it for something else. The hdmi back-pointer is
2401          * now stored in card->drvdata and should be retrieved with
2402          * snd_soc_card_get_drvdata() if needed.
2403          */
2404         snd_soc_card_set_drvdata(card, vc4_hdmi);
2405         ret = devm_snd_soc_register_card(dev, card);
2406         if (ret)
2407                 dev_err_probe(dev, ret, "Could not register sound card\n");
2408
2409         return ret;
2410
2411 }
2412
2413 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2414 {
2415         struct vc4_hdmi *vc4_hdmi = priv;
2416         struct drm_connector *connector = &vc4_hdmi->connector;
2417         struct drm_device *dev = connector->dev;
2418
2419         if (dev && dev->registered)
2420                 drm_connector_helper_hpd_irq_event(connector);
2421
2422         return IRQ_HANDLED;
2423 }
2424
2425 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2426 {
2427         struct drm_connector *connector = &vc4_hdmi->connector;
2428         struct platform_device *pdev = vc4_hdmi->pdev;
2429         int ret;
2430
2431         if (vc4_hdmi->variant->external_irq_controller) {
2432                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2433                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2434
2435                 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2436                                                 NULL,
2437                                                 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2438                                                 "vc4 hdmi hpd connected", vc4_hdmi);
2439                 if (ret)
2440                         return ret;
2441
2442                 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2443                                                 NULL,
2444                                                 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2445                                                 "vc4 hdmi hpd disconnected", vc4_hdmi);
2446                 if (ret)
2447                         return ret;
2448
2449                 connector->polled = DRM_CONNECTOR_POLL_HPD;
2450         }
2451
2452         return 0;
2453 }
2454
2455 #ifdef CONFIG_DRM_VC4_HDMI_CEC
2456 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2457 {
2458         struct vc4_hdmi *vc4_hdmi = priv;
2459
2460         if (vc4_hdmi->cec_rx_msg.len)
2461                 cec_received_msg(vc4_hdmi->cec_adap,
2462                                  &vc4_hdmi->cec_rx_msg);
2463
2464         return IRQ_HANDLED;
2465 }
2466
2467 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2468 {
2469         struct vc4_hdmi *vc4_hdmi = priv;
2470
2471         if (vc4_hdmi->cec_tx_ok) {
2472                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2473                                   0, 0, 0, 0);
2474         } else {
2475                 /*
2476                  * This CEC implementation makes 1 retry, so if we
2477                  * get a NACK, then that means it made 2 attempts.
2478                  */
2479                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2480                                   0, 2, 0, 0);
2481         }
2482         return IRQ_HANDLED;
2483 }
2484
2485 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2486 {
2487         struct vc4_hdmi *vc4_hdmi = priv;
2488         irqreturn_t ret;
2489
2490         if (vc4_hdmi->cec_irq_was_rx)
2491                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2492         else
2493                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2494
2495         return ret;
2496 }
2497
2498 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2499 {
2500         struct drm_device *dev = vc4_hdmi->connector.dev;
2501         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2502         unsigned int i;
2503
2504         lockdep_assert_held(&vc4_hdmi->hw_lock);
2505
2506         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2507                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2508
2509         if (msg->len > 16) {
2510                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2511                 return;
2512         }
2513
2514         for (i = 0; i < msg->len; i += 4) {
2515                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2516
2517                 msg->msg[i] = val & 0xff;
2518                 msg->msg[i + 1] = (val >> 8) & 0xff;
2519                 msg->msg[i + 2] = (val >> 16) & 0xff;
2520                 msg->msg[i + 3] = (val >> 24) & 0xff;
2521         }
2522 }
2523
2524 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2525 {
2526         u32 cntrl1;
2527
2528         /*
2529          * We don't need to protect the register access using
2530          * drm_dev_enter() there because the interrupt handler lifetime
2531          * is tied to the device itself, and not to the DRM device.
2532          *
2533          * So when the device will be gone, one of the first thing we
2534          * will be doing will be to unregister the interrupt handler,
2535          * and then unregister the DRM device. drm_dev_enter() would
2536          * thus always succeed if we are here.
2537          */
2538
2539         lockdep_assert_held(&vc4_hdmi->hw_lock);
2540
2541         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2542         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2543         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2544         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2545
2546         return IRQ_WAKE_THREAD;
2547 }
2548
2549 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2550 {
2551         struct vc4_hdmi *vc4_hdmi = priv;
2552         irqreturn_t ret;
2553
2554         spin_lock(&vc4_hdmi->hw_lock);
2555         ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2556         spin_unlock(&vc4_hdmi->hw_lock);
2557
2558         return ret;
2559 }
2560
2561 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2562 {
2563         u32 cntrl1;
2564
2565         lockdep_assert_held(&vc4_hdmi->hw_lock);
2566
2567         /*
2568          * We don't need to protect the register access using
2569          * drm_dev_enter() there because the interrupt handler lifetime
2570          * is tied to the device itself, and not to the DRM device.
2571          *
2572          * So when the device will be gone, one of the first thing we
2573          * will be doing will be to unregister the interrupt handler,
2574          * and then unregister the DRM device. drm_dev_enter() would
2575          * thus always succeed if we are here.
2576          */
2577
2578         vc4_hdmi->cec_rx_msg.len = 0;
2579         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2580         vc4_cec_read_msg(vc4_hdmi, cntrl1);
2581         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2582         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2583         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2584
2585         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2586
2587         return IRQ_WAKE_THREAD;
2588 }
2589
2590 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
2591 {
2592         struct vc4_hdmi *vc4_hdmi = priv;
2593         irqreturn_t ret;
2594
2595         spin_lock(&vc4_hdmi->hw_lock);
2596         ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2597         spin_unlock(&vc4_hdmi->hw_lock);
2598
2599         return ret;
2600 }
2601
2602 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2603 {
2604         struct vc4_hdmi *vc4_hdmi = priv;
2605         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2606         irqreturn_t ret;
2607         u32 cntrl5;
2608
2609         /*
2610          * We don't need to protect the register access using
2611          * drm_dev_enter() there because the interrupt handler lifetime
2612          * is tied to the device itself, and not to the DRM device.
2613          *
2614          * So when the device will be gone, one of the first thing we
2615          * will be doing will be to unregister the interrupt handler,
2616          * and then unregister the DRM device. drm_dev_enter() would
2617          * thus always succeed if we are here.
2618          */
2619
2620         if (!(stat & VC4_HDMI_CPU_CEC))
2621                 return IRQ_NONE;
2622
2623         spin_lock(&vc4_hdmi->hw_lock);
2624         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2625         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2626         if (vc4_hdmi->cec_irq_was_rx)
2627                 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2628         else
2629                 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2630
2631         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2632         spin_unlock(&vc4_hdmi->hw_lock);
2633
2634         return ret;
2635 }
2636
2637 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2638 {
2639         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2640         struct drm_device *drm = vc4_hdmi->connector.dev;
2641         /* clock period in microseconds */
2642         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2643         unsigned long flags;
2644         u32 val;
2645         int ret;
2646         int idx;
2647
2648         /*
2649          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2650          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2651          * .detect or .get_modes might call .adap_enable, which leads to this
2652          * function being called with that mutex held.
2653          *
2654          * Concurrency is not an issue for the moment since we don't share any
2655          * state with KMS, so we can ignore the lock for now, but we need to
2656          * keep it in mind if we were to change that assumption.
2657          */
2658
2659         if (!drm_dev_enter(drm, &idx))
2660                 /*
2661                  * We can't return an error code, because the CEC
2662                  * framework will emit WARN_ON messages at unbind
2663                  * otherwise.
2664                  */
2665                 return 0;
2666
2667         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2668         if (ret) {
2669                 drm_dev_exit(idx);
2670                 return ret;
2671         }
2672
2673         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2674
2675         val = HDMI_READ(HDMI_CEC_CNTRL_5);
2676         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2677                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2678                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2679         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2680                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2681
2682         HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2683                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2684         HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2685         HDMI_WRITE(HDMI_CEC_CNTRL_2,
2686                    ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2687                    ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2688                    ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2689                    ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2690                    ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2691         HDMI_WRITE(HDMI_CEC_CNTRL_3,
2692                    ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2693                    ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2694                    ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2695                    ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2696         HDMI_WRITE(HDMI_CEC_CNTRL_4,
2697                    ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2698                    ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2699                    ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2700                    ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2701
2702         if (!vc4_hdmi->variant->external_irq_controller)
2703                 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2704
2705         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2706
2707         drm_dev_exit(idx);
2708
2709         return 0;
2710 }
2711
2712 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2713 {
2714         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2715         struct drm_device *drm = vc4_hdmi->connector.dev;
2716         unsigned long flags;
2717         int idx;
2718
2719         if (!drm_dev_enter(drm, &idx))
2720                 /*
2721                  * We can't return an error code, because the CEC
2722                  * framework will emit WARN_ON messages at unbind
2723                  * otherwise.
2724                  */
2725                 return 0;
2726
2727         /*
2728          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2729          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2730          * .detect or .get_modes might call .adap_enable, which leads to this
2731          * function being called with that mutex held.
2732          *
2733          * Concurrency is not an issue for the moment since we don't share any
2734          * state with KMS, so we can ignore the lock for now, but we need to
2735          * keep it in mind if we were to change that assumption.
2736          */
2737
2738         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2739
2740         if (!vc4_hdmi->variant->external_irq_controller)
2741                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2742
2743         HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2744                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2745
2746         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2747
2748         pm_runtime_put(&vc4_hdmi->pdev->dev);
2749
2750         drm_dev_exit(idx);
2751
2752         return 0;
2753 }
2754
2755 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2756 {
2757         if (enable)
2758                 return vc4_hdmi_cec_enable(adap);
2759         else
2760                 return vc4_hdmi_cec_disable(adap);
2761 }
2762
2763 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2764 {
2765         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2766         struct drm_device *drm = vc4_hdmi->connector.dev;
2767         unsigned long flags;
2768         int idx;
2769
2770         /*
2771          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2772          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2773          * .detect or .get_modes might call .adap_enable, which leads to this
2774          * function being called with that mutex held.
2775          *
2776          * Concurrency is not an issue for the moment since we don't share any
2777          * state with KMS, so we can ignore the lock for now, but we need to
2778          * keep it in mind if we were to change that assumption.
2779          */
2780
2781         if (!drm_dev_enter(drm, &idx))
2782                 /*
2783                  * We can't return an error code, because the CEC
2784                  * framework will emit WARN_ON messages at unbind
2785                  * otherwise.
2786                  */
2787                 return 0;
2788
2789         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2790         HDMI_WRITE(HDMI_CEC_CNTRL_1,
2791                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2792                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2793         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2794
2795         drm_dev_exit(idx);
2796
2797         return 0;
2798 }
2799
2800 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2801                                       u32 signal_free_time, struct cec_msg *msg)
2802 {
2803         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2804         struct drm_device *dev = vc4_hdmi->connector.dev;
2805         unsigned long flags;
2806         u32 val;
2807         unsigned int i;
2808         int idx;
2809
2810         /*
2811          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2812          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2813          * .detect or .get_modes might call .adap_enable, which leads to this
2814          * function being called with that mutex held.
2815          *
2816          * Concurrency is not an issue for the moment since we don't share any
2817          * state with KMS, so we can ignore the lock for now, but we need to
2818          * keep it in mind if we were to change that assumption.
2819          */
2820
2821         if (!drm_dev_enter(dev, &idx))
2822                 return -ENODEV;
2823
2824         if (msg->len > 16) {
2825                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2826                 drm_dev_exit(idx);
2827                 return -ENOMEM;
2828         }
2829
2830         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2831
2832         for (i = 0; i < msg->len; i += 4)
2833                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2834                            (msg->msg[i]) |
2835                            (msg->msg[i + 1] << 8) |
2836                            (msg->msg[i + 2] << 16) |
2837                            (msg->msg[i + 3] << 24));
2838
2839         val = HDMI_READ(HDMI_CEC_CNTRL_1);
2840         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2841         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2842         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2843         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2844         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2845
2846         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2847
2848         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2849
2850         drm_dev_exit(idx);
2851
2852         return 0;
2853 }
2854
2855 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2856         .adap_enable = vc4_hdmi_cec_adap_enable,
2857         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2858         .adap_transmit = vc4_hdmi_cec_adap_transmit,
2859 };
2860
2861 static void vc4_hdmi_cec_release(void *ptr)
2862 {
2863         struct vc4_hdmi *vc4_hdmi = ptr;
2864
2865         cec_unregister_adapter(vc4_hdmi->cec_adap);
2866         vc4_hdmi->cec_adap = NULL;
2867 }
2868
2869 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2870 {
2871         struct cec_connector_info conn_info;
2872         struct platform_device *pdev = vc4_hdmi->pdev;
2873         struct device *dev = &pdev->dev;
2874         int ret;
2875
2876         if (!of_find_property(dev->of_node, "interrupts", NULL)) {
2877                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
2878                 return 0;
2879         }
2880
2881         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
2882                                                   vc4_hdmi, "vc4",
2883                                                   CEC_CAP_DEFAULTS |
2884                                                   CEC_CAP_CONNECTOR_INFO, 1);
2885         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
2886         if (ret < 0)
2887                 return ret;
2888
2889         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
2890         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
2891
2892         if (vc4_hdmi->variant->external_irq_controller) {
2893                 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
2894                                                 vc4_cec_irq_handler_rx_bare,
2895                                                 vc4_cec_irq_handler_rx_thread, 0,
2896                                                 "vc4 hdmi cec rx", vc4_hdmi);
2897                 if (ret)
2898                         goto err_delete_cec_adap;
2899
2900                 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
2901                                                 vc4_cec_irq_handler_tx_bare,
2902                                                 vc4_cec_irq_handler_tx_thread, 0,
2903                                                 "vc4 hdmi cec tx", vc4_hdmi);
2904                 if (ret)
2905                         goto err_delete_cec_adap;
2906         } else {
2907                 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
2908                                                 vc4_cec_irq_handler,
2909                                                 vc4_cec_irq_handler_thread, 0,
2910                                                 "vc4 hdmi cec", vc4_hdmi);
2911                 if (ret)
2912                         goto err_delete_cec_adap;
2913         }
2914
2915         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
2916         if (ret < 0)
2917                 goto err_delete_cec_adap;
2918
2919         /*
2920          * NOTE: Strictly speaking, we should probably use a DRM-managed
2921          * registration there to avoid removing the CEC adapter by the
2922          * time the DRM driver doesn't have any user anymore.
2923          *
2924          * However, the CEC framework already cleans up the CEC adapter
2925          * only when the last user has closed its file descriptor, so we
2926          * don't need to handle it in DRM.
2927          *
2928          * By the time the device-managed hook is executed, we will give
2929          * up our reference to the CEC adapter and therefore don't
2930          * really care when it's actually freed.
2931          *
2932          * There's still a problematic sequence: if we unregister our
2933          * CEC adapter, but the userspace keeps a handle on the CEC
2934          * adapter but not the DRM device for some reason. In such a
2935          * case, our vc4_hdmi structure will be freed, but the
2936          * cec_adapter structure will have a dangling pointer to what
2937          * used to be our HDMI controller. If we get a CEC call at that
2938          * moment, we could end up with a use-after-free. Fortunately,
2939          * the CEC framework already handles this too, by calling
2940          * cec_is_registered() in cec_ioctl() and cec_poll().
2941          */
2942         ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
2943         if (ret)
2944                 return ret;
2945
2946         return 0;
2947
2948 err_delete_cec_adap:
2949         cec_delete_adapter(vc4_hdmi->cec_adap);
2950
2951         return ret;
2952 }
2953 #else
2954 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2955 {
2956         return 0;
2957 }
2958 #endif
2959
2960 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
2961 {
2962         struct debugfs_reg32 *regs = ptr;
2963
2964         kfree(regs);
2965 }
2966
2967 static int vc4_hdmi_build_regset(struct drm_device *drm,
2968                                  struct vc4_hdmi *vc4_hdmi,
2969                                  struct debugfs_regset32 *regset,
2970                                  enum vc4_hdmi_regs reg)
2971 {
2972         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2973         struct debugfs_reg32 *regs, *new_regs;
2974         unsigned int count = 0;
2975         unsigned int i;
2976         int ret;
2977
2978         regs = kcalloc(variant->num_registers, sizeof(*regs),
2979                        GFP_KERNEL);
2980         if (!regs)
2981                 return -ENOMEM;
2982
2983         for (i = 0; i < variant->num_registers; i++) {
2984                 const struct vc4_hdmi_register *field = &variant->registers[i];
2985
2986                 if (field->reg != reg)
2987                         continue;
2988
2989                 regs[count].name = field->name;
2990                 regs[count].offset = field->offset;
2991                 count++;
2992         }
2993
2994         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
2995         if (!new_regs)
2996                 return -ENOMEM;
2997
2998         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
2999         regset->regs = new_regs;
3000         regset->nregs = count;
3001
3002         ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
3003         if (ret)
3004                 return ret;
3005
3006         return 0;
3007 }
3008
3009 static int vc4_hdmi_init_resources(struct drm_device *drm,
3010                                    struct vc4_hdmi *vc4_hdmi)
3011 {
3012         struct platform_device *pdev = vc4_hdmi->pdev;
3013         struct device *dev = &pdev->dev;
3014         int ret;
3015
3016         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
3017         if (IS_ERR(vc4_hdmi->hdmicore_regs))
3018                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
3019
3020         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
3021         if (IS_ERR(vc4_hdmi->hd_regs))
3022                 return PTR_ERR(vc4_hdmi->hd_regs);
3023
3024         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3025         if (ret)
3026                 return ret;
3027
3028         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3029         if (ret)
3030                 return ret;
3031
3032         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
3033         if (IS_ERR(vc4_hdmi->pixel_clock)) {
3034                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
3035                 if (ret != -EPROBE_DEFER)
3036                         DRM_ERROR("Failed to get pixel clock\n");
3037                 return ret;
3038         }
3039
3040         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3041         if (IS_ERR(vc4_hdmi->hsm_clock)) {
3042                 DRM_ERROR("Failed to get HDMI state machine clock\n");
3043                 return PTR_ERR(vc4_hdmi->hsm_clock);
3044         }
3045         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
3046         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
3047
3048         return 0;
3049 }
3050
3051 static int vc5_hdmi_init_resources(struct drm_device *drm,
3052                                    struct vc4_hdmi *vc4_hdmi)
3053 {
3054         struct platform_device *pdev = vc4_hdmi->pdev;
3055         struct device *dev = &pdev->dev;
3056         struct resource *res;
3057         int ret;
3058
3059         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
3060         if (!res)
3061                 return -ENODEV;
3062
3063         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
3064                                                resource_size(res));
3065         if (!vc4_hdmi->hdmicore_regs)
3066                 return -ENOMEM;
3067
3068         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
3069         if (!res)
3070                 return -ENODEV;
3071
3072         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
3073         if (!vc4_hdmi->hd_regs)
3074                 return -ENOMEM;
3075
3076         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
3077         if (!res)
3078                 return -ENODEV;
3079
3080         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
3081         if (!vc4_hdmi->cec_regs)
3082                 return -ENOMEM;
3083
3084         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
3085         if (!res)
3086                 return -ENODEV;
3087
3088         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
3089         if (!vc4_hdmi->csc_regs)
3090                 return -ENOMEM;
3091
3092         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
3093         if (!res)
3094                 return -ENODEV;
3095
3096         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
3097         if (!vc4_hdmi->dvp_regs)
3098                 return -ENOMEM;
3099
3100         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
3101         if (!res)
3102                 return -ENODEV;
3103
3104         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
3105         if (!vc4_hdmi->phy_regs)
3106                 return -ENOMEM;
3107
3108         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
3109         if (!res)
3110                 return -ENODEV;
3111
3112         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
3113         if (!vc4_hdmi->ram_regs)
3114                 return -ENOMEM;
3115
3116         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
3117         if (!res)
3118                 return -ENODEV;
3119
3120         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
3121         if (!vc4_hdmi->rm_regs)
3122                 return -ENOMEM;
3123
3124         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3125         if (IS_ERR(vc4_hdmi->hsm_clock)) {
3126                 DRM_ERROR("Failed to get HDMI state machine clock\n");
3127                 return PTR_ERR(vc4_hdmi->hsm_clock);
3128         }
3129
3130         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3131         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3132                 DRM_ERROR("Failed to get pixel bvb clock\n");
3133                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3134         }
3135
3136         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3137         if (IS_ERR(vc4_hdmi->audio_clock)) {
3138                 DRM_ERROR("Failed to get audio clock\n");
3139                 return PTR_ERR(vc4_hdmi->audio_clock);
3140         }
3141
3142         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3143         if (IS_ERR(vc4_hdmi->cec_clock)) {
3144                 DRM_ERROR("Failed to get CEC clock\n");
3145                 return PTR_ERR(vc4_hdmi->cec_clock);
3146         }
3147
3148         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3149         if (IS_ERR(vc4_hdmi->reset)) {
3150                 DRM_ERROR("Failed to get HDMI reset line\n");
3151                 return PTR_ERR(vc4_hdmi->reset);
3152         }
3153
3154         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3155         if (ret)
3156                 return ret;
3157
3158         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3159         if (ret)
3160                 return ret;
3161
3162         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3163         if (ret)
3164                 return ret;
3165
3166         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3167         if (ret)
3168                 return ret;
3169
3170         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3171         if (ret)
3172                 return ret;
3173
3174         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3175         if (ret)
3176                 return ret;
3177
3178         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3179         if (ret)
3180                 return ret;
3181
3182         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3183         if (ret)
3184                 return ret;
3185
3186         return 0;
3187 }
3188
3189 static int vc4_hdmi_runtime_suspend(struct device *dev)
3190 {
3191         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3192
3193         clk_disable_unprepare(vc4_hdmi->hsm_clock);
3194
3195         return 0;
3196 }
3197
3198 static int vc4_hdmi_runtime_resume(struct device *dev)
3199 {
3200         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3201         unsigned long __maybe_unused flags;
3202         u32 __maybe_unused value;
3203         int ret;
3204
3205         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
3206         if (ret)
3207                 return ret;
3208
3209         if (vc4_hdmi->variant->reset)
3210                 vc4_hdmi->variant->reset(vc4_hdmi);
3211
3212 #ifdef CONFIG_DRM_VC4_HDMI_CEC
3213         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3214         value = HDMI_READ(HDMI_CEC_CNTRL_1);
3215         /* Set the logical address to Unregistered */
3216         value |= VC4_HDMI_CEC_ADDR_MASK;
3217         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3218         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3219
3220         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3221
3222         if (!vc4_hdmi->variant->external_irq_controller) {
3223                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3224                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3225                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3226         }
3227 #endif
3228
3229         return 0;
3230 }
3231
3232 static void vc4_hdmi_put_ddc_device(void *ptr)
3233 {
3234         struct vc4_hdmi *vc4_hdmi = ptr;
3235
3236         put_device(&vc4_hdmi->ddc->dev);
3237 }
3238
3239 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3240 {
3241         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3242         struct platform_device *pdev = to_platform_device(dev);
3243         struct drm_device *drm = dev_get_drvdata(master);
3244         struct vc4_hdmi *vc4_hdmi;
3245         struct drm_encoder *encoder;
3246         struct device_node *ddc_node;
3247         int ret;
3248
3249         vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3250         if (!vc4_hdmi)
3251                 return -ENOMEM;
3252
3253         mutex_init(&vc4_hdmi->mutex);
3254         spin_lock_init(&vc4_hdmi->hw_lock);
3255         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3256
3257         dev_set_drvdata(dev, vc4_hdmi);
3258         encoder = &vc4_hdmi->encoder.base;
3259         vc4_hdmi->encoder.type = variant->encoder_type;
3260         vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3261         vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3262         vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3263         vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3264         vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3265         vc4_hdmi->pdev = pdev;
3266         vc4_hdmi->variant = variant;
3267
3268         /*
3269          * Since we don't know the state of the controller and its
3270          * display (if any), let's assume it's always enabled.
3271          * vc4_hdmi_disable_scrambling() will thus run at boot, make
3272          * sure it's disabled, and avoid any inconsistency.
3273          */
3274         if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3275                 vc4_hdmi->scdc_enabled = true;
3276
3277         ret = variant->init_resources(drm, vc4_hdmi);
3278         if (ret)
3279                 return ret;
3280
3281         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3282         if (!ddc_node) {
3283                 DRM_ERROR("Failed to find ddc node in device tree\n");
3284                 return -ENODEV;
3285         }
3286
3287         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3288         of_node_put(ddc_node);
3289         if (!vc4_hdmi->ddc) {
3290                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
3291                 return -EPROBE_DEFER;
3292         }
3293
3294         ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3295         if (ret)
3296                 return ret;
3297
3298         /* Only use the GPIO HPD pin if present in the DT, otherwise
3299          * we'll use the HDMI core's register.
3300          */
3301         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3302         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3303                 return PTR_ERR(vc4_hdmi->hpd_gpio);
3304         }
3305
3306         vc4_hdmi->disable_wifi_frequencies =
3307                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3308
3309         if (variant->max_pixel_clock == 600000000) {
3310                 struct vc4_dev *vc4 = to_vc4_dev(drm);
3311                 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
3312
3313                 if (max_rate < 550000000)
3314                         vc4_hdmi->disable_4kp60 = true;
3315         }
3316
3317         ret = devm_pm_runtime_enable(dev);
3318         if (ret)
3319                 return ret;
3320
3321         /*
3322          *  We need to have the device powered up at this point to call
3323          *  our reset hook and for the CEC init.
3324          */
3325         ret = pm_runtime_resume_and_get(dev);
3326         if (ret)
3327                 return ret;
3328
3329         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3330              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
3331             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3332                 clk_prepare_enable(vc4_hdmi->pixel_clock);
3333                 clk_prepare_enable(vc4_hdmi->hsm_clock);
3334                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3335         }
3336
3337         ret = drmm_encoder_init(drm, encoder,
3338                                 NULL,
3339                                 DRM_MODE_ENCODER_TMDS,
3340                                 NULL);
3341         if (ret)
3342                 goto err_put_runtime_pm;
3343
3344         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3345
3346         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3347         if (ret)
3348                 goto err_put_runtime_pm;
3349
3350         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3351         if (ret)
3352                 goto err_put_runtime_pm;
3353
3354         ret = vc4_hdmi_cec_init(vc4_hdmi);
3355         if (ret)
3356                 goto err_put_runtime_pm;
3357
3358         ret = vc4_hdmi_audio_init(vc4_hdmi);
3359         if (ret)
3360                 goto err_put_runtime_pm;
3361
3362         vc4_debugfs_add_file(drm, variant->debugfs_name,
3363                              vc4_hdmi_debugfs_regs,
3364                              vc4_hdmi);
3365
3366         pm_runtime_put_sync(dev);
3367
3368         return 0;
3369
3370 err_put_runtime_pm:
3371         pm_runtime_put_sync(dev);
3372
3373         return ret;
3374 }
3375
3376 static const struct component_ops vc4_hdmi_ops = {
3377         .bind   = vc4_hdmi_bind,
3378 };
3379
3380 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3381 {
3382         return component_add(&pdev->dev, &vc4_hdmi_ops);
3383 }
3384
3385 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
3386 {
3387         component_del(&pdev->dev, &vc4_hdmi_ops);
3388         return 0;
3389 }
3390
3391 static const struct vc4_hdmi_variant bcm2835_variant = {
3392         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3393         .debugfs_name           = "hdmi_regs",
3394         .card_name              = "vc4-hdmi",
3395         .max_pixel_clock        = 162000000,
3396         .registers              = vc4_hdmi_fields,
3397         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
3398
3399         .init_resources         = vc4_hdmi_init_resources,
3400         .csc_setup              = vc4_hdmi_csc_setup,
3401         .reset                  = vc4_hdmi_reset,
3402         .set_timings            = vc4_hdmi_set_timings,
3403         .phy_init               = vc4_hdmi_phy_init,
3404         .phy_disable            = vc4_hdmi_phy_disable,
3405         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
3406         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
3407         .channel_map            = vc4_hdmi_channel_map,
3408         .supports_hdr           = false,
3409 };
3410
3411 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3412         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3413         .debugfs_name           = "hdmi0_regs",
3414         .card_name              = "vc4-hdmi-0",
3415         .max_pixel_clock        = 600000000,
3416         .registers              = vc5_hdmi_hdmi0_fields,
3417         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3418         .phy_lane_mapping       = {
3419                 PHY_LANE_0,
3420                 PHY_LANE_1,
3421                 PHY_LANE_2,
3422                 PHY_LANE_CK,
3423         },
3424         .unsupported_odd_h_timings      = true,
3425         .external_irq_controller        = true,
3426
3427         .init_resources         = vc5_hdmi_init_resources,
3428         .csc_setup              = vc5_hdmi_csc_setup,
3429         .reset                  = vc5_hdmi_reset,
3430         .set_timings            = vc5_hdmi_set_timings,
3431         .phy_init               = vc5_hdmi_phy_init,
3432         .phy_disable            = vc5_hdmi_phy_disable,
3433         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
3434         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
3435         .channel_map            = vc5_hdmi_channel_map,
3436         .supports_hdr           = true,
3437         .hp_detect              = vc5_hdmi_hp_detect,
3438 };
3439
3440 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3441         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
3442         .debugfs_name           = "hdmi1_regs",
3443         .card_name              = "vc4-hdmi-1",
3444         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
3445         .registers              = vc5_hdmi_hdmi1_fields,
3446         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3447         .phy_lane_mapping       = {
3448                 PHY_LANE_1,
3449                 PHY_LANE_0,
3450                 PHY_LANE_CK,
3451                 PHY_LANE_2,
3452         },
3453         .unsupported_odd_h_timings      = true,
3454         .external_irq_controller        = true,
3455
3456         .init_resources         = vc5_hdmi_init_resources,
3457         .csc_setup              = vc5_hdmi_csc_setup,
3458         .reset                  = vc5_hdmi_reset,
3459         .set_timings            = vc5_hdmi_set_timings,
3460         .phy_init               = vc5_hdmi_phy_init,
3461         .phy_disable            = vc5_hdmi_phy_disable,
3462         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
3463         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
3464         .channel_map            = vc5_hdmi_channel_map,
3465         .supports_hdr           = true,
3466         .hp_detect              = vc5_hdmi_hp_detect,
3467 };
3468
3469 static const struct of_device_id vc4_hdmi_dt_match[] = {
3470         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3471         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3472         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3473         {}
3474 };
3475
3476 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3477         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3478                            vc4_hdmi_runtime_resume,
3479                            NULL)
3480 };
3481
3482 struct platform_driver vc4_hdmi_driver = {
3483         .probe = vc4_hdmi_dev_probe,
3484         .remove = vc4_hdmi_dev_remove,
3485         .driver = {
3486                 .name = "vc4_hdmi",
3487                 .of_match_table = vc4_hdmi_dt_match,
3488                 .pm = &vc4_hdmi_pm_ops,
3489         },
3490 };