drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/display/drm_hdmi_helper.h>
  35 #include <drm/display/drm_scdc_helper.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_drv.h>
  38 #include <drm/drm_probe_helper.h>
  39 #include <drm/drm_simple_kms_helper.h>
  40 #include <linux/clk.h>
  41 #include <linux/component.h>
  42 #include <linux/gpio/consumer.h>
  43 #include <linux/i2c.h>
  44 #include <linux/module.h>
  45 #include <linux/moduleparam.h>
  46 #include <linux/of.h>
  47 #include <linux/of_address.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/rational.h>
  50 #include <linux/reset.h>
  51 #include <sound/dmaengine_pcm.h>
  52 #include <sound/hdmi-codec.h>
  53 #include <sound/pcm_drm_eld.h>
  54 #include <sound/pcm_params.h>
  55 #include <sound/soc.h>
  56 #include "media/cec.h"
  57 #include "vc4_drv.h"
  58 #include "vc4_hdmi.h"
  59 #include "vc4_hdmi_regs.h"
  60 #include "vc4_regs.h"
  61
  62 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  63 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  64 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  65 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  66 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  67 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  68
  69 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  70 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  71 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  72 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  73
  74 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  75 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  76 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  77 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  78 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  79 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  80
  81 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  82 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  83
  84 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  85 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  86 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT   0
  87 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK    VC4_MASK(3, 0)
  88
  89 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  90
  91 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  93
  94 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  95 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  96
  97 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  98
  99 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
 100 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
 101
 102 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK   VC4_MASK(7, 0)
 103 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE     BIT(0)
 104 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE   BIT(4)
 105
 106 # define VC4_HD_M_SW_RST                        BIT(2)
 107 # define VC4_HD_M_ENABLE                        BIT(0)
 108
 109 #define HSM_MIN_CLOCK_FREQ      120000000
 110 #define CEC_CLOCK_FREQ 40000
 111
 112 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 113
 114 /* bit field to force hotplug detection. bit0 = HDMI0 */
 115 static int force_hotplug = 0;
 116 module_param(force_hotplug, int, 0644);
 117
 118 static const char * const output_format_str[] = {
 119         [VC4_HDMI_OUTPUT_RGB]           = "RGB",
 120         [VC4_HDMI_OUTPUT_YUV420]        = "YUV 4:2:0",
 121         [VC4_HDMI_OUTPUT_YUV422]        = "YUV 4:2:2",
 122         [VC4_HDMI_OUTPUT_YUV444]        = "YUV 4:4:4",
 123 };
 124
 125 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt)
 126 {
 127         if (fmt >= ARRAY_SIZE(output_format_str))
 128                 return "invalid";
 129
 130         return output_format_str[fmt];
 131 }
 132
 133 static unsigned long long
 134 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
 135                                     unsigned int bpc, enum vc4_hdmi_output_format fmt);
 136
 137 static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi)
 138 {
 139         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 140
 141         lockdep_assert_held(&vc4_hdmi->mutex);
 142
 143         if (!display->is_hdmi)
 144                 return false;
 145
 146         if (!display->hdmi.scdc.supported ||
 147             !display->hdmi.scdc.scrambling.supported)
 148                 return false;
 149
 150         return true;
 151 }
 152
 153 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
 154                                            unsigned int bpc,
 155                                            enum vc4_hdmi_output_format fmt)
 156 {
 157         unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
 158
 159         return clock > HDMI_14_MAX_TMDS_CLK;
 160 }
 161
 162 static bool vc4_hdmi_is_full_range(struct vc4_hdmi *vc4_hdmi,
 163                                    struct vc4_hdmi_connector_state *vc4_state)
 164 {
 165         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 166         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 167
 168         if (vc4_state->broadcast_rgb == VC4_HDMI_BROADCAST_RGB_LIMITED)
 169                 return false;
 170         else if (vc4_state->broadcast_rgb == VC4_HDMI_BROADCAST_RGB_FULL)
 171                 return true;
 172
 173         return !display->is_hdmi ||
 174                 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
 175 }
 176
 177 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 178 {
 179         struct drm_debugfs_entry *entry = m->private;
 180         struct vc4_hdmi *vc4_hdmi = entry->file.data;
 181         struct drm_device *drm = vc4_hdmi->connector.dev;
 182         struct drm_printer p = drm_seq_file_printer(m);
 183         int idx;
 184
 185         if (!drm_dev_enter(drm, &idx))
 186                 return -ENODEV;
 187
 188         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 189
 190         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 191         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 192         drm_print_regset32(&p, &vc4_hdmi->cec_regset);
 193         drm_print_regset32(&p, &vc4_hdmi->csc_regset);
 194         drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
 195         drm_print_regset32(&p, &vc4_hdmi->phy_regset);
 196         drm_print_regset32(&p, &vc4_hdmi->ram_regset);
 197         drm_print_regset32(&p, &vc4_hdmi->rm_regset);
 198
 199         pm_runtime_put(&vc4_hdmi->pdev->dev);
 200
 201         drm_dev_exit(idx);
 202
 203         return 0;
 204 }
 205
 206 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 207 {
 208         struct drm_device *drm = vc4_hdmi->connector.dev;
 209         unsigned long flags;
 210         int idx;
 211
 212         /*
 213          * We can be called by our bind callback, when the
 214          * connector->dev pointer might not be initialised yet.
 215          */
 216         if (drm && !drm_dev_enter(drm, &idx))
 217                 return;
 218
 219         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 220
 221         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 222         udelay(1);
 223         HDMI_WRITE(HDMI_M_CTL, 0);
 224
 225         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 226
 227         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 228                    VC4_HDMI_SW_RESET_HDMI |
 229                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 230
 231         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 232
 233         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 234
 235         if (drm)
 236                 drm_dev_exit(idx);
 237 }
 238
 239 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 240 {
 241         struct drm_device *drm = vc4_hdmi->connector.dev;
 242         unsigned long flags;
 243         int idx;
 244
 245         /*
 246          * We can be called by our bind callback, when the
 247          * connector->dev pointer might not be initialised yet.
 248          */
 249         if (drm && !drm_dev_enter(drm, &idx))
 250                 return;
 251
 252         reset_control_reset(vc4_hdmi->reset);
 253
 254         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 255
 256         HDMI_WRITE(HDMI_DVP_CTL, 0);
 257
 258         HDMI_WRITE(HDMI_CLOCK_STOP,
 259                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 260
 261         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 262
 263         if (drm)
 264                 drm_dev_exit(idx);
 265 }
 266
 267 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 268 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 269 {
 270         struct drm_device *drm = vc4_hdmi->connector.dev;
 271         unsigned long cec_rate;
 272         unsigned long flags;
 273         u16 clk_cnt;
 274         u32 value;
 275         int idx;
 276
 277         /*
 278          * This function is called by our runtime_resume implementation
 279          * and thus at bind time, when we haven't registered our
 280          * connector yet and thus don't have a pointer to the DRM
 281          * device.
 282          */
 283         if (drm && !drm_dev_enter(drm, &idx))
 284                 return;
 285
 286         cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
 287
 288         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 289
 290         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 291         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 292
 293         /*
 294          * Set the clock divider: the hsm_clock rate and this divider
 295          * setting will give a 40 kHz CEC clock.
 296          */
 297         clk_cnt = cec_rate / CEC_CLOCK_FREQ;
 298         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 299         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 300
 301         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 302
 303         if (drm)
 304                 drm_dev_exit(idx);
 305 }
 306 #else
 307 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 308 #endif
 309
 310 static int reset_pipe(struct drm_crtc *crtc,
 311                         struct drm_modeset_acquire_ctx *ctx)
 312 {
 313         struct drm_atomic_state *state;
 314         struct drm_crtc_state *crtc_state;
 315         int ret;
 316
 317         state = drm_atomic_state_alloc(crtc->dev);
 318         if (!state)
 319                 return -ENOMEM;
 320
 321         state->acquire_ctx = ctx;
 322
 323         crtc_state = drm_atomic_get_crtc_state(state, crtc);
 324         if (IS_ERR(crtc_state)) {
 325                 ret = PTR_ERR(crtc_state);
 326                 goto out;
 327         }
 328
 329         crtc_state->connectors_changed = true;
 330
 331         ret = drm_atomic_commit(state);
 332 out:
 333         drm_atomic_state_put(state);
 334
 335         return ret;
 336 }
 337
 338 static int vc4_hdmi_reset_link(struct drm_connector *connector,
 339                                struct drm_modeset_acquire_ctx *ctx)
 340 {
 341         struct drm_device *drm;
 342         struct vc4_hdmi *vc4_hdmi;
 343         struct drm_connector_state *conn_state;
 344         struct drm_crtc_state *crtc_state;
 345         struct drm_crtc *crtc;
 346         bool scrambling_needed;
 347         u8 config;
 348         int ret;
 349
 350         if (!connector)
 351                 return 0;
 352
 353         drm = connector->dev;
 354         ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx);
 355         if (ret)
 356                 return ret;
 357
 358         conn_state = connector->state;
 359         crtc = conn_state->crtc;
 360         if (!crtc)
 361                 return 0;
 362
 363         ret = drm_modeset_lock(&crtc->mutex, ctx);
 364         if (ret)
 365                 return ret;
 366
 367         crtc_state = crtc->state;
 368         if (!crtc_state->active)
 369                 return 0;
 370
 371         vc4_hdmi = connector_to_vc4_hdmi(connector);
 372         mutex_lock(&vc4_hdmi->mutex);
 373
 374         if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) {
 375                 mutex_unlock(&vc4_hdmi->mutex);
 376                 return 0;
 377         }
 378
 379         scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
 380                                                            vc4_hdmi->output_bpc,
 381                                                            vc4_hdmi->output_format);
 382         if (!scrambling_needed) {
 383                 mutex_unlock(&vc4_hdmi->mutex);
 384                 return 0;
 385         }
 386
 387         if (conn_state->commit &&
 388             !try_wait_for_completion(&conn_state->commit->hw_done)) {
 389                 mutex_unlock(&vc4_hdmi->mutex);
 390                 return 0;
 391         }
 392
 393         ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
 394         if (ret < 0) {
 395                 drm_err(drm, "Failed to read TMDS config: %d\n", ret);
 396                 mutex_unlock(&vc4_hdmi->mutex);
 397                 return 0;
 398         }
 399
 400         if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) {
 401                 mutex_unlock(&vc4_hdmi->mutex);
 402                 return 0;
 403         }
 404
 405         mutex_unlock(&vc4_hdmi->mutex);
 406
 407         /*
 408          * HDMI 2.0 says that one should not send scrambled data
 409          * prior to configuring the sink scrambling, and that
 410          * TMDS clock/data transmission should be suspended when
 411          * changing the TMDS clock rate in the sink. So let's
 412          * just do a full modeset here, even though some sinks
 413          * would be perfectly happy if were to just reconfigure
 414          * the SCDC settings on the fly.
 415          */
 416         return reset_pipe(crtc, ctx);
 417 }
 418
 419 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi,
 420                                     struct drm_modeset_acquire_ctx *ctx,
 421                                     enum drm_connector_status status)
 422 {
 423         struct drm_connector *connector = &vc4_hdmi->connector;
 424         struct edid *edid;
 425         int ret;
 426
 427         /*
 428          * NOTE: This function should really be called with
 429          * vc4_hdmi->mutex held, but doing so results in reentrancy
 430          * issues since cec_s_phys_addr_from_edid might call
 431          * .adap_enable, which leads to that funtion being called with
 432          * our mutex held.
 433          *
 434          * A similar situation occurs with vc4_hdmi_reset_link() that
 435          * will call into our KMS hooks if the scrambling was enabled.
 436          *
 437          * Concurrency isn't an issue at the moment since we don't share
 438          * any state with any of the other frameworks so we can ignore
 439          * the lock for now.
 440          */
 441
 442         if (status == connector_status_disconnected) {
 443                 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 444                 return;
 445         }
 446
 447         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 448         if (!edid)
 449                 return;
 450
 451         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 452         kfree(edid);
 453
 454         for (;;) {
 455                 ret = vc4_hdmi_reset_link(connector, ctx);
 456                 if (ret == -EDEADLK) {
 457                         drm_modeset_backoff(ctx);
 458                         continue;
 459                 }
 460
 461                 break;
 462         }
 463 }
 464
 465 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
 466                                          struct drm_modeset_acquire_ctx *ctx,
 467                                          bool force)
 468 {
 469         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 470         enum drm_connector_status status = connector_status_disconnected;
 471
 472         /*
 473          * NOTE: This function should really take vc4_hdmi->mutex, but
 474          * doing so results in reentrancy issues since
 475          * vc4_hdmi_handle_hotplug() can call into other functions that
 476          * would take the mutex while it's held here.
 477          *
 478          * Concurrency isn't an issue at the moment since we don't share
 479          * any state with any of the other frameworks so we can ignore
 480          * the lock for now.
 481          */
 482
 483         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 484
 485         if (force_hotplug & BIT(vc4_hdmi->encoder.type - VC4_ENCODER_TYPE_HDMI0))
 486                 status = connector_status_connected;
 487         else if (vc4_hdmi->hpd_gpio) {
 488                 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
 489                         status = connector_status_connected;
 490         } else {
 491                 if (vc4_hdmi->variant->hp_detect &&
 492                     vc4_hdmi->variant->hp_detect(vc4_hdmi))
 493                         status = connector_status_connected;
 494         }
 495
 496         vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status);
 497         pm_runtime_put(&vc4_hdmi->pdev->dev);
 498
 499         return status;
 500 }
 501
 502 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 503 {
 504         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 505         struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
 506         int ret = 0;
 507         struct edid *edid;
 508
 509         /*
 510          * NOTE: This function should really take vc4_hdmi->mutex, but
 511          * doing so results in reentrancy issues since
 512          * cec_s_phys_addr_from_edid might call .adap_enable, which
 513          * leads to that funtion being called with our mutex held.
 514          *
 515          * Concurrency isn't an issue at the moment since we don't share
 516          * any state with any of the other frameworks so we can ignore
 517          * the lock for now.
 518          */
 519
 520         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 521         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 522         if (!edid)
 523                 return -ENODEV;
 524
 525         drm_connector_update_edid_property(connector, edid);
 526         ret = drm_add_edid_modes(connector, edid);
 527         kfree(edid);
 528
 529         if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) {
 530                 struct drm_device *drm = connector->dev;
 531                 const struct drm_display_mode *mode;
 532
 533                 list_for_each_entry(mode, &connector->probed_modes, head) {
 534                         if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) {
 535                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 536                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 537                         }
 538                 }
 539         }
 540
 541         return ret;
 542 }
 543
 544 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 545                                            struct drm_atomic_state *state)
 546 {
 547         struct drm_connector_state *old_state =
 548                 drm_atomic_get_old_connector_state(state, connector);
 549         struct vc4_hdmi_connector_state *old_vc4_state =
 550                 conn_state_to_vc4_hdmi_conn_state(old_state);
 551         struct drm_connector_state *new_state =
 552                 drm_atomic_get_new_connector_state(state, connector);
 553         struct vc4_hdmi_connector_state *new_vc4_state =
 554                 conn_state_to_vc4_hdmi_conn_state(new_state);
 555         struct drm_crtc *crtc = new_state->crtc;
 556
 557         if (!crtc)
 558                 return 0;
 559
 560         if (old_state->tv.margins.left != new_state->tv.margins.left ||
 561             old_state->tv.margins.right != new_state->tv.margins.right ||
 562             old_state->tv.margins.top != new_state->tv.margins.top ||
 563             old_state->tv.margins.bottom != new_state->tv.margins.bottom) {
 564                 struct drm_crtc_state *crtc_state;
 565                 int ret;
 566
 567                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 568                 if (IS_ERR(crtc_state))
 569                         return PTR_ERR(crtc_state);
 570
 571                 /*
 572                  * Strictly speaking, we should be calling
 573                  * drm_atomic_helper_check_planes() after our call to
 574                  * drm_atomic_add_affected_planes(). However, the
 575                  * connector atomic_check is called as part of
 576                  * drm_atomic_helper_check_modeset() that already
 577                  * happens before a call to
 578                  * drm_atomic_helper_check_planes() in
 579                  * drm_atomic_helper_check().
 580                  */
 581                 ret = drm_atomic_add_affected_planes(state, crtc);
 582                 if (ret)
 583                         return ret;
 584         }
 585
 586         if (old_state->colorspace != new_state->colorspace ||
 587             old_vc4_state->broadcast_rgb != new_vc4_state->broadcast_rgb ||
 588             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 589                 struct drm_crtc_state *crtc_state;
 590
 591                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 592                 if (IS_ERR(crtc_state))
 593                         return PTR_ERR(crtc_state);
 594
 595                 crtc_state->mode_changed = true;
 596         }
 597
 598         return 0;
 599 }
 600
 601 static int vc4_hdmi_connector_get_property(struct drm_connector *connector,
 602                                            const struct drm_connector_state *state,
 603                                            struct drm_property *property,
 604                                            uint64_t *val)
 605 {
 606         struct drm_device *drm = connector->dev;
 607         struct vc4_hdmi *vc4_hdmi =
 608                 connector_to_vc4_hdmi(connector);
 609         const struct vc4_hdmi_connector_state *vc4_conn_state =
 610                 conn_state_to_vc4_hdmi_conn_state(state);
 611
 612         if (property == vc4_hdmi->broadcast_rgb_property) {
 613                 *val = vc4_conn_state->broadcast_rgb;
 614         } else {
 615                 drm_dbg(drm, "Unknown property [PROP:%d:%s]\n",
 616                         property->base.id, property->name);
 617                 return -EINVAL;
 618         }
 619
 620         return 0;
 621 }
 622
 623 static int vc4_hdmi_connector_set_property(struct drm_connector *connector,
 624                                            struct drm_connector_state *state,
 625                                            struct drm_property *property,
 626                                            uint64_t val)
 627 {
 628         struct drm_device *drm = connector->dev;
 629         struct vc4_hdmi *vc4_hdmi =
 630                 connector_to_vc4_hdmi(connector);
 631         struct vc4_hdmi_connector_state *vc4_conn_state =
 632                 conn_state_to_vc4_hdmi_conn_state(state);
 633
 634         if (property == vc4_hdmi->broadcast_rgb_property) {
 635                 vc4_conn_state->broadcast_rgb = val;
 636                 return 0;
 637         }
 638
 639         drm_dbg(drm, "Unknown property [PROP:%d:%s]\n",
 640                 property->base.id, property->name);
 641         return -EINVAL;
 642 }
 643
 644 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 645 {
 646         struct vc4_hdmi_connector_state *old_state =
 647                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 648         struct vc4_hdmi_connector_state *new_state =
 649                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 650
 651         if (connector->state)
 652                 __drm_atomic_helper_connector_destroy_state(connector->state);
 653
 654         kfree(old_state);
 655         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 656
 657         if (!new_state)
 658                 return;
 659
 660         new_state->base.max_bpc = 8;
 661         new_state->base.max_requested_bpc = 8;
 662         new_state->output_format = VC4_HDMI_OUTPUT_RGB;
 663         new_state->broadcast_rgb = VC4_HDMI_BROADCAST_RGB_AUTO;
 664         drm_atomic_helper_connector_tv_margins_reset(connector);
 665 }
 666
 667 static struct drm_connector_state *
 668 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 669 {
 670         struct drm_connector_state *conn_state = connector->state;
 671         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 672         struct vc4_hdmi_connector_state *new_state;
 673
 674         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 675         if (!new_state)
 676                 return NULL;
 677
 678         new_state->tmds_char_rate = vc4_state->tmds_char_rate;
 679         new_state->output_bpc = vc4_state->output_bpc;
 680         new_state->output_format = vc4_state->output_format;
 681         new_state->broadcast_rgb = vc4_state->broadcast_rgb;
 682         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 683
 684         return &new_state->base;
 685 }
 686
 687 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 688         .fill_modes = drm_helper_probe_single_connector_modes,
 689         .reset = vc4_hdmi_connector_reset,
 690         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 691         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 692         .atomic_get_property = vc4_hdmi_connector_get_property,
 693         .atomic_set_property = vc4_hdmi_connector_set_property,
 694 };
 695
 696 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 697         .detect_ctx = vc4_hdmi_connector_detect_ctx,
 698         .get_modes = vc4_hdmi_connector_get_modes,
 699         .atomic_check = vc4_hdmi_connector_atomic_check,
 700 };
 701
 702 static const struct drm_prop_enum_list broadcast_rgb_names[] = {
 703         { VC4_HDMI_BROADCAST_RGB_AUTO, "Automatic" },
 704         { VC4_HDMI_BROADCAST_RGB_FULL, "Full" },
 705         { VC4_HDMI_BROADCAST_RGB_LIMITED, "Limited 16:235" },
 706 };
 707
 708 static void
 709 vc4_hdmi_attach_broadcast_rgb_property(struct drm_device *dev,
 710                                        struct vc4_hdmi *vc4_hdmi)
 711 {
 712         struct drm_property *prop = vc4_hdmi->broadcast_rgb_property;
 713
 714         if (!prop) {
 715                 prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
 716                                                 "Broadcast RGB",
 717                                                 broadcast_rgb_names,
 718                                                 ARRAY_SIZE(broadcast_rgb_names));
 719                 if (!prop)
 720                         return;
 721
 722                 vc4_hdmi->broadcast_rgb_property = prop;
 723         }
 724
 725         drm_object_attach_property(&vc4_hdmi->connector.base, prop,
 726                                    VC4_HDMI_BROADCAST_RGB_AUTO);
 727 }
 728
 729 static int vc4_hdmi_connector_init(struct drm_device *dev,
 730                                    struct vc4_hdmi *vc4_hdmi)
 731 {
 732         struct drm_connector *connector = &vc4_hdmi->connector;
 733         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
 734         int ret;
 735
 736         ret = drmm_connector_init(dev, connector,
 737                                   &vc4_hdmi_connector_funcs,
 738                                   DRM_MODE_CONNECTOR_HDMIA,
 739                                   vc4_hdmi->ddc);
 740         if (ret)
 741                 return ret;
 742
 743         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 744
 745         /*
 746          * Some of the properties below require access to state, like bpc.
 747          * Allocate some default initial connector state with our reset helper.
 748          */
 749         if (connector->funcs->reset)
 750                 connector->funcs->reset(connector);
 751
 752         /* Create and attach TV margin props to this connector. */
 753         ret = drm_mode_create_tv_margin_properties(dev);
 754         if (ret)
 755                 return ret;
 756
 757         ret = drm_mode_create_hdmi_colorspace_property(connector, 0);
 758         if (ret)
 759                 return ret;
 760
 761         drm_connector_attach_colorspace_property(connector);
 762         drm_connector_attach_tv_margin_properties(connector);
 763
 764         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 765                              DRM_CONNECTOR_POLL_DISCONNECT);
 766
 767         connector->interlace_allowed = 1;
 768         connector->doublescan_allowed = 0;
 769         connector->stereo_allowed = 1;
 770
 771         if (vc4_hdmi->variant->supports_hdr) {
 772                 drm_connector_attach_max_bpc_property(connector, 8, 12);
 773                 drm_connector_attach_hdr_output_metadata_property(connector);
 774         } else {
 775                 drm_connector_attach_max_bpc_property(connector, 8, 8);
 776         }
 777
 778         vc4_hdmi_attach_broadcast_rgb_property(dev, vc4_hdmi);
 779
 780         drm_connector_attach_encoder(connector, encoder);
 781
 782         return 0;
 783 }
 784
 785 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 786                                 enum hdmi_infoframe_type type,
 787                                 bool poll)
 788 {
 789         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 790         struct drm_device *drm = vc4_hdmi->connector.dev;
 791         u32 packet_id = type - 0x80;
 792         unsigned long flags;
 793         int ret = 0;
 794         int idx;
 795
 796         if (!drm_dev_enter(drm, &idx))
 797                 return -ENODEV;
 798
 799         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 800         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 801                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 802         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 803
 804         if (poll) {
 805                 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 806                                  BIT(packet_id)), 100);
 807         }
 808
 809         drm_dev_exit(idx);
 810         return ret;
 811 }
 812
 813 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 814                                      union hdmi_infoframe *frame)
 815 {
 816         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 817         struct drm_device *drm = vc4_hdmi->connector.dev;
 818         u32 packet_id = frame->any.type - 0x80;
 819         const struct vc4_hdmi_register *ram_packet_start =
 820                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 821         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 822         u32 packet_reg_next = ram_packet_start->offset +
 823                 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
 824         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 825                                                        ram_packet_start->reg);
 826         uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
 827         unsigned long flags;
 828         ssize_t len, i;
 829         int ret;
 830         int idx;
 831
 832         if (!drm_dev_enter(drm, &idx))
 833                 return;
 834
 835         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 836                     VC4_HDMI_RAM_PACKET_ENABLE),
 837                   "Packet RAM has to be on to store the packet.");
 838
 839         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 840         if (len < 0)
 841                 goto out;
 842
 843         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 844         if (ret) {
 845                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 846                 goto out;
 847         }
 848
 849         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 850
 851         for (i = 0; i < len; i += 7) {
 852                 writel(buffer[i + 0] << 0 |
 853                        buffer[i + 1] << 8 |
 854                        buffer[i + 2] << 16,
 855                        base + packet_reg);
 856                 packet_reg += 4;
 857
 858                 writel(buffer[i + 3] << 0 |
 859                        buffer[i + 4] << 8 |
 860                        buffer[i + 5] << 16 |
 861                        buffer[i + 6] << 24,
 862                        base + packet_reg);
 863                 packet_reg += 4;
 864         }
 865
 866         /*
 867          * clear remainder of packet ram as it's included in the
 868          * infoframe and triggers a checksum error on hdmi analyser
 869          */
 870         for (; packet_reg < packet_reg_next; packet_reg += 4)
 871                 writel(0, base + packet_reg);
 872
 873         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 874                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 875
 876         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 877
 878         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 879                         BIT(packet_id)), 100);
 880         if (ret)
 881                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 882
 883 out:
 884         drm_dev_exit(idx);
 885 }
 886
 887 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
 888                                               enum vc4_hdmi_output_format fmt)
 889 {
 890         switch (fmt) {
 891         case VC4_HDMI_OUTPUT_RGB:
 892                 frame->colorspace = HDMI_COLORSPACE_RGB;
 893                 break;
 894
 895         case VC4_HDMI_OUTPUT_YUV420:
 896                 frame->colorspace = HDMI_COLORSPACE_YUV420;
 897                 break;
 898
 899         case VC4_HDMI_OUTPUT_YUV422:
 900                 frame->colorspace = HDMI_COLORSPACE_YUV422;
 901                 break;
 902
 903         case VC4_HDMI_OUTPUT_YUV444:
 904                 frame->colorspace = HDMI_COLORSPACE_YUV444;
 905                 break;
 906
 907         default:
 908                 break;
 909         }
 910 }
 911
 912 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 913 {
 914         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 915         struct drm_connector *connector = &vc4_hdmi->connector;
 916         struct drm_connector_state *cstate = connector->state;
 917         struct vc4_hdmi_connector_state *vc4_state =
 918                 conn_state_to_vc4_hdmi_conn_state(cstate);
 919         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 920         union hdmi_infoframe frame;
 921         int ret;
 922
 923         lockdep_assert_held(&vc4_hdmi->mutex);
 924
 925         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 926                                                        connector, mode);
 927         if (ret < 0) {
 928                 DRM_ERROR("couldn't fill AVI infoframe\n");
 929                 return;
 930         }
 931
 932         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 933                                            connector, mode,
 934                                            vc4_hdmi_is_full_range(vc4_hdmi, vc4_state) ?
 935                                            HDMI_QUANTIZATION_RANGE_FULL :
 936                                            HDMI_QUANTIZATION_RANGE_LIMITED);
 937         drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
 938         vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format);
 939         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 940
 941         vc4_hdmi_write_infoframe(encoder, &frame);
 942 }
 943
 944 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 945 {
 946         union hdmi_infoframe frame;
 947         int ret;
 948
 949         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 950         if (ret < 0) {
 951                 DRM_ERROR("couldn't fill SPD infoframe\n");
 952                 return;
 953         }
 954
 955         frame.spd.sdi = HDMI_SPD_SDI_PC;
 956
 957         vc4_hdmi_write_infoframe(encoder, &frame);
 958 }
 959
 960 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 961 {
 962         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 963         struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
 964         union hdmi_infoframe frame;
 965
 966         memcpy(&frame.audio, audio, sizeof(*audio));
 967
 968         if (vc4_hdmi->packet_ram_enabled)
 969                 vc4_hdmi_write_infoframe(encoder, &frame);
 970 }
 971
 972 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 973 {
 974         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 975         struct drm_connector *connector = &vc4_hdmi->connector;
 976         struct drm_connector_state *conn_state = connector->state;
 977         union hdmi_infoframe frame;
 978
 979         lockdep_assert_held(&vc4_hdmi->mutex);
 980
 981         if (!vc4_hdmi->variant->supports_hdr)
 982                 return;
 983
 984         if (!conn_state->hdr_output_metadata)
 985                 return;
 986
 987         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 988                 return;
 989
 990         vc4_hdmi_write_infoframe(encoder, &frame);
 991 }
 992
 993 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 994 {
 995         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 996
 997         lockdep_assert_held(&vc4_hdmi->mutex);
 998
 999         vc4_hdmi_set_avi_infoframe(encoder);
1000         vc4_hdmi_set_spd_infoframe(encoder);
1001         /*
1002          * If audio was streaming, then we need to reenabled the audio
1003          * infoframe here during encoder_enable.
1004          */
1005         if (vc4_hdmi->audio.streaming)
1006                 vc4_hdmi_set_audio_infoframe(encoder);
1007
1008         vc4_hdmi_set_hdr_infoframe(encoder);
1009 }
1010
1011 #define SCRAMBLING_POLLING_DELAY_MS     1000
1012
1013 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
1014 {
1015         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1016         struct drm_connector *connector = &vc4_hdmi->connector;
1017         struct drm_device *drm = connector->dev;
1018         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1019         unsigned long flags;
1020         int idx;
1021
1022         lockdep_assert_held(&vc4_hdmi->mutex);
1023
1024         if (!vc4_hdmi_supports_scrambling(vc4_hdmi))
1025                 return;
1026
1027         if (!vc4_hdmi_mode_needs_scrambling(mode,
1028                                             vc4_hdmi->output_bpc,
1029                                             vc4_hdmi->output_format))
1030                 return;
1031
1032         if (!drm_dev_enter(drm, &idx))
1033                 return;
1034
1035         drm_scdc_set_high_tmds_clock_ratio(connector, true);
1036         drm_scdc_set_scrambling(connector, true);
1037
1038         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1039         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
1040                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
1041         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1042
1043         drm_dev_exit(idx);
1044
1045         vc4_hdmi->scdc_enabled = true;
1046
1047         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
1048                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
1049 }
1050
1051 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
1052 {
1053         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1054         struct drm_connector *connector = &vc4_hdmi->connector;
1055         struct drm_device *drm = connector->dev;
1056         unsigned long flags;
1057         int idx;
1058
1059         lockdep_assert_held(&vc4_hdmi->mutex);
1060
1061         if (!vc4_hdmi->scdc_enabled)
1062                 return;
1063
1064         vc4_hdmi->scdc_enabled = false;
1065
1066         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
1067                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
1068
1069         if (!drm_dev_enter(drm, &idx))
1070                 return;
1071
1072         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1073         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
1074                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
1075         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1076
1077         drm_scdc_set_scrambling(connector, false);
1078         drm_scdc_set_high_tmds_clock_ratio(connector, false);
1079
1080         drm_dev_exit(idx);
1081 }
1082
1083 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
1084 {
1085         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
1086                                                  struct vc4_hdmi,
1087                                                  scrambling_work);
1088         struct drm_connector *connector = &vc4_hdmi->connector;
1089
1090         if (drm_scdc_get_scrambling_status(connector))
1091                 return;
1092
1093         drm_scdc_set_high_tmds_clock_ratio(connector, true);
1094         drm_scdc_set_scrambling(connector, true);
1095
1096         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
1097                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
1098 }
1099
1100 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
1101                                                struct drm_atomic_state *state)
1102 {
1103         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1104         struct drm_device *drm = vc4_hdmi->connector.dev;
1105         struct vc4_dev *vc4 = to_vc4_dev(drm);
1106         unsigned long flags;
1107         int idx;
1108
1109         mutex_lock(&vc4_hdmi->mutex);
1110
1111         vc4_hdmi->packet_ram_enabled = false;
1112
1113         if (!drm_dev_enter(drm, &idx))
1114                 goto out;
1115
1116         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1117
1118         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
1119
1120         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
1121
1122         if (vc4->gen >= VC4_GEN_6)
1123                 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
1124                            VC4_HD_VID_CTL_BLANKPIX);
1125
1126         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1127
1128         mdelay(1);
1129
1130         /*
1131          * TODO: This should work on BCM2712, but doesn't for some
1132          * reason and result in a system lockup.
1133          */
1134         if (vc4->gen < VC4_GEN_6) {
1135                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1136                 HDMI_WRITE(HDMI_VID_CTL,
1137                            HDMI_READ(HDMI_VID_CTL) &
1138                            ~VC4_HD_VID_CTL_ENABLE);
1139                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1140         }
1141
1142         vc4_hdmi_disable_scrambling(encoder);
1143
1144         drm_dev_exit(idx);
1145
1146 out:
1147         mutex_unlock(&vc4_hdmi->mutex);
1148 }
1149
1150 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
1151                                                  struct drm_atomic_state *state)
1152 {
1153         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1154         struct drm_device *drm = vc4_hdmi->connector.dev;
1155         unsigned long flags;
1156         int ret;
1157         int idx;
1158
1159         mutex_lock(&vc4_hdmi->mutex);
1160
1161         if (!drm_dev_enter(drm, &idx))
1162                 goto out;
1163
1164         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1165         HDMI_WRITE(HDMI_VID_CTL,
1166                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
1167         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1168
1169         if (vc4_hdmi->variant->phy_disable)
1170                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
1171
1172         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
1173         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1174
1175         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
1176         if (ret < 0)
1177                 DRM_ERROR("Failed to release power domain: %d\n", ret);
1178
1179         drm_dev_exit(idx);
1180
1181 out:
1182         mutex_unlock(&vc4_hdmi->mutex);
1183 }
1184
1185 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1186                                struct drm_connector_state *state,
1187                                const struct drm_display_mode *mode)
1188 {
1189         struct vc4_hdmi_connector_state *vc4_state =
1190                 conn_state_to_vc4_hdmi_conn_state(state);
1191         struct drm_device *drm = vc4_hdmi->connector.dev;
1192         unsigned long flags;
1193         u32 csc_ctl;
1194         int idx;
1195
1196         if (!drm_dev_enter(drm, &idx))
1197                 return;
1198
1199         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1200
1201         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
1202                                 VC4_HD_CSC_CTL_ORDER);
1203
1204         if (!vc4_hdmi_is_full_range(vc4_hdmi, vc4_state)) {
1205                 /* CEA VICs other than #1 requre limited range RGB
1206                  * output unless overridden by an AVI infoframe.
1207                  * Apply a colorspace conversion to squash 0-255 down
1208                  * to 16-235.  The matrix here is:
1209                  *
1210                  * [ 0      0      0.8594 16]
1211                  * [ 0      0.8594 0      16]
1212                  * [ 0.8594 0      0      16]
1213                  * [ 0      0      0       1]
1214                  */
1215                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
1216                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
1217                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1218                                          VC4_HD_CSC_CTL_MODE);
1219
1220                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
1221                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
1222                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
1223                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
1224                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
1225                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
1226         }
1227
1228         /* The RGB order applies even when CSC is disabled. */
1229         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1230
1231         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1232
1233         drm_dev_exit(idx);
1234 }
1235
1236 /*
1237  * Matrices for (internal) RGB to RGB output.
1238  *
1239  * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1240  */
1241 static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = {
1242         {
1243                 /*
1244                  * Full range - unity
1245                  *
1246                  * [ 1      0      0      0]
1247                  * [ 0      1      0      0]
1248                  * [ 0      0      1      0]
1249                  */
1250                 { 0x2000, 0x0000, 0x0000, 0x0000 },
1251                 { 0x0000, 0x2000, 0x0000, 0x0000 },
1252                 { 0x0000, 0x0000, 0x2000, 0x0000 },
1253         },
1254         {
1255                 /*
1256                  * Limited range
1257                  *
1258                  * CEA VICs other than #1 require limited range RGB
1259                  * output unless overridden by an AVI infoframe. Apply a
1260                  * colorspace conversion to squash 0-255 down to 16-235.
1261                  * The matrix here is:
1262                  *
1263                  * [ 0.8594 0      0      16]
1264                  * [ 0      0.8594 0      16]
1265                  * [ 0      0      0.8594 16]
1266                  */
1267                 { 0x1b80, 0x0000, 0x0000, 0x0400 },
1268                 { 0x0000, 0x1b80, 0x0000, 0x0400 },
1269                 { 0x0000, 0x0000, 0x1b80, 0x0400 },
1270         },
1271 };
1272
1273 /*
1274  * Conversion between Full Range RGB and YUV using the BT.601 Colorspace
1275  *
1276  * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1277  */
1278 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = {
1279         {
1280                 /*
1281                  * Full Range
1282                  *
1283                  * [  0.299000  0.587000  0.114000  0   ]
1284                  * [ -0.168736 -0.331264  0.500000  128 ]
1285                  * [  0.500000 -0.418688 -0.081312  128 ]
1286                  */
1287                 { 0x0991, 0x12c9, 0x03a6, 0x0000 },
1288                 { 0xfa9b, 0xf567, 0x1000, 0x2000 },
1289                 { 0x1000, 0xf29b, 0xfd67, 0x2000 },
1290         },
1291         {
1292                 /* Limited Range
1293                  *
1294                  * [  0.255785  0.502160  0.097523  16  ]
1295                  * [ -0.147644 -0.289856  0.437500  128 ]
1296                  * [  0.437500 -0.366352 -0.071148  128 ]
1297                  */
1298                 { 0x082f, 0x1012, 0x031f, 0x0400 },
1299                 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1300                 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1301         },
1302 };
1303
1304 /*
1305  * Conversion between Full Range RGB and YUV using the BT.709 Colorspace
1306  *
1307  * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1308  */
1309 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = {
1310         {
1311                 /*
1312                  * Full Range
1313                  *
1314                  * [  0.212600  0.715200  0.072200  0   ]
1315                  * [ -0.114572 -0.385428  0.500000  128 ]
1316                  * [  0.500000 -0.454153 -0.045847  128 ]
1317                  */
1318                 { 0x06ce, 0x16e3, 0x024f, 0x0000 },
1319                 { 0xfc56, 0xf3ac, 0x1000, 0x2000 },
1320                 { 0x1000, 0xf179, 0xfe89, 0x2000 },
1321         },
1322         {
1323                 /*
1324                  * Limited Range
1325                  *
1326                  * [  0.181906  0.611804  0.061758  16  ]
1327                  * [ -0.100268 -0.337232  0.437500  128 ]
1328                  * [  0.437500 -0.397386 -0.040114  128 ]
1329                  */
1330                 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1331                 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1332                 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1333         },
1334 };
1335
1336 /*
1337  * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace
1338  *
1339  * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1340  */
1341 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = {
1342         {
1343                 /*
1344                  * Full Range
1345                  *
1346                  * [  0.262700  0.678000  0.059300  0   ]
1347                  * [ -0.139630 -0.360370  0.500000  128 ]
1348                  * [  0.500000 -0.459786 -0.040214  128 ]
1349                  */
1350                 { 0x0868, 0x15b2, 0x01e6, 0x0000 },
1351                 { 0xfb89, 0xf479, 0x1000, 0x2000 },
1352                 { 0x1000, 0xf14a, 0xfeb8, 0x2000 },
1353         },
1354         {
1355                 /* Limited Range
1356                  *
1357                  * [  0.224732  0.580008  0.050729  16  ]
1358                  * [ -0.122176 -0.315324  0.437500  128 ]
1359                  * [  0.437500 -0.402312 -0.035188  128 ]
1360                  */
1361                 { 0x082f, 0x1012, 0x031f, 0x0400 },
1362                 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1363                 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1364         },
1365 };
1366
1367 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1368                                     const u16 coeffs[3][4])
1369 {
1370         lockdep_assert_held(&vc4_hdmi->hw_lock);
1371
1372         HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1373         HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1374         HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1375         HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1376         HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1377         HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1378 }
1379
1380 static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi,
1381                                          const u16 coeffs[3][4])
1382 {
1383         lockdep_assert_held(&vc4_hdmi->hw_lock);
1384
1385         /* YUV444 needs the CSC matrices using the channels in a different order */
1386         HDMI_WRITE(HDMI_CSC_12_11, (coeffs[1][1] << 16) | coeffs[1][0]);
1387         HDMI_WRITE(HDMI_CSC_14_13, (coeffs[1][3] << 16) | coeffs[1][2]);
1388         HDMI_WRITE(HDMI_CSC_22_21, (coeffs[2][1] << 16) | coeffs[2][0]);
1389         HDMI_WRITE(HDMI_CSC_24_23, (coeffs[2][3] << 16) | coeffs[2][2]);
1390         HDMI_WRITE(HDMI_CSC_32_31, (coeffs[0][1] << 16) | coeffs[0][0]);
1391         HDMI_WRITE(HDMI_CSC_34_33, (coeffs[0][3] << 16) | coeffs[0][2]);
1392 }
1393
1394 static const u16
1395 (*vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi *vc4_hdmi, u32 colorspace, bool limited))[4]
1396 {
1397         switch (colorspace) {
1398         case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC:
1399         case DRM_MODE_COLORIMETRY_XVYCC_601:
1400         case DRM_MODE_COLORIMETRY_SYCC_601:
1401         case DRM_MODE_COLORIMETRY_OPYCC_601:
1402         case DRM_MODE_COLORIMETRY_BT601_YCC:
1403                 return vc5_hdmi_csc_full_rgb_to_yuv_bt601[limited];
1404
1405         default:
1406         case DRM_MODE_COLORIMETRY_NO_DATA:
1407         case DRM_MODE_COLORIMETRY_BT709_YCC:
1408         case DRM_MODE_COLORIMETRY_XVYCC_709:
1409         case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED:
1410         case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT:
1411                 return vc5_hdmi_csc_full_rgb_to_yuv_bt709[limited];
1412
1413         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1414         case DRM_MODE_COLORIMETRY_BT2020_YCC:
1415         case DRM_MODE_COLORIMETRY_BT2020_RGB:
1416         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1417         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1418                 return vc5_hdmi_csc_full_rgb_to_yuv_bt2020[limited];
1419         }
1420 }
1421
1422 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1423                                struct drm_connector_state *state,
1424                                const struct drm_display_mode *mode)
1425 {
1426         struct drm_device *drm = vc4_hdmi->connector.dev;
1427         struct vc4_hdmi_connector_state *vc4_state =
1428                 conn_state_to_vc4_hdmi_conn_state(state);
1429         unsigned int lim_range = vc4_hdmi_is_full_range(vc4_hdmi, vc4_state) ? 0 : 1;
1430         unsigned long flags;
1431         const u16 (*csc)[4];
1432         u32 if_cfg = 0;
1433         u32 if_xbar = 0x543210;
1434         u32 csc_chan_ctl = 0;
1435         u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1436                                                                VC5_MT_CP_CSC_CTL_MODE);
1437         int idx;
1438
1439         if (!drm_dev_enter(drm, &idx))
1440                 return;
1441
1442         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1443
1444         switch (vc4_state->output_format) {
1445         case VC4_HDMI_OUTPUT_YUV444:
1446                 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1447
1448                 vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc);
1449                 break;
1450
1451         case VC4_HDMI_OUTPUT_YUV422:
1452                 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1453
1454                 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1455                                          VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1456                         VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1457                         VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1458
1459                 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1460                                               VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1461
1462                 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1463                                         VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1464
1465                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc);
1466                 break;
1467
1468         case VC4_HDMI_OUTPUT_RGB:
1469                 if_xbar = 0x354021;
1470
1471                 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_rgb[lim_range]);
1472                 break;
1473
1474         default:
1475                 break;
1476         }
1477
1478         HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1479         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1480         HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1481         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1482
1483         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1484
1485         drm_dev_exit(idx);
1486 }
1487
1488 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1489                                  struct drm_connector_state *state,
1490                                  const struct drm_display_mode *mode)
1491 {
1492         struct drm_device *drm = vc4_hdmi->connector.dev;
1493         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1494         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1495         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1496         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1497         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1498                                    VC4_HDMI_VERTA_VSP) |
1499                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1500                                    VC4_HDMI_VERTA_VFP) |
1501                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1502         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1503                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1504                                    interlaced,
1505                                    VC4_HDMI_VERTB_VBP));
1506         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1507                           VC4_SET_FIELD(mode->crtc_vtotal -
1508                                         mode->crtc_vsync_end,
1509                                         VC4_HDMI_VERTB_VBP));
1510         unsigned long flags;
1511         u32 reg;
1512         int idx;
1513
1514         if (!drm_dev_enter(drm, &idx))
1515                 return;
1516
1517         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1518
1519         HDMI_WRITE(HDMI_HORZA,
1520                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1521                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1522                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1523                                  VC4_HDMI_HORZA_HAP));
1524
1525         HDMI_WRITE(HDMI_HORZB,
1526                    VC4_SET_FIELD((mode->htotal -
1527                                   mode->hsync_end) * pixel_rep,
1528                                  VC4_HDMI_HORZB_HBP) |
1529                    VC4_SET_FIELD((mode->hsync_end -
1530                                   mode->hsync_start) * pixel_rep,
1531                                  VC4_HDMI_HORZB_HSP) |
1532                    VC4_SET_FIELD((mode->hsync_start -
1533                                   mode->hdisplay) * pixel_rep,
1534                                  VC4_HDMI_HORZB_HFP));
1535
1536         HDMI_WRITE(HDMI_VERTA0, verta);
1537         HDMI_WRITE(HDMI_VERTA1, verta);
1538
1539         HDMI_WRITE(HDMI_VERTB0, vertb_even);
1540         HDMI_WRITE(HDMI_VERTB1, vertb);
1541
1542         reg = HDMI_READ(HDMI_MISC_CONTROL);
1543         reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1544         reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1545         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1546
1547         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1548
1549         drm_dev_exit(idx);
1550 }
1551
1552 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1553                                  struct drm_connector_state *state,
1554                                  const struct drm_display_mode *mode)
1555 {
1556         struct drm_device *drm = vc4_hdmi->connector.dev;
1557         const struct vc4_hdmi_connector_state *vc4_state =
1558                 conn_state_to_vc4_hdmi_conn_state(state);
1559         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1560         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1561         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1562         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1563         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1564                                    VC5_HDMI_VERTA_VSP) |
1565                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1566                                    VC5_HDMI_VERTA_VFP) |
1567                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1568         u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1569                                    VC5_HDMI_VERTB_VSPO) |
1570                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1571                                    interlaced,
1572                                    VC4_HDMI_VERTB_VBP));
1573         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1574                           VC4_SET_FIELD(mode->crtc_vtotal -
1575                                         mode->crtc_vsync_end,
1576                                         VC4_HDMI_VERTB_VBP));
1577         unsigned long flags;
1578         unsigned char gcp;
1579         u32 reg;
1580         int idx;
1581
1582         if (!drm_dev_enter(drm, &idx))
1583                 return;
1584
1585         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1586
1587         HDMI_WRITE(HDMI_HORZA,
1588                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1589                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1590                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1591                                  VC5_HDMI_HORZA_HAP) |
1592                    VC4_SET_FIELD((mode->hsync_start -
1593                                   mode->hdisplay) * pixel_rep,
1594                                  VC5_HDMI_HORZA_HFP));
1595
1596         HDMI_WRITE(HDMI_HORZB,
1597                    VC4_SET_FIELD((mode->htotal -
1598                                   mode->hsync_end) * pixel_rep,
1599                                  VC5_HDMI_HORZB_HBP) |
1600                    VC4_SET_FIELD((mode->hsync_end -
1601                                   mode->hsync_start) * pixel_rep,
1602                                  VC5_HDMI_HORZB_HSP));
1603
1604         HDMI_WRITE(HDMI_VERTA0, verta);
1605         HDMI_WRITE(HDMI_VERTA1, verta);
1606
1607         HDMI_WRITE(HDMI_VERTB0, vertb_even);
1608         HDMI_WRITE(HDMI_VERTB1, vertb);
1609
1610         switch (vc4_state->output_bpc) {
1611         case 12:
1612                 gcp = 6;
1613                 break;
1614         case 10:
1615                 gcp = 5;
1616                 break;
1617         case 8:
1618         default:
1619                 gcp = 0;
1620                 break;
1621         }
1622
1623         /*
1624          * YCC422 is always 36-bit and not considered deep colour so
1625          * doesn't signal in GCP.
1626          */
1627         if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {
1628                 gcp = 0;
1629         }
1630
1631         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1632         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1633                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1634         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1635                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1636         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1637
1638         reg = HDMI_READ(HDMI_GCP_WORD_1);
1639         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1640         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1641         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK;
1642         reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE;
1643         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1644
1645         reg = HDMI_READ(HDMI_GCP_CONFIG);
1646         reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1647         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1648
1649         reg = HDMI_READ(HDMI_MISC_CONTROL);
1650         reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1651         reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1652         HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1653
1654         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1655
1656         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1657
1658         drm_dev_exit(idx);
1659 }
1660
1661 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1662 {
1663         struct drm_device *drm = vc4_hdmi->connector.dev;
1664         unsigned long flags;
1665         u32 drift;
1666         int ret;
1667         int idx;
1668
1669         if (!drm_dev_enter(drm, &idx))
1670                 return;
1671
1672         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1673
1674         drift = HDMI_READ(HDMI_FIFO_CTL);
1675         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1676
1677         HDMI_WRITE(HDMI_FIFO_CTL,
1678                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1679         HDMI_WRITE(HDMI_FIFO_CTL,
1680                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1681
1682         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1683
1684         usleep_range(1000, 1100);
1685
1686         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1687
1688         HDMI_WRITE(HDMI_FIFO_CTL,
1689                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1690         HDMI_WRITE(HDMI_FIFO_CTL,
1691                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
1692
1693         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1694
1695         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1696                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1697         WARN_ONCE(ret, "Timeout waiting for "
1698                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1699
1700         drm_dev_exit(idx);
1701 }
1702
1703 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1704                                                 struct drm_atomic_state *state)
1705 {
1706         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1707         struct drm_device *drm = vc4_hdmi->connector.dev;
1708         struct drm_connector *connector = &vc4_hdmi->connector;
1709         struct drm_connector_state *conn_state =
1710                 drm_atomic_get_new_connector_state(state, connector);
1711         struct vc4_hdmi_connector_state *vc4_conn_state =
1712                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1713         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1714         unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate;
1715         unsigned long bvb_rate, hsm_rate;
1716         unsigned long flags;
1717         int ret;
1718         int idx;
1719
1720         mutex_lock(&vc4_hdmi->mutex);
1721
1722         if (!drm_dev_enter(drm, &idx))
1723                 goto out;
1724
1725         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1726         if (ret < 0) {
1727                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1728                 goto err_dev_exit;
1729         }
1730
1731         /*
1732          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1733          * be faster than pixel clock, infinitesimally faster, tested in
1734          * simulation. Otherwise, exact value is unimportant for HDMI
1735          * operation." This conflicts with bcm2835's vc4 documentation, which
1736          * states HSM's clock has to be at least 108% of the pixel clock.
1737          *
1738          * Real life tests reveal that vc4's firmware statement holds up, and
1739          * users are able to use pixel clocks closer to HSM's, namely for
1740          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1741          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1742          * 162MHz.
1743          *
1744          * Additionally, the AXI clock needs to be at least 25% of
1745          * pixel clock, but HSM ends up being the limiting factor.
1746          */
1747         hsm_rate = max_t(unsigned long,
1748                          HSM_MIN_CLOCK_FREQ,
1749                          (tmds_char_rate / 100) * 101);
1750         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1751         if (ret) {
1752                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1753                 goto err_put_runtime_pm;
1754         }
1755
1756         ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1757         if (ret) {
1758                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1759                 goto err_put_runtime_pm;
1760         }
1761
1762         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1763         if (ret) {
1764                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1765                 goto err_put_runtime_pm;
1766         }
1767
1768         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1769
1770         if (tmds_char_rate > 297000000)
1771                 bvb_rate = 300000000;
1772         else if (tmds_char_rate > 148500000)
1773                 bvb_rate = 150000000;
1774         else
1775                 bvb_rate = 75000000;
1776
1777         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1778         if (ret) {
1779                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1780                 goto err_disable_pixel_clock;
1781         }
1782
1783         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1784         if (ret) {
1785                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1786                 goto err_disable_pixel_clock;
1787         }
1788
1789         if (vc4_hdmi->variant->phy_init)
1790                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1791
1792         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1793
1794         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1795                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1796                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1797                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1798
1799         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1800
1801         if (vc4_hdmi->variant->set_timings)
1802                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1803
1804         drm_dev_exit(idx);
1805
1806         mutex_unlock(&vc4_hdmi->mutex);
1807
1808         return;
1809
1810 err_disable_pixel_clock:
1811         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1812 err_put_runtime_pm:
1813         pm_runtime_put(&vc4_hdmi->pdev->dev);
1814 err_dev_exit:
1815         drm_dev_exit(idx);
1816 out:
1817         mutex_unlock(&vc4_hdmi->mutex);
1818         return;
1819 }
1820
1821 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1822                                              struct drm_atomic_state *state)
1823 {
1824         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1825         struct drm_device *drm = vc4_hdmi->connector.dev;
1826         struct drm_connector *connector = &vc4_hdmi->connector;
1827         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1828         struct drm_connector_state *conn_state =
1829                 drm_atomic_get_new_connector_state(state, connector);
1830         unsigned long flags;
1831         int idx;
1832
1833         mutex_lock(&vc4_hdmi->mutex);
1834
1835         if (!drm_dev_enter(drm, &idx))
1836                 goto out;
1837
1838         if (vc4_hdmi->variant->csc_setup)
1839                 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1840
1841         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1842         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1843         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1844
1845         drm_dev_exit(idx);
1846
1847 out:
1848         mutex_unlock(&vc4_hdmi->mutex);
1849 }
1850
1851 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1852                                               struct drm_atomic_state *state)
1853 {
1854         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1855         struct drm_device *drm = vc4_hdmi->connector.dev;
1856         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1857         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1858         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1859         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1860         unsigned long flags;
1861         int ret;
1862         int idx;
1863
1864         mutex_lock(&vc4_hdmi->mutex);
1865
1866         if (!drm_dev_enter(drm, &idx))
1867                 goto out;
1868
1869         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1870
1871         HDMI_WRITE(HDMI_VID_CTL,
1872                    HDMI_READ(HDMI_VID_CTL) |
1873                    VC4_HD_VID_CTL_ENABLE |
1874                    VC4_HD_VID_CTL_CLRRGB |
1875                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1876                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1877                    VC4_HD_VID_CTL_BLANK_INSERT_EN |
1878                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1879                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1880
1881         HDMI_WRITE(HDMI_VID_CTL,
1882                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1883
1884         if (display->is_hdmi) {
1885                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1886                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1887                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1888
1889                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1890
1891                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1892                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1893                 WARN_ONCE(ret, "Timeout waiting for "
1894                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1895         } else {
1896                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1897                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1898                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1899                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1900                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1901                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1902
1903                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1904
1905                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1906                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1907                 WARN_ONCE(ret, "Timeout waiting for "
1908                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1909         }
1910
1911         if (display->is_hdmi) {
1912                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1913
1914                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1915                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1916
1917                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1918                            VC4_HDMI_RAM_PACKET_ENABLE);
1919
1920                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1921                 vc4_hdmi->packet_ram_enabled = true;
1922
1923                 vc4_hdmi_set_infoframes(encoder);
1924         }
1925
1926         vc4_hdmi_recenter_fifo(vc4_hdmi);
1927         vc4_hdmi_enable_scrambling(encoder);
1928
1929         drm_dev_exit(idx);
1930
1931 out:
1932         mutex_unlock(&vc4_hdmi->mutex);
1933 }
1934
1935 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1936                                              struct drm_crtc_state *crtc_state,
1937                                              struct drm_connector_state *conn_state)
1938 {
1939         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1940         struct vc4_hdmi_connector_state *vc4_state =
1941                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1942
1943         mutex_lock(&vc4_hdmi->mutex);
1944         drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1945                       &crtc_state->adjusted_mode);
1946         vc4_hdmi->output_bpc = vc4_state->output_bpc;
1947         vc4_hdmi->output_format = vc4_state->output_format;
1948         mutex_unlock(&vc4_hdmi->mutex);
1949 }
1950
1951 static bool
1952 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi,
1953                                   const struct drm_display_info *info,
1954                                   const struct drm_display_mode *mode,
1955                                   unsigned int format, unsigned int bpc)
1956 {
1957         struct drm_device *dev = vc4_hdmi->connector.dev;
1958         u8 vic = drm_match_cea_mode(mode);
1959
1960         if (vic == 1 && bpc != 8) {
1961                 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc);
1962                 return false;
1963         }
1964
1965         if (!info->is_hdmi &&
1966             (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) {
1967                 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n");
1968                 return false;
1969         }
1970
1971         switch (format) {
1972         case VC4_HDMI_OUTPUT_RGB:
1973                 drm_dbg(dev, "RGB Format, checking the constraints.\n");
1974
1975                 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1976                         drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1977                         return false;
1978                 }
1979
1980                 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1981                         drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1982                         return false;
1983                 }
1984
1985                 drm_dbg(dev, "RGB format supported in that configuration.\n");
1986
1987                 return true;
1988
1989         case VC4_HDMI_OUTPUT_YUV422:
1990                 drm_dbg(dev, "YUV422 format, checking the constraints.\n");
1991
1992                 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) {
1993                         drm_dbg(dev, "Sink doesn't support YUV422.\n");
1994                         return false;
1995                 }
1996
1997                 if (bpc != 12) {
1998                         drm_dbg(dev, "YUV422 only supports 12 bpc.\n");
1999                         return false;
2000                 }
2001
2002                 drm_dbg(dev, "YUV422 format supported in that configuration.\n");
2003
2004                 return true;
2005
2006         case VC4_HDMI_OUTPUT_YUV444:
2007                 drm_dbg(dev, "YUV444 format, checking the constraints.\n");
2008
2009                 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) {
2010                         drm_dbg(dev, "Sink doesn't support YUV444.\n");
2011                         return false;
2012                 }
2013
2014                 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) {
2015                         drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
2016                         return false;
2017                 }
2018
2019                 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) {
2020                         drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
2021                         return false;
2022                 }
2023
2024                 drm_dbg(dev, "YUV444 format supported in that configuration.\n");
2025
2026                 return true;
2027         }
2028
2029         return false;
2030 }
2031
2032 static enum drm_mode_status
2033 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
2034                              const struct drm_display_mode *mode,
2035                              unsigned long long clock)
2036 {
2037         const struct drm_connector *connector = &vc4_hdmi->connector;
2038         const struct drm_display_info *info = &connector->display_info;
2039         struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
2040
2041         if (clock > vc4_hdmi->variant->max_pixel_clock)
2042                 return MODE_CLOCK_HIGH;
2043
2044         if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK)
2045                 return MODE_CLOCK_HIGH;
2046
2047         /* 4096x2160@60 is not reliable without overclocking core */
2048         if (!vc4->hvs->vc5_hdmi_enable_4096by2160 &&
2049             mode->hdisplay > 3840 && mode->vdisplay >= 2160 &&
2050             drm_mode_vrefresh(mode) >= 50)
2051                 return MODE_CLOCK_HIGH;
2052
2053         if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000))
2054                 return MODE_CLOCK_HIGH;
2055
2056         return MODE_OK;
2057 }
2058
2059 static unsigned long long
2060 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
2061                                     unsigned int bpc,
2062                                     enum vc4_hdmi_output_format fmt)
2063 {
2064         unsigned long long clock = mode->clock * 1000ULL;
2065
2066         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2067                 clock = clock * 2;
2068
2069         if (fmt == VC4_HDMI_OUTPUT_YUV422)
2070                 bpc = 8;
2071
2072         clock = clock * bpc;
2073         do_div(clock, 8);
2074
2075         return clock;
2076 }
2077
2078 static int
2079 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
2080                                struct vc4_hdmi_connector_state *vc4_state,
2081                                const struct drm_display_mode *mode,
2082                                unsigned int bpc, unsigned int fmt)
2083 {
2084         unsigned long long clock;
2085
2086         clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
2087         if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, clock) != MODE_OK)
2088                 return -EINVAL;
2089
2090         vc4_state->tmds_char_rate = clock;
2091
2092         return 0;
2093 }
2094
2095 static int
2096 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi,
2097                                 struct vc4_hdmi_connector_state *vc4_state,
2098                                 const struct drm_display_mode *mode,
2099                                 unsigned int bpc)
2100 {
2101         struct drm_device *dev = vc4_hdmi->connector.dev;
2102         const struct drm_connector *connector = &vc4_hdmi->connector;
2103         const struct drm_display_info *info = &connector->display_info;
2104         unsigned int format;
2105
2106         drm_dbg(dev, "Trying with an RGB output\n");
2107
2108         format = VC4_HDMI_OUTPUT_RGB;
2109         if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
2110                 int ret;
2111
2112                 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
2113                                                      mode, bpc, format);
2114                 if (!ret) {
2115                         vc4_state->output_format = format;
2116                         return 0;
2117                 }
2118         }
2119
2120         drm_dbg(dev, "Failed, Trying with an YUV422 output\n");
2121
2122         format = VC4_HDMI_OUTPUT_YUV422;
2123         if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
2124                 int ret;
2125
2126                 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
2127                                                      mode, bpc, format);
2128                 if (!ret) {
2129                         vc4_state->output_format = format;
2130                         return 0;
2131                 }
2132         }
2133
2134         drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n");
2135
2136         return -EINVAL;
2137 }
2138
2139 static int
2140 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi,
2141                                 struct vc4_hdmi_connector_state *vc4_state,
2142                                 const struct drm_display_mode *mode)
2143 {
2144         struct drm_device *dev = vc4_hdmi->connector.dev;
2145         struct drm_connector_state *conn_state = &vc4_state->base;
2146         unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_requested_bpc, 8, 12);
2147         unsigned int bpc;
2148         int ret;
2149
2150         for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
2151                 drm_dbg(dev, "Trying with a %d bpc output\n", bpc);
2152
2153                 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state,
2154                                                       mode, bpc);
2155                 if (ret)
2156                         continue;
2157
2158                 vc4_state->output_bpc = bpc;
2159
2160                 drm_dbg(dev,
2161                         "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n",
2162                         mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
2163                         vc4_state->output_bpc,
2164                         vc4_hdmi_output_fmt_str(vc4_state->output_format),
2165                         vc4_state->tmds_char_rate);
2166
2167                 break;
2168         }
2169
2170         return ret;
2171 }
2172
2173 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
2174 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
2175
2176 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
2177                                          struct drm_crtc_state *crtc_state,
2178                                          struct drm_connector_state *conn_state)
2179 {
2180         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
2181         struct drm_connector *connector = &vc4_hdmi->connector;
2182         struct drm_connector_state *old_conn_state =
2183                 drm_atomic_get_old_connector_state(conn_state->state, connector);
2184         struct vc4_hdmi_connector_state *old_vc4_state =
2185                 conn_state_to_vc4_hdmi_conn_state(old_conn_state);
2186         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
2187         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
2188         unsigned long long tmds_char_rate = mode->clock * 1000;
2189         unsigned long long tmds_bit_rate;
2190         int ret;
2191
2192         if (vc4_hdmi->variant->unsupported_odd_h_timings) {
2193                 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2194                         /* Only try to fixup DBLCLK modes to get 480i and 576i
2195                          * working.
2196                          * A generic solution for all modes with odd horizontal
2197                          * timing values seems impossible based on trying to
2198                          * solve it for 1366x768 monitors.
2199                          */
2200                         if ((mode->hsync_start - mode->hdisplay) & 1)
2201                                 mode->hsync_start--;
2202                         if ((mode->hsync_end - mode->hsync_start) & 1)
2203                                 mode->hsync_end--;
2204                 }
2205
2206                 /* Now check whether we still have odd values remaining */
2207                 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
2208                     (mode->hsync_end % 2) || (mode->htotal % 2))
2209                         return -EINVAL;
2210         }
2211
2212         /*
2213          * The 1440p@60 pixel rate is in the same range than the first
2214          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
2215          * bandwidth). Slightly lower the frequency to bring it out of
2216          * the WiFi range.
2217          */
2218         tmds_bit_rate = tmds_char_rate * 10;
2219         if (vc4_hdmi->disable_wifi_frequencies &&
2220             (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
2221              tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
2222                 mode->clock = 238560;
2223                 tmds_char_rate = mode->clock * 1000;
2224         }
2225
2226         ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode);
2227         if (ret)
2228                 return ret;
2229
2230         /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */
2231         if (vc4_state->output_bpc != old_vc4_state->output_bpc ||
2232             vc4_state->output_format != old_vc4_state->output_format)
2233                 crtc_state->mode_changed = true;
2234
2235         return 0;
2236 }
2237
2238 static enum drm_mode_status
2239 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
2240                             const struct drm_display_mode *mode)
2241 {
2242         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
2243
2244         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
2245             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
2246             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
2247              (mode->hsync_end % 2) || (mode->htotal % 2)))
2248                 return MODE_H_ILLEGAL;
2249
2250         return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, mode->clock * 1000);
2251 }
2252
2253 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
2254         .atomic_check = vc4_hdmi_encoder_atomic_check,
2255         .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
2256         .mode_valid = vc4_hdmi_encoder_mode_valid,
2257 };
2258
2259 static int vc4_hdmi_late_register(struct drm_encoder *encoder)
2260 {
2261         struct drm_device *drm = encoder->dev;
2262         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
2263         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2264
2265         drm_debugfs_add_file(drm, variant->debugfs_name,
2266                              vc4_hdmi_debugfs_regs, vc4_hdmi);
2267
2268         return 0;
2269 }
2270
2271 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
2272         .late_register = vc4_hdmi_late_register,
2273 };
2274
2275 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2276 {
2277         int i;
2278         u32 channel_map = 0;
2279
2280         for (i = 0; i < 8; i++) {
2281                 if (channel_mask & BIT(i))
2282                         channel_map |= i << (3 * i);
2283         }
2284         return channel_map;
2285 }
2286
2287 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
2288 {
2289         int i;
2290         u32 channel_map = 0;
2291
2292         for (i = 0; i < 8; i++) {
2293                 if (channel_mask & BIT(i))
2294                         channel_map |= i << (4 * i);
2295         }
2296         return channel_map;
2297 }
2298
2299 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
2300 {
2301         struct drm_device *drm = vc4_hdmi->connector.dev;
2302         unsigned long flags;
2303         u32 hotplug;
2304         int idx;
2305
2306         if (!drm_dev_enter(drm, &idx))
2307                 return false;
2308
2309         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2310         hotplug = HDMI_READ(HDMI_HOTPLUG);
2311         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2312
2313         drm_dev_exit(idx);
2314
2315         return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
2316 }
2317
2318 /* HDMI audio codec callbacks */
2319 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
2320                                          unsigned int samplerate)
2321 {
2322         struct drm_device *drm = vc4_hdmi->connector.dev;
2323         u32 hsm_clock;
2324         unsigned long flags;
2325         unsigned long n, m;
2326         int idx;
2327
2328         if (!drm_dev_enter(drm, &idx))
2329                 return;
2330
2331         hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
2332         rational_best_approximation(hsm_clock, samplerate,
2333                                     VC4_HD_MAI_SMP_N_MASK >>
2334                                     VC4_HD_MAI_SMP_N_SHIFT,
2335                                     (VC4_HD_MAI_SMP_M_MASK >>
2336                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
2337                                     &n, &m);
2338
2339         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2340         HDMI_WRITE(HDMI_MAI_SMP,
2341                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
2342                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
2343         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2344
2345         drm_dev_exit(idx);
2346 }
2347
2348 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
2349 {
2350         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
2351         u32 n, cts;
2352         u64 tmp;
2353
2354         lockdep_assert_held(&vc4_hdmi->mutex);
2355         lockdep_assert_held(&vc4_hdmi->hw_lock);
2356
2357         n = 128 * samplerate / 1000;
2358         tmp = (u64)(mode->clock * 1000) * n;
2359         do_div(tmp, 128 * samplerate);
2360         cts = tmp;
2361
2362         HDMI_WRITE(HDMI_CRP_CFG,
2363                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
2364                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
2365
2366         /*
2367          * We could get slightly more accurate clocks in some cases by
2368          * providing a CTS_1 value.  The two CTS values are alternated
2369          * between based on the period fields
2370          */
2371         HDMI_WRITE(HDMI_CTS_0, cts);
2372         HDMI_WRITE(HDMI_CTS_1, cts);
2373 }
2374
2375 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
2376 {
2377         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
2378
2379         return snd_soc_card_get_drvdata(card);
2380 }
2381
2382 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
2383 {
2384         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
2385
2386         lockdep_assert_held(&vc4_hdmi->mutex);
2387
2388         /*
2389          * If the encoder is currently in DVI mode, treat the codec DAI
2390          * as missing.
2391          */
2392         if (!display->is_hdmi)
2393                 return false;
2394
2395         return true;
2396 }
2397
2398 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
2399 {
2400         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2401         struct drm_device *drm = vc4_hdmi->connector.dev;
2402         unsigned long flags;
2403         int ret = 0;
2404         int idx;
2405
2406         mutex_lock(&vc4_hdmi->mutex);
2407
2408         if (!drm_dev_enter(drm, &idx)) {
2409                 ret = -ENODEV;
2410                 goto out;
2411         }
2412
2413         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2414                 ret = -ENOTSUPP;
2415                 goto out_dev_exit;
2416         }
2417
2418         vc4_hdmi->audio.streaming = true;
2419
2420         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2421         HDMI_WRITE(HDMI_MAI_CTL,
2422                    VC4_HD_MAI_CTL_RESET |
2423                    VC4_HD_MAI_CTL_FLUSH |
2424                    VC4_HD_MAI_CTL_DLATE |
2425                    VC4_HD_MAI_CTL_ERRORE |
2426                    VC4_HD_MAI_CTL_ERRORF);
2427         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2428
2429         if (vc4_hdmi->variant->phy_rng_enable)
2430                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
2431
2432 out_dev_exit:
2433         drm_dev_exit(idx);
2434 out:
2435         mutex_unlock(&vc4_hdmi->mutex);
2436
2437         return ret;
2438 }
2439
2440 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
2441 {
2442         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2443         struct device *dev = &vc4_hdmi->pdev->dev;
2444         unsigned long flags;
2445         int ret;
2446
2447         lockdep_assert_held(&vc4_hdmi->mutex);
2448
2449         vc4_hdmi->audio.streaming = false;
2450         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
2451         if (ret)
2452                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
2453
2454         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2455
2456         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
2457         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
2458         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
2459
2460         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2461 }
2462
2463 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
2464 {
2465         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2466         struct drm_device *drm = vc4_hdmi->connector.dev;
2467         unsigned long flags;
2468         int idx;
2469
2470         mutex_lock(&vc4_hdmi->mutex);
2471
2472         if (!drm_dev_enter(drm, &idx))
2473                 goto out;
2474
2475         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2476
2477         HDMI_WRITE(HDMI_MAI_CTL,
2478                    VC4_HD_MAI_CTL_DLATE |
2479                    VC4_HD_MAI_CTL_ERRORE |
2480                    VC4_HD_MAI_CTL_ERRORF);
2481
2482         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2483
2484         if (vc4_hdmi->variant->phy_rng_disable)
2485                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
2486
2487         vc4_hdmi->audio.streaming = false;
2488         vc4_hdmi_audio_reset(vc4_hdmi);
2489
2490         drm_dev_exit(idx);
2491
2492 out:
2493         mutex_unlock(&vc4_hdmi->mutex);
2494 }
2495
2496 static int sample_rate_to_mai_fmt(int samplerate)
2497 {
2498         switch (samplerate) {
2499         case 8000:
2500                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
2501         case 11025:
2502                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
2503         case 12000:
2504                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
2505         case 16000:
2506                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
2507         case 22050:
2508                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
2509         case 24000:
2510                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
2511         case 32000:
2512                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
2513         case 44100:
2514                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
2515         case 48000:
2516                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
2517         case 64000:
2518                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
2519         case 88200:
2520                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
2521         case 96000:
2522                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
2523         case 128000:
2524                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2525         case 176400:
2526                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2527         case 192000:
2528                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2529         default:
2530                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2531         }
2532 }
2533
2534 /* HDMI audio codec callbacks */
2535 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
2536                                   struct hdmi_codec_daifmt *daifmt,
2537                                   struct hdmi_codec_params *params)
2538 {
2539         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2540         struct drm_device *drm = vc4_hdmi->connector.dev;
2541         struct vc4_dev *vc4 = to_vc4_dev(drm);
2542         struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2543         unsigned int sample_rate = params->sample_rate;
2544         unsigned int channels = params->channels;
2545         unsigned long flags;
2546         u32 audio_packet_config, channel_mask;
2547         u32 channel_map;
2548         u32 mai_audio_format;
2549         u32 mai_sample_rate;
2550         int ret = 0;
2551         int idx;
2552
2553         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2554                 sample_rate, params->sample_width, channels);
2555
2556         mutex_lock(&vc4_hdmi->mutex);
2557
2558         if (!drm_dev_enter(drm, &idx)) {
2559                 ret = -ENODEV;
2560                 goto out;
2561         }
2562
2563         if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2564                 ret = -EINVAL;
2565                 goto out_dev_exit;
2566         }
2567
2568         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2569
2570         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2571         HDMI_WRITE(HDMI_MAI_CTL,
2572                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2573                    VC4_HD_MAI_CTL_WHOLSMP |
2574                    VC4_HD_MAI_CTL_CHALIGN |
2575                    VC4_HD_MAI_CTL_ENABLE);
2576
2577         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2578         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2579             params->channels == 8)
2580                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2581         else
2582                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2583         HDMI_WRITE(HDMI_MAI_FMT,
2584                    VC4_SET_FIELD(mai_sample_rate,
2585                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2586                    VC4_SET_FIELD(mai_audio_format,
2587                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2588
2589         /* The B frame identifier should match the value used by alsa-lib (8) */
2590         audio_packet_config =
2591                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2592                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2593                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2594
2595         channel_mask = GENMASK(channels - 1, 0);
2596         audio_packet_config |= VC4_SET_FIELD(channel_mask,
2597                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2598
2599         /* Set the MAI threshold */
2600         if (vc4->gen >= VC4_GEN_5)
2601                 HDMI_WRITE(HDMI_MAI_THR,
2602                         VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
2603                         VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
2604                         VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQHIGH) |
2605                         VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQLOW));
2606         else
2607                 HDMI_WRITE(HDMI_MAI_THR,
2608                         VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICHIGH) |
2609                         VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICLOW) |
2610                         VC4_SET_FIELD(0x6, VC4_HD_MAI_THR_DREQHIGH) |
2611                         VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_DREQLOW));
2612
2613         HDMI_WRITE(HDMI_MAI_CONFIG,
2614                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2615                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2616                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2617
2618         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2619         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2620         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2621
2622         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2623
2624         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2625
2626         memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
2627         vc4_hdmi_set_audio_infoframe(encoder);
2628
2629 out_dev_exit:
2630         drm_dev_exit(idx);
2631 out:
2632         mutex_unlock(&vc4_hdmi->mutex);
2633
2634         return ret;
2635 }
2636
2637 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2638         .name = "vc4-hdmi-cpu-dai-component",
2639         .legacy_dai_naming = 1,
2640 };
2641
2642 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2643 {
2644         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2645
2646         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2647
2648         return 0;
2649 }
2650
2651 static const struct snd_soc_dai_ops vc4_snd_dai_ops = {
2652         .probe  = vc4_hdmi_audio_cpu_dai_probe,
2653 };
2654
2655 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2656         .name = "vc4-hdmi-cpu-dai",
2657         .ops = &vc4_snd_dai_ops,
2658         .playback = {
2659                 .stream_name = "Playback",
2660                 .channels_min = 1,
2661                 .channels_max = 8,
2662                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2663                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2664                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2665                          SNDRV_PCM_RATE_192000,
2666                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2667         },
2668 };
2669
2670 static const struct snd_dmaengine_pcm_config pcm_conf = {
2671         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2672         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2673 };
2674
2675 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
2676                                   uint8_t *buf, size_t len)
2677 {
2678         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2679         struct drm_connector *connector = &vc4_hdmi->connector;
2680
2681         mutex_lock(&vc4_hdmi->mutex);
2682         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2683         mutex_unlock(&vc4_hdmi->mutex);
2684
2685         return 0;
2686 }
2687
2688 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
2689         .get_eld = vc4_hdmi_audio_get_eld,
2690         .prepare = vc4_hdmi_audio_prepare,
2691         .audio_shutdown = vc4_hdmi_audio_shutdown,
2692         .audio_startup = vc4_hdmi_audio_startup,
2693 };
2694
2695 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
2696         .ops = &vc4_hdmi_codec_ops,
2697         .max_i2s_channels = 8,
2698         .i2s = 1,
2699 };
2700
2701 static void vc4_hdmi_audio_codec_release(void *ptr)
2702 {
2703         struct vc4_hdmi *vc4_hdmi = ptr;
2704
2705         platform_device_unregister(vc4_hdmi->audio.codec_pdev);
2706         vc4_hdmi->audio.codec_pdev = NULL;
2707 }
2708
2709 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2710 {
2711         const struct vc4_hdmi_register *mai_data =
2712                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2713         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2714         struct snd_soc_card *card = &vc4_hdmi->audio.card;
2715         struct device *dev = &vc4_hdmi->pdev->dev;
2716         struct platform_device *codec_pdev;
2717         struct resource *iomem;
2718         int index, len;
2719         int ret;
2720
2721         /*
2722          * ASoC makes it a bit hard to retrieve a pointer to the
2723          * vc4_hdmi structure. Registering the card will overwrite our
2724          * device drvdata with a pointer to the snd_soc_card structure,
2725          * which can then be used to retrieve whatever drvdata we want
2726          * to associate.
2727          *
2728          * However, that doesn't fly in the case where we wouldn't
2729          * register an ASoC card (because of an old DT that is missing
2730          * the dmas properties for example), then the card isn't
2731          * registered and the device drvdata wouldn't be set.
2732          *
2733          * We can deal with both cases by making sure a snd_soc_card
2734          * pointer and a vc4_hdmi structure are pointing to the same
2735          * memory address, so we can treat them indistinctly without any
2736          * issue.
2737          */
2738         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2739         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2740
2741         if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
2742                 dev_warn(dev,
2743                          "'dmas' DT property is missing or empty, no HDMI audio\n");
2744                 return 0;
2745         }
2746
2747         if (mai_data->reg != VC4_HD) {
2748                 WARN_ONCE(true, "MAI isn't in the HD block\n");
2749                 return -EINVAL;
2750         }
2751
2752         /*
2753          * Get the physical address of VC4_HD_MAI_DATA.
2754          */
2755         index = of_property_match_string(dev->of_node, "reg-names", "hd");
2756         /* Before BCM2711, we don't have a named register range */
2757         if (index < 0)
2758                 index = 1;
2759         iomem = platform_get_resource(vc4_hdmi->pdev, IORESOURCE_MEM, index);
2760
2761         vc4_hdmi->audio.dma_data.addr = iomem->start + mai_data->offset;
2762         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2763         vc4_hdmi->audio.dma_data.maxburst = 2;
2764
2765         /*
2766          * NOTE: Strictly speaking, we should probably use a DRM-managed
2767          * registration there to avoid removing all the audio components
2768          * by the time the driver doesn't have any user anymore.
2769          *
2770          * However, the ASoC core uses a number of devm_kzalloc calls
2771          * when registering, even when using non-device-managed
2772          * functions (such as in snd_soc_register_component()).
2773          *
2774          * If we call snd_soc_unregister_component() in a DRM-managed
2775          * action, the device-managed actions have already been executed
2776          * and thus we would access memory that has been freed.
2777          *
2778          * Using device-managed hooks here probably leaves us open to a
2779          * bunch of issues if userspace still has a handle on the ALSA
2780          * device when the device is removed. However, this is mitigated
2781          * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2782          * path to prevent the access to the device resources if it
2783          * isn't there anymore.
2784          *
2785          * Then, the vc4_hdmi structure is DRM-managed and thus only
2786          * freed whenever the last user has closed the DRM device file.
2787          * It should thus outlive ALSA in most situations.
2788          */
2789         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2790         if (ret) {
2791                 dev_err(dev, "Could not register PCM component: %d\n", ret);
2792                 return ret;
2793         }
2794
2795         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2796                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
2797         if (ret) {
2798                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2799                 return ret;
2800         }
2801
2802         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
2803                                                    PLATFORM_DEVID_AUTO,
2804                                                    &vc4_hdmi_codec_pdata,
2805                                                    sizeof(vc4_hdmi_codec_pdata));
2806         if (IS_ERR(codec_pdev)) {
2807                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
2808                 return PTR_ERR(codec_pdev);
2809         }
2810         vc4_hdmi->audio.codec_pdev = codec_pdev;
2811
2812         ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi);
2813         if (ret)
2814                 return ret;
2815
2816         dai_link->cpus          = &vc4_hdmi->audio.cpu;
2817         dai_link->codecs        = &vc4_hdmi->audio.codec;
2818         dai_link->platforms     = &vc4_hdmi->audio.platform;
2819
2820         dai_link->num_cpus      = 1;
2821         dai_link->num_codecs    = 1;
2822         dai_link->num_platforms = 1;
2823
2824         dai_link->name = "MAI";
2825         dai_link->stream_name = "MAI PCM";
2826         dai_link->codecs->dai_name = "i2s-hifi";
2827         dai_link->cpus->dai_name = dev_name(dev);
2828         dai_link->codecs->name = dev_name(&codec_pdev->dev);
2829         dai_link->platforms->name = dev_name(dev);
2830
2831         card->dai_link = dai_link;
2832         card->num_links = 1;
2833         card->name = vc4_hdmi->variant->card_name;
2834         card->driver_name = "vc4-hdmi";
2835         card->dev = dev;
2836         card->owner = THIS_MODULE;
2837
2838         /*
2839          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2840          * stores a pointer to the snd card object in dev->driver_data. This
2841          * means we cannot use it for something else. The hdmi back-pointer is
2842          * now stored in card->drvdata and should be retrieved with
2843          * snd_soc_card_get_drvdata() if needed.
2844          */
2845         snd_soc_card_set_drvdata(card, vc4_hdmi);
2846         ret = devm_snd_soc_register_card(dev, card);
2847         if (ret)
2848                 dev_err_probe(dev, ret, "Could not register sound card\n");
2849
2850         return ret;
2851
2852 }
2853
2854 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2855 {
2856         struct vc4_hdmi *vc4_hdmi = priv;
2857         struct drm_connector *connector = &vc4_hdmi->connector;
2858         struct drm_device *dev = connector->dev;
2859
2860         if (dev && dev->registered)
2861                 drm_connector_helper_hpd_irq_event(connector);
2862
2863         return IRQ_HANDLED;
2864 }
2865
2866 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2867 {
2868         struct drm_connector *connector = &vc4_hdmi->connector;
2869         struct platform_device *pdev = vc4_hdmi->pdev;
2870         int ret;
2871
2872         if (vc4_hdmi->variant->external_irq_controller) {
2873                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2874                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2875
2876                 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2877                                                 NULL,
2878                                                 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2879                                                 "vc4 hdmi hpd connected", vc4_hdmi);
2880                 if (ret)
2881                         return ret;
2882
2883                 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2884                                                 NULL,
2885                                                 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2886                                                 "vc4 hdmi hpd disconnected", vc4_hdmi);
2887                 if (ret)
2888                         return ret;
2889
2890                 connector->polled = DRM_CONNECTOR_POLL_HPD;
2891         }
2892
2893         return 0;
2894 }
2895
2896 #ifdef CONFIG_DRM_VC4_HDMI_CEC
2897 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2898 {
2899         struct vc4_hdmi *vc4_hdmi = priv;
2900
2901         if (vc4_hdmi->cec_rx_msg.len)
2902                 cec_received_msg(vc4_hdmi->cec_adap,
2903                                  &vc4_hdmi->cec_rx_msg);
2904
2905         return IRQ_HANDLED;
2906 }
2907
2908 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2909 {
2910         struct vc4_hdmi *vc4_hdmi = priv;
2911
2912         if (vc4_hdmi->cec_tx_ok) {
2913                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2914                                   0, 0, 0, 0);
2915         } else {
2916                 /*
2917                  * This CEC implementation makes 1 retry, so if we
2918                  * get a NACK, then that means it made 2 attempts.
2919                  */
2920                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2921                                   0, 2, 0, 0);
2922         }
2923         return IRQ_HANDLED;
2924 }
2925
2926 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2927 {
2928         struct vc4_hdmi *vc4_hdmi = priv;
2929         irqreturn_t ret;
2930
2931         if (vc4_hdmi->cec_irq_was_rx)
2932                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2933         else
2934                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2935
2936         return ret;
2937 }
2938
2939 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2940 {
2941         struct drm_device *dev = vc4_hdmi->connector.dev;
2942         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2943         unsigned int i;
2944
2945         lockdep_assert_held(&vc4_hdmi->hw_lock);
2946
2947         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2948                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2949
2950         if (msg->len > 16) {
2951                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2952                 return;
2953         }
2954
2955         for (i = 0; i < msg->len; i += 4) {
2956                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2957
2958                 msg->msg[i] = val & 0xff;
2959                 msg->msg[i + 1] = (val >> 8) & 0xff;
2960                 msg->msg[i + 2] = (val >> 16) & 0xff;
2961                 msg->msg[i + 3] = (val >> 24) & 0xff;
2962         }
2963 }
2964
2965 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2966 {
2967         u32 cntrl1;
2968
2969         /*
2970          * We don't need to protect the register access using
2971          * drm_dev_enter() there because the interrupt handler lifetime
2972          * is tied to the device itself, and not to the DRM device.
2973          *
2974          * So when the device will be gone, one of the first thing we
2975          * will be doing will be to unregister the interrupt handler,
2976          * and then unregister the DRM device. drm_dev_enter() would
2977          * thus always succeed if we are here.
2978          */
2979
2980         lockdep_assert_held(&vc4_hdmi->hw_lock);
2981
2982         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2983         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2984         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2985         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2986
2987         return IRQ_WAKE_THREAD;
2988 }
2989
2990 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2991 {
2992         struct vc4_hdmi *vc4_hdmi = priv;
2993         irqreturn_t ret;
2994
2995         spin_lock(&vc4_hdmi->hw_lock);
2996         ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2997         spin_unlock(&vc4_hdmi->hw_lock);
2998
2999         return ret;
3000 }
3001
3002 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
3003 {
3004         u32 cntrl1;
3005
3006         lockdep_assert_held(&vc4_hdmi->hw_lock);
3007
3008         /*
3009          * We don't need to protect the register access using
3010          * drm_dev_enter() there because the interrupt handler lifetime
3011          * is tied to the device itself, and not to the DRM device.
3012          *
3013          * So when the device will be gone, one of the first thing we
3014          * will be doing will be to unregister the interrupt handler,
3015          * and then unregister the DRM device. drm_dev_enter() would
3016          * thus always succeed if we are here.
3017          */
3018
3019         vc4_hdmi->cec_rx_msg.len = 0;
3020         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
3021         vc4_cec_read_msg(vc4_hdmi, cntrl1);
3022         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
3023         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
3024         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
3025
3026         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
3027
3028         return IRQ_WAKE_THREAD;
3029 }
3030
3031 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
3032 {
3033         struct vc4_hdmi *vc4_hdmi = priv;
3034         irqreturn_t ret;
3035
3036         spin_lock(&vc4_hdmi->hw_lock);
3037         ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
3038         spin_unlock(&vc4_hdmi->hw_lock);
3039
3040         return ret;
3041 }
3042
3043 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
3044 {
3045         struct vc4_hdmi *vc4_hdmi = priv;
3046         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
3047         irqreturn_t ret;
3048         u32 cntrl5;
3049
3050         /*
3051          * We don't need to protect the register access using
3052          * drm_dev_enter() there because the interrupt handler lifetime
3053          * is tied to the device itself, and not to the DRM device.
3054          *
3055          * So when the device will be gone, one of the first thing we
3056          * will be doing will be to unregister the interrupt handler,
3057          * and then unregister the DRM device. drm_dev_enter() would
3058          * thus always succeed if we are here.
3059          */
3060
3061         if (!(stat & VC4_HDMI_CPU_CEC))
3062                 return IRQ_NONE;
3063
3064         spin_lock(&vc4_hdmi->hw_lock);
3065         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
3066         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
3067         if (vc4_hdmi->cec_irq_was_rx)
3068                 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
3069         else
3070                 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
3071
3072         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
3073         spin_unlock(&vc4_hdmi->hw_lock);
3074
3075         return ret;
3076 }
3077
3078 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
3079 {
3080         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
3081         struct drm_device *drm = vc4_hdmi->connector.dev;
3082         /* clock period in microseconds */
3083         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
3084         unsigned long flags;
3085         u32 val;
3086         int ret;
3087         int idx;
3088
3089         if (!drm_dev_enter(drm, &idx))
3090                 /*
3091                  * We can't return an error code, because the CEC
3092                  * framework will emit WARN_ON messages at unbind
3093                  * otherwise.
3094                  */
3095                 return 0;
3096
3097         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
3098         if (ret) {
3099                 drm_dev_exit(idx);
3100                 return ret;
3101         }
3102
3103         mutex_lock(&vc4_hdmi->mutex);
3104
3105         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3106
3107         val = HDMI_READ(HDMI_CEC_CNTRL_5);
3108         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
3109                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
3110                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
3111         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
3112                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
3113
3114         HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
3115                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
3116         HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
3117         HDMI_WRITE(HDMI_CEC_CNTRL_2,
3118                    ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
3119                    ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
3120                    ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
3121                    ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
3122                    ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
3123         HDMI_WRITE(HDMI_CEC_CNTRL_3,
3124                    ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
3125                    ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
3126                    ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
3127                    ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
3128         HDMI_WRITE(HDMI_CEC_CNTRL_4,
3129                    ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
3130                    ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
3131                    ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
3132                    ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
3133
3134         if (!vc4_hdmi->variant->external_irq_controller)
3135                 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
3136
3137         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3138
3139         mutex_unlock(&vc4_hdmi->mutex);
3140         drm_dev_exit(idx);
3141
3142         return 0;
3143 }
3144
3145 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
3146 {
3147         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
3148         struct drm_device *drm = vc4_hdmi->connector.dev;
3149         unsigned long flags;
3150         int idx;
3151
3152         if (!drm_dev_enter(drm, &idx))
3153                 /*
3154                  * We can't return an error code, because the CEC
3155                  * framework will emit WARN_ON messages at unbind
3156                  * otherwise.
3157                  */
3158                 return 0;
3159
3160         mutex_lock(&vc4_hdmi->mutex);
3161
3162         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3163
3164         if (!vc4_hdmi->variant->external_irq_controller)
3165                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
3166
3167         HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
3168                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
3169
3170         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3171
3172         mutex_unlock(&vc4_hdmi->mutex);
3173
3174         pm_runtime_put(&vc4_hdmi->pdev->dev);
3175
3176         drm_dev_exit(idx);
3177
3178         return 0;
3179 }
3180
3181 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
3182 {
3183         if (enable)
3184                 return vc4_hdmi_cec_enable(adap);
3185         else
3186                 return vc4_hdmi_cec_disable(adap);
3187 }
3188
3189 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
3190 {
3191         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
3192         struct drm_device *drm = vc4_hdmi->connector.dev;
3193         unsigned long flags;
3194         int idx;
3195
3196         if (!drm_dev_enter(drm, &idx))
3197                 /*
3198                  * We can't return an error code, because the CEC
3199                  * framework will emit WARN_ON messages at unbind
3200                  * otherwise.
3201                  */
3202                 return 0;
3203
3204         mutex_lock(&vc4_hdmi->mutex);
3205         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3206         HDMI_WRITE(HDMI_CEC_CNTRL_1,
3207                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
3208                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
3209         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3210         mutex_unlock(&vc4_hdmi->mutex);
3211
3212         drm_dev_exit(idx);
3213
3214         return 0;
3215 }
3216
3217 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
3218                                       u32 signal_free_time, struct cec_msg *msg)
3219 {
3220         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
3221         struct drm_device *dev = vc4_hdmi->connector.dev;
3222         unsigned long flags;
3223         u32 val;
3224         unsigned int i;
3225         int idx;
3226
3227         if (!drm_dev_enter(dev, &idx))
3228                 return -ENODEV;
3229
3230         if (msg->len > 16) {
3231                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
3232                 drm_dev_exit(idx);
3233                 return -ENOMEM;
3234         }
3235
3236         mutex_lock(&vc4_hdmi->mutex);
3237
3238         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3239
3240         for (i = 0; i < msg->len; i += 4)
3241                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
3242                            (msg->msg[i]) |
3243                            (msg->msg[i + 1] << 8) |
3244                            (msg->msg[i + 2] << 16) |
3245                            (msg->msg[i + 3] << 24));
3246
3247         val = HDMI_READ(HDMI_CEC_CNTRL_1);
3248         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
3249         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
3250         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
3251         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
3252         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
3253
3254         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
3255
3256         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3257         mutex_unlock(&vc4_hdmi->mutex);
3258         drm_dev_exit(idx);
3259
3260         return 0;
3261 }
3262
3263 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
3264         .adap_enable = vc4_hdmi_cec_adap_enable,
3265         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
3266         .adap_transmit = vc4_hdmi_cec_adap_transmit,
3267 };
3268
3269 static void vc4_hdmi_cec_release(void *ptr)
3270 {
3271         struct vc4_hdmi *vc4_hdmi = ptr;
3272
3273         cec_unregister_adapter(vc4_hdmi->cec_adap);
3274         vc4_hdmi->cec_adap = NULL;
3275 }
3276
3277 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3278 {
3279         struct cec_connector_info conn_info;
3280         struct platform_device *pdev = vc4_hdmi->pdev;
3281         struct device *dev = &pdev->dev;
3282         int ret;
3283
3284         if (!of_property_present(dev->of_node, "interrupts")) {
3285                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
3286                 return 0;
3287         }
3288
3289         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
3290                                                   vc4_hdmi,
3291                                                   vc4_hdmi->variant->card_name,
3292                                                   CEC_CAP_DEFAULTS |
3293                                                   CEC_CAP_CONNECTOR_INFO, 1);
3294         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
3295         if (ret < 0)
3296                 return ret;
3297
3298         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
3299         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
3300
3301         if (vc4_hdmi->variant->external_irq_controller) {
3302                 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
3303                                                 vc4_cec_irq_handler_rx_bare,
3304                                                 vc4_cec_irq_handler_rx_thread, 0,
3305                                                 "vc4 hdmi cec rx", vc4_hdmi);
3306                 if (ret)
3307                         goto err_delete_cec_adap;
3308
3309                 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
3310                                                 vc4_cec_irq_handler_tx_bare,
3311                                                 vc4_cec_irq_handler_tx_thread, 0,
3312                                                 "vc4 hdmi cec tx", vc4_hdmi);
3313                 if (ret)
3314                         goto err_delete_cec_adap;
3315         } else {
3316                 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
3317                                                 vc4_cec_irq_handler,
3318                                                 vc4_cec_irq_handler_thread, 0,
3319                                                 "vc4 hdmi cec", vc4_hdmi);
3320                 if (ret)
3321                         goto err_delete_cec_adap;
3322         }
3323
3324         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
3325         if (ret < 0)
3326                 goto err_delete_cec_adap;
3327
3328         /*
3329          * NOTE: Strictly speaking, we should probably use a DRM-managed
3330          * registration there to avoid removing the CEC adapter by the
3331          * time the DRM driver doesn't have any user anymore.
3332          *
3333          * However, the CEC framework already cleans up the CEC adapter
3334          * only when the last user has closed its file descriptor, so we
3335          * don't need to handle it in DRM.
3336          *
3337          * By the time the device-managed hook is executed, we will give
3338          * up our reference to the CEC adapter and therefore don't
3339          * really care when it's actually freed.
3340          *
3341          * There's still a problematic sequence: if we unregister our
3342          * CEC adapter, but the userspace keeps a handle on the CEC
3343          * adapter but not the DRM device for some reason. In such a
3344          * case, our vc4_hdmi structure will be freed, but the
3345          * cec_adapter structure will have a dangling pointer to what
3346          * used to be our HDMI controller. If we get a CEC call at that
3347          * moment, we could end up with a use-after-free. Fortunately,
3348          * the CEC framework already handles this too, by calling
3349          * cec_is_registered() in cec_ioctl() and cec_poll().
3350          */
3351         ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
3352         if (ret)
3353                 return ret;
3354
3355         return 0;
3356
3357 err_delete_cec_adap:
3358         cec_delete_adapter(vc4_hdmi->cec_adap);
3359
3360         return ret;
3361 }
3362 #else
3363 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
3364 {
3365         return 0;
3366 }
3367 #endif
3368
3369 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
3370 {
3371         struct debugfs_reg32 *regs = ptr;
3372
3373         kfree(regs);
3374 }
3375
3376 static int vc4_hdmi_build_regset(struct drm_device *drm,
3377                                  struct vc4_hdmi *vc4_hdmi,
3378                                  struct debugfs_regset32 *regset,
3379                                  enum vc4_hdmi_regs reg)
3380 {
3381         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
3382         struct debugfs_reg32 *regs, *new_regs;
3383         unsigned int count = 0;
3384         unsigned int i;
3385         int ret;
3386
3387         regs = kcalloc(variant->num_registers, sizeof(*regs),
3388                        GFP_KERNEL);
3389         if (!regs)
3390                 return -ENOMEM;
3391
3392         for (i = 0; i < variant->num_registers; i++) {
3393                 const struct vc4_hdmi_register *field = &variant->registers[i];
3394
3395                 if (field->reg != reg)
3396                         continue;
3397
3398                 regs[count].name = field->name;
3399                 regs[count].offset = field->offset;
3400                 count++;
3401         }
3402
3403         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
3404         if (!new_regs)
3405                 return -ENOMEM;
3406
3407         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
3408         regset->regs = new_regs;
3409         regset->nregs = count;
3410
3411         ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
3412         if (ret)
3413                 return ret;
3414
3415         return 0;
3416 }
3417
3418 static int vc4_hdmi_init_resources(struct drm_device *drm,
3419                                    struct vc4_hdmi *vc4_hdmi)
3420 {
3421         struct platform_device *pdev = vc4_hdmi->pdev;
3422         struct device *dev = &pdev->dev;
3423         int ret;
3424
3425         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
3426         if (IS_ERR(vc4_hdmi->hdmicore_regs))
3427                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
3428
3429         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
3430         if (IS_ERR(vc4_hdmi->hd_regs))
3431                 return PTR_ERR(vc4_hdmi->hd_regs);
3432
3433         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3434         if (ret)
3435                 return ret;
3436
3437         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3438         if (ret)
3439                 return ret;
3440
3441         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
3442         if (IS_ERR(vc4_hdmi->pixel_clock)) {
3443                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
3444                 if (ret != -EPROBE_DEFER)
3445                         DRM_ERROR("Failed to get pixel clock\n");
3446                 return ret;
3447         }
3448
3449         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3450         if (IS_ERR(vc4_hdmi->hsm_clock)) {
3451                 DRM_ERROR("Failed to get HDMI state machine clock\n");
3452                 return PTR_ERR(vc4_hdmi->hsm_clock);
3453         }
3454         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
3455         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
3456
3457         return 0;
3458 }
3459
3460 static int vc5_hdmi_init_resources(struct drm_device *drm,
3461                                    struct vc4_hdmi *vc4_hdmi)
3462 {
3463         struct platform_device *pdev = vc4_hdmi->pdev;
3464         struct device *dev = &pdev->dev;
3465         struct resource *res;
3466         int ret;
3467
3468         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
3469         if (!res)
3470                 return -ENODEV;
3471
3472         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
3473                                                resource_size(res));
3474         if (!vc4_hdmi->hdmicore_regs)
3475                 return -ENOMEM;
3476
3477         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
3478         if (!res)
3479                 return -ENODEV;
3480
3481         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
3482         if (!vc4_hdmi->hd_regs)
3483                 return -ENOMEM;
3484
3485         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
3486         if (!res)
3487                 return -ENODEV;
3488
3489         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
3490         if (!vc4_hdmi->cec_regs)
3491                 return -ENOMEM;
3492
3493         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
3494         if (!res)
3495                 return -ENODEV;
3496
3497         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
3498         if (!vc4_hdmi->csc_regs)
3499                 return -ENOMEM;
3500
3501         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
3502         if (!res)
3503                 return -ENODEV;
3504
3505         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
3506         if (!vc4_hdmi->dvp_regs)
3507                 return -ENOMEM;
3508
3509         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
3510         if (!res)
3511                 return -ENODEV;
3512
3513         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
3514         if (!vc4_hdmi->phy_regs)
3515                 return -ENOMEM;
3516
3517         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
3518         if (!res)
3519                 return -ENODEV;
3520
3521         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
3522         if (!vc4_hdmi->ram_regs)
3523                 return -ENOMEM;
3524
3525         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
3526         if (!res)
3527                 return -ENODEV;
3528
3529         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
3530         if (!vc4_hdmi->rm_regs)
3531                 return -ENOMEM;
3532
3533         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3534         if (IS_ERR(vc4_hdmi->hsm_clock)) {
3535                 DRM_ERROR("Failed to get HDMI state machine clock\n");
3536                 return PTR_ERR(vc4_hdmi->hsm_clock);
3537         }
3538
3539         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3540         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3541                 DRM_ERROR("Failed to get pixel bvb clock\n");
3542                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3543         }
3544
3545         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3546         if (IS_ERR(vc4_hdmi->audio_clock)) {
3547                 DRM_ERROR("Failed to get audio clock\n");
3548                 return PTR_ERR(vc4_hdmi->audio_clock);
3549         }
3550
3551         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3552         if (IS_ERR(vc4_hdmi->cec_clock)) {
3553                 DRM_ERROR("Failed to get CEC clock\n");
3554                 return PTR_ERR(vc4_hdmi->cec_clock);
3555         }
3556
3557         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3558         if (IS_ERR(vc4_hdmi->reset)) {
3559                 DRM_ERROR("Failed to get HDMI reset line\n");
3560                 return PTR_ERR(vc4_hdmi->reset);
3561         }
3562
3563         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3564         if (ret)
3565                 return ret;
3566
3567         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3568         if (ret)
3569                 return ret;
3570
3571         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3572         if (ret)
3573                 return ret;
3574
3575         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3576         if (ret)
3577                 return ret;
3578
3579         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3580         if (ret)
3581                 return ret;
3582
3583         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3584         if (ret)
3585                 return ret;
3586
3587         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3588         if (ret)
3589                 return ret;
3590
3591         ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3592         if (ret)
3593                 return ret;
3594
3595         return 0;
3596 }
3597
3598 static int vc4_hdmi_runtime_suspend(struct device *dev)
3599 {
3600         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3601
3602         clk_disable_unprepare(vc4_hdmi->audio_clock);
3603         clk_disable_unprepare(vc4_hdmi->hsm_clock);
3604
3605         return 0;
3606 }
3607
3608 static int vc4_hdmi_runtime_resume(struct device *dev)
3609 {
3610         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3611         unsigned long __maybe_unused flags;
3612         u32 __maybe_unused value;
3613         unsigned long rate;
3614         int ret;
3615
3616         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
3617         if (ret)
3618                 return ret;
3619
3620         /*
3621          * Whenever the RaspberryPi boots without an HDMI monitor
3622          * plugged in, the firmware won't have initialized the HSM clock
3623          * rate and it will be reported as 0.
3624          *
3625          * If we try to access a register of the controller in such a
3626          * case, it will lead to a silent CPU stall. Let's make sure we
3627          * prevent such a case.
3628          */
3629         rate = clk_get_rate(vc4_hdmi->hsm_clock);
3630         if (!rate) {
3631                 ret = -EINVAL;
3632                 goto err_disable_clk;
3633         }
3634
3635         ret = clk_prepare_enable(vc4_hdmi->audio_clock);
3636         if (ret)
3637                 goto err_disable_clk;
3638
3639         if (vc4_hdmi->variant->reset)
3640                 vc4_hdmi->variant->reset(vc4_hdmi);
3641
3642 #ifdef CONFIG_DRM_VC4_HDMI_CEC
3643         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3644         value = HDMI_READ(HDMI_CEC_CNTRL_1);
3645         /* Set the logical address to Unregistered */
3646         value |= VC4_HDMI_CEC_ADDR_MASK;
3647         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3648         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3649
3650         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3651
3652         if (!vc4_hdmi->variant->external_irq_controller) {
3653                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3654                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3655                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3656         }
3657 #endif
3658
3659         return 0;
3660
3661 err_disable_clk:
3662         clk_disable_unprepare(vc4_hdmi->hsm_clock);
3663         return ret;
3664 }
3665
3666 static void vc4_hdmi_put_ddc_device(void *ptr)
3667 {
3668         struct vc4_hdmi *vc4_hdmi = ptr;
3669
3670         put_device(&vc4_hdmi->ddc->dev);
3671 }
3672
3673 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3674 {
3675         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3676         struct platform_device *pdev = to_platform_device(dev);
3677         struct drm_device *drm = dev_get_drvdata(master);
3678         struct vc4_hdmi *vc4_hdmi;
3679         struct drm_encoder *encoder;
3680         struct device_node *ddc_node;
3681         int ret;
3682
3683         vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3684         if (!vc4_hdmi)
3685                 return -ENOMEM;
3686
3687         ret = drmm_mutex_init(drm, &vc4_hdmi->mutex);
3688         if (ret)
3689                 return ret;
3690
3691         spin_lock_init(&vc4_hdmi->hw_lock);
3692         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3693
3694         dev_set_drvdata(dev, vc4_hdmi);
3695         encoder = &vc4_hdmi->encoder.base;
3696         vc4_hdmi->encoder.type = variant->encoder_type;
3697         vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3698         vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3699         vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3700         vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3701         vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3702         vc4_hdmi->pdev = pdev;
3703         vc4_hdmi->variant = variant;
3704
3705         /*
3706          * Since we don't know the state of the controller and its
3707          * display (if any), let's assume it's always enabled.
3708          * vc4_hdmi_disable_scrambling() will thus run at boot, make
3709          * sure it's disabled, and avoid any inconsistency.
3710          */
3711         if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3712                 vc4_hdmi->scdc_enabled = true;
3713
3714         ret = variant->init_resources(drm, vc4_hdmi);
3715         if (ret)
3716                 return ret;
3717
3718         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3719         if (!ddc_node) {
3720                 DRM_ERROR("Failed to find ddc node in device tree\n");
3721                 return -ENODEV;
3722         }
3723
3724         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3725         of_node_put(ddc_node);
3726         if (!vc4_hdmi->ddc) {
3727                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
3728                 return -EPROBE_DEFER;
3729         }
3730
3731         ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3732         if (ret)
3733                 return ret;
3734
3735         /* Only use the GPIO HPD pin if present in the DT, otherwise
3736          * we'll use the HDMI core's register.
3737          */
3738         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3739         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3740                 return PTR_ERR(vc4_hdmi->hpd_gpio);
3741         }
3742
3743         vc4_hdmi->disable_wifi_frequencies =
3744                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3745
3746         ret = devm_pm_runtime_enable(dev);
3747         if (ret)
3748                 return ret;
3749
3750         /*
3751          *  We need to have the device powered up at this point to call
3752          *  our reset hook and for the CEC init.
3753          */
3754         ret = pm_runtime_resume_and_get(dev);
3755         if (ret)
3756                 return ret;
3757
3758         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3759              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1") ||
3760              of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi0") ||
3761              of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi1")) &&
3762             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3763                 clk_prepare_enable(vc4_hdmi->pixel_clock);
3764                 clk_prepare_enable(vc4_hdmi->hsm_clock);
3765                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3766         }
3767
3768         ret = drmm_encoder_init(drm, encoder,
3769                                 &vc4_hdmi_encoder_funcs,
3770                                 DRM_MODE_ENCODER_TMDS,
3771                                 NULL);
3772         if (ret)
3773                 goto err_put_runtime_pm;
3774
3775         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3776
3777         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3778         if (ret)
3779                 goto err_put_runtime_pm;
3780
3781         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3782         if (ret)
3783                 goto err_put_runtime_pm;
3784
3785         ret = vc4_hdmi_cec_init(vc4_hdmi);
3786         if (ret)
3787                 goto err_put_runtime_pm;
3788
3789         ret = vc4_hdmi_audio_init(vc4_hdmi);
3790         if (ret)
3791                 goto err_put_runtime_pm;
3792
3793         pm_runtime_put_sync(dev);
3794
3795         return 0;
3796
3797 err_put_runtime_pm:
3798         pm_runtime_put_sync(dev);
3799
3800         return ret;
3801 }
3802
3803 static const struct component_ops vc4_hdmi_ops = {
3804         .bind   = vc4_hdmi_bind,
3805 };
3806
3807 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3808 {
3809         return component_add(&pdev->dev, &vc4_hdmi_ops);
3810 }
3811
3812 static void vc4_hdmi_dev_remove(struct platform_device *pdev)
3813 {
3814         component_del(&pdev->dev, &vc4_hdmi_ops);
3815 }
3816
3817 static const struct vc4_hdmi_variant bcm2835_variant = {
3818         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3819         .debugfs_name           = "hdmi_regs",
3820         .card_name              = "vc4-hdmi",
3821         .max_pixel_clock        = 162000000,
3822         .registers              = vc4_hdmi_fields,
3823         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
3824
3825         .init_resources         = vc4_hdmi_init_resources,
3826         .csc_setup              = vc4_hdmi_csc_setup,
3827         .reset                  = vc4_hdmi_reset,
3828         .set_timings            = vc4_hdmi_set_timings,
3829         .phy_init               = vc4_hdmi_phy_init,
3830         .phy_disable            = vc4_hdmi_phy_disable,
3831         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
3832         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
3833         .channel_map            = vc4_hdmi_channel_map,
3834         .supports_hdr           = false,
3835 };
3836
3837 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3838         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3839         .debugfs_name           = "hdmi0_regs",
3840         .card_name              = "vc4-hdmi-0",
3841         .max_pixel_clock        = 600000000,
3842         .registers              = vc5_hdmi_hdmi0_fields,
3843         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3844         .phy_lane_mapping       = {
3845                 PHY_LANE_0,
3846                 PHY_LANE_1,
3847                 PHY_LANE_2,
3848                 PHY_LANE_CK,
3849         },
3850         .unsupported_odd_h_timings      = true,
3851         .external_irq_controller        = true,
3852
3853         .init_resources         = vc5_hdmi_init_resources,
3854         .csc_setup              = vc5_hdmi_csc_setup,
3855         .reset                  = vc5_hdmi_reset,
3856         .set_timings            = vc5_hdmi_set_timings,
3857         .phy_init               = vc5_hdmi_phy_init,
3858         .phy_disable            = vc5_hdmi_phy_disable,
3859         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
3860         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
3861         .channel_map            = vc5_hdmi_channel_map,
3862         .supports_hdr           = true,
3863         .hp_detect              = vc5_hdmi_hp_detect,
3864 };
3865
3866 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3867         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
3868         .debugfs_name           = "hdmi1_regs",
3869         .card_name              = "vc4-hdmi-1",
3870         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
3871         .registers              = vc5_hdmi_hdmi1_fields,
3872         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3873         .phy_lane_mapping       = {
3874                 PHY_LANE_1,
3875                 PHY_LANE_0,
3876                 PHY_LANE_CK,
3877                 PHY_LANE_2,
3878         },
3879         .unsupported_odd_h_timings      = true,
3880         .external_irq_controller        = true,
3881
3882         .init_resources         = vc5_hdmi_init_resources,
3883         .csc_setup              = vc5_hdmi_csc_setup,
3884         .reset                  = vc5_hdmi_reset,
3885         .set_timings            = vc5_hdmi_set_timings,
3886         .phy_init               = vc5_hdmi_phy_init,
3887         .phy_disable            = vc5_hdmi_phy_disable,
3888         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
3889         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
3890         .channel_map            = vc5_hdmi_channel_map,
3891         .supports_hdr           = true,
3892         .hp_detect              = vc5_hdmi_hp_detect,
3893 };
3894
3895 static const struct vc4_hdmi_variant bcm2712_hdmi0_variant = {
3896         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
3897         .debugfs_name           = "hdmi0_regs",
3898         .card_name              = "vc4-hdmi-0",
3899         .max_pixel_clock        = 600000000,
3900         .registers              = vc6_hdmi_hdmi0_fields,
3901         .num_registers          = ARRAY_SIZE(vc6_hdmi_hdmi0_fields),
3902         .phy_lane_mapping       = {
3903                 PHY_LANE_0,
3904                 PHY_LANE_1,
3905                 PHY_LANE_2,
3906                 PHY_LANE_CK,
3907         },
3908         .unsupported_odd_h_timings      = false,
3909         .external_irq_controller        = true,
3910
3911         .init_resources         = vc5_hdmi_init_resources,
3912         .csc_setup              = vc5_hdmi_csc_setup,
3913         .reset                  = vc5_hdmi_reset,
3914         .set_timings            = vc5_hdmi_set_timings,
3915         .phy_init               = vc6_hdmi_phy_init,
3916         .phy_disable            = vc6_hdmi_phy_disable,
3917         .channel_map            = vc5_hdmi_channel_map,
3918         .supports_hdr           = true,
3919         .hp_detect              = vc5_hdmi_hp_detect,
3920 };
3921
3922 static const struct vc4_hdmi_variant bcm2712_hdmi1_variant = {
3923         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
3924         .debugfs_name           = "hdmi1_regs",
3925         .card_name              = "vc4-hdmi-1",
3926         .max_pixel_clock        = 600000000,
3927         .registers              = vc6_hdmi_hdmi1_fields,
3928         .num_registers          = ARRAY_SIZE(vc6_hdmi_hdmi1_fields),
3929         .phy_lane_mapping       = {
3930                 PHY_LANE_0,
3931                 PHY_LANE_1,
3932                 PHY_LANE_2,
3933                 PHY_LANE_CK,
3934         },
3935         .unsupported_odd_h_timings      = false,
3936         .external_irq_controller        = true,
3937
3938         .init_resources         = vc5_hdmi_init_resources,
3939         .csc_setup              = vc5_hdmi_csc_setup,
3940         .reset                  = vc5_hdmi_reset,
3941         .set_timings            = vc5_hdmi_set_timings,
3942         .phy_init               = vc6_hdmi_phy_init,
3943         .phy_disable            = vc6_hdmi_phy_disable,
3944         .channel_map            = vc5_hdmi_channel_map,
3945         .supports_hdr           = true,
3946         .hp_detect              = vc5_hdmi_hp_detect,
3947 };
3948
3949 static const struct of_device_id vc4_hdmi_dt_match[] = {
3950         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3951         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3952         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3953         { .compatible = "brcm,bcm2712-hdmi0", .data = &bcm2712_hdmi0_variant },
3954         { .compatible = "brcm,bcm2712-hdmi1", .data = &bcm2712_hdmi1_variant },
3955         {}
3956 };
3957
3958 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3959         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3960                            vc4_hdmi_runtime_resume,
3961                            NULL)
3962 };
3963
3964 struct platform_driver vc4_hdmi_driver = {
3965         .probe = vc4_hdmi_dev_probe,
3966         .remove_new = vc4_hdmi_dev_remove,
3967         .driver = {
3968                 .name = "vc4_hdmi",
3969                 .of_match_table = vc4_hdmi_dt_match,
3970                 .pm = &vc4_hdmi_pm_ops,
3971         },
3972 };