drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <drm/drm_simple_kms_helper.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include <linux/clk.h>
  40 #include <linux/component.h>
  41 #include <linux/i2c.h>
  42 #include <linux/of_address.h>
  43 #include <linux/of_gpio.h>
  44 #include <linux/of_platform.h>
  45 #include <linux/pm_runtime.h>
  46 #include <linux/rational.h>
  47 #include <linux/reset.h>
  48 #include <sound/dmaengine_pcm.h>
  49 #include <sound/hdmi-codec.h>
  50 #include <sound/pcm_drm_eld.h>
  51 #include <sound/pcm_params.h>
  52 #include <sound/soc.h>
  53 #include "media/cec.h"
  54 #include "vc4_drv.h"
  55 #include "vc4_hdmi.h"
  56 #include "vc4_hdmi_regs.h"
  57 #include "vc4_regs.h"
  58
  59 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  60 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  61 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  62 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  63 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  64 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  65
  66 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  67 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  68 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  69 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  70
  71 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  72 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  73 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  74 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  75 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  76 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  77
  78 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  79 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  80
  81 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  82
  83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  85
  86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  88
  89 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  90
  91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
  92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
  93
  94 # define VC4_HD_M_SW_RST                        BIT(2)
  95 # define VC4_HD_M_ENABLE                        BIT(0)
  96
  97 #define HSM_MIN_CLOCK_FREQ      120000000
  98 #define CEC_CLOCK_FREQ 40000
  99
 100 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 101
 102 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode)
 103 {
 104         return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK;
 105 }
 106
 107 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 108 {
 109         struct drm_info_node *node = (struct drm_info_node *)m->private;
 110         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
 111         struct drm_printer p = drm_seq_file_printer(m);
 112
 113         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 114         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 115
 116         return 0;
 117 }
 118
 119 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 120 {
 121         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 122         udelay(1);
 123         HDMI_WRITE(HDMI_M_CTL, 0);
 124
 125         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 126
 127         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 128                    VC4_HDMI_SW_RESET_HDMI |
 129                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 130
 131         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 132 }
 133
 134 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 135 {
 136         reset_control_reset(vc4_hdmi->reset);
 137
 138         HDMI_WRITE(HDMI_DVP_CTL, 0);
 139
 140         HDMI_WRITE(HDMI_CLOCK_STOP,
 141                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 142 }
 143
 144 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 145 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 146 {
 147         u16 clk_cnt;
 148         u32 value;
 149
 150         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 151         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 152
 153         /*
 154          * Set the clock divider: the hsm_clock rate and this divider
 155          * setting will give a 40 kHz CEC clock.
 156          */
 157         clk_cnt = clk_get_rate(vc4_hdmi->cec_clock) / CEC_CLOCK_FREQ;
 158         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 159         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 160 }
 161 #else
 162 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 163 #endif
 164
 165 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder);
 166
 167 static enum drm_connector_status
 168 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 169 {
 170         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 171         bool connected = false;
 172
 173         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 174
 175         if (vc4_hdmi->hpd_gpio &&
 176             gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) {
 177                 connected = true;
 178         } else if (drm_probe_ddc(vc4_hdmi->ddc)) {
 179                 connected = true;
 180         } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) {
 181                 connected = true;
 182         }
 183
 184         if (connected) {
 185                 if (connector->status != connector_status_connected) {
 186                         struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
 187
 188                         if (edid) {
 189                                 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 190                                 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
 191                                 kfree(edid);
 192                         }
 193                 }
 194
 195                 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base);
 196                 pm_runtime_put(&vc4_hdmi->pdev->dev);
 197                 return connector_status_connected;
 198         }
 199
 200         cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 201         pm_runtime_put(&vc4_hdmi->pdev->dev);
 202         return connector_status_disconnected;
 203 }
 204
 205 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 206 {
 207         drm_connector_unregister(connector);
 208         drm_connector_cleanup(connector);
 209 }
 210
 211 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 212 {
 213         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 214         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 215         int ret = 0;
 216         struct edid *edid;
 217
 218         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 219         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 220         if (!edid)
 221                 return -ENODEV;
 222
 223         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 224
 225         drm_connector_update_edid_property(connector, edid);
 226         ret = drm_add_edid_modes(connector, edid);
 227         kfree(edid);
 228
 229         if (vc4_hdmi->disable_4kp60) {
 230                 struct drm_device *drm = connector->dev;
 231                 struct drm_display_mode *mode;
 232
 233                 list_for_each_entry(mode, &connector->probed_modes, head) {
 234                         if (vc4_hdmi_mode_needs_scrambling(mode)) {
 235                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 236                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 237                         }
 238                 }
 239         }
 240
 241         return ret;
 242 }
 243
 244 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 245                                            struct drm_atomic_state *state)
 246 {
 247         struct drm_connector_state *old_state =
 248                 drm_atomic_get_old_connector_state(state, connector);
 249         struct drm_connector_state *new_state =
 250                 drm_atomic_get_new_connector_state(state, connector);
 251         struct drm_crtc *crtc = new_state->crtc;
 252
 253         if (!crtc)
 254                 return 0;
 255
 256         if (old_state->colorspace != new_state->colorspace ||
 257             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 258                 struct drm_crtc_state *crtc_state;
 259
 260                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 261                 if (IS_ERR(crtc_state))
 262                         return PTR_ERR(crtc_state);
 263
 264                 crtc_state->mode_changed = true;
 265         }
 266
 267         return 0;
 268 }
 269
 270 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 271 {
 272         struct vc4_hdmi_connector_state *old_state =
 273                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 274         struct vc4_hdmi_connector_state *new_state =
 275                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 276
 277         if (connector->state)
 278                 __drm_atomic_helper_connector_destroy_state(connector->state);
 279
 280         kfree(old_state);
 281         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 282
 283         if (!new_state)
 284                 return;
 285
 286         new_state->base.max_bpc = 8;
 287         new_state->base.max_requested_bpc = 8;
 288         drm_atomic_helper_connector_tv_reset(connector);
 289 }
 290
 291 static struct drm_connector_state *
 292 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 293 {
 294         struct drm_connector_state *conn_state = connector->state;
 295         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 296         struct vc4_hdmi_connector_state *new_state;
 297
 298         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 299         if (!new_state)
 300                 return NULL;
 301
 302         new_state->pixel_rate = vc4_state->pixel_rate;
 303         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 304
 305         return &new_state->base;
 306 }
 307
 308 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 309         .detect = vc4_hdmi_connector_detect,
 310         .fill_modes = drm_helper_probe_single_connector_modes,
 311         .destroy = vc4_hdmi_connector_destroy,
 312         .reset = vc4_hdmi_connector_reset,
 313         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 314         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 315 };
 316
 317 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 318         .get_modes = vc4_hdmi_connector_get_modes,
 319         .atomic_check = vc4_hdmi_connector_atomic_check,
 320 };
 321
 322 static int vc4_hdmi_connector_init(struct drm_device *dev,
 323                                    struct vc4_hdmi *vc4_hdmi)
 324 {
 325         struct drm_connector *connector = &vc4_hdmi->connector;
 326         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 327         int ret;
 328
 329         drm_connector_init_with_ddc(dev, connector,
 330                                     &vc4_hdmi_connector_funcs,
 331                                     DRM_MODE_CONNECTOR_HDMIA,
 332                                     vc4_hdmi->ddc);
 333         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 334
 335         /*
 336          * Some of the properties below require access to state, like bpc.
 337          * Allocate some default initial connector state with our reset helper.
 338          */
 339         if (connector->funcs->reset)
 340                 connector->funcs->reset(connector);
 341
 342         /* Create and attach TV margin props to this connector. */
 343         ret = drm_mode_create_tv_margin_properties(dev);
 344         if (ret)
 345                 return ret;
 346
 347         ret = drm_mode_create_hdmi_colorspace_property(connector);
 348         if (ret)
 349                 return ret;
 350
 351         drm_connector_attach_colorspace_property(connector);
 352         drm_connector_attach_tv_margin_properties(connector);
 353         drm_connector_attach_max_bpc_property(connector, 8, 12);
 354
 355         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 356                              DRM_CONNECTOR_POLL_DISCONNECT);
 357
 358         connector->interlace_allowed = 1;
 359         connector->doublescan_allowed = 0;
 360
 361         if (vc4_hdmi->variant->supports_hdr)
 362                 drm_connector_attach_hdr_output_metadata_property(connector);
 363
 364         drm_connector_attach_encoder(connector, encoder);
 365
 366         return 0;
 367 }
 368
 369 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 370                                 enum hdmi_infoframe_type type,
 371                                 bool poll)
 372 {
 373         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 374         u32 packet_id = type - 0x80;
 375
 376         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 377                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 378
 379         if (!poll)
 380                 return 0;
 381
 382         return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 383                           BIT(packet_id)), 100);
 384 }
 385
 386 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 387                                      union hdmi_infoframe *frame)
 388 {
 389         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 390         u32 packet_id = frame->any.type - 0x80;
 391         const struct vc4_hdmi_register *ram_packet_start =
 392                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 393         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 394         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 395                                                        ram_packet_start->reg);
 396         uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
 397         ssize_t len, i;
 398         int ret;
 399
 400         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 401                     VC4_HDMI_RAM_PACKET_ENABLE),
 402                   "Packet RAM has to be on to store the packet.");
 403
 404         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 405         if (len < 0)
 406                 return;
 407
 408         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 409         if (ret) {
 410                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 411                 return;
 412         }
 413
 414         for (i = 0; i < len; i += 7) {
 415                 writel(buffer[i + 0] << 0 |
 416                        buffer[i + 1] << 8 |
 417                        buffer[i + 2] << 16,
 418                        base + packet_reg);
 419                 packet_reg += 4;
 420
 421                 writel(buffer[i + 3] << 0 |
 422                        buffer[i + 4] << 8 |
 423                        buffer[i + 5] << 16 |
 424                        buffer[i + 6] << 24,
 425                        base + packet_reg);
 426                 packet_reg += 4;
 427         }
 428
 429         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 430                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 431         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 432                         BIT(packet_id)), 100);
 433         if (ret)
 434                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 435 }
 436
 437 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 438 {
 439         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 440         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 441         struct drm_connector *connector = &vc4_hdmi->connector;
 442         struct drm_connector_state *cstate = connector->state;
 443         struct drm_crtc *crtc = encoder->crtc;
 444         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 445         union hdmi_infoframe frame;
 446         int ret;
 447
 448         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 449                                                        connector, mode);
 450         if (ret < 0) {
 451                 DRM_ERROR("couldn't fill AVI infoframe\n");
 452                 return;
 453         }
 454
 455         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 456                                            connector, mode,
 457                                            vc4_encoder->limited_rgb_range ?
 458                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 459                                            HDMI_QUANTIZATION_RANGE_FULL);
 460         drm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate);
 461         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 462
 463         vc4_hdmi_write_infoframe(encoder, &frame);
 464 }
 465
 466 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 467 {
 468         union hdmi_infoframe frame;
 469         int ret;
 470
 471         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 472         if (ret < 0) {
 473                 DRM_ERROR("couldn't fill SPD infoframe\n");
 474                 return;
 475         }
 476
 477         frame.spd.sdi = HDMI_SPD_SDI_PC;
 478
 479         vc4_hdmi_write_infoframe(encoder, &frame);
 480 }
 481
 482 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 483 {
 484         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 485         struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
 486         union hdmi_infoframe frame;
 487
 488         memcpy(&frame.audio, audio, sizeof(*audio));
 489         vc4_hdmi_write_infoframe(encoder, &frame);
 490 }
 491
 492 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 493 {
 494         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 495         struct drm_connector *connector = &vc4_hdmi->connector;
 496         struct drm_connector_state *conn_state = connector->state;
 497         union hdmi_infoframe frame;
 498
 499         if (!vc4_hdmi->variant->supports_hdr)
 500                 return;
 501
 502         if (!conn_state->hdr_output_metadata)
 503                 return;
 504
 505         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 506                 return;
 507
 508         vc4_hdmi_write_infoframe(encoder, &frame);
 509 }
 510
 511 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 512 {
 513         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 514
 515         vc4_hdmi_set_avi_infoframe(encoder);
 516         vc4_hdmi_set_spd_infoframe(encoder);
 517         /*
 518          * If audio was streaming, then we need to reenabled the audio
 519          * infoframe here during encoder_enable.
 520          */
 521         if (vc4_hdmi->audio.streaming)
 522                 vc4_hdmi_set_audio_infoframe(encoder);
 523
 524         vc4_hdmi_set_hdr_infoframe(encoder);
 525 }
 526
 527 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
 528                                          struct drm_display_mode *mode)
 529 {
 530         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 531         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 532         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 533
 534         if (!vc4_encoder->hdmi_monitor)
 535                 return false;
 536
 537         if (!display->hdmi.scdc.supported ||
 538             !display->hdmi.scdc.scrambling.supported)
 539                 return false;
 540
 541         return true;
 542 }
 543
 544 #define SCRAMBLING_POLLING_DELAY_MS     1000
 545
 546 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 547 {
 548         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 549         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 550
 551         if (!vc4_hdmi_supports_scrambling(encoder, mode))
 552                 return;
 553
 554         if (!vc4_hdmi_mode_needs_scrambling(mode))
 555                 return;
 556
 557         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 558         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 559
 560         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
 561                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 562
 563         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 564                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 565 }
 566
 567 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
 568 {
 569         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 570         struct drm_crtc *crtc = encoder->crtc;
 571
 572         /*
 573          * At boot, encoder->crtc will be NULL. Since we don't know the
 574          * state of the scrambler and in order to avoid any
 575          * inconsistency, let's disable it all the time.
 576          */
 577         if (crtc && !vc4_hdmi_supports_scrambling(encoder, &crtc->mode))
 578                 return;
 579
 580         if (crtc && !vc4_hdmi_mode_needs_scrambling(&crtc->mode))
 581                 return;
 582
 583         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
 584                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
 585
 586         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
 587                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 588
 589         drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
 590         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
 591 }
 592
 593 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
 594 {
 595         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
 596                                                  struct vc4_hdmi,
 597                                                  scrambling_work);
 598
 599         if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
 600                 return;
 601
 602         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 603         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 604
 605         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 606                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 607 }
 608
 609 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 610                                                struct drm_atomic_state *state)
 611 {
 612         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 613
 614         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 615
 616         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
 617
 618         mdelay(1);
 619
 620         HDMI_WRITE(HDMI_VID_CTL,
 621                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 622         vc4_hdmi_disable_scrambling(encoder);
 623 }
 624
 625 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
 626                                                  struct drm_atomic_state *state)
 627 {
 628         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 629         int ret;
 630
 631         HDMI_WRITE(HDMI_VID_CTL,
 632                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 633
 634         if (vc4_hdmi->variant->phy_disable)
 635                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 636
 637         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 638         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 639
 640         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 641         if (ret < 0)
 642                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 643 }
 644
 645 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 646 {
 647 }
 648
 649 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 650 {
 651         u32 csc_ctl;
 652
 653         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 654                                 VC4_HD_CSC_CTL_ORDER);
 655
 656         if (enable) {
 657                 /* CEA VICs other than #1 requre limited range RGB
 658                  * output unless overridden by an AVI infoframe.
 659                  * Apply a colorspace conversion to squash 0-255 down
 660                  * to 16-235.  The matrix here is:
 661                  *
 662                  * [ 0      0      0.8594 16]
 663                  * [ 0      0.8594 0      16]
 664                  * [ 0.8594 0      0      16]
 665                  * [ 0      0      0       1]
 666                  */
 667                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 668                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 669                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 670                                          VC4_HD_CSC_CTL_MODE);
 671
 672                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 673                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 674                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 675                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 676                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 677                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 678         }
 679
 680         /* The RGB order applies even when CSC is disabled. */
 681         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 682 }
 683
 684 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 685 {
 686         u32 csc_ctl;
 687
 688         csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
 689
 690         if (enable) {
 691                 /* CEA VICs other than #1 requre limited range RGB
 692                  * output unless overridden by an AVI infoframe.
 693                  * Apply a colorspace conversion to squash 0-255 down
 694                  * to 16-235.  The matrix here is:
 695                  *
 696                  * [ 0.8594 0      0      16]
 697                  * [ 0      0.8594 0      16]
 698                  * [ 0      0      0.8594 16]
 699                  * [ 0      0      0       1]
 700                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 701                  */
 702                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
 703                 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
 704                 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
 705                 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
 706                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 707                 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
 708         } else {
 709                 /* Still use the matrix for full range, but make it unity.
 710                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 711                  */
 712                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
 713                 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
 714                 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
 715                 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
 716                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 717                 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
 718         }
 719
 720         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 721 }
 722
 723 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 724                                  struct drm_connector_state *state,
 725                                  struct drm_display_mode *mode)
 726 {
 727         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 728         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 729         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 730         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 731         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 732                                    VC4_HDMI_VERTA_VSP) |
 733                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 734                                    VC4_HDMI_VERTA_VFP) |
 735                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 736         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 737                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 738                                    VC4_HDMI_VERTB_VBP));
 739         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 740                           VC4_SET_FIELD(mode->crtc_vtotal -
 741                                         mode->crtc_vsync_end -
 742                                         interlaced,
 743                                         VC4_HDMI_VERTB_VBP));
 744
 745         HDMI_WRITE(HDMI_HORZA,
 746                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 747                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 748                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 749                                  VC4_HDMI_HORZA_HAP));
 750
 751         HDMI_WRITE(HDMI_HORZB,
 752                    VC4_SET_FIELD((mode->htotal -
 753                                   mode->hsync_end) * pixel_rep,
 754                                  VC4_HDMI_HORZB_HBP) |
 755                    VC4_SET_FIELD((mode->hsync_end -
 756                                   mode->hsync_start) * pixel_rep,
 757                                  VC4_HDMI_HORZB_HSP) |
 758                    VC4_SET_FIELD((mode->hsync_start -
 759                                   mode->hdisplay) * pixel_rep,
 760                                  VC4_HDMI_HORZB_HFP));
 761
 762         HDMI_WRITE(HDMI_VERTA0, verta);
 763         HDMI_WRITE(HDMI_VERTA1, verta);
 764
 765         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 766         HDMI_WRITE(HDMI_VERTB1, vertb);
 767 }
 768
 769 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 770                                  struct drm_connector_state *state,
 771                                  struct drm_display_mode *mode)
 772 {
 773         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 774         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 775         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 776         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 777         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 778                                    VC5_HDMI_VERTA_VSP) |
 779                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 780                                    VC5_HDMI_VERTA_VFP) |
 781                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
 782         u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 783                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 784                                    VC4_HDMI_VERTB_VBP));
 785         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 786                           VC4_SET_FIELD(mode->crtc_vtotal -
 787                                         mode->crtc_vsync_end -
 788                                         interlaced,
 789                                         VC4_HDMI_VERTB_VBP));
 790         unsigned char gcp;
 791         bool gcp_en;
 792         u32 reg;
 793
 794         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
 795         HDMI_WRITE(HDMI_HORZA,
 796                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
 797                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
 798                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 799                                  VC5_HDMI_HORZA_HAP) |
 800                    VC4_SET_FIELD((mode->hsync_start -
 801                                   mode->hdisplay) * pixel_rep,
 802                                  VC5_HDMI_HORZA_HFP));
 803
 804         HDMI_WRITE(HDMI_HORZB,
 805                    VC4_SET_FIELD((mode->htotal -
 806                                   mode->hsync_end) * pixel_rep,
 807                                  VC5_HDMI_HORZB_HBP) |
 808                    VC4_SET_FIELD((mode->hsync_end -
 809                                   mode->hsync_start) * pixel_rep,
 810                                  VC5_HDMI_HORZB_HSP));
 811
 812         HDMI_WRITE(HDMI_VERTA0, verta);
 813         HDMI_WRITE(HDMI_VERTA1, verta);
 814
 815         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 816         HDMI_WRITE(HDMI_VERTB1, vertb);
 817
 818         switch (state->max_bpc) {
 819         case 12:
 820                 gcp = 6;
 821                 gcp_en = true;
 822                 break;
 823         case 10:
 824                 gcp = 5;
 825                 gcp_en = true;
 826                 break;
 827         case 8:
 828         default:
 829                 gcp = 4;
 830                 gcp_en = false;
 831                 break;
 832         }
 833
 834         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
 835         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
 836                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
 837         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
 838                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
 839         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
 840
 841         reg = HDMI_READ(HDMI_GCP_WORD_1);
 842         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
 843         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
 844         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
 845
 846         reg = HDMI_READ(HDMI_GCP_CONFIG);
 847         reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
 848         reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
 849         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
 850
 851         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
 852 }
 853
 854 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
 855 {
 856         u32 drift;
 857         int ret;
 858
 859         drift = HDMI_READ(HDMI_FIFO_CTL);
 860         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 861
 862         HDMI_WRITE(HDMI_FIFO_CTL,
 863                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 864         HDMI_WRITE(HDMI_FIFO_CTL,
 865                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 866         usleep_range(1000, 1100);
 867         HDMI_WRITE(HDMI_FIFO_CTL,
 868                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 869         HDMI_WRITE(HDMI_FIFO_CTL,
 870                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 871
 872         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
 873                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
 874         WARN_ONCE(ret, "Timeout waiting for "
 875                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
 876 }
 877
 878 static struct drm_connector_state *
 879 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder,
 880                                      struct drm_atomic_state *state)
 881 {
 882         struct drm_connector_state *conn_state;
 883         struct drm_connector *connector;
 884         unsigned int i;
 885
 886         for_each_new_connector_in_state(state, connector, conn_state, i) {
 887                 if (conn_state->best_encoder == encoder)
 888                         return conn_state;
 889         }
 890
 891         return NULL;
 892 }
 893
 894 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
 895                                                 struct drm_atomic_state *state)
 896 {
 897         struct drm_connector_state *conn_state =
 898                 vc4_hdmi_encoder_get_connector_state(encoder, state);
 899         struct vc4_hdmi_connector_state *vc4_conn_state =
 900                 conn_state_to_vc4_hdmi_conn_state(conn_state);
 901         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 902         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 903         unsigned long pixel_rate = vc4_conn_state->pixel_rate;
 904         unsigned long bvb_rate, hsm_rate;
 905         int ret;
 906
 907         /*
 908          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
 909          * be faster than pixel clock, infinitesimally faster, tested in
 910          * simulation. Otherwise, exact value is unimportant for HDMI
 911          * operation." This conflicts with bcm2835's vc4 documentation, which
 912          * states HSM's clock has to be at least 108% of the pixel clock.
 913          *
 914          * Real life tests reveal that vc4's firmware statement holds up, and
 915          * users are able to use pixel clocks closer to HSM's, namely for
 916          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
 917          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
 918          * 162MHz.
 919          *
 920          * Additionally, the AXI clock needs to be at least 25% of
 921          * pixel clock, but HSM ends up being the limiting factor.
 922          */
 923         hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
 924         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
 925         if (ret) {
 926                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
 927                 return;
 928         }
 929
 930         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
 931         if (ret < 0) {
 932                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
 933                 return;
 934         }
 935
 936         ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
 937         if (ret) {
 938                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
 939                 goto err_put_runtime_pm;
 940         }
 941
 942         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
 943         if (ret) {
 944                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
 945                 goto err_put_runtime_pm;
 946         }
 947
 948
 949         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
 950
 951         if (pixel_rate > 297000000)
 952                 bvb_rate = 300000000;
 953         else if (pixel_rate > 148500000)
 954                 bvb_rate = 150000000;
 955         else
 956                 bvb_rate = 75000000;
 957
 958         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
 959         if (ret) {
 960                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
 961                 goto err_disable_pixel_clock;
 962         }
 963
 964         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
 965         if (ret) {
 966                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
 967                 goto err_disable_pixel_clock;
 968         }
 969
 970         if (vc4_hdmi->variant->phy_init)
 971                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
 972
 973         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 974                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
 975                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
 976                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
 977
 978         if (vc4_hdmi->variant->set_timings)
 979                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
 980
 981         return;
 982
 983 err_disable_pixel_clock:
 984         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 985 err_put_runtime_pm:
 986         pm_runtime_put(&vc4_hdmi->pdev->dev);
 987
 988         return;
 989 }
 990
 991 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
 992                                              struct drm_atomic_state *state)
 993 {
 994         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 995         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 996         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 997
 998         if (vc4_encoder->hdmi_monitor &&
 999             drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
1000                 if (vc4_hdmi->variant->csc_setup)
1001                         vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
1002
1003                 vc4_encoder->limited_rgb_range = true;
1004         } else {
1005                 if (vc4_hdmi->variant->csc_setup)
1006                         vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
1007
1008                 vc4_encoder->limited_rgb_range = false;
1009         }
1010
1011         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1012 }
1013
1014 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1015                                               struct drm_atomic_state *state)
1016 {
1017         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1018         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1019         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1020         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1021         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1022         int ret;
1023
1024         HDMI_WRITE(HDMI_VID_CTL,
1025                    VC4_HD_VID_CTL_ENABLE |
1026                    VC4_HD_VID_CTL_CLRRGB |
1027                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1028                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1029                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1030                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1031
1032         HDMI_WRITE(HDMI_VID_CTL,
1033                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1034
1035         if (vc4_encoder->hdmi_monitor) {
1036                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1037                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1038                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1039
1040                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1041                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1042                 WARN_ONCE(ret, "Timeout waiting for "
1043                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1044         } else {
1045                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1046                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1047                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1048                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1049                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1050                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1051
1052                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1053                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1054                 WARN_ONCE(ret, "Timeout waiting for "
1055                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1056         }
1057
1058         if (vc4_encoder->hdmi_monitor) {
1059                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1060                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1061                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1062                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1063                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
1064
1065                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1066                            VC4_HDMI_RAM_PACKET_ENABLE);
1067
1068                 vc4_hdmi_set_infoframes(encoder);
1069         }
1070
1071         vc4_hdmi_recenter_fifo(vc4_hdmi);
1072         vc4_hdmi_enable_scrambling(encoder);
1073 }
1074
1075 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
1076 {
1077 }
1078
1079 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
1080 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
1081
1082 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1083                                          struct drm_crtc_state *crtc_state,
1084                                          struct drm_connector_state *conn_state)
1085 {
1086         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1087         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1088         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1089         unsigned long long pixel_rate = mode->clock * 1000;
1090         unsigned long long tmds_rate;
1091
1092         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1093             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1094             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1095              (mode->hsync_end % 2) || (mode->htotal % 2)))
1096                 return -EINVAL;
1097
1098         /*
1099          * The 1440p@60 pixel rate is in the same range than the first
1100          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1101          * bandwidth). Slightly lower the frequency to bring it out of
1102          * the WiFi range.
1103          */
1104         tmds_rate = pixel_rate * 10;
1105         if (vc4_hdmi->disable_wifi_frequencies &&
1106             (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1107              tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1108                 mode->clock = 238560;
1109                 pixel_rate = mode->clock * 1000;
1110         }
1111
1112         if (conn_state->max_bpc == 12) {
1113                 pixel_rate = pixel_rate * 150;
1114                 do_div(pixel_rate, 100);
1115         } else if (conn_state->max_bpc == 10) {
1116                 pixel_rate = pixel_rate * 125;
1117                 do_div(pixel_rate, 100);
1118         }
1119
1120         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1121                 pixel_rate = pixel_rate * 2;
1122
1123         if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
1124                 return -EINVAL;
1125
1126         if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK))
1127                 return -EINVAL;
1128
1129         vc4_state->pixel_rate = pixel_rate;
1130
1131         return 0;
1132 }
1133
1134 static enum drm_mode_status
1135 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1136                             const struct drm_display_mode *mode)
1137 {
1138         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1139
1140         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1141             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1142             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1143              (mode->hsync_end % 2) || (mode->htotal % 2)))
1144                 return MODE_H_ILLEGAL;
1145
1146         if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
1147                 return MODE_CLOCK_HIGH;
1148
1149         if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode))
1150                 return MODE_CLOCK_HIGH;
1151
1152         return MODE_OK;
1153 }
1154
1155 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1156         .atomic_check = vc4_hdmi_encoder_atomic_check,
1157         .mode_valid = vc4_hdmi_encoder_mode_valid,
1158         .disable = vc4_hdmi_encoder_disable,
1159         .enable = vc4_hdmi_encoder_enable,
1160 };
1161
1162 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1163 {
1164         int i;
1165         u32 channel_map = 0;
1166
1167         for (i = 0; i < 8; i++) {
1168                 if (channel_mask & BIT(i))
1169                         channel_map |= i << (3 * i);
1170         }
1171         return channel_map;
1172 }
1173
1174 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1175 {
1176         int i;
1177         u32 channel_map = 0;
1178
1179         for (i = 0; i < 8; i++) {
1180                 if (channel_mask & BIT(i))
1181                         channel_map |= i << (4 * i);
1182         }
1183         return channel_map;
1184 }
1185
1186 /* HDMI audio codec callbacks */
1187 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1188                                          unsigned int samplerate)
1189 {
1190         u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1191         unsigned long n, m;
1192
1193         rational_best_approximation(hsm_clock, samplerate,
1194                                     VC4_HD_MAI_SMP_N_MASK >>
1195                                     VC4_HD_MAI_SMP_N_SHIFT,
1196                                     (VC4_HD_MAI_SMP_M_MASK >>
1197                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
1198                                     &n, &m);
1199
1200         HDMI_WRITE(HDMI_MAI_SMP,
1201                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1202                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1203 }
1204
1205 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1206 {
1207         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1208         struct drm_crtc *crtc = encoder->crtc;
1209         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1210         u32 n, cts;
1211         u64 tmp;
1212
1213         n = 128 * samplerate / 1000;
1214         tmp = (u64)(mode->clock * 1000) * n;
1215         do_div(tmp, 128 * samplerate);
1216         cts = tmp;
1217
1218         HDMI_WRITE(HDMI_CRP_CFG,
1219                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1220                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1221
1222         /*
1223          * We could get slightly more accurate clocks in some cases by
1224          * providing a CTS_1 value.  The two CTS values are alternated
1225          * between based on the period fields
1226          */
1227         HDMI_WRITE(HDMI_CTS_0, cts);
1228         HDMI_WRITE(HDMI_CTS_1, cts);
1229 }
1230
1231 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1232 {
1233         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1234
1235         return snd_soc_card_get_drvdata(card);
1236 }
1237
1238 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1239 {
1240         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1241         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1242
1243         /*
1244          * If the HDMI encoder hasn't probed, or the encoder is
1245          * currently in DVI mode, treat the codec dai as missing.
1246          */
1247         if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1248                                 VC4_HDMI_RAM_PACKET_ENABLE))
1249                 return -ENODEV;
1250
1251         vc4_hdmi->audio.streaming = true;
1252
1253         HDMI_WRITE(HDMI_MAI_CTL,
1254                    VC4_HD_MAI_CTL_RESET |
1255                    VC4_HD_MAI_CTL_FLUSH |
1256                    VC4_HD_MAI_CTL_DLATE |
1257                    VC4_HD_MAI_CTL_ERRORE |
1258                    VC4_HD_MAI_CTL_ERRORF);
1259
1260         if (vc4_hdmi->variant->phy_rng_enable)
1261                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1262
1263         return 0;
1264 }
1265
1266 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1267 {
1268         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1269         struct device *dev = &vc4_hdmi->pdev->dev;
1270         int ret;
1271
1272         vc4_hdmi->audio.streaming = false;
1273         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1274         if (ret)
1275                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1276
1277         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1278         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1279         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1280 }
1281
1282 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1283 {
1284         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1285
1286         HDMI_WRITE(HDMI_MAI_CTL,
1287                    VC4_HD_MAI_CTL_DLATE |
1288                    VC4_HD_MAI_CTL_ERRORE |
1289                    VC4_HD_MAI_CTL_ERRORF);
1290
1291         if (vc4_hdmi->variant->phy_rng_disable)
1292                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1293
1294         vc4_hdmi->audio.streaming = false;
1295         vc4_hdmi_audio_reset(vc4_hdmi);
1296 }
1297
1298 static int sample_rate_to_mai_fmt(int samplerate)
1299 {
1300         switch (samplerate) {
1301         case 8000:
1302                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1303         case 11025:
1304                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1305         case 12000:
1306                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1307         case 16000:
1308                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1309         case 22050:
1310                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1311         case 24000:
1312                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1313         case 32000:
1314                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1315         case 44100:
1316                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1317         case 48000:
1318                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1319         case 64000:
1320                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
1321         case 88200:
1322                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
1323         case 96000:
1324                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
1325         case 128000:
1326                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
1327         case 176400:
1328                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
1329         case 192000:
1330                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
1331         default:
1332                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
1333         }
1334 }
1335
1336 /* HDMI audio codec callbacks */
1337 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
1338                                   struct hdmi_codec_daifmt *daifmt,
1339                                   struct hdmi_codec_params *params)
1340 {
1341         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1342         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1343         unsigned int sample_rate = params->sample_rate;
1344         unsigned int channels = params->channels;
1345         u32 audio_packet_config, channel_mask;
1346         u32 channel_map;
1347         u32 mai_audio_format;
1348         u32 mai_sample_rate;
1349
1350         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1351                 sample_rate, params->sample_width, channels);
1352
1353         HDMI_WRITE(HDMI_MAI_CTL,
1354                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
1355                    VC4_HD_MAI_CTL_WHOLSMP |
1356                    VC4_HD_MAI_CTL_CHALIGN |
1357                    VC4_HD_MAI_CTL_ENABLE);
1358
1359         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
1360
1361         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
1362         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
1363             params->channels == 8)
1364                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
1365         else
1366                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
1367         HDMI_WRITE(HDMI_MAI_FMT,
1368                    VC4_SET_FIELD(mai_sample_rate,
1369                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
1370                    VC4_SET_FIELD(mai_audio_format,
1371                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
1372
1373         /* The B frame identifier should match the value used by alsa-lib (8) */
1374         audio_packet_config =
1375                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1376                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1377                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1378
1379         channel_mask = GENMASK(channels - 1, 0);
1380         audio_packet_config |= VC4_SET_FIELD(channel_mask,
1381                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1382
1383         /* Set the MAI threshold */
1384         HDMI_WRITE(HDMI_MAI_THR,
1385                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1386                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1387                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1388                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1389
1390         HDMI_WRITE(HDMI_MAI_CONFIG,
1391                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1392                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
1393                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1394
1395         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1396         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1397         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1398         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
1399
1400         memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
1401         vc4_hdmi_set_audio_infoframe(encoder);
1402
1403         return 0;
1404 }
1405
1406 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1407         .name = "vc4-hdmi-cpu-dai-component",
1408 };
1409
1410 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1411 {
1412         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1413
1414         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1415
1416         return 0;
1417 }
1418
1419 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1420         .name = "vc4-hdmi-cpu-dai",
1421         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1422         .playback = {
1423                 .stream_name = "Playback",
1424                 .channels_min = 1,
1425                 .channels_max = 8,
1426                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1427                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1428                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1429                          SNDRV_PCM_RATE_192000,
1430                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1431         },
1432 };
1433
1434 static const struct snd_dmaengine_pcm_config pcm_conf = {
1435         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1436         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1437 };
1438
1439 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
1440                                   uint8_t *buf, size_t len)
1441 {
1442         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1443         struct drm_connector *connector = &vc4_hdmi->connector;
1444
1445         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1446
1447         return 0;
1448 }
1449
1450 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
1451         .get_eld = vc4_hdmi_audio_get_eld,
1452         .prepare = vc4_hdmi_audio_prepare,
1453         .audio_shutdown = vc4_hdmi_audio_shutdown,
1454         .audio_startup = vc4_hdmi_audio_startup,
1455 };
1456
1457 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
1458         .ops = &vc4_hdmi_codec_ops,
1459         .max_i2s_channels = 8,
1460         .i2s = 1,
1461 };
1462
1463 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1464 {
1465         const struct vc4_hdmi_register *mai_data =
1466                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1467         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1468         struct snd_soc_card *card = &vc4_hdmi->audio.card;
1469         struct device *dev = &vc4_hdmi->pdev->dev;
1470         struct platform_device *codec_pdev;
1471         const __be32 *addr;
1472         int index;
1473         int ret;
1474
1475         if (!of_find_property(dev->of_node, "dmas", NULL)) {
1476                 dev_warn(dev,
1477                          "'dmas' DT property is missing, no HDMI audio\n");
1478                 return 0;
1479         }
1480
1481         if (mai_data->reg != VC4_HD) {
1482                 WARN_ONCE(true, "MAI isn't in the HD block\n");
1483                 return -EINVAL;
1484         }
1485
1486         /*
1487          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1488          * the bus address specified in the DT, because the physical address
1489          * (the one returned by platform_get_resource()) is not appropriate
1490          * for DMA transfers.
1491          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1492          */
1493         index = of_property_match_string(dev->of_node, "reg-names", "hd");
1494         /* Before BCM2711, we don't have a named register range */
1495         if (index < 0)
1496                 index = 1;
1497
1498         addr = of_get_address(dev->of_node, index, NULL, NULL);
1499
1500         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1501         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1502         vc4_hdmi->audio.dma_data.maxburst = 2;
1503
1504         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1505         if (ret) {
1506                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1507                 return ret;
1508         }
1509
1510         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1511                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1512         if (ret) {
1513                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1514                 return ret;
1515         }
1516
1517         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1518                                                    PLATFORM_DEVID_AUTO,
1519                                                    &vc4_hdmi_codec_pdata,
1520                                                    sizeof(vc4_hdmi_codec_pdata));
1521         if (IS_ERR(codec_pdev)) {
1522                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
1523                 return PTR_ERR(codec_pdev);
1524         }
1525         vc4_hdmi->audio.codec_pdev = codec_pdev;
1526
1527         dai_link->cpus          = &vc4_hdmi->audio.cpu;
1528         dai_link->codecs        = &vc4_hdmi->audio.codec;
1529         dai_link->platforms     = &vc4_hdmi->audio.platform;
1530
1531         dai_link->num_cpus      = 1;
1532         dai_link->num_codecs    = 1;
1533         dai_link->num_platforms = 1;
1534
1535         dai_link->name = "MAI";
1536         dai_link->stream_name = "MAI PCM";
1537         dai_link->codecs->dai_name = "i2s-hifi";
1538         dai_link->cpus->dai_name = dev_name(dev);
1539         dai_link->codecs->name = dev_name(&codec_pdev->dev);
1540         dai_link->platforms->name = dev_name(dev);
1541
1542         card->dai_link = dai_link;
1543         card->num_links = 1;
1544         card->name = vc4_hdmi->variant->card_name;
1545         card->driver_name = "vc4-hdmi";
1546         card->dev = dev;
1547         card->owner = THIS_MODULE;
1548
1549         /*
1550          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1551          * stores a pointer to the snd card object in dev->driver_data. This
1552          * means we cannot use it for something else. The hdmi back-pointer is
1553          * now stored in card->drvdata and should be retrieved with
1554          * snd_soc_card_get_drvdata() if needed.
1555          */
1556         snd_soc_card_set_drvdata(card, vc4_hdmi);
1557         ret = devm_snd_soc_register_card(dev, card);
1558         if (ret)
1559                 dev_err_probe(dev, ret, "Could not register sound card\n");
1560
1561         return ret;
1562
1563 }
1564
1565 static void vc4_hdmi_audio_exit(struct vc4_hdmi *vc4_hdmi)
1566 {
1567         platform_device_unregister(vc4_hdmi->audio.codec_pdev);
1568         vc4_hdmi->audio.codec_pdev = NULL;
1569 }
1570
1571 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
1572 {
1573         struct vc4_hdmi *vc4_hdmi = priv;
1574         struct drm_device *dev = vc4_hdmi->connector.dev;
1575
1576         if (dev && dev->registered)
1577                 drm_kms_helper_hotplug_event(dev);
1578
1579         return IRQ_HANDLED;
1580 }
1581
1582 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
1583 {
1584         struct drm_connector *connector = &vc4_hdmi->connector;
1585         struct platform_device *pdev = vc4_hdmi->pdev;
1586         int ret;
1587
1588         if (vc4_hdmi->variant->external_irq_controller) {
1589                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
1590                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
1591
1592                 ret = request_threaded_irq(hpd_con,
1593                                            NULL,
1594                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1595                                            "vc4 hdmi hpd connected", vc4_hdmi);
1596                 if (ret)
1597                         return ret;
1598
1599                 ret = request_threaded_irq(hpd_rm,
1600                                            NULL,
1601                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1602                                            "vc4 hdmi hpd disconnected", vc4_hdmi);
1603                 if (ret) {
1604                         free_irq(hpd_con, vc4_hdmi);
1605                         return ret;
1606                 }
1607
1608                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1609         }
1610
1611         return 0;
1612 }
1613
1614 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi)
1615 {
1616         struct platform_device *pdev = vc4_hdmi->pdev;
1617
1618         if (vc4_hdmi->variant->external_irq_controller) {
1619                 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi);
1620                 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi);
1621         }
1622 }
1623
1624 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1625 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1626 {
1627         struct vc4_hdmi *vc4_hdmi = priv;
1628
1629         if (vc4_hdmi->cec_rx_msg.len)
1630                 cec_received_msg(vc4_hdmi->cec_adap,
1631                                  &vc4_hdmi->cec_rx_msg);
1632
1633         return IRQ_HANDLED;
1634 }
1635
1636 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1637 {
1638         struct vc4_hdmi *vc4_hdmi = priv;
1639
1640         if (vc4_hdmi->cec_tx_ok) {
1641                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1642                                   0, 0, 0, 0);
1643         } else {
1644                 /*
1645                  * This CEC implementation makes 1 retry, so if we
1646                  * get a NACK, then that means it made 2 attempts.
1647                  */
1648                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1649                                   0, 2, 0, 0);
1650         }
1651         return IRQ_HANDLED;
1652 }
1653
1654 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1655 {
1656         struct vc4_hdmi *vc4_hdmi = priv;
1657         irqreturn_t ret;
1658
1659         if (vc4_hdmi->cec_irq_was_rx)
1660                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1661         else
1662                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1663
1664         return ret;
1665 }
1666
1667 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1668 {
1669         struct drm_device *dev = vc4_hdmi->connector.dev;
1670         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1671         unsigned int i;
1672
1673         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1674                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1675
1676         if (msg->len > 16) {
1677                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1678                 return;
1679         }
1680
1681         for (i = 0; i < msg->len; i += 4) {
1682                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1683
1684                 msg->msg[i] = val & 0xff;
1685                 msg->msg[i + 1] = (val >> 8) & 0xff;
1686                 msg->msg[i + 2] = (val >> 16) & 0xff;
1687                 msg->msg[i + 3] = (val >> 24) & 0xff;
1688         }
1689 }
1690
1691 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1692 {
1693         struct vc4_hdmi *vc4_hdmi = priv;
1694         u32 cntrl1;
1695
1696         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1697         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1698         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1699         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1700
1701         return IRQ_WAKE_THREAD;
1702 }
1703
1704 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1705 {
1706         struct vc4_hdmi *vc4_hdmi = priv;
1707         u32 cntrl1;
1708
1709         vc4_hdmi->cec_rx_msg.len = 0;
1710         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1711         vc4_cec_read_msg(vc4_hdmi, cntrl1);
1712         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1713         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1714         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1715
1716         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1717
1718         return IRQ_WAKE_THREAD;
1719 }
1720
1721 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1722 {
1723         struct vc4_hdmi *vc4_hdmi = priv;
1724         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1725         irqreturn_t ret;
1726         u32 cntrl5;
1727
1728         if (!(stat & VC4_HDMI_CPU_CEC))
1729                 return IRQ_NONE;
1730
1731         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1732         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1733         if (vc4_hdmi->cec_irq_was_rx)
1734                 ret = vc4_cec_irq_handler_rx_bare(irq, priv);
1735         else
1736                 ret = vc4_cec_irq_handler_tx_bare(irq, priv);
1737
1738         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1739         return ret;
1740 }
1741
1742 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1743 {
1744         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1745         /* clock period in microseconds */
1746         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1747         u32 val = HDMI_READ(HDMI_CEC_CNTRL_5);
1748
1749         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1750                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1751                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1752         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1753                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1754
1755         if (enable) {
1756                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1757                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1758                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1759                 HDMI_WRITE(HDMI_CEC_CNTRL_2,
1760                            ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1761                            ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1762                            ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1763                            ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1764                            ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1765                 HDMI_WRITE(HDMI_CEC_CNTRL_3,
1766                            ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1767                            ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1768                            ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1769                            ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1770                 HDMI_WRITE(HDMI_CEC_CNTRL_4,
1771                            ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1772                            ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1773                            ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1774                            ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1775
1776                 if (!vc4_hdmi->variant->external_irq_controller)
1777                         HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1778         } else {
1779                 if (!vc4_hdmi->variant->external_irq_controller)
1780                         HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1781                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1782                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1783         }
1784         return 0;
1785 }
1786
1787 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1788 {
1789         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1790
1791         HDMI_WRITE(HDMI_CEC_CNTRL_1,
1792                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1793                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1794         return 0;
1795 }
1796
1797 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1798                                       u32 signal_free_time, struct cec_msg *msg)
1799 {
1800         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1801         struct drm_device *dev = vc4_hdmi->connector.dev;
1802         u32 val;
1803         unsigned int i;
1804
1805         if (msg->len > 16) {
1806                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
1807                 return -ENOMEM;
1808         }
1809
1810         for (i = 0; i < msg->len; i += 4)
1811                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
1812                            (msg->msg[i]) |
1813                            (msg->msg[i + 1] << 8) |
1814                            (msg->msg[i + 2] << 16) |
1815                            (msg->msg[i + 3] << 24));
1816
1817         val = HDMI_READ(HDMI_CEC_CNTRL_1);
1818         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1819         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1820         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1821         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1822         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1823
1824         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1825         return 0;
1826 }
1827
1828 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1829         .adap_enable = vc4_hdmi_cec_adap_enable,
1830         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1831         .adap_transmit = vc4_hdmi_cec_adap_transmit,
1832 };
1833
1834 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1835 {
1836         struct cec_connector_info conn_info;
1837         struct platform_device *pdev = vc4_hdmi->pdev;
1838         struct device *dev = &pdev->dev;
1839         u32 value;
1840         int ret;
1841
1842         if (!of_find_property(dev->of_node, "interrupts", NULL)) {
1843                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
1844                 return 0;
1845         }
1846
1847         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1848                                                   vc4_hdmi, "vc4",
1849                                                   CEC_CAP_DEFAULTS |
1850                                                   CEC_CAP_CONNECTOR_INFO, 1);
1851         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
1852         if (ret < 0)
1853                 return ret;
1854
1855         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
1856         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
1857
1858         value = HDMI_READ(HDMI_CEC_CNTRL_1);
1859         /* Set the logical address to Unregistered */
1860         value |= VC4_HDMI_CEC_ADDR_MASK;
1861         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
1862
1863         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1864
1865         if (vc4_hdmi->variant->external_irq_controller) {
1866                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"),
1867                                            vc4_cec_irq_handler_rx_bare,
1868                                            vc4_cec_irq_handler_rx_thread, 0,
1869                                            "vc4 hdmi cec rx", vc4_hdmi);
1870                 if (ret)
1871                         goto err_delete_cec_adap;
1872
1873                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"),
1874                                            vc4_cec_irq_handler_tx_bare,
1875                                            vc4_cec_irq_handler_tx_thread, 0,
1876                                            "vc4 hdmi cec tx", vc4_hdmi);
1877                 if (ret)
1878                         goto err_remove_cec_rx_handler;
1879         } else {
1880                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
1881
1882                 ret = request_threaded_irq(platform_get_irq(pdev, 0),
1883                                            vc4_cec_irq_handler,
1884                                            vc4_cec_irq_handler_thread, 0,
1885                                            "vc4 hdmi cec", vc4_hdmi);
1886                 if (ret)
1887                         goto err_delete_cec_adap;
1888         }
1889
1890         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
1891         if (ret < 0)
1892                 goto err_remove_handlers;
1893
1894         return 0;
1895
1896 err_remove_handlers:
1897         if (vc4_hdmi->variant->external_irq_controller)
1898                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
1899         else
1900                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
1901
1902 err_remove_cec_rx_handler:
1903         if (vc4_hdmi->variant->external_irq_controller)
1904                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
1905
1906 err_delete_cec_adap:
1907         cec_delete_adapter(vc4_hdmi->cec_adap);
1908
1909         return ret;
1910 }
1911
1912 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
1913 {
1914         struct platform_device *pdev = vc4_hdmi->pdev;
1915
1916         if (vc4_hdmi->variant->external_irq_controller) {
1917                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
1918                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
1919         } else {
1920                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
1921         }
1922
1923         cec_unregister_adapter(vc4_hdmi->cec_adap);
1924 }
1925 #else
1926 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1927 {
1928         return 0;
1929 }
1930
1931 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
1932
1933 #endif
1934
1935 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
1936                                  struct debugfs_regset32 *regset,
1937                                  enum vc4_hdmi_regs reg)
1938 {
1939         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1940         struct debugfs_reg32 *regs, *new_regs;
1941         unsigned int count = 0;
1942         unsigned int i;
1943
1944         regs = kcalloc(variant->num_registers, sizeof(*regs),
1945                        GFP_KERNEL);
1946         if (!regs)
1947                 return -ENOMEM;
1948
1949         for (i = 0; i < variant->num_registers; i++) {
1950                 const struct vc4_hdmi_register *field = &variant->registers[i];
1951
1952                 if (field->reg != reg)
1953                         continue;
1954
1955                 regs[count].name = field->name;
1956                 regs[count].offset = field->offset;
1957                 count++;
1958         }
1959
1960         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
1961         if (!new_regs)
1962                 return -ENOMEM;
1963
1964         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
1965         regset->regs = new_regs;
1966         regset->nregs = count;
1967
1968         return 0;
1969 }
1970
1971 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1972 {
1973         struct platform_device *pdev = vc4_hdmi->pdev;
1974         struct device *dev = &pdev->dev;
1975         int ret;
1976
1977         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1978         if (IS_ERR(vc4_hdmi->hdmicore_regs))
1979                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1980
1981         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1982         if (IS_ERR(vc4_hdmi->hd_regs))
1983                 return PTR_ERR(vc4_hdmi->hd_regs);
1984
1985         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
1986         if (ret)
1987                 return ret;
1988
1989         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
1990         if (ret)
1991                 return ret;
1992
1993         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1994         if (IS_ERR(vc4_hdmi->pixel_clock)) {
1995                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
1996                 if (ret != -EPROBE_DEFER)
1997                         DRM_ERROR("Failed to get pixel clock\n");
1998                 return ret;
1999         }
2000
2001         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2002         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2003                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2004                 return PTR_ERR(vc4_hdmi->hsm_clock);
2005         }
2006         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2007         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2008
2009         return 0;
2010 }
2011
2012 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2013 {
2014         struct platform_device *pdev = vc4_hdmi->pdev;
2015         struct device *dev = &pdev->dev;
2016         struct resource *res;
2017
2018         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2019         if (!res)
2020                 return -ENODEV;
2021
2022         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2023                                                resource_size(res));
2024         if (!vc4_hdmi->hdmicore_regs)
2025                 return -ENOMEM;
2026
2027         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2028         if (!res)
2029                 return -ENODEV;
2030
2031         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2032         if (!vc4_hdmi->hd_regs)
2033                 return -ENOMEM;
2034
2035         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2036         if (!res)
2037                 return -ENODEV;
2038
2039         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2040         if (!vc4_hdmi->cec_regs)
2041                 return -ENOMEM;
2042
2043         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2044         if (!res)
2045                 return -ENODEV;
2046
2047         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2048         if (!vc4_hdmi->csc_regs)
2049                 return -ENOMEM;
2050
2051         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2052         if (!res)
2053                 return -ENODEV;
2054
2055         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2056         if (!vc4_hdmi->dvp_regs)
2057                 return -ENOMEM;
2058
2059         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2060         if (!res)
2061                 return -ENODEV;
2062
2063         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2064         if (!vc4_hdmi->phy_regs)
2065                 return -ENOMEM;
2066
2067         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2068         if (!res)
2069                 return -ENODEV;
2070
2071         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2072         if (!vc4_hdmi->ram_regs)
2073                 return -ENOMEM;
2074
2075         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2076         if (!res)
2077                 return -ENODEV;
2078
2079         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2080         if (!vc4_hdmi->rm_regs)
2081                 return -ENOMEM;
2082
2083         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2084         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2085                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2086                 return PTR_ERR(vc4_hdmi->hsm_clock);
2087         }
2088
2089         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2090         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2091                 DRM_ERROR("Failed to get pixel bvb clock\n");
2092                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2093         }
2094
2095         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2096         if (IS_ERR(vc4_hdmi->audio_clock)) {
2097                 DRM_ERROR("Failed to get audio clock\n");
2098                 return PTR_ERR(vc4_hdmi->audio_clock);
2099         }
2100
2101         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2102         if (IS_ERR(vc4_hdmi->cec_clock)) {
2103                 DRM_ERROR("Failed to get CEC clock\n");
2104                 return PTR_ERR(vc4_hdmi->cec_clock);
2105         }
2106
2107         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2108         if (IS_ERR(vc4_hdmi->reset)) {
2109                 DRM_ERROR("Failed to get HDMI reset line\n");
2110                 return PTR_ERR(vc4_hdmi->reset);
2111         }
2112
2113         return 0;
2114 }
2115
2116 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev)
2117 {
2118         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2119
2120         clk_disable_unprepare(vc4_hdmi->hsm_clock);
2121
2122         return 0;
2123 }
2124
2125 static int vc4_hdmi_runtime_resume(struct device *dev)
2126 {
2127         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2128         int ret;
2129
2130         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
2131         if (ret)
2132                 return ret;
2133
2134         return 0;
2135 }
2136
2137 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2138 {
2139         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2140         struct platform_device *pdev = to_platform_device(dev);
2141         struct drm_device *drm = dev_get_drvdata(master);
2142         struct vc4_hdmi *vc4_hdmi;
2143         struct drm_encoder *encoder;
2144         struct device_node *ddc_node;
2145         int ret;
2146
2147         vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2148         if (!vc4_hdmi)
2149                 return -ENOMEM;
2150         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2151
2152         dev_set_drvdata(dev, vc4_hdmi);
2153         encoder = &vc4_hdmi->encoder.base.base;
2154         vc4_hdmi->encoder.base.type = variant->encoder_type;
2155         vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2156         vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2157         vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2158         vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2159         vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2160         vc4_hdmi->pdev = pdev;
2161         vc4_hdmi->variant = variant;
2162
2163         ret = variant->init_resources(vc4_hdmi);
2164         if (ret)
2165                 return ret;
2166
2167         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2168         if (!ddc_node) {
2169                 DRM_ERROR("Failed to find ddc node in device tree\n");
2170                 return -ENODEV;
2171         }
2172
2173         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2174         of_node_put(ddc_node);
2175         if (!vc4_hdmi->ddc) {
2176                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2177                 return -EPROBE_DEFER;
2178         }
2179
2180         /* Only use the GPIO HPD pin if present in the DT, otherwise
2181          * we'll use the HDMI core's register.
2182          */
2183         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2184         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
2185                 ret = PTR_ERR(vc4_hdmi->hpd_gpio);
2186                 goto err_put_ddc;
2187         }
2188
2189         vc4_hdmi->disable_wifi_frequencies =
2190                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2191
2192         if (variant->max_pixel_clock == 600000000) {
2193                 struct vc4_dev *vc4 = to_vc4_dev(drm);
2194                 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
2195
2196                 if (max_rate < 550000000)
2197                         vc4_hdmi->disable_4kp60 = true;
2198         }
2199
2200         /*
2201          * If we boot without any cable connected to the HDMI connector,
2202          * the firmware will skip the HSM initialization and leave it
2203          * with a rate of 0, resulting in a bus lockup when we're
2204          * accessing the registers even if it's enabled.
2205          *
2206          * Let's put a sensible default at runtime_resume so that we
2207          * don't end up in this situation.
2208          */
2209         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
2210         if (ret)
2211                 goto err_put_ddc;
2212
2213         /*
2214          * We need to have the device powered up at this point to call
2215          * our reset hook and for the CEC init.
2216          */
2217         ret = vc4_hdmi_runtime_resume(dev);
2218         if (ret)
2219                 goto err_put_ddc;
2220
2221         pm_runtime_get_noresume(dev);
2222         pm_runtime_set_active(dev);
2223         pm_runtime_enable(dev);
2224
2225         if (vc4_hdmi->variant->reset)
2226                 vc4_hdmi->variant->reset(vc4_hdmi);
2227
2228         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
2229              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
2230             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
2231                 clk_prepare_enable(vc4_hdmi->pixel_clock);
2232                 clk_prepare_enable(vc4_hdmi->hsm_clock);
2233                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
2234         }
2235
2236         drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2237         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2238
2239         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2240         if (ret)
2241                 goto err_destroy_encoder;
2242
2243         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
2244         if (ret)
2245                 goto err_destroy_conn;
2246
2247         ret = vc4_hdmi_cec_init(vc4_hdmi);
2248         if (ret)
2249                 goto err_free_hotplug;
2250
2251         ret = vc4_hdmi_audio_init(vc4_hdmi);
2252         if (ret)
2253                 goto err_free_cec;
2254
2255         vc4_debugfs_add_file(drm, variant->debugfs_name,
2256                              vc4_hdmi_debugfs_regs,
2257                              vc4_hdmi);
2258
2259         pm_runtime_put_sync(dev);
2260
2261         return 0;
2262
2263 err_free_cec:
2264         vc4_hdmi_cec_exit(vc4_hdmi);
2265 err_free_hotplug:
2266         vc4_hdmi_hotplug_exit(vc4_hdmi);
2267 err_destroy_conn:
2268         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2269 err_destroy_encoder:
2270         drm_encoder_cleanup(encoder);
2271         pm_runtime_put_sync(dev);
2272         pm_runtime_disable(dev);
2273 err_put_ddc:
2274         put_device(&vc4_hdmi->ddc->dev);
2275
2276         return ret;
2277 }
2278
2279 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2280                             void *data)
2281 {
2282         struct vc4_hdmi *vc4_hdmi;
2283
2284         /*
2285          * ASoC makes it a bit hard to retrieve a pointer to the
2286          * vc4_hdmi structure. Registering the card will overwrite our
2287          * device drvdata with a pointer to the snd_soc_card structure,
2288          * which can then be used to retrieve whatever drvdata we want
2289          * to associate.
2290          *
2291          * However, that doesn't fly in the case where we wouldn't
2292          * register an ASoC card (because of an old DT that is missing
2293          * the dmas properties for example), then the card isn't
2294          * registered and the device drvdata wouldn't be set.
2295          *
2296          * We can deal with both cases by making sure a snd_soc_card
2297          * pointer and a vc4_hdmi structure are pointing to the same
2298          * memory address, so we can treat them indistinctly without any
2299          * issue.
2300          */
2301         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2302         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2303         vc4_hdmi = dev_get_drvdata(dev);
2304
2305         kfree(vc4_hdmi->hdmi_regset.regs);
2306         kfree(vc4_hdmi->hd_regset.regs);
2307
2308         vc4_hdmi_audio_exit(vc4_hdmi);
2309         vc4_hdmi_cec_exit(vc4_hdmi);
2310         vc4_hdmi_hotplug_exit(vc4_hdmi);
2311         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2312         drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2313
2314         pm_runtime_disable(dev);
2315
2316         put_device(&vc4_hdmi->ddc->dev);
2317 }
2318
2319 static const struct component_ops vc4_hdmi_ops = {
2320         .bind   = vc4_hdmi_bind,
2321         .unbind = vc4_hdmi_unbind,
2322 };
2323
2324 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2325 {
2326         return component_add(&pdev->dev, &vc4_hdmi_ops);
2327 }
2328
2329 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2330 {
2331         component_del(&pdev->dev, &vc4_hdmi_ops);
2332         return 0;
2333 }
2334
2335 static const struct vc4_hdmi_variant bcm2835_variant = {
2336         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2337         .debugfs_name           = "hdmi_regs",
2338         .card_name              = "vc4-hdmi",
2339         .max_pixel_clock        = 162000000,
2340         .registers              = vc4_hdmi_fields,
2341         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
2342
2343         .init_resources         = vc4_hdmi_init_resources,
2344         .csc_setup              = vc4_hdmi_csc_setup,
2345         .reset                  = vc4_hdmi_reset,
2346         .set_timings            = vc4_hdmi_set_timings,
2347         .phy_init               = vc4_hdmi_phy_init,
2348         .phy_disable            = vc4_hdmi_phy_disable,
2349         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
2350         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
2351         .channel_map            = vc4_hdmi_channel_map,
2352         .supports_hdr           = false,
2353 };
2354
2355 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2356         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2357         .debugfs_name           = "hdmi0_regs",
2358         .card_name              = "vc4-hdmi-0",
2359         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2360         .registers              = vc5_hdmi_hdmi0_fields,
2361         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2362         .phy_lane_mapping       = {
2363                 PHY_LANE_0,
2364                 PHY_LANE_1,
2365                 PHY_LANE_2,
2366                 PHY_LANE_CK,
2367         },
2368         .unsupported_odd_h_timings      = true,
2369         .external_irq_controller        = true,
2370
2371         .init_resources         = vc5_hdmi_init_resources,
2372         .csc_setup              = vc5_hdmi_csc_setup,
2373         .reset                  = vc5_hdmi_reset,
2374         .set_timings            = vc5_hdmi_set_timings,
2375         .phy_init               = vc5_hdmi_phy_init,
2376         .phy_disable            = vc5_hdmi_phy_disable,
2377         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2378         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2379         .channel_map            = vc5_hdmi_channel_map,
2380         .supports_hdr           = true,
2381 };
2382
2383 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2384         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
2385         .debugfs_name           = "hdmi1_regs",
2386         .card_name              = "vc4-hdmi-1",
2387         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2388         .registers              = vc5_hdmi_hdmi1_fields,
2389         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2390         .phy_lane_mapping       = {
2391                 PHY_LANE_1,
2392                 PHY_LANE_0,
2393                 PHY_LANE_CK,
2394                 PHY_LANE_2,
2395         },
2396         .unsupported_odd_h_timings      = true,
2397         .external_irq_controller        = true,
2398
2399         .init_resources         = vc5_hdmi_init_resources,
2400         .csc_setup              = vc5_hdmi_csc_setup,
2401         .reset                  = vc5_hdmi_reset,
2402         .set_timings            = vc5_hdmi_set_timings,
2403         .phy_init               = vc5_hdmi_phy_init,
2404         .phy_disable            = vc5_hdmi_phy_disable,
2405         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2406         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2407         .channel_map            = vc5_hdmi_channel_map,
2408         .supports_hdr           = true,
2409 };
2410
2411 static const struct of_device_id vc4_hdmi_dt_match[] = {
2412         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2413         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2414         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2415         {}
2416 };
2417
2418 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
2419         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
2420                            vc4_hdmi_runtime_resume,
2421                            NULL)
2422 };
2423
2424 struct platform_driver vc4_hdmi_driver = {
2425         .probe = vc4_hdmi_dev_probe,
2426         .remove = vc4_hdmi_dev_remove,
2427         .driver = {
2428                 .name = "vc4_hdmi",
2429                 .of_match_table = vc4_hdmi_dt_match,
2430                 .pm = &vc4_hdmi_pm_ops,
2431         },
2432 };