drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <drm/drm_simple_kms_helper.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include <linux/clk.h>
  40 #include <linux/component.h>
  41 #include <linux/i2c.h>
  42 #include <linux/of_address.h>
  43 #include <linux/of_gpio.h>
  44 #include <linux/of_platform.h>
  45 #include <linux/pm_runtime.h>
  46 #include <linux/rational.h>
  47 #include <linux/reset.h>
  48 #include <sound/dmaengine_pcm.h>
  49 #include <sound/hdmi-codec.h>
  50 #include <sound/pcm_drm_eld.h>
  51 #include <sound/pcm_params.h>
  52 #include <sound/soc.h>
  53 #include "media/cec.h"
  54 #include "vc4_drv.h"
  55 #include "vc4_hdmi.h"
  56 #include "vc4_hdmi_regs.h"
  57 #include "vc4_regs.h"
  58
  59 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  60 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  61 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  62 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  63 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  64 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  65
  66 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  67 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  68 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  69 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  70
  71 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  72 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  73 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  74 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  75 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  76 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  77
  78 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  79 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  80
  81 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  82
  83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  85
  86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  88
  89 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  90
  91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
  92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
  93
  94 # define VC4_HD_M_SW_RST                        BIT(2)
  95 # define VC4_HD_M_ENABLE                        BIT(0)
  96
  97 #define HSM_MIN_CLOCK_FREQ      120000000
  98 #define CEC_CLOCK_FREQ 40000
  99
 100 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 101
 102 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode)
 103 {
 104         return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK;
 105 }
 106
 107 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 108 {
 109         struct drm_info_node *node = (struct drm_info_node *)m->private;
 110         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
 111         struct drm_printer p = drm_seq_file_printer(m);
 112
 113         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 114         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 115
 116         return 0;
 117 }
 118
 119 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 120 {
 121         unsigned long flags;
 122
 123         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 124
 125         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 126         udelay(1);
 127         HDMI_WRITE(HDMI_M_CTL, 0);
 128
 129         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 130
 131         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 132                    VC4_HDMI_SW_RESET_HDMI |
 133                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 134
 135         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 136
 137         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 138 }
 139
 140 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 141 {
 142         unsigned long flags;
 143
 144         reset_control_reset(vc4_hdmi->reset);
 145
 146         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 147
 148         HDMI_WRITE(HDMI_DVP_CTL, 0);
 149
 150         HDMI_WRITE(HDMI_CLOCK_STOP,
 151                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 152
 153         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 154 }
 155
 156 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 157 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 158 {
 159         unsigned long cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
 160         unsigned long flags;
 161         u16 clk_cnt;
 162         u32 value;
 163
 164         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 165
 166         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 167         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 168
 169         /*
 170          * Set the clock divider: the hsm_clock rate and this divider
 171          * setting will give a 40 kHz CEC clock.
 172          */
 173         clk_cnt = cec_rate / CEC_CLOCK_FREQ;
 174         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 175         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 176
 177         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 178 }
 179 #else
 180 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 181 #endif
 182
 183 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder);
 184
 185 static enum drm_connector_status
 186 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 187 {
 188         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 189         bool connected = false;
 190
 191         mutex_lock(&vc4_hdmi->mutex);
 192
 193         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 194
 195         if (vc4_hdmi->hpd_gpio) {
 196                 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
 197                         connected = true;
 198         } else {
 199                 unsigned long flags;
 200                 u32 hotplug;
 201
 202                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 203                 hotplug = HDMI_READ(HDMI_HOTPLUG);
 204                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 205
 206                 if (hotplug & VC4_HDMI_HOTPLUG_CONNECTED)
 207                         connected = true;
 208         }
 209
 210         if (connected) {
 211                 if (connector->status != connector_status_connected) {
 212                         struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
 213
 214                         if (edid) {
 215                                 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 216                                 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
 217                                 kfree(edid);
 218                         }
 219                 }
 220
 221                 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base);
 222                 pm_runtime_put(&vc4_hdmi->pdev->dev);
 223                 mutex_unlock(&vc4_hdmi->mutex);
 224                 return connector_status_connected;
 225         }
 226
 227         cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 228         pm_runtime_put(&vc4_hdmi->pdev->dev);
 229         mutex_unlock(&vc4_hdmi->mutex);
 230         return connector_status_disconnected;
 231 }
 232
 233 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 234 {
 235         drm_connector_unregister(connector);
 236         drm_connector_cleanup(connector);
 237 }
 238
 239 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 240 {
 241         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 242         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 243         int ret = 0;
 244         struct edid *edid;
 245
 246         mutex_lock(&vc4_hdmi->mutex);
 247
 248         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 249         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 250         if (!edid) {
 251                 ret = -ENODEV;
 252                 goto out;
 253         }
 254
 255         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 256
 257         drm_connector_update_edid_property(connector, edid);
 258         ret = drm_add_edid_modes(connector, edid);
 259         kfree(edid);
 260
 261         if (vc4_hdmi->disable_4kp60) {
 262                 struct drm_device *drm = connector->dev;
 263                 struct drm_display_mode *mode;
 264
 265                 list_for_each_entry(mode, &connector->probed_modes, head) {
 266                         if (vc4_hdmi_mode_needs_scrambling(mode)) {
 267                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 268                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 269                         }
 270                 }
 271         }
 272
 273 out:
 274         mutex_unlock(&vc4_hdmi->mutex);
 275
 276         return ret;
 277 }
 278
 279 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 280                                            struct drm_atomic_state *state)
 281 {
 282         struct drm_connector_state *old_state =
 283                 drm_atomic_get_old_connector_state(state, connector);
 284         struct drm_connector_state *new_state =
 285                 drm_atomic_get_new_connector_state(state, connector);
 286         struct drm_crtc *crtc = new_state->crtc;
 287
 288         if (!crtc)
 289                 return 0;
 290
 291         if (old_state->colorspace != new_state->colorspace ||
 292             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 293                 struct drm_crtc_state *crtc_state;
 294
 295                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 296                 if (IS_ERR(crtc_state))
 297                         return PTR_ERR(crtc_state);
 298
 299                 crtc_state->mode_changed = true;
 300         }
 301
 302         return 0;
 303 }
 304
 305 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 306 {
 307         struct vc4_hdmi_connector_state *old_state =
 308                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 309         struct vc4_hdmi_connector_state *new_state =
 310                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 311
 312         if (connector->state)
 313                 __drm_atomic_helper_connector_destroy_state(connector->state);
 314
 315         kfree(old_state);
 316         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 317
 318         if (!new_state)
 319                 return;
 320
 321         new_state->base.max_bpc = 8;
 322         new_state->base.max_requested_bpc = 8;
 323         drm_atomic_helper_connector_tv_reset(connector);
 324 }
 325
 326 static struct drm_connector_state *
 327 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 328 {
 329         struct drm_connector_state *conn_state = connector->state;
 330         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 331         struct vc4_hdmi_connector_state *new_state;
 332
 333         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 334         if (!new_state)
 335                 return NULL;
 336
 337         new_state->pixel_rate = vc4_state->pixel_rate;
 338         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 339
 340         return &new_state->base;
 341 }
 342
 343 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 344         .detect = vc4_hdmi_connector_detect,
 345         .fill_modes = drm_helper_probe_single_connector_modes,
 346         .destroy = vc4_hdmi_connector_destroy,
 347         .reset = vc4_hdmi_connector_reset,
 348         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 349         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 350 };
 351
 352 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 353         .get_modes = vc4_hdmi_connector_get_modes,
 354         .atomic_check = vc4_hdmi_connector_atomic_check,
 355 };
 356
 357 static int vc4_hdmi_connector_init(struct drm_device *dev,
 358                                    struct vc4_hdmi *vc4_hdmi)
 359 {
 360         struct drm_connector *connector = &vc4_hdmi->connector;
 361         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 362         int ret;
 363
 364         drm_connector_init_with_ddc(dev, connector,
 365                                     &vc4_hdmi_connector_funcs,
 366                                     DRM_MODE_CONNECTOR_HDMIA,
 367                                     vc4_hdmi->ddc);
 368         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 369
 370         /*
 371          * Some of the properties below require access to state, like bpc.
 372          * Allocate some default initial connector state with our reset helper.
 373          */
 374         if (connector->funcs->reset)
 375                 connector->funcs->reset(connector);
 376
 377         /* Create and attach TV margin props to this connector. */
 378         ret = drm_mode_create_tv_margin_properties(dev);
 379         if (ret)
 380                 return ret;
 381
 382         ret = drm_mode_create_hdmi_colorspace_property(connector);
 383         if (ret)
 384                 return ret;
 385
 386         drm_connector_attach_colorspace_property(connector);
 387         drm_connector_attach_tv_margin_properties(connector);
 388         drm_connector_attach_max_bpc_property(connector, 8, 12);
 389
 390         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 391                              DRM_CONNECTOR_POLL_DISCONNECT);
 392
 393         connector->interlace_allowed = 1;
 394         connector->doublescan_allowed = 0;
 395
 396         if (vc4_hdmi->variant->supports_hdr)
 397                 drm_connector_attach_hdr_output_metadata_property(connector);
 398
 399         drm_connector_attach_encoder(connector, encoder);
 400
 401         return 0;
 402 }
 403
 404 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 405                                 enum hdmi_infoframe_type type,
 406                                 bool poll)
 407 {
 408         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 409         u32 packet_id = type - 0x80;
 410         unsigned long flags;
 411
 412         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 413         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 414                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 415         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 416
 417         if (!poll)
 418                 return 0;
 419
 420         return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 421                           BIT(packet_id)), 100);
 422 }
 423
 424 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 425                                      union hdmi_infoframe *frame)
 426 {
 427         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 428         u32 packet_id = frame->any.type - 0x80;
 429         const struct vc4_hdmi_register *ram_packet_start =
 430                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 431         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 432         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 433                                                        ram_packet_start->reg);
 434         uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
 435         unsigned long flags;
 436         ssize_t len, i;
 437         int ret;
 438
 439         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 440                     VC4_HDMI_RAM_PACKET_ENABLE),
 441                   "Packet RAM has to be on to store the packet.");
 442
 443         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 444         if (len < 0)
 445                 return;
 446
 447         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 448         if (ret) {
 449                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 450                 return;
 451         }
 452
 453         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 454
 455         for (i = 0; i < len; i += 7) {
 456                 writel(buffer[i + 0] << 0 |
 457                        buffer[i + 1] << 8 |
 458                        buffer[i + 2] << 16,
 459                        base + packet_reg);
 460                 packet_reg += 4;
 461
 462                 writel(buffer[i + 3] << 0 |
 463                        buffer[i + 4] << 8 |
 464                        buffer[i + 5] << 16 |
 465                        buffer[i + 6] << 24,
 466                        base + packet_reg);
 467                 packet_reg += 4;
 468         }
 469
 470         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 471                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 472
 473         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 474
 475         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 476                         BIT(packet_id)), 100);
 477         if (ret)
 478                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 479 }
 480
 481 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 482 {
 483         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 484         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 485         struct drm_connector *connector = &vc4_hdmi->connector;
 486         struct drm_connector_state *cstate = connector->state;
 487         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 488         union hdmi_infoframe frame;
 489         int ret;
 490
 491         lockdep_assert_held(&vc4_hdmi->mutex);
 492
 493         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 494                                                        connector, mode);
 495         if (ret < 0) {
 496                 DRM_ERROR("couldn't fill AVI infoframe\n");
 497                 return;
 498         }
 499
 500         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 501                                            connector, mode,
 502                                            vc4_encoder->limited_rgb_range ?
 503                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 504                                            HDMI_QUANTIZATION_RANGE_FULL);
 505         drm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate);
 506         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 507
 508         vc4_hdmi_write_infoframe(encoder, &frame);
 509 }
 510
 511 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 512 {
 513         union hdmi_infoframe frame;
 514         int ret;
 515
 516         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 517         if (ret < 0) {
 518                 DRM_ERROR("couldn't fill SPD infoframe\n");
 519                 return;
 520         }
 521
 522         frame.spd.sdi = HDMI_SPD_SDI_PC;
 523
 524         vc4_hdmi_write_infoframe(encoder, &frame);
 525 }
 526
 527 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 528 {
 529         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 530         struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
 531         union hdmi_infoframe frame;
 532
 533         memcpy(&frame.audio, audio, sizeof(*audio));
 534         vc4_hdmi_write_infoframe(encoder, &frame);
 535 }
 536
 537 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 538 {
 539         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 540         struct drm_connector *connector = &vc4_hdmi->connector;
 541         struct drm_connector_state *conn_state = connector->state;
 542         union hdmi_infoframe frame;
 543
 544         lockdep_assert_held(&vc4_hdmi->mutex);
 545
 546         if (!vc4_hdmi->variant->supports_hdr)
 547                 return;
 548
 549         if (!conn_state->hdr_output_metadata)
 550                 return;
 551
 552         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 553                 return;
 554
 555         vc4_hdmi_write_infoframe(encoder, &frame);
 556 }
 557
 558 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 559 {
 560         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 561
 562         lockdep_assert_held(&vc4_hdmi->mutex);
 563
 564         vc4_hdmi_set_avi_infoframe(encoder);
 565         vc4_hdmi_set_spd_infoframe(encoder);
 566         /*
 567          * If audio was streaming, then we need to reenabled the audio
 568          * infoframe here during encoder_enable.
 569          */
 570         if (vc4_hdmi->audio.streaming)
 571                 vc4_hdmi_set_audio_infoframe(encoder);
 572
 573         vc4_hdmi_set_hdr_infoframe(encoder);
 574 }
 575
 576 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
 577                                          struct drm_display_mode *mode)
 578 {
 579         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 580         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 581         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 582
 583         lockdep_assert_held(&vc4_hdmi->mutex);
 584
 585         if (!vc4_encoder->hdmi_monitor)
 586                 return false;
 587
 588         if (!display->hdmi.scdc.supported ||
 589             !display->hdmi.scdc.scrambling.supported)
 590                 return false;
 591
 592         return true;
 593 }
 594
 595 #define SCRAMBLING_POLLING_DELAY_MS     1000
 596
 597 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 598 {
 599         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 600         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 601         unsigned long flags;
 602
 603         lockdep_assert_held(&vc4_hdmi->mutex);
 604
 605         if (!vc4_hdmi_supports_scrambling(encoder, mode))
 606                 return;
 607
 608         if (!vc4_hdmi_mode_needs_scrambling(mode))
 609                 return;
 610
 611         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 612         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 613
 614         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 615         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
 616                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 617         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 618
 619         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 620                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 621 }
 622
 623 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
 624 {
 625         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 626         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
 627         struct drm_crtc *crtc = encoder->crtc;
 628         unsigned long flags;
 629
 630         lockdep_assert_held(&vc4_hdmi->mutex);
 631
 632         /*
 633          * At boot, encoder->crtc will be NULL. Since we don't know the
 634          * state of the scrambler and in order to avoid any
 635          * inconsistency, let's disable it all the time.
 636          */
 637         if (crtc && !vc4_hdmi_supports_scrambling(encoder, mode))
 638                 return;
 639
 640         if (crtc && !vc4_hdmi_mode_needs_scrambling(mode))
 641                 return;
 642
 643         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
 644                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
 645
 646         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 647         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
 648                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 649         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 650
 651         drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
 652         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
 653 }
 654
 655 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
 656 {
 657         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
 658                                                  struct vc4_hdmi,
 659                                                  scrambling_work);
 660
 661         if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
 662                 return;
 663
 664         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 665         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 666
 667         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 668                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 669 }
 670
 671 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 672                                                struct drm_atomic_state *state)
 673 {
 674         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 675         unsigned long flags;
 676
 677         mutex_lock(&vc4_hdmi->mutex);
 678
 679         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 680
 681         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 682
 683         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
 684
 685         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 686
 687         mdelay(1);
 688
 689         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 690         HDMI_WRITE(HDMI_VID_CTL,
 691                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 692         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 693
 694         vc4_hdmi_disable_scrambling(encoder);
 695
 696         mutex_unlock(&vc4_hdmi->mutex);
 697 }
 698
 699 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
 700                                                  struct drm_atomic_state *state)
 701 {
 702         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 703         unsigned long flags;
 704         int ret;
 705
 706         mutex_lock(&vc4_hdmi->mutex);
 707
 708         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 709         HDMI_WRITE(HDMI_VID_CTL,
 710                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 711         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 712
 713         if (vc4_hdmi->variant->phy_disable)
 714                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 715
 716         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 717         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 718
 719         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 720         if (ret < 0)
 721                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 722
 723         mutex_unlock(&vc4_hdmi->mutex);
 724 }
 725
 726 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 727 {
 728 }
 729
 730 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 731 {
 732         unsigned long flags;
 733         u32 csc_ctl;
 734
 735         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 736
 737         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 738                                 VC4_HD_CSC_CTL_ORDER);
 739
 740         if (enable) {
 741                 /* CEA VICs other than #1 requre limited range RGB
 742                  * output unless overridden by an AVI infoframe.
 743                  * Apply a colorspace conversion to squash 0-255 down
 744                  * to 16-235.  The matrix here is:
 745                  *
 746                  * [ 0      0      0.8594 16]
 747                  * [ 0      0.8594 0      16]
 748                  * [ 0.8594 0      0      16]
 749                  * [ 0      0      0       1]
 750                  */
 751                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 752                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 753                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 754                                          VC4_HD_CSC_CTL_MODE);
 755
 756                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 757                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 758                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 759                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 760                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 761                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 762         }
 763
 764         /* The RGB order applies even when CSC is disabled. */
 765         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 766
 767         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 768 }
 769
 770 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 771 {
 772         unsigned long flags;
 773         u32 csc_ctl;
 774
 775         csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
 776
 777         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 778
 779         if (enable) {
 780                 /* CEA VICs other than #1 requre limited range RGB
 781                  * output unless overridden by an AVI infoframe.
 782                  * Apply a colorspace conversion to squash 0-255 down
 783                  * to 16-235.  The matrix here is:
 784                  *
 785                  * [ 0.8594 0      0      16]
 786                  * [ 0      0.8594 0      16]
 787                  * [ 0      0      0.8594 16]
 788                  * [ 0      0      0       1]
 789                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 790                  */
 791                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
 792                 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
 793                 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
 794                 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
 795                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 796                 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
 797         } else {
 798                 /* Still use the matrix for full range, but make it unity.
 799                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 800                  */
 801                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
 802                 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
 803                 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
 804                 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
 805                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 806                 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
 807         }
 808
 809         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 810
 811         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 812 }
 813
 814 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 815                                  struct drm_connector_state *state,
 816                                  struct drm_display_mode *mode)
 817 {
 818         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 819         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 820         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 821         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 822         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 823                                    VC4_HDMI_VERTA_VSP) |
 824                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 825                                    VC4_HDMI_VERTA_VFP) |
 826                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 827         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 828                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 829                                    VC4_HDMI_VERTB_VBP));
 830         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 831                           VC4_SET_FIELD(mode->crtc_vtotal -
 832                                         mode->crtc_vsync_end -
 833                                         interlaced,
 834                                         VC4_HDMI_VERTB_VBP));
 835         unsigned long flags;
 836
 837         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 838
 839         HDMI_WRITE(HDMI_HORZA,
 840                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 841                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 842                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 843                                  VC4_HDMI_HORZA_HAP));
 844
 845         HDMI_WRITE(HDMI_HORZB,
 846                    VC4_SET_FIELD((mode->htotal -
 847                                   mode->hsync_end) * pixel_rep,
 848                                  VC4_HDMI_HORZB_HBP) |
 849                    VC4_SET_FIELD((mode->hsync_end -
 850                                   mode->hsync_start) * pixel_rep,
 851                                  VC4_HDMI_HORZB_HSP) |
 852                    VC4_SET_FIELD((mode->hsync_start -
 853                                   mode->hdisplay) * pixel_rep,
 854                                  VC4_HDMI_HORZB_HFP));
 855
 856         HDMI_WRITE(HDMI_VERTA0, verta);
 857         HDMI_WRITE(HDMI_VERTA1, verta);
 858
 859         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 860         HDMI_WRITE(HDMI_VERTB1, vertb);
 861
 862         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 863 }
 864
 865 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 866                                  struct drm_connector_state *state,
 867                                  struct drm_display_mode *mode)
 868 {
 869         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 870         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 871         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 872         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 873         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 874                                    VC5_HDMI_VERTA_VSP) |
 875                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 876                                    VC5_HDMI_VERTA_VFP) |
 877                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
 878         u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 879                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 880                                    VC4_HDMI_VERTB_VBP));
 881         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 882                           VC4_SET_FIELD(mode->crtc_vtotal -
 883                                         mode->crtc_vsync_end -
 884                                         interlaced,
 885                                         VC4_HDMI_VERTB_VBP));
 886         unsigned long flags;
 887         unsigned char gcp;
 888         bool gcp_en;
 889         u32 reg;
 890
 891         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 892
 893         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
 894         HDMI_WRITE(HDMI_HORZA,
 895                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
 896                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
 897                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 898                                  VC5_HDMI_HORZA_HAP) |
 899                    VC4_SET_FIELD((mode->hsync_start -
 900                                   mode->hdisplay) * pixel_rep,
 901                                  VC5_HDMI_HORZA_HFP));
 902
 903         HDMI_WRITE(HDMI_HORZB,
 904                    VC4_SET_FIELD((mode->htotal -
 905                                   mode->hsync_end) * pixel_rep,
 906                                  VC5_HDMI_HORZB_HBP) |
 907                    VC4_SET_FIELD((mode->hsync_end -
 908                                   mode->hsync_start) * pixel_rep,
 909                                  VC5_HDMI_HORZB_HSP));
 910
 911         HDMI_WRITE(HDMI_VERTA0, verta);
 912         HDMI_WRITE(HDMI_VERTA1, verta);
 913
 914         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 915         HDMI_WRITE(HDMI_VERTB1, vertb);
 916
 917         switch (state->max_bpc) {
 918         case 12:
 919                 gcp = 6;
 920                 gcp_en = true;
 921                 break;
 922         case 10:
 923                 gcp = 5;
 924                 gcp_en = true;
 925                 break;
 926         case 8:
 927         default:
 928                 gcp = 4;
 929                 gcp_en = false;
 930                 break;
 931         }
 932
 933         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
 934         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
 935                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
 936         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
 937                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
 938         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
 939
 940         reg = HDMI_READ(HDMI_GCP_WORD_1);
 941         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
 942         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
 943         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
 944
 945         reg = HDMI_READ(HDMI_GCP_CONFIG);
 946         reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
 947         reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
 948         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
 949
 950         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
 951
 952         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 953 }
 954
 955 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
 956 {
 957         unsigned long flags;
 958         u32 drift;
 959         int ret;
 960
 961         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 962
 963         drift = HDMI_READ(HDMI_FIFO_CTL);
 964         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 965
 966         HDMI_WRITE(HDMI_FIFO_CTL,
 967                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 968         HDMI_WRITE(HDMI_FIFO_CTL,
 969                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 970
 971         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 972
 973         usleep_range(1000, 1100);
 974
 975         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
 976
 977         HDMI_WRITE(HDMI_FIFO_CTL,
 978                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 979         HDMI_WRITE(HDMI_FIFO_CTL,
 980                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 981
 982         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
 983
 984         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
 985                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
 986         WARN_ONCE(ret, "Timeout waiting for "
 987                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
 988 }
 989
 990 static struct drm_connector_state *
 991 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder,
 992                                      struct drm_atomic_state *state)
 993 {
 994         struct drm_connector_state *conn_state;
 995         struct drm_connector *connector;
 996         unsigned int i;
 997
 998         for_each_new_connector_in_state(state, connector, conn_state, i) {
 999                 if (conn_state->best_encoder == encoder)
1000                         return conn_state;
1001         }
1002
1003         return NULL;
1004 }
1005
1006 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1007                                                 struct drm_atomic_state *state)
1008 {
1009         struct drm_connector_state *conn_state =
1010                 vc4_hdmi_encoder_get_connector_state(encoder, state);
1011         struct vc4_hdmi_connector_state *vc4_conn_state =
1012                 conn_state_to_vc4_hdmi_conn_state(conn_state);
1013         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1014         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1015         unsigned long pixel_rate = vc4_conn_state->pixel_rate;
1016         unsigned long bvb_rate, hsm_rate;
1017         unsigned long flags;
1018         int ret;
1019
1020         mutex_lock(&vc4_hdmi->mutex);
1021
1022         /*
1023          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1024          * be faster than pixel clock, infinitesimally faster, tested in
1025          * simulation. Otherwise, exact value is unimportant for HDMI
1026          * operation." This conflicts with bcm2835's vc4 documentation, which
1027          * states HSM's clock has to be at least 108% of the pixel clock.
1028          *
1029          * Real life tests reveal that vc4's firmware statement holds up, and
1030          * users are able to use pixel clocks closer to HSM's, namely for
1031          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1032          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1033          * 162MHz.
1034          *
1035          * Additionally, the AXI clock needs to be at least 25% of
1036          * pixel clock, but HSM ends up being the limiting factor.
1037          */
1038         hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
1039         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1040         if (ret) {
1041                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1042                 goto out;
1043         }
1044
1045         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1046         if (ret < 0) {
1047                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1048                 goto out;
1049         }
1050
1051         ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
1052         if (ret) {
1053                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1054                 goto err_put_runtime_pm;
1055         }
1056
1057         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1058         if (ret) {
1059                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1060                 goto err_put_runtime_pm;
1061         }
1062
1063
1064         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1065
1066         if (pixel_rate > 297000000)
1067                 bvb_rate = 300000000;
1068         else if (pixel_rate > 148500000)
1069                 bvb_rate = 150000000;
1070         else
1071                 bvb_rate = 75000000;
1072
1073         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1074         if (ret) {
1075                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1076                 goto err_disable_pixel_clock;
1077         }
1078
1079         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1080         if (ret) {
1081                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1082                 goto err_disable_pixel_clock;
1083         }
1084
1085         if (vc4_hdmi->variant->phy_init)
1086                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1087
1088         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1089
1090         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1091                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1092                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1093                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1094
1095         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1096
1097         if (vc4_hdmi->variant->set_timings)
1098                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1099
1100         mutex_unlock(&vc4_hdmi->mutex);
1101
1102         return;
1103
1104 err_disable_pixel_clock:
1105         clk_disable_unprepare(vc4_hdmi->pixel_clock);
1106 err_put_runtime_pm:
1107         pm_runtime_put(&vc4_hdmi->pdev->dev);
1108 out:
1109         mutex_unlock(&vc4_hdmi->mutex);
1110         return;
1111 }
1112
1113 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1114                                              struct drm_atomic_state *state)
1115 {
1116         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1117         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1118         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1119         unsigned long flags;
1120
1121         mutex_lock(&vc4_hdmi->mutex);
1122
1123         if (vc4_encoder->hdmi_monitor &&
1124             drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
1125                 if (vc4_hdmi->variant->csc_setup)
1126                         vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
1127
1128                 vc4_encoder->limited_rgb_range = true;
1129         } else {
1130                 if (vc4_hdmi->variant->csc_setup)
1131                         vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
1132
1133                 vc4_encoder->limited_rgb_range = false;
1134         }
1135
1136         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1137         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1138         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1139
1140         mutex_unlock(&vc4_hdmi->mutex);
1141 }
1142
1143 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1144                                               struct drm_atomic_state *state)
1145 {
1146         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1147         struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1148         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1149         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1150         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1151         unsigned long flags;
1152         int ret;
1153
1154         mutex_lock(&vc4_hdmi->mutex);
1155
1156         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1157
1158         HDMI_WRITE(HDMI_VID_CTL,
1159                    VC4_HD_VID_CTL_ENABLE |
1160                    VC4_HD_VID_CTL_CLRRGB |
1161                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1162                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1163                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1164                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1165
1166         HDMI_WRITE(HDMI_VID_CTL,
1167                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1168
1169         if (vc4_encoder->hdmi_monitor) {
1170                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1171                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1172                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1173
1174                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1175
1176                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1177                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1178                 WARN_ONCE(ret, "Timeout waiting for "
1179                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1180         } else {
1181                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1182                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1183                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1184                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1185                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1186                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1187
1188                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1189
1190                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1191                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1192                 WARN_ONCE(ret, "Timeout waiting for "
1193                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1194         }
1195
1196         if (vc4_encoder->hdmi_monitor) {
1197                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1198
1199                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1200                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1201                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1202                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1203                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
1204
1205                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1206                            VC4_HDMI_RAM_PACKET_ENABLE);
1207
1208                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1209
1210                 vc4_hdmi_set_infoframes(encoder);
1211         }
1212
1213         vc4_hdmi_recenter_fifo(vc4_hdmi);
1214         vc4_hdmi_enable_scrambling(encoder);
1215
1216         mutex_unlock(&vc4_hdmi->mutex);
1217 }
1218
1219 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
1220 {
1221 }
1222
1223 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1224                                              struct drm_crtc_state *crtc_state,
1225                                              struct drm_connector_state *conn_state)
1226 {
1227         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1228
1229         mutex_lock(&vc4_hdmi->mutex);
1230         memcpy(&vc4_hdmi->saved_adjusted_mode,
1231                &crtc_state->adjusted_mode,
1232                sizeof(vc4_hdmi->saved_adjusted_mode));
1233         mutex_unlock(&vc4_hdmi->mutex);
1234 }
1235
1236 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
1237 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
1238
1239 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1240                                          struct drm_crtc_state *crtc_state,
1241                                          struct drm_connector_state *conn_state)
1242 {
1243         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1244         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1245         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1246         unsigned long long pixel_rate = mode->clock * 1000;
1247         unsigned long long tmds_rate;
1248
1249         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1250             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1251             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1252              (mode->hsync_end % 2) || (mode->htotal % 2)))
1253                 return -EINVAL;
1254
1255         /*
1256          * The 1440p@60 pixel rate is in the same range than the first
1257          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1258          * bandwidth). Slightly lower the frequency to bring it out of
1259          * the WiFi range.
1260          */
1261         tmds_rate = pixel_rate * 10;
1262         if (vc4_hdmi->disable_wifi_frequencies &&
1263             (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1264              tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1265                 mode->clock = 238560;
1266                 pixel_rate = mode->clock * 1000;
1267         }
1268
1269         if (conn_state->max_bpc == 12) {
1270                 pixel_rate = pixel_rate * 150;
1271                 do_div(pixel_rate, 100);
1272         } else if (conn_state->max_bpc == 10) {
1273                 pixel_rate = pixel_rate * 125;
1274                 do_div(pixel_rate, 100);
1275         }
1276
1277         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1278                 pixel_rate = pixel_rate * 2;
1279
1280         if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
1281                 return -EINVAL;
1282
1283         if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK))
1284                 return -EINVAL;
1285
1286         vc4_state->pixel_rate = pixel_rate;
1287
1288         return 0;
1289 }
1290
1291 static enum drm_mode_status
1292 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1293                             const struct drm_display_mode *mode)
1294 {
1295         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1296
1297         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1298             !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1299             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1300              (mode->hsync_end % 2) || (mode->htotal % 2)))
1301                 return MODE_H_ILLEGAL;
1302
1303         if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
1304                 return MODE_CLOCK_HIGH;
1305
1306         if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode))
1307                 return MODE_CLOCK_HIGH;
1308
1309         return MODE_OK;
1310 }
1311
1312 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1313         .atomic_check = vc4_hdmi_encoder_atomic_check,
1314         .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1315         .mode_valid = vc4_hdmi_encoder_mode_valid,
1316         .disable = vc4_hdmi_encoder_disable,
1317         .enable = vc4_hdmi_encoder_enable,
1318 };
1319
1320 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1321 {
1322         int i;
1323         u32 channel_map = 0;
1324
1325         for (i = 0; i < 8; i++) {
1326                 if (channel_mask & BIT(i))
1327                         channel_map |= i << (3 * i);
1328         }
1329         return channel_map;
1330 }
1331
1332 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1333 {
1334         int i;
1335         u32 channel_map = 0;
1336
1337         for (i = 0; i < 8; i++) {
1338                 if (channel_mask & BIT(i))
1339                         channel_map |= i << (4 * i);
1340         }
1341         return channel_map;
1342 }
1343
1344 /* HDMI audio codec callbacks */
1345 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1346                                          unsigned int samplerate)
1347 {
1348         u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1349         unsigned long flags;
1350         unsigned long n, m;
1351
1352         rational_best_approximation(hsm_clock, samplerate,
1353                                     VC4_HD_MAI_SMP_N_MASK >>
1354                                     VC4_HD_MAI_SMP_N_SHIFT,
1355                                     (VC4_HD_MAI_SMP_M_MASK >>
1356                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
1357                                     &n, &m);
1358
1359         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1360         HDMI_WRITE(HDMI_MAI_SMP,
1361                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1362                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1363         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1364 }
1365
1366 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1367 {
1368         const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1369         u32 n, cts;
1370         u64 tmp;
1371
1372         lockdep_assert_held(&vc4_hdmi->mutex);
1373         lockdep_assert_held(&vc4_hdmi->hw_lock);
1374
1375         n = 128 * samplerate / 1000;
1376         tmp = (u64)(mode->clock * 1000) * n;
1377         do_div(tmp, 128 * samplerate);
1378         cts = tmp;
1379
1380         HDMI_WRITE(HDMI_CRP_CFG,
1381                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1382                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1383
1384         /*
1385          * We could get slightly more accurate clocks in some cases by
1386          * providing a CTS_1 value.  The two CTS values are alternated
1387          * between based on the period fields
1388          */
1389         HDMI_WRITE(HDMI_CTS_0, cts);
1390         HDMI_WRITE(HDMI_CTS_1, cts);
1391 }
1392
1393 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1394 {
1395         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1396
1397         return snd_soc_card_get_drvdata(card);
1398 }
1399
1400 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1401 {
1402         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1403         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1404         unsigned long flags;
1405
1406         mutex_lock(&vc4_hdmi->mutex);
1407
1408         /*
1409          * If the HDMI encoder hasn't probed, or the encoder is
1410          * currently in DVI mode, treat the codec dai as missing.
1411          */
1412         if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1413                                 VC4_HDMI_RAM_PACKET_ENABLE)) {
1414                 mutex_unlock(&vc4_hdmi->mutex);
1415                 return -ENODEV;
1416         }
1417
1418         vc4_hdmi->audio.streaming = true;
1419
1420         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1421         HDMI_WRITE(HDMI_MAI_CTL,
1422                    VC4_HD_MAI_CTL_RESET |
1423                    VC4_HD_MAI_CTL_FLUSH |
1424                    VC4_HD_MAI_CTL_DLATE |
1425                    VC4_HD_MAI_CTL_ERRORE |
1426                    VC4_HD_MAI_CTL_ERRORF);
1427         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1428
1429         if (vc4_hdmi->variant->phy_rng_enable)
1430                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1431
1432         mutex_unlock(&vc4_hdmi->mutex);
1433
1434         return 0;
1435 }
1436
1437 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1438 {
1439         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1440         struct device *dev = &vc4_hdmi->pdev->dev;
1441         unsigned long flags;
1442         int ret;
1443
1444         lockdep_assert_held(&vc4_hdmi->mutex);
1445
1446         vc4_hdmi->audio.streaming = false;
1447         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1448         if (ret)
1449                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1450
1451         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1452
1453         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1454         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1455         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1456
1457         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1458 }
1459
1460 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1461 {
1462         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1463         unsigned long flags;
1464
1465         mutex_lock(&vc4_hdmi->mutex);
1466
1467         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1468
1469         HDMI_WRITE(HDMI_MAI_CTL,
1470                    VC4_HD_MAI_CTL_DLATE |
1471                    VC4_HD_MAI_CTL_ERRORE |
1472                    VC4_HD_MAI_CTL_ERRORF);
1473
1474         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1475
1476         if (vc4_hdmi->variant->phy_rng_disable)
1477                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1478
1479         vc4_hdmi->audio.streaming = false;
1480         vc4_hdmi_audio_reset(vc4_hdmi);
1481
1482         mutex_unlock(&vc4_hdmi->mutex);
1483 }
1484
1485 static int sample_rate_to_mai_fmt(int samplerate)
1486 {
1487         switch (samplerate) {
1488         case 8000:
1489                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1490         case 11025:
1491                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1492         case 12000:
1493                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1494         case 16000:
1495                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1496         case 22050:
1497                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1498         case 24000:
1499                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1500         case 32000:
1501                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1502         case 44100:
1503                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1504         case 48000:
1505                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1506         case 64000:
1507                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
1508         case 88200:
1509                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
1510         case 96000:
1511                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
1512         case 128000:
1513                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
1514         case 176400:
1515                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
1516         case 192000:
1517                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
1518         default:
1519                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
1520         }
1521 }
1522
1523 /* HDMI audio codec callbacks */
1524 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
1525                                   struct hdmi_codec_daifmt *daifmt,
1526                                   struct hdmi_codec_params *params)
1527 {
1528         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1529         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1530         unsigned int sample_rate = params->sample_rate;
1531         unsigned int channels = params->channels;
1532         unsigned long flags;
1533         u32 audio_packet_config, channel_mask;
1534         u32 channel_map;
1535         u32 mai_audio_format;
1536         u32 mai_sample_rate;
1537
1538         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1539                 sample_rate, params->sample_width, channels);
1540
1541         mutex_lock(&vc4_hdmi->mutex);
1542
1543         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
1544
1545         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1546         HDMI_WRITE(HDMI_MAI_CTL,
1547                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
1548                    VC4_HD_MAI_CTL_WHOLSMP |
1549                    VC4_HD_MAI_CTL_CHALIGN |
1550                    VC4_HD_MAI_CTL_ENABLE);
1551
1552         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
1553         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
1554             params->channels == 8)
1555                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
1556         else
1557                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
1558         HDMI_WRITE(HDMI_MAI_FMT,
1559                    VC4_SET_FIELD(mai_sample_rate,
1560                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
1561                    VC4_SET_FIELD(mai_audio_format,
1562                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
1563
1564         /* The B frame identifier should match the value used by alsa-lib (8) */
1565         audio_packet_config =
1566                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1567                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1568                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1569
1570         channel_mask = GENMASK(channels - 1, 0);
1571         audio_packet_config |= VC4_SET_FIELD(channel_mask,
1572                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1573
1574         /* Set the MAI threshold */
1575         HDMI_WRITE(HDMI_MAI_THR,
1576                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1577                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1578                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1579                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1580
1581         HDMI_WRITE(HDMI_MAI_CONFIG,
1582                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1583                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
1584                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1585
1586         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1587         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1588         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1589
1590         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
1591
1592         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1593
1594         memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
1595         vc4_hdmi_set_audio_infoframe(encoder);
1596
1597         mutex_unlock(&vc4_hdmi->mutex);
1598
1599         return 0;
1600 }
1601
1602 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1603         .name = "vc4-hdmi-cpu-dai-component",
1604 };
1605
1606 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1607 {
1608         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1609
1610         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1611
1612         return 0;
1613 }
1614
1615 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1616         .name = "vc4-hdmi-cpu-dai",
1617         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1618         .playback = {
1619                 .stream_name = "Playback",
1620                 .channels_min = 1,
1621                 .channels_max = 8,
1622                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1623                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1624                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1625                          SNDRV_PCM_RATE_192000,
1626                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1627         },
1628 };
1629
1630 static const struct snd_dmaengine_pcm_config pcm_conf = {
1631         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1632         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1633 };
1634
1635 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
1636                                   uint8_t *buf, size_t len)
1637 {
1638         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1639         struct drm_connector *connector = &vc4_hdmi->connector;
1640
1641         mutex_lock(&vc4_hdmi->mutex);
1642         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1643         mutex_unlock(&vc4_hdmi->mutex);
1644
1645         return 0;
1646 }
1647
1648 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
1649         .get_eld = vc4_hdmi_audio_get_eld,
1650         .prepare = vc4_hdmi_audio_prepare,
1651         .audio_shutdown = vc4_hdmi_audio_shutdown,
1652         .audio_startup = vc4_hdmi_audio_startup,
1653 };
1654
1655 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
1656         .ops = &vc4_hdmi_codec_ops,
1657         .max_i2s_channels = 8,
1658         .i2s = 1,
1659 };
1660
1661 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1662 {
1663         const struct vc4_hdmi_register *mai_data =
1664                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1665         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1666         struct snd_soc_card *card = &vc4_hdmi->audio.card;
1667         struct device *dev = &vc4_hdmi->pdev->dev;
1668         struct platform_device *codec_pdev;
1669         const __be32 *addr;
1670         int index;
1671         int ret;
1672
1673         if (!of_find_property(dev->of_node, "dmas", NULL)) {
1674                 dev_warn(dev,
1675                          "'dmas' DT property is missing, no HDMI audio\n");
1676                 return 0;
1677         }
1678
1679         if (mai_data->reg != VC4_HD) {
1680                 WARN_ONCE(true, "MAI isn't in the HD block\n");
1681                 return -EINVAL;
1682         }
1683
1684         /*
1685          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1686          * the bus address specified in the DT, because the physical address
1687          * (the one returned by platform_get_resource()) is not appropriate
1688          * for DMA transfers.
1689          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1690          */
1691         index = of_property_match_string(dev->of_node, "reg-names", "hd");
1692         /* Before BCM2711, we don't have a named register range */
1693         if (index < 0)
1694                 index = 1;
1695
1696         addr = of_get_address(dev->of_node, index, NULL, NULL);
1697
1698         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1699         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1700         vc4_hdmi->audio.dma_data.maxburst = 2;
1701
1702         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1703         if (ret) {
1704                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1705                 return ret;
1706         }
1707
1708         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1709                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1710         if (ret) {
1711                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1712                 return ret;
1713         }
1714
1715         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1716                                                    PLATFORM_DEVID_AUTO,
1717                                                    &vc4_hdmi_codec_pdata,
1718                                                    sizeof(vc4_hdmi_codec_pdata));
1719         if (IS_ERR(codec_pdev)) {
1720                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
1721                 return PTR_ERR(codec_pdev);
1722         }
1723         vc4_hdmi->audio.codec_pdev = codec_pdev;
1724
1725         dai_link->cpus          = &vc4_hdmi->audio.cpu;
1726         dai_link->codecs        = &vc4_hdmi->audio.codec;
1727         dai_link->platforms     = &vc4_hdmi->audio.platform;
1728
1729         dai_link->num_cpus      = 1;
1730         dai_link->num_codecs    = 1;
1731         dai_link->num_platforms = 1;
1732
1733         dai_link->name = "MAI";
1734         dai_link->stream_name = "MAI PCM";
1735         dai_link->codecs->dai_name = "i2s-hifi";
1736         dai_link->cpus->dai_name = dev_name(dev);
1737         dai_link->codecs->name = dev_name(&codec_pdev->dev);
1738         dai_link->platforms->name = dev_name(dev);
1739
1740         card->dai_link = dai_link;
1741         card->num_links = 1;
1742         card->name = vc4_hdmi->variant->card_name;
1743         card->driver_name = "vc4-hdmi";
1744         card->dev = dev;
1745         card->owner = THIS_MODULE;
1746
1747         /*
1748          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1749          * stores a pointer to the snd card object in dev->driver_data. This
1750          * means we cannot use it for something else. The hdmi back-pointer is
1751          * now stored in card->drvdata and should be retrieved with
1752          * snd_soc_card_get_drvdata() if needed.
1753          */
1754         snd_soc_card_set_drvdata(card, vc4_hdmi);
1755         ret = devm_snd_soc_register_card(dev, card);
1756         if (ret)
1757                 dev_err_probe(dev, ret, "Could not register sound card\n");
1758
1759         return ret;
1760
1761 }
1762
1763 static void vc4_hdmi_audio_exit(struct vc4_hdmi *vc4_hdmi)
1764 {
1765         platform_device_unregister(vc4_hdmi->audio.codec_pdev);
1766         vc4_hdmi->audio.codec_pdev = NULL;
1767 }
1768
1769 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
1770 {
1771         struct vc4_hdmi *vc4_hdmi = priv;
1772         struct drm_device *dev = vc4_hdmi->connector.dev;
1773
1774         if (dev && dev->registered)
1775                 drm_kms_helper_hotplug_event(dev);
1776
1777         return IRQ_HANDLED;
1778 }
1779
1780 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
1781 {
1782         struct drm_connector *connector = &vc4_hdmi->connector;
1783         struct platform_device *pdev = vc4_hdmi->pdev;
1784         int ret;
1785
1786         if (vc4_hdmi->variant->external_irq_controller) {
1787                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
1788                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
1789
1790                 ret = request_threaded_irq(hpd_con,
1791                                            NULL,
1792                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1793                                            "vc4 hdmi hpd connected", vc4_hdmi);
1794                 if (ret)
1795                         return ret;
1796
1797                 ret = request_threaded_irq(hpd_rm,
1798                                            NULL,
1799                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1800                                            "vc4 hdmi hpd disconnected", vc4_hdmi);
1801                 if (ret) {
1802                         free_irq(hpd_con, vc4_hdmi);
1803                         return ret;
1804                 }
1805
1806                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1807         }
1808
1809         return 0;
1810 }
1811
1812 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi)
1813 {
1814         struct platform_device *pdev = vc4_hdmi->pdev;
1815
1816         if (vc4_hdmi->variant->external_irq_controller) {
1817                 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi);
1818                 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi);
1819         }
1820 }
1821
1822 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1823 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1824 {
1825         struct vc4_hdmi *vc4_hdmi = priv;
1826
1827         if (vc4_hdmi->cec_rx_msg.len)
1828                 cec_received_msg(vc4_hdmi->cec_adap,
1829                                  &vc4_hdmi->cec_rx_msg);
1830
1831         return IRQ_HANDLED;
1832 }
1833
1834 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1835 {
1836         struct vc4_hdmi *vc4_hdmi = priv;
1837
1838         if (vc4_hdmi->cec_tx_ok) {
1839                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1840                                   0, 0, 0, 0);
1841         } else {
1842                 /*
1843                  * This CEC implementation makes 1 retry, so if we
1844                  * get a NACK, then that means it made 2 attempts.
1845                  */
1846                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1847                                   0, 2, 0, 0);
1848         }
1849         return IRQ_HANDLED;
1850 }
1851
1852 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1853 {
1854         struct vc4_hdmi *vc4_hdmi = priv;
1855         irqreturn_t ret;
1856
1857         if (vc4_hdmi->cec_irq_was_rx)
1858                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1859         else
1860                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1861
1862         return ret;
1863 }
1864
1865 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1866 {
1867         struct drm_device *dev = vc4_hdmi->connector.dev;
1868         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1869         unsigned int i;
1870
1871         lockdep_assert_held(&vc4_hdmi->hw_lock);
1872
1873         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1874                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1875
1876         if (msg->len > 16) {
1877                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1878                 return;
1879         }
1880
1881         for (i = 0; i < msg->len; i += 4) {
1882                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1883
1884                 msg->msg[i] = val & 0xff;
1885                 msg->msg[i + 1] = (val >> 8) & 0xff;
1886                 msg->msg[i + 2] = (val >> 16) & 0xff;
1887                 msg->msg[i + 3] = (val >> 24) & 0xff;
1888         }
1889 }
1890
1891 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
1892 {
1893         u32 cntrl1;
1894
1895         lockdep_assert_held(&vc4_hdmi->hw_lock);
1896
1897         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1898         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1899         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1900         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1901
1902         return IRQ_WAKE_THREAD;
1903 }
1904
1905 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1906 {
1907         struct vc4_hdmi *vc4_hdmi = priv;
1908         irqreturn_t ret;
1909
1910         spin_lock(&vc4_hdmi->hw_lock);
1911         ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
1912         spin_unlock(&vc4_hdmi->hw_lock);
1913
1914         return ret;
1915 }
1916
1917 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
1918 {
1919         u32 cntrl1;
1920
1921         lockdep_assert_held(&vc4_hdmi->hw_lock);
1922
1923         vc4_hdmi->cec_rx_msg.len = 0;
1924         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1925         vc4_cec_read_msg(vc4_hdmi, cntrl1);
1926         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1927         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1928         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1929
1930         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1931
1932         return IRQ_WAKE_THREAD;
1933 }
1934
1935 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1936 {
1937         struct vc4_hdmi *vc4_hdmi = priv;
1938         irqreturn_t ret;
1939
1940         spin_lock(&vc4_hdmi->hw_lock);
1941         ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
1942         spin_unlock(&vc4_hdmi->hw_lock);
1943
1944         return ret;
1945 }
1946
1947 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1948 {
1949         struct vc4_hdmi *vc4_hdmi = priv;
1950         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1951         irqreturn_t ret;
1952         u32 cntrl5;
1953
1954         if (!(stat & VC4_HDMI_CPU_CEC))
1955                 return IRQ_NONE;
1956
1957         spin_lock(&vc4_hdmi->hw_lock);
1958         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1959         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1960         if (vc4_hdmi->cec_irq_was_rx)
1961                 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
1962         else
1963                 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
1964
1965         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1966         spin_unlock(&vc4_hdmi->hw_lock);
1967
1968         return ret;
1969 }
1970
1971 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
1972 {
1973         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1974         /* clock period in microseconds */
1975         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1976         unsigned long flags;
1977         u32 val;
1978         int ret;
1979
1980         /*
1981          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
1982          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
1983          * .detect or .get_modes might call .adap_enable, which leads to this
1984          * function being called with that mutex held.
1985          *
1986          * Concurrency is not an issue for the moment since we don't share any
1987          * state with KMS, so we can ignore the lock for now, but we need to
1988          * keep it in mind if we were to change that assumption.
1989          */
1990
1991         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1992         if (ret)
1993                 return ret;
1994
1995         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1996
1997         val = HDMI_READ(HDMI_CEC_CNTRL_5);
1998         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1999                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2000                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2001         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2002                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2003
2004         HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2005                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2006         HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2007         HDMI_WRITE(HDMI_CEC_CNTRL_2,
2008                    ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2009                    ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2010                    ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2011                    ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2012                    ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2013         HDMI_WRITE(HDMI_CEC_CNTRL_3,
2014                    ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2015                    ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2016                    ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2017                    ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2018         HDMI_WRITE(HDMI_CEC_CNTRL_4,
2019                    ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2020                    ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2021                    ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2022                    ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2023
2024         if (!vc4_hdmi->variant->external_irq_controller)
2025                 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2026
2027         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2028
2029         return 0;
2030 }
2031
2032 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2033 {
2034         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2035         unsigned long flags;
2036
2037         /*
2038          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2039          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2040          * .detect or .get_modes might call .adap_enable, which leads to this
2041          * function being called with that mutex held.
2042          *
2043          * Concurrency is not an issue for the moment since we don't share any
2044          * state with KMS, so we can ignore the lock for now, but we need to
2045          * keep it in mind if we were to change that assumption.
2046          */
2047
2048         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2049
2050         if (!vc4_hdmi->variant->external_irq_controller)
2051                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2052
2053         HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2054                    VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2055
2056         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2057
2058         pm_runtime_put(&vc4_hdmi->pdev->dev);
2059
2060         return 0;
2061 }
2062
2063 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2064 {
2065         if (enable)
2066                 return vc4_hdmi_cec_enable(adap);
2067         else
2068                 return vc4_hdmi_cec_disable(adap);
2069 }
2070
2071 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2072 {
2073         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2074         unsigned long flags;
2075
2076         /*
2077          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2078          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2079          * .detect or .get_modes might call .adap_enable, which leads to this
2080          * function being called with that mutex held.
2081          *
2082          * Concurrency is not an issue for the moment since we don't share any
2083          * state with KMS, so we can ignore the lock for now, but we need to
2084          * keep it in mind if we were to change that assumption.
2085          */
2086
2087         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2088         HDMI_WRITE(HDMI_CEC_CNTRL_1,
2089                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2090                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2091         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2092
2093         return 0;
2094 }
2095
2096 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2097                                       u32 signal_free_time, struct cec_msg *msg)
2098 {
2099         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2100         struct drm_device *dev = vc4_hdmi->connector.dev;
2101         unsigned long flags;
2102         u32 val;
2103         unsigned int i;
2104
2105         /*
2106          * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2107          * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2108          * .detect or .get_modes might call .adap_enable, which leads to this
2109          * function being called with that mutex held.
2110          *
2111          * Concurrency is not an issue for the moment since we don't share any
2112          * state with KMS, so we can ignore the lock for now, but we need to
2113          * keep it in mind if we were to change that assumption.
2114          */
2115
2116         if (msg->len > 16) {
2117                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2118                 return -ENOMEM;
2119         }
2120
2121         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2122
2123         for (i = 0; i < msg->len; i += 4)
2124                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2125                            (msg->msg[i]) |
2126                            (msg->msg[i + 1] << 8) |
2127                            (msg->msg[i + 2] << 16) |
2128                            (msg->msg[i + 3] << 24));
2129
2130         val = HDMI_READ(HDMI_CEC_CNTRL_1);
2131         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2132         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2133         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2134         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2135         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2136
2137         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2138
2139         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2140
2141         return 0;
2142 }
2143
2144 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2145         .adap_enable = vc4_hdmi_cec_adap_enable,
2146         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2147         .adap_transmit = vc4_hdmi_cec_adap_transmit,
2148 };
2149
2150 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2151 {
2152         struct cec_connector_info conn_info;
2153         struct platform_device *pdev = vc4_hdmi->pdev;
2154         struct device *dev = &pdev->dev;
2155         unsigned long flags;
2156         u32 value;
2157         int ret;
2158
2159         if (!of_find_property(dev->of_node, "interrupts", NULL)) {
2160                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
2161                 return 0;
2162         }
2163
2164         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
2165                                                   vc4_hdmi, "vc4",
2166                                                   CEC_CAP_DEFAULTS |
2167                                                   CEC_CAP_CONNECTOR_INFO, 1);
2168         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
2169         if (ret < 0)
2170                 return ret;
2171
2172         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
2173         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
2174
2175         spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2176         value = HDMI_READ(HDMI_CEC_CNTRL_1);
2177         /* Set the logical address to Unregistered */
2178         value |= VC4_HDMI_CEC_ADDR_MASK;
2179         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
2180         spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2181
2182         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
2183
2184         if (vc4_hdmi->variant->external_irq_controller) {
2185                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"),
2186                                            vc4_cec_irq_handler_rx_bare,
2187                                            vc4_cec_irq_handler_rx_thread, 0,
2188                                            "vc4 hdmi cec rx", vc4_hdmi);
2189                 if (ret)
2190                         goto err_delete_cec_adap;
2191
2192                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"),
2193                                            vc4_cec_irq_handler_tx_bare,
2194                                            vc4_cec_irq_handler_tx_thread, 0,
2195                                            "vc4 hdmi cec tx", vc4_hdmi);
2196                 if (ret)
2197                         goto err_remove_cec_rx_handler;
2198         } else {
2199                 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2200                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
2201                 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2202
2203                 ret = request_threaded_irq(platform_get_irq(pdev, 0),
2204                                            vc4_cec_irq_handler,
2205                                            vc4_cec_irq_handler_thread, 0,
2206                                            "vc4 hdmi cec", vc4_hdmi);
2207                 if (ret)
2208                         goto err_delete_cec_adap;
2209         }
2210
2211         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
2212         if (ret < 0)
2213                 goto err_remove_handlers;
2214
2215         return 0;
2216
2217 err_remove_handlers:
2218         if (vc4_hdmi->variant->external_irq_controller)
2219                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
2220         else
2221                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
2222
2223 err_remove_cec_rx_handler:
2224         if (vc4_hdmi->variant->external_irq_controller)
2225                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
2226
2227 err_delete_cec_adap:
2228         cec_delete_adapter(vc4_hdmi->cec_adap);
2229
2230         return ret;
2231 }
2232
2233 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
2234 {
2235         struct platform_device *pdev = vc4_hdmi->pdev;
2236
2237         if (vc4_hdmi->variant->external_irq_controller) {
2238                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
2239                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
2240         } else {
2241                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
2242         }
2243
2244         cec_unregister_adapter(vc4_hdmi->cec_adap);
2245 }
2246 #else
2247 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2248 {
2249         return 0;
2250 }
2251
2252 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
2253
2254 #endif
2255
2256 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
2257                                  struct debugfs_regset32 *regset,
2258                                  enum vc4_hdmi_regs reg)
2259 {
2260         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2261         struct debugfs_reg32 *regs, *new_regs;
2262         unsigned int count = 0;
2263         unsigned int i;
2264
2265         regs = kcalloc(variant->num_registers, sizeof(*regs),
2266                        GFP_KERNEL);
2267         if (!regs)
2268                 return -ENOMEM;
2269
2270         for (i = 0; i < variant->num_registers; i++) {
2271                 const struct vc4_hdmi_register *field = &variant->registers[i];
2272
2273                 if (field->reg != reg)
2274                         continue;
2275
2276                 regs[count].name = field->name;
2277                 regs[count].offset = field->offset;
2278                 count++;
2279         }
2280
2281         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
2282         if (!new_regs)
2283                 return -ENOMEM;
2284
2285         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
2286         regset->regs = new_regs;
2287         regset->nregs = count;
2288
2289         return 0;
2290 }
2291
2292 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2293 {
2294         struct platform_device *pdev = vc4_hdmi->pdev;
2295         struct device *dev = &pdev->dev;
2296         int ret;
2297
2298         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
2299         if (IS_ERR(vc4_hdmi->hdmicore_regs))
2300                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
2301
2302         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
2303         if (IS_ERR(vc4_hdmi->hd_regs))
2304                 return PTR_ERR(vc4_hdmi->hd_regs);
2305
2306         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2307         if (ret)
2308                 return ret;
2309
2310         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2311         if (ret)
2312                 return ret;
2313
2314         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
2315         if (IS_ERR(vc4_hdmi->pixel_clock)) {
2316                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
2317                 if (ret != -EPROBE_DEFER)
2318                         DRM_ERROR("Failed to get pixel clock\n");
2319                 return ret;
2320         }
2321
2322         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2323         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2324                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2325                 return PTR_ERR(vc4_hdmi->hsm_clock);
2326         }
2327         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2328         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2329
2330         return 0;
2331 }
2332
2333 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
2334 {
2335         struct platform_device *pdev = vc4_hdmi->pdev;
2336         struct device *dev = &pdev->dev;
2337         struct resource *res;
2338
2339         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2340         if (!res)
2341                 return -ENODEV;
2342
2343         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2344                                                resource_size(res));
2345         if (!vc4_hdmi->hdmicore_regs)
2346                 return -ENOMEM;
2347
2348         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2349         if (!res)
2350                 return -ENODEV;
2351
2352         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2353         if (!vc4_hdmi->hd_regs)
2354                 return -ENOMEM;
2355
2356         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2357         if (!res)
2358                 return -ENODEV;
2359
2360         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2361         if (!vc4_hdmi->cec_regs)
2362                 return -ENOMEM;
2363
2364         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2365         if (!res)
2366                 return -ENODEV;
2367
2368         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2369         if (!vc4_hdmi->csc_regs)
2370                 return -ENOMEM;
2371
2372         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2373         if (!res)
2374                 return -ENODEV;
2375
2376         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2377         if (!vc4_hdmi->dvp_regs)
2378                 return -ENOMEM;
2379
2380         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2381         if (!res)
2382                 return -ENODEV;
2383
2384         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2385         if (!vc4_hdmi->phy_regs)
2386                 return -ENOMEM;
2387
2388         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2389         if (!res)
2390                 return -ENODEV;
2391
2392         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2393         if (!vc4_hdmi->ram_regs)
2394                 return -ENOMEM;
2395
2396         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2397         if (!res)
2398                 return -ENODEV;
2399
2400         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2401         if (!vc4_hdmi->rm_regs)
2402                 return -ENOMEM;
2403
2404         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2405         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2406                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2407                 return PTR_ERR(vc4_hdmi->hsm_clock);
2408         }
2409
2410         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2411         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2412                 DRM_ERROR("Failed to get pixel bvb clock\n");
2413                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2414         }
2415
2416         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2417         if (IS_ERR(vc4_hdmi->audio_clock)) {
2418                 DRM_ERROR("Failed to get audio clock\n");
2419                 return PTR_ERR(vc4_hdmi->audio_clock);
2420         }
2421
2422         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2423         if (IS_ERR(vc4_hdmi->cec_clock)) {
2424                 DRM_ERROR("Failed to get CEC clock\n");
2425                 return PTR_ERR(vc4_hdmi->cec_clock);
2426         }
2427
2428         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2429         if (IS_ERR(vc4_hdmi->reset)) {
2430                 DRM_ERROR("Failed to get HDMI reset line\n");
2431                 return PTR_ERR(vc4_hdmi->reset);
2432         }
2433
2434         return 0;
2435 }
2436
2437 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev)
2438 {
2439         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2440
2441         clk_disable_unprepare(vc4_hdmi->hsm_clock);
2442
2443         return 0;
2444 }
2445
2446 static int vc4_hdmi_runtime_resume(struct device *dev)
2447 {
2448         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2449         int ret;
2450
2451         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
2452         if (ret)
2453                 return ret;
2454
2455         return 0;
2456 }
2457
2458 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2459 {
2460         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2461         struct platform_device *pdev = to_platform_device(dev);
2462         struct drm_device *drm = dev_get_drvdata(master);
2463         struct vc4_hdmi *vc4_hdmi;
2464         struct drm_encoder *encoder;
2465         struct device_node *ddc_node;
2466         int ret;
2467
2468         vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2469         if (!vc4_hdmi)
2470                 return -ENOMEM;
2471         mutex_init(&vc4_hdmi->mutex);
2472         spin_lock_init(&vc4_hdmi->hw_lock);
2473         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2474
2475         dev_set_drvdata(dev, vc4_hdmi);
2476         encoder = &vc4_hdmi->encoder.base.base;
2477         vc4_hdmi->encoder.base.type = variant->encoder_type;
2478         vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2479         vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2480         vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2481         vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2482         vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2483         vc4_hdmi->pdev = pdev;
2484         vc4_hdmi->variant = variant;
2485
2486         ret = variant->init_resources(vc4_hdmi);
2487         if (ret)
2488                 return ret;
2489
2490         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2491         if (!ddc_node) {
2492                 DRM_ERROR("Failed to find ddc node in device tree\n");
2493                 return -ENODEV;
2494         }
2495
2496         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2497         of_node_put(ddc_node);
2498         if (!vc4_hdmi->ddc) {
2499                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2500                 return -EPROBE_DEFER;
2501         }
2502
2503         /* Only use the GPIO HPD pin if present in the DT, otherwise
2504          * we'll use the HDMI core's register.
2505          */
2506         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2507         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
2508                 ret = PTR_ERR(vc4_hdmi->hpd_gpio);
2509                 goto err_put_ddc;
2510         }
2511
2512         vc4_hdmi->disable_wifi_frequencies =
2513                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2514
2515         if (variant->max_pixel_clock == 600000000) {
2516                 struct vc4_dev *vc4 = to_vc4_dev(drm);
2517                 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
2518
2519                 if (max_rate < 550000000)
2520                         vc4_hdmi->disable_4kp60 = true;
2521         }
2522
2523         /*
2524          * If we boot without any cable connected to the HDMI connector,
2525          * the firmware will skip the HSM initialization and leave it
2526          * with a rate of 0, resulting in a bus lockup when we're
2527          * accessing the registers even if it's enabled.
2528          *
2529          * Let's put a sensible default at runtime_resume so that we
2530          * don't end up in this situation.
2531          */
2532         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
2533         if (ret)
2534                 goto err_put_ddc;
2535
2536         /*
2537          * We need to have the device powered up at this point to call
2538          * our reset hook and for the CEC init.
2539          */
2540         ret = vc4_hdmi_runtime_resume(dev);
2541         if (ret)
2542                 goto err_put_ddc;
2543
2544         pm_runtime_get_noresume(dev);
2545         pm_runtime_set_active(dev);
2546         pm_runtime_enable(dev);
2547
2548         if (vc4_hdmi->variant->reset)
2549                 vc4_hdmi->variant->reset(vc4_hdmi);
2550
2551         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
2552              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
2553             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
2554                 clk_prepare_enable(vc4_hdmi->pixel_clock);
2555                 clk_prepare_enable(vc4_hdmi->hsm_clock);
2556                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
2557         }
2558
2559         drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2560         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2561
2562         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2563         if (ret)
2564                 goto err_destroy_encoder;
2565
2566         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
2567         if (ret)
2568                 goto err_destroy_conn;
2569
2570         ret = vc4_hdmi_cec_init(vc4_hdmi);
2571         if (ret)
2572                 goto err_free_hotplug;
2573
2574         ret = vc4_hdmi_audio_init(vc4_hdmi);
2575         if (ret)
2576                 goto err_free_cec;
2577
2578         vc4_debugfs_add_file(drm, variant->debugfs_name,
2579                              vc4_hdmi_debugfs_regs,
2580                              vc4_hdmi);
2581
2582         pm_runtime_put_sync(dev);
2583
2584         return 0;
2585
2586 err_free_cec:
2587         vc4_hdmi_cec_exit(vc4_hdmi);
2588 err_free_hotplug:
2589         vc4_hdmi_hotplug_exit(vc4_hdmi);
2590 err_destroy_conn:
2591         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2592 err_destroy_encoder:
2593         drm_encoder_cleanup(encoder);
2594         pm_runtime_put_sync(dev);
2595         pm_runtime_disable(dev);
2596 err_put_ddc:
2597         put_device(&vc4_hdmi->ddc->dev);
2598
2599         return ret;
2600 }
2601
2602 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2603                             void *data)
2604 {
2605         struct vc4_hdmi *vc4_hdmi;
2606
2607         /*
2608          * ASoC makes it a bit hard to retrieve a pointer to the
2609          * vc4_hdmi structure. Registering the card will overwrite our
2610          * device drvdata with a pointer to the snd_soc_card structure,
2611          * which can then be used to retrieve whatever drvdata we want
2612          * to associate.
2613          *
2614          * However, that doesn't fly in the case where we wouldn't
2615          * register an ASoC card (because of an old DT that is missing
2616          * the dmas properties for example), then the card isn't
2617          * registered and the device drvdata wouldn't be set.
2618          *
2619          * We can deal with both cases by making sure a snd_soc_card
2620          * pointer and a vc4_hdmi structure are pointing to the same
2621          * memory address, so we can treat them indistinctly without any
2622          * issue.
2623          */
2624         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2625         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2626         vc4_hdmi = dev_get_drvdata(dev);
2627
2628         kfree(vc4_hdmi->hdmi_regset.regs);
2629         kfree(vc4_hdmi->hd_regset.regs);
2630
2631         vc4_hdmi_audio_exit(vc4_hdmi);
2632         vc4_hdmi_cec_exit(vc4_hdmi);
2633         vc4_hdmi_hotplug_exit(vc4_hdmi);
2634         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2635         drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2636
2637         pm_runtime_disable(dev);
2638
2639         put_device(&vc4_hdmi->ddc->dev);
2640 }
2641
2642 static const struct component_ops vc4_hdmi_ops = {
2643         .bind   = vc4_hdmi_bind,
2644         .unbind = vc4_hdmi_unbind,
2645 };
2646
2647 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2648 {
2649         return component_add(&pdev->dev, &vc4_hdmi_ops);
2650 }
2651
2652 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2653 {
2654         component_del(&pdev->dev, &vc4_hdmi_ops);
2655         return 0;
2656 }
2657
2658 static const struct vc4_hdmi_variant bcm2835_variant = {
2659         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2660         .debugfs_name           = "hdmi_regs",
2661         .card_name              = "vc4-hdmi",
2662         .max_pixel_clock        = 162000000,
2663         .registers              = vc4_hdmi_fields,
2664         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
2665
2666         .init_resources         = vc4_hdmi_init_resources,
2667         .csc_setup              = vc4_hdmi_csc_setup,
2668         .reset                  = vc4_hdmi_reset,
2669         .set_timings            = vc4_hdmi_set_timings,
2670         .phy_init               = vc4_hdmi_phy_init,
2671         .phy_disable            = vc4_hdmi_phy_disable,
2672         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
2673         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
2674         .channel_map            = vc4_hdmi_channel_map,
2675         .supports_hdr           = false,
2676 };
2677
2678 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2679         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2680         .debugfs_name           = "hdmi0_regs",
2681         .card_name              = "vc4-hdmi-0",
2682         .max_pixel_clock        = 600000000,
2683         .registers              = vc5_hdmi_hdmi0_fields,
2684         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2685         .phy_lane_mapping       = {
2686                 PHY_LANE_0,
2687                 PHY_LANE_1,
2688                 PHY_LANE_2,
2689                 PHY_LANE_CK,
2690         },
2691         .unsupported_odd_h_timings      = true,
2692         .external_irq_controller        = true,
2693
2694         .init_resources         = vc5_hdmi_init_resources,
2695         .csc_setup              = vc5_hdmi_csc_setup,
2696         .reset                  = vc5_hdmi_reset,
2697         .set_timings            = vc5_hdmi_set_timings,
2698         .phy_init               = vc5_hdmi_phy_init,
2699         .phy_disable            = vc5_hdmi_phy_disable,
2700         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2701         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2702         .channel_map            = vc5_hdmi_channel_map,
2703         .supports_hdr           = true,
2704 };
2705
2706 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2707         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
2708         .debugfs_name           = "hdmi1_regs",
2709         .card_name              = "vc4-hdmi-1",
2710         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2711         .registers              = vc5_hdmi_hdmi1_fields,
2712         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2713         .phy_lane_mapping       = {
2714                 PHY_LANE_1,
2715                 PHY_LANE_0,
2716                 PHY_LANE_CK,
2717                 PHY_LANE_2,
2718         },
2719         .unsupported_odd_h_timings      = true,
2720         .external_irq_controller        = true,
2721
2722         .init_resources         = vc5_hdmi_init_resources,
2723         .csc_setup              = vc5_hdmi_csc_setup,
2724         .reset                  = vc5_hdmi_reset,
2725         .set_timings            = vc5_hdmi_set_timings,
2726         .phy_init               = vc5_hdmi_phy_init,
2727         .phy_disable            = vc5_hdmi_phy_disable,
2728         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2729         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2730         .channel_map            = vc5_hdmi_channel_map,
2731         .supports_hdr           = true,
2732 };
2733
2734 static const struct of_device_id vc4_hdmi_dt_match[] = {
2735         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2736         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2737         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2738         {}
2739 };
2740
2741 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
2742         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
2743                            vc4_hdmi_runtime_resume,
2744                            NULL)
2745 };
2746
2747 struct platform_driver vc4_hdmi_driver = {
2748         .probe = vc4_hdmi_dev_probe,
2749         .remove = vc4_hdmi_dev_remove,
2750         .driver = {
2751                 .name = "vc4_hdmi",
2752                 .of_match_table = vc4_hdmi_dt_match,
2753                 .pm = &vc4_hdmi_pm_ops,
2754         },
2755 };