drivers/gpu/drm/vc4/vc4_gem.c

   1 /*
   2  * Copyright © 2014 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/device.h>
  28 #include <linux/io.h>
  29 #include <linux/sched/signal.h>
  30
  31 #include "uapi/drm/vc4_drm.h"
  32 #include "vc4_drv.h"
  33 #include "vc4_regs.h"
  34 #include "vc4_trace.h"
  35
  36 static void
  37 vc4_queue_hangcheck(struct drm_device *dev)
  38 {
  39         struct vc4_dev *vc4 = to_vc4_dev(dev);
  40
  41         mod_timer(&vc4->hangcheck.timer,
  42                   round_jiffies_up(jiffies + msecs_to_jiffies(100)));
  43 }
  44
  45 struct vc4_hang_state {
  46         struct drm_vc4_get_hang_state user_state;
  47
  48         u32 bo_count;
  49         struct drm_gem_object **bo;
  50 };
  51
  52 static void
  53 vc4_free_hang_state(struct drm_device *dev, struct vc4_hang_state *state)
  54 {
  55         unsigned int i;
  56
  57         for (i = 0; i < state->user_state.bo_count; i++)
  58                 drm_gem_object_unreference_unlocked(state->bo[i]);
  59
  60         kfree(state);
  61 }
  62
  63 int
  64 vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
  65                          struct drm_file *file_priv)
  66 {
  67         struct drm_vc4_get_hang_state *get_state = data;
  68         struct drm_vc4_get_hang_state_bo *bo_state;
  69         struct vc4_hang_state *kernel_state;
  70         struct drm_vc4_get_hang_state *state;
  71         struct vc4_dev *vc4 = to_vc4_dev(dev);
  72         unsigned long irqflags;
  73         u32 i;
  74         int ret = 0;
  75
  76         spin_lock_irqsave(&vc4->job_lock, irqflags);
  77         kernel_state = vc4->hang_state;
  78         if (!kernel_state) {
  79                 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
  80                 return -ENOENT;
  81         }
  82         state = &kernel_state->user_state;
  83
  84         /* If the user's array isn't big enough, just return the
  85          * required array size.
  86          */
  87         if (get_state->bo_count < state->bo_count) {
  88                 get_state->bo_count = state->bo_count;
  89                 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
  90                 return 0;
  91         }
  92
  93         vc4->hang_state = NULL;
  94         spin_unlock_irqrestore(&vc4->job_lock, irqflags);
  95
  96         /* Save the user's BO pointer, so we don't stomp it with the memcpy. */
  97         state->bo = get_state->bo;
  98         memcpy(get_state, state, sizeof(*state));
  99
 100         bo_state = kcalloc(state->bo_count, sizeof(*bo_state), GFP_KERNEL);
 101         if (!bo_state) {
 102                 ret = -ENOMEM;
 103                 goto err_free;
 104         }
 105
 106         for (i = 0; i < state->bo_count; i++) {
 107                 struct vc4_bo *vc4_bo = to_vc4_bo(kernel_state->bo[i]);
 108                 u32 handle;
 109
 110                 ret = drm_gem_handle_create(file_priv, kernel_state->bo[i],
 111                                             &handle);
 112
 113                 if (ret) {
 114                         state->bo_count = i - 1;
 115                         goto err;
 116                 }
 117                 bo_state[i].handle = handle;
 118                 bo_state[i].paddr = vc4_bo->base.paddr;
 119                 bo_state[i].size = vc4_bo->base.base.size;
 120         }
 121
 122         if (copy_to_user((void __user *)(uintptr_t)get_state->bo,
 123                          bo_state,
 124                          state->bo_count * sizeof(*bo_state)))
 125                 ret = -EFAULT;
 126
 127         kfree(bo_state);
 128
 129 err_free:
 130
 131         vc4_free_hang_state(dev, kernel_state);
 132
 133 err:
 134         return ret;
 135 }
 136
 137 static void
 138 vc4_save_hang_state(struct drm_device *dev)
 139 {
 140         struct vc4_dev *vc4 = to_vc4_dev(dev);
 141         struct drm_vc4_get_hang_state *state;
 142         struct vc4_hang_state *kernel_state;
 143         struct vc4_exec_info *exec[2];
 144         struct vc4_bo *bo;
 145         unsigned long irqflags;
 146         unsigned int i, j, unref_list_count, prev_idx;
 147
 148         kernel_state = kcalloc(1, sizeof(*kernel_state), GFP_KERNEL);
 149         if (!kernel_state)
 150                 return;
 151
 152         state = &kernel_state->user_state;
 153
 154         spin_lock_irqsave(&vc4->job_lock, irqflags);
 155         exec[0] = vc4_first_bin_job(vc4);
 156         exec[1] = vc4_first_render_job(vc4);
 157         if (!exec[0] && !exec[1]) {
 158                 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
 159                 return;
 160         }
 161
 162         /* Get the bos from both binner and renderer into hang state. */
 163         state->bo_count = 0;
 164         for (i = 0; i < 2; i++) {
 165                 if (!exec[i])
 166                         continue;
 167
 168                 unref_list_count = 0;
 169                 list_for_each_entry(bo, &exec[i]->unref_list, unref_head)
 170                         unref_list_count++;
 171                 state->bo_count += exec[i]->bo_count + unref_list_count;
 172         }
 173
 174         kernel_state->bo = kcalloc(state->bo_count,
 175                                    sizeof(*kernel_state->bo), GFP_ATOMIC);
 176
 177         if (!kernel_state->bo) {
 178                 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
 179                 return;
 180         }
 181
 182         prev_idx = 0;
 183         for (i = 0; i < 2; i++) {
 184                 if (!exec[i])
 185                         continue;
 186
 187                 for (j = 0; j < exec[i]->bo_count; j++) {
 188                         drm_gem_object_reference(&exec[i]->bo[j]->base);
 189                         kernel_state->bo[j + prev_idx] = &exec[i]->bo[j]->base;
 190                 }
 191
 192                 list_for_each_entry(bo, &exec[i]->unref_list, unref_head) {
 193                         drm_gem_object_reference(&bo->base.base);
 194                         kernel_state->bo[j + prev_idx] = &bo->base.base;
 195                         j++;
 196                 }
 197                 prev_idx = j + 1;
 198         }
 199
 200         if (exec[0])
 201                 state->start_bin = exec[0]->ct0ca;
 202         if (exec[1])
 203                 state->start_render = exec[1]->ct1ca;
 204
 205         spin_unlock_irqrestore(&vc4->job_lock, irqflags);
 206
 207         state->ct0ca = V3D_READ(V3D_CTNCA(0));
 208         state->ct0ea = V3D_READ(V3D_CTNEA(0));
 209
 210         state->ct1ca = V3D_READ(V3D_CTNCA(1));
 211         state->ct1ea = V3D_READ(V3D_CTNEA(1));
 212
 213         state->ct0cs = V3D_READ(V3D_CTNCS(0));
 214         state->ct1cs = V3D_READ(V3D_CTNCS(1));
 215
 216         state->ct0ra0 = V3D_READ(V3D_CT00RA0);
 217         state->ct1ra0 = V3D_READ(V3D_CT01RA0);
 218
 219         state->bpca = V3D_READ(V3D_BPCA);
 220         state->bpcs = V3D_READ(V3D_BPCS);
 221         state->bpoa = V3D_READ(V3D_BPOA);
 222         state->bpos = V3D_READ(V3D_BPOS);
 223
 224         state->vpmbase = V3D_READ(V3D_VPMBASE);
 225
 226         state->dbge = V3D_READ(V3D_DBGE);
 227         state->fdbgo = V3D_READ(V3D_FDBGO);
 228         state->fdbgb = V3D_READ(V3D_FDBGB);
 229         state->fdbgr = V3D_READ(V3D_FDBGR);
 230         state->fdbgs = V3D_READ(V3D_FDBGS);
 231         state->errstat = V3D_READ(V3D_ERRSTAT);
 232
 233         spin_lock_irqsave(&vc4->job_lock, irqflags);
 234         if (vc4->hang_state) {
 235                 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
 236                 vc4_free_hang_state(dev, kernel_state);
 237         } else {
 238                 vc4->hang_state = kernel_state;
 239                 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
 240         }
 241 }
 242
 243 static void
 244 vc4_reset(struct drm_device *dev)
 245 {
 246         struct vc4_dev *vc4 = to_vc4_dev(dev);
 247
 248         DRM_INFO("Resetting GPU.\n");
 249
 250         mutex_lock(&vc4->power_lock);
 251         if (vc4->power_refcount) {
 252                 /* Power the device off and back on the by dropping the
 253                  * reference on runtime PM.
 254                  */
 255                 pm_runtime_put_sync_suspend(&vc4->v3d->pdev->dev);
 256                 pm_runtime_get_sync(&vc4->v3d->pdev->dev);
 257         }
 258         mutex_unlock(&vc4->power_lock);
 259
 260         vc4_irq_reset(dev);
 261
 262         /* Rearm the hangcheck -- another job might have been waiting
 263          * for our hung one to get kicked off, and vc4_irq_reset()
 264          * would have started it.
 265          */
 266         vc4_queue_hangcheck(dev);
 267 }
 268
 269 static void
 270 vc4_reset_work(struct work_struct *work)
 271 {
 272         struct vc4_dev *vc4 =
 273                 container_of(work, struct vc4_dev, hangcheck.reset_work);
 274
 275         vc4_save_hang_state(vc4->dev);
 276
 277         vc4_reset(vc4->dev);
 278 }
 279
 280 static void
 281 vc4_hangcheck_elapsed(unsigned long data)
 282 {
 283         struct drm_device *dev = (struct drm_device *)data;
 284         struct vc4_dev *vc4 = to_vc4_dev(dev);
 285         uint32_t ct0ca, ct1ca;
 286         unsigned long irqflags;
 287         struct vc4_exec_info *bin_exec, *render_exec;
 288
 289         spin_lock_irqsave(&vc4->job_lock, irqflags);
 290
 291         bin_exec = vc4_first_bin_job(vc4);
 292         render_exec = vc4_first_render_job(vc4);
 293
 294         /* If idle, we can stop watching for hangs. */
 295         if (!bin_exec && !render_exec) {
 296                 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
 297                 return;
 298         }
 299
 300         ct0ca = V3D_READ(V3D_CTNCA(0));
 301         ct1ca = V3D_READ(V3D_CTNCA(1));
 302
 303         /* If we've made any progress in execution, rearm the timer
 304          * and wait.
 305          */
 306         if ((bin_exec && ct0ca != bin_exec->last_ct0ca) ||
 307             (render_exec && ct1ca != render_exec->last_ct1ca)) {
 308                 if (bin_exec)
 309                         bin_exec->last_ct0ca = ct0ca;
 310                 if (render_exec)
 311                         render_exec->last_ct1ca = ct1ca;
 312                 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
 313                 vc4_queue_hangcheck(dev);
 314                 return;
 315         }
 316
 317         spin_unlock_irqrestore(&vc4->job_lock, irqflags);
 318
 319         /* We've gone too long with no progress, reset.  This has to
 320          * be done from a work struct, since resetting can sleep and
 321          * this timer hook isn't allowed to.
 322          */
 323         schedule_work(&vc4->hangcheck.reset_work);
 324 }
 325
 326 static void
 327 submit_cl(struct drm_device *dev, uint32_t thread, uint32_t start, uint32_t end)
 328 {
 329         struct vc4_dev *vc4 = to_vc4_dev(dev);
 330
 331         /* Set the current and end address of the control list.
 332          * Writing the end register is what starts the job.
 333          */
 334         V3D_WRITE(V3D_CTNCA(thread), start);
 335         V3D_WRITE(V3D_CTNEA(thread), end);
 336 }
 337
 338 int
 339 vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno, uint64_t timeout_ns,
 340                    bool interruptible)
 341 {
 342         struct vc4_dev *vc4 = to_vc4_dev(dev);
 343         int ret = 0;
 344         unsigned long timeout_expire;
 345         DEFINE_WAIT(wait);
 346
 347         if (vc4->finished_seqno >= seqno)
 348                 return 0;
 349
 350         if (timeout_ns == 0)
 351                 return -ETIME;
 352
 353         timeout_expire = jiffies + nsecs_to_jiffies(timeout_ns);
 354
 355         trace_vc4_wait_for_seqno_begin(dev, seqno, timeout_ns);
 356         for (;;) {
 357                 prepare_to_wait(&vc4->job_wait_queue, &wait,
 358                                 interruptible ? TASK_INTERRUPTIBLE :
 359                                 TASK_UNINTERRUPTIBLE);
 360
 361                 if (interruptible && signal_pending(current)) {
 362                         ret = -ERESTARTSYS;
 363                         break;
 364                 }
 365
 366                 if (vc4->finished_seqno >= seqno)
 367                         break;
 368
 369                 if (timeout_ns != ~0ull) {
 370                         if (time_after_eq(jiffies, timeout_expire)) {
 371                                 ret = -ETIME;
 372                                 break;
 373                         }
 374                         schedule_timeout(timeout_expire - jiffies);
 375                 } else {
 376                         schedule();
 377                 }
 378         }
 379
 380         finish_wait(&vc4->job_wait_queue, &wait);
 381         trace_vc4_wait_for_seqno_end(dev, seqno);
 382
 383         return ret;
 384 }
 385
 386 static void
 387 vc4_flush_caches(struct drm_device *dev)
 388 {
 389         struct vc4_dev *vc4 = to_vc4_dev(dev);
 390
 391         /* Flush the GPU L2 caches.  These caches sit on top of system
 392          * L3 (the 128kb or so shared with the CPU), and are
 393          * non-allocating in the L3.
 394          */
 395         V3D_WRITE(V3D_L2CACTL,
 396                   V3D_L2CACTL_L2CCLR);
 397
 398         V3D_WRITE(V3D_SLCACTL,
 399                   VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) |
 400                   VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC) |
 401                   VC4_SET_FIELD(0xf, V3D_SLCACTL_UCC) |
 402                   VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC));
 403 }
 404
 405 /* Sets the registers for the next job to be actually be executed in
 406  * the hardware.
 407  *
 408  * The job_lock should be held during this.
 409  */
 410 void
 411 vc4_submit_next_bin_job(struct drm_device *dev)
 412 {
 413         struct vc4_dev *vc4 = to_vc4_dev(dev);
 414         struct vc4_exec_info *exec;
 415
 416 again:
 417         exec = vc4_first_bin_job(vc4);
 418         if (!exec)
 419                 return;
 420
 421         vc4_flush_caches(dev);
 422
 423         /* Either put the job in the binner if it uses the binner, or
 424          * immediately move it to the to-be-rendered queue.
 425          */
 426         if (exec->ct0ca != exec->ct0ea) {
 427                 submit_cl(dev, 0, exec->ct0ca, exec->ct0ea);
 428         } else {
 429                 vc4_move_job_to_render(dev, exec);
 430                 goto again;
 431         }
 432 }
 433
 434 void
 435 vc4_submit_next_render_job(struct drm_device *dev)
 436 {
 437         struct vc4_dev *vc4 = to_vc4_dev(dev);
 438         struct vc4_exec_info *exec = vc4_first_render_job(vc4);
 439
 440         if (!exec)
 441                 return;
 442
 443         submit_cl(dev, 1, exec->ct1ca, exec->ct1ea);
 444 }
 445
 446 void
 447 vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec)
 448 {
 449         struct vc4_dev *vc4 = to_vc4_dev(dev);
 450         bool was_empty = list_empty(&vc4->render_job_list);
 451
 452         list_move_tail(&exec->head, &vc4->render_job_list);
 453         if (was_empty)
 454                 vc4_submit_next_render_job(dev);
 455 }
 456
 457 static void
 458 vc4_update_bo_seqnos(struct vc4_exec_info *exec, uint64_t seqno)
 459 {
 460         struct vc4_bo *bo;
 461         unsigned i;
 462
 463         for (i = 0; i < exec->bo_count; i++) {
 464                 bo = to_vc4_bo(&exec->bo[i]->base);
 465                 bo->seqno = seqno;
 466         }
 467
 468         list_for_each_entry(bo, &exec->unref_list, unref_head) {
 469                 bo->seqno = seqno;
 470         }
 471
 472         for (i = 0; i < exec->rcl_write_bo_count; i++) {
 473                 bo = to_vc4_bo(&exec->rcl_write_bo[i]->base);
 474                 bo->write_seqno = seqno;
 475         }
 476 }
 477
 478 /* Queues a struct vc4_exec_info for execution.  If no job is
 479  * currently executing, then submits it.
 480  *
 481  * Unlike most GPUs, our hardware only handles one command list at a
 482  * time.  To queue multiple jobs at once, we'd need to edit the
 483  * previous command list to have a jump to the new one at the end, and
 484  * then bump the end address.  That's a change for a later date,
 485  * though.
 486  */
 487 static void
 488 vc4_queue_submit(struct drm_device *dev, struct vc4_exec_info *exec)
 489 {
 490         struct vc4_dev *vc4 = to_vc4_dev(dev);
 491         uint64_t seqno;
 492         unsigned long irqflags;
 493
 494         spin_lock_irqsave(&vc4->job_lock, irqflags);
 495
 496         seqno = ++vc4->emit_seqno;
 497         exec->seqno = seqno;
 498         vc4_update_bo_seqnos(exec, seqno);
 499
 500         list_add_tail(&exec->head, &vc4->bin_job_list);
 501
 502         /* If no job was executing, kick ours off.  Otherwise, it'll
 503          * get started when the previous job's flush done interrupt
 504          * occurs.
 505          */
 506         if (vc4_first_bin_job(vc4) == exec) {
 507                 vc4_submit_next_bin_job(dev);
 508                 vc4_queue_hangcheck(dev);
 509         }
 510
 511         spin_unlock_irqrestore(&vc4->job_lock, irqflags);
 512 }
 513
 514 /**
 515  * vc4_cl_lookup_bos() - Sets up exec->bo[] with the GEM objects
 516  * referenced by the job.
 517  * @dev: DRM device
 518  * @file_priv: DRM file for this fd
 519  * @exec: V3D job being set up
 520  *
 521  * The command validator needs to reference BOs by their index within
 522  * the submitted job's BO list.  This does the validation of the job's
 523  * BO list and reference counting for the lifetime of the job.
 524  *
 525  * Note that this function doesn't need to unreference the BOs on
 526  * failure, because that will happen at vc4_complete_exec() time.
 527  */
 528 static int
 529 vc4_cl_lookup_bos(struct drm_device *dev,
 530                   struct drm_file *file_priv,
 531                   struct vc4_exec_info *exec)
 532 {
 533         struct drm_vc4_submit_cl *args = exec->args;
 534         uint32_t *handles;
 535         int ret = 0;
 536         int i;
 537
 538         exec->bo_count = args->bo_handle_count;
 539
 540         if (!exec->bo_count) {
 541                 /* See comment on bo_index for why we have to check
 542                  * this.
 543                  */
 544                 DRM_ERROR("Rendering requires BOs to validate\n");
 545                 return -EINVAL;
 546         }
 547
 548         exec->bo = drm_calloc_large(exec->bo_count,
 549                                     sizeof(struct drm_gem_cma_object *));
 550         if (!exec->bo) {
 551                 DRM_ERROR("Failed to allocate validated BO pointers\n");
 552                 return -ENOMEM;
 553         }
 554
 555         handles = drm_malloc_ab(exec->bo_count, sizeof(uint32_t));
 556         if (!handles) {
 557                 ret = -ENOMEM;
 558                 DRM_ERROR("Failed to allocate incoming GEM handles\n");
 559                 goto fail;
 560         }
 561
 562         if (copy_from_user(handles,
 563                            (void __user *)(uintptr_t)args->bo_handles,
 564                            exec->bo_count * sizeof(uint32_t))) {
 565                 ret = -EFAULT;
 566                 DRM_ERROR("Failed to copy in GEM handles\n");
 567                 goto fail;
 568         }
 569
 570         spin_lock(&file_priv->table_lock);
 571         for (i = 0; i < exec->bo_count; i++) {
 572                 struct drm_gem_object *bo = idr_find(&file_priv->object_idr,
 573                                                      handles[i]);
 574                 if (!bo) {
 575                         DRM_ERROR("Failed to look up GEM BO %d: %d\n",
 576                                   i, handles[i]);
 577                         ret = -EINVAL;
 578                         spin_unlock(&file_priv->table_lock);
 579                         goto fail;
 580                 }
 581                 drm_gem_object_reference(bo);
 582                 exec->bo[i] = (struct drm_gem_cma_object *)bo;
 583         }
 584         spin_unlock(&file_priv->table_lock);
 585
 586 fail:
 587         drm_free_large(handles);
 588         return ret;
 589 }
 590
 591 static int
 592 vc4_get_bcl(struct drm_device *dev, struct vc4_exec_info *exec)
 593 {
 594         struct drm_vc4_submit_cl *args = exec->args;
 595         void *temp = NULL;
 596         void *bin;
 597         int ret = 0;
 598         uint32_t bin_offset = 0;
 599         uint32_t shader_rec_offset = roundup(bin_offset + args->bin_cl_size,
 600                                              16);
 601         uint32_t uniforms_offset = shader_rec_offset + args->shader_rec_size;
 602         uint32_t exec_size = uniforms_offset + args->uniforms_size;
 603         uint32_t temp_size = exec_size + (sizeof(struct vc4_shader_state) *
 604                                           args->shader_rec_count);
 605         struct vc4_bo *bo;
 606
 607         if (shader_rec_offset < args->bin_cl_size ||
 608             uniforms_offset < shader_rec_offset ||
 609             exec_size < uniforms_offset ||
 610             args->shader_rec_count >= (UINT_MAX /
 611                                           sizeof(struct vc4_shader_state)) ||
 612             temp_size < exec_size) {
 613                 DRM_ERROR("overflow in exec arguments\n");
 614                 ret = -EINVAL;
 615                 goto fail;
 616         }
 617
 618         /* Allocate space where we'll store the copied in user command lists
 619          * and shader records.
 620          *
 621          * We don't just copy directly into the BOs because we need to
 622          * read the contents back for validation, and I think the
 623          * bo->vaddr is uncached access.
 624          */
 625         temp = drm_malloc_ab(temp_size, 1);
 626         if (!temp) {
 627                 DRM_ERROR("Failed to allocate storage for copying "
 628                           "in bin/render CLs.\n");
 629                 ret = -ENOMEM;
 630                 goto fail;
 631         }
 632         bin = temp + bin_offset;
 633         exec->shader_rec_u = temp + shader_rec_offset;
 634         exec->uniforms_u = temp + uniforms_offset;
 635         exec->shader_state = temp + exec_size;
 636         exec->shader_state_size = args->shader_rec_count;
 637
 638         if (copy_from_user(bin,
 639                            (void __user *)(uintptr_t)args->bin_cl,
 640                            args->bin_cl_size)) {
 641                 ret = -EFAULT;
 642                 goto fail;
 643         }
 644
 645         if (copy_from_user(exec->shader_rec_u,
 646                            (void __user *)(uintptr_t)args->shader_rec,
 647                            args->shader_rec_size)) {
 648                 ret = -EFAULT;
 649                 goto fail;
 650         }
 651
 652         if (copy_from_user(exec->uniforms_u,
 653                            (void __user *)(uintptr_t)args->uniforms,
 654                            args->uniforms_size)) {
 655                 ret = -EFAULT;
 656                 goto fail;
 657         }
 658
 659         bo = vc4_bo_create(dev, exec_size, true);
 660         if (IS_ERR(bo)) {
 661                 DRM_ERROR("Couldn't allocate BO for binning\n");
 662                 ret = PTR_ERR(bo);
 663                 goto fail;
 664         }
 665         exec->exec_bo = &bo->base;
 666
 667         list_add_tail(&to_vc4_bo(&exec->exec_bo->base)->unref_head,
 668                       &exec->unref_list);
 669
 670         exec->ct0ca = exec->exec_bo->paddr + bin_offset;
 671
 672         exec->bin_u = bin;
 673
 674         exec->shader_rec_v = exec->exec_bo->vaddr + shader_rec_offset;
 675         exec->shader_rec_p = exec->exec_bo->paddr + shader_rec_offset;
 676         exec->shader_rec_size = args->shader_rec_size;
 677
 678         exec->uniforms_v = exec->exec_bo->vaddr + uniforms_offset;
 679         exec->uniforms_p = exec->exec_bo->paddr + uniforms_offset;
 680         exec->uniforms_size = args->uniforms_size;
 681
 682         ret = vc4_validate_bin_cl(dev,
 683                                   exec->exec_bo->vaddr + bin_offset,
 684                                   bin,
 685                                   exec);
 686         if (ret)
 687                 goto fail;
 688
 689         ret = vc4_validate_shader_recs(dev, exec);
 690         if (ret)
 691                 goto fail;
 692
 693         /* Block waiting on any previous rendering into the CS's VBO,
 694          * IB, or textures, so that pixels are actually written by the
 695          * time we try to read them.
 696          */
 697         ret = vc4_wait_for_seqno(dev, exec->bin_dep_seqno, ~0ull, true);
 698
 699 fail:
 700         drm_free_large(temp);
 701         return ret;
 702 }
 703
 704 static void
 705 vc4_complete_exec(struct drm_device *dev, struct vc4_exec_info *exec)
 706 {
 707         struct vc4_dev *vc4 = to_vc4_dev(dev);
 708         unsigned i;
 709
 710         if (exec->bo) {
 711                 for (i = 0; i < exec->bo_count; i++)
 712                         drm_gem_object_unreference_unlocked(&exec->bo[i]->base);
 713                 drm_free_large(exec->bo);
 714         }
 715
 716         while (!list_empty(&exec->unref_list)) {
 717                 struct vc4_bo *bo = list_first_entry(&exec->unref_list,
 718                                                      struct vc4_bo, unref_head);
 719                 list_del(&bo->unref_head);
 720                 drm_gem_object_unreference_unlocked(&bo->base.base);
 721         }
 722
 723         mutex_lock(&vc4->power_lock);
 724         if (--vc4->power_refcount == 0) {
 725                 pm_runtime_mark_last_busy(&vc4->v3d->pdev->dev);
 726                 pm_runtime_put_autosuspend(&vc4->v3d->pdev->dev);
 727         }
 728         mutex_unlock(&vc4->power_lock);
 729
 730         kfree(exec);
 731 }
 732
 733 void
 734 vc4_job_handle_completed(struct vc4_dev *vc4)
 735 {
 736         unsigned long irqflags;
 737         struct vc4_seqno_cb *cb, *cb_temp;
 738
 739         spin_lock_irqsave(&vc4->job_lock, irqflags);
 740         while (!list_empty(&vc4->job_done_list)) {
 741                 struct vc4_exec_info *exec =
 742                         list_first_entry(&vc4->job_done_list,
 743                                          struct vc4_exec_info, head);
 744                 list_del(&exec->head);
 745
 746                 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
 747                 vc4_complete_exec(vc4->dev, exec);
 748                 spin_lock_irqsave(&vc4->job_lock, irqflags);
 749         }
 750
 751         list_for_each_entry_safe(cb, cb_temp, &vc4->seqno_cb_list, work.entry) {
 752                 if (cb->seqno <= vc4->finished_seqno) {
 753                         list_del_init(&cb->work.entry);
 754                         schedule_work(&cb->work);
 755                 }
 756         }
 757
 758         spin_unlock_irqrestore(&vc4->job_lock, irqflags);
 759 }
 760
 761 static void vc4_seqno_cb_work(struct work_struct *work)
 762 {
 763         struct vc4_seqno_cb *cb = container_of(work, struct vc4_seqno_cb, work);
 764
 765         cb->func(cb);
 766 }
 767
 768 int vc4_queue_seqno_cb(struct drm_device *dev,
 769                        struct vc4_seqno_cb *cb, uint64_t seqno,
 770                        void (*func)(struct vc4_seqno_cb *cb))
 771 {
 772         struct vc4_dev *vc4 = to_vc4_dev(dev);
 773         int ret = 0;
 774         unsigned long irqflags;
 775
 776         cb->func = func;
 777         INIT_WORK(&cb->work, vc4_seqno_cb_work);
 778
 779         spin_lock_irqsave(&vc4->job_lock, irqflags);
 780         if (seqno > vc4->finished_seqno) {
 781                 cb->seqno = seqno;
 782                 list_add_tail(&cb->work.entry, &vc4->seqno_cb_list);
 783         } else {
 784                 schedule_work(&cb->work);
 785         }
 786         spin_unlock_irqrestore(&vc4->job_lock, irqflags);
 787
 788         return ret;
 789 }
 790
 791 /* Scheduled when any job has been completed, this walks the list of
 792  * jobs that had completed and unrefs their BOs and frees their exec
 793  * structs.
 794  */
 795 static void
 796 vc4_job_done_work(struct work_struct *work)
 797 {
 798         struct vc4_dev *vc4 =
 799                 container_of(work, struct vc4_dev, job_done_work);
 800
 801         vc4_job_handle_completed(vc4);
 802 }
 803
 804 static int
 805 vc4_wait_for_seqno_ioctl_helper(struct drm_device *dev,
 806                                 uint64_t seqno,
 807                                 uint64_t *timeout_ns)
 808 {
 809         unsigned long start = jiffies;
 810         int ret = vc4_wait_for_seqno(dev, seqno, *timeout_ns, true);
 811
 812         if ((ret == -EINTR || ret == -ERESTARTSYS) && *timeout_ns != ~0ull) {
 813                 uint64_t delta = jiffies_to_nsecs(jiffies - start);
 814
 815                 if (*timeout_ns >= delta)
 816                         *timeout_ns -= delta;
 817         }
 818
 819         return ret;
 820 }
 821
 822 int
 823 vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
 824                      struct drm_file *file_priv)
 825 {
 826         struct drm_vc4_wait_seqno *args = data;
 827
 828         return vc4_wait_for_seqno_ioctl_helper(dev, args->seqno,
 829                                                &args->timeout_ns);
 830 }
 831
 832 int
 833 vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
 834                   struct drm_file *file_priv)
 835 {
 836         int ret;
 837         struct drm_vc4_wait_bo *args = data;
 838         struct drm_gem_object *gem_obj;
 839         struct vc4_bo *bo;
 840
 841         if (args->pad != 0)
 842                 return -EINVAL;
 843
 844         gem_obj = drm_gem_object_lookup(file_priv, args->handle);
 845         if (!gem_obj) {
 846                 DRM_ERROR("Failed to look up GEM BO %d\n", args->handle);
 847                 return -EINVAL;
 848         }
 849         bo = to_vc4_bo(gem_obj);
 850
 851         ret = vc4_wait_for_seqno_ioctl_helper(dev, bo->seqno,
 852                                               &args->timeout_ns);
 853
 854         drm_gem_object_unreference_unlocked(gem_obj);
 855         return ret;
 856 }
 857
 858 /**
 859  * vc4_submit_cl_ioctl() - Submits a job (frame) to the VC4.
 860  * @dev: DRM device
 861  * @data: ioctl argument
 862  * @file_priv: DRM file for this fd
 863  *
 864  * This is the main entrypoint for userspace to submit a 3D frame to
 865  * the GPU.  Userspace provides the binner command list (if
 866  * applicable), and the kernel sets up the render command list to draw
 867  * to the framebuffer described in the ioctl, using the command lists
 868  * that the 3D engine's binner will produce.
 869  */
 870 int
 871 vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
 872                     struct drm_file *file_priv)
 873 {
 874         struct vc4_dev *vc4 = to_vc4_dev(dev);
 875         struct drm_vc4_submit_cl *args = data;
 876         struct vc4_exec_info *exec;
 877         int ret = 0;
 878
 879         if ((args->flags & ~VC4_SUBMIT_CL_USE_CLEAR_COLOR) != 0) {
 880                 DRM_ERROR("Unknown flags: 0x%02x\n", args->flags);
 881                 return -EINVAL;
 882         }
 883
 884         exec = kcalloc(1, sizeof(*exec), GFP_KERNEL);
 885         if (!exec) {
 886                 DRM_ERROR("malloc failure on exec struct\n");
 887                 return -ENOMEM;
 888         }
 889
 890         mutex_lock(&vc4->power_lock);
 891         if (vc4->power_refcount++ == 0)
 892                 ret = pm_runtime_get_sync(&vc4->v3d->pdev->dev);
 893         mutex_unlock(&vc4->power_lock);
 894         if (ret < 0) {
 895                 kfree(exec);
 896                 return ret;
 897         }
 898
 899         exec->args = args;
 900         INIT_LIST_HEAD(&exec->unref_list);
 901
 902         ret = vc4_cl_lookup_bos(dev, file_priv, exec);
 903         if (ret)
 904                 goto fail;
 905
 906         if (exec->args->bin_cl_size != 0) {
 907                 ret = vc4_get_bcl(dev, exec);
 908                 if (ret)
 909                         goto fail;
 910         } else {
 911                 exec->ct0ca = 0;
 912                 exec->ct0ea = 0;
 913         }
 914
 915         ret = vc4_get_rcl(dev, exec);
 916         if (ret)
 917                 goto fail;
 918
 919         /* Clear this out of the struct we'll be putting in the queue,
 920          * since it's part of our stack.
 921          */
 922         exec->args = NULL;
 923
 924         vc4_queue_submit(dev, exec);
 925
 926         /* Return the seqno for our job. */
 927         args->seqno = vc4->emit_seqno;
 928
 929         return 0;
 930
 931 fail:
 932         vc4_complete_exec(vc4->dev, exec);
 933
 934         return ret;
 935 }
 936
 937 void
 938 vc4_gem_init(struct drm_device *dev)
 939 {
 940         struct vc4_dev *vc4 = to_vc4_dev(dev);
 941
 942         INIT_LIST_HEAD(&vc4->bin_job_list);
 943         INIT_LIST_HEAD(&vc4->render_job_list);
 944         INIT_LIST_HEAD(&vc4->job_done_list);
 945         INIT_LIST_HEAD(&vc4->seqno_cb_list);
 946         spin_lock_init(&vc4->job_lock);
 947
 948         INIT_WORK(&vc4->hangcheck.reset_work, vc4_reset_work);
 949         setup_timer(&vc4->hangcheck.timer,
 950                     vc4_hangcheck_elapsed,
 951                     (unsigned long)dev);
 952
 953         INIT_WORK(&vc4->job_done_work, vc4_job_done_work);
 954
 955         mutex_init(&vc4->power_lock);
 956 }
 957
 958 void
 959 vc4_gem_destroy(struct drm_device *dev)
 960 {
 961         struct vc4_dev *vc4 = to_vc4_dev(dev);
 962
 963         /* Waiting for exec to finish would need to be done before
 964          * unregistering V3D.
 965          */
 966         WARN_ON(vc4->emit_seqno != vc4->finished_seqno);
 967
 968         /* V3D should already have disabled its interrupt and cleared
 969          * the overflow allocation registers.  Now free the object.
 970          */
 971         if (vc4->overflow_mem) {
 972                 drm_gem_object_unreference_unlocked(&vc4->overflow_mem->base.base);
 973                 vc4->overflow_mem = NULL;
 974         }
 975
 976         if (vc4->hang_state)
 977                 vc4_free_hang_state(dev, vc4->hang_state);
 978
 979         vc4_bo_cache_destroy(dev);
 980 }