2 * Copyright © 2014 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/device.h>
29 #include <linux/sched/signal.h>
31 #include "uapi/drm/vc4_drm.h"
34 #include "vc4_trace.h"
37 vc4_queue_hangcheck(struct drm_device *dev)
39 struct vc4_dev *vc4 = to_vc4_dev(dev);
41 mod_timer(&vc4->hangcheck.timer,
42 round_jiffies_up(jiffies + msecs_to_jiffies(100)));
45 struct vc4_hang_state {
46 struct drm_vc4_get_hang_state user_state;
49 struct drm_gem_object **bo;
53 vc4_free_hang_state(struct drm_device *dev, struct vc4_hang_state *state)
57 for (i = 0; i < state->user_state.bo_count; i++)
58 drm_gem_object_unreference_unlocked(state->bo[i]);
64 vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
65 struct drm_file *file_priv)
67 struct drm_vc4_get_hang_state *get_state = data;
68 struct drm_vc4_get_hang_state_bo *bo_state;
69 struct vc4_hang_state *kernel_state;
70 struct drm_vc4_get_hang_state *state;
71 struct vc4_dev *vc4 = to_vc4_dev(dev);
72 unsigned long irqflags;
76 spin_lock_irqsave(&vc4->job_lock, irqflags);
77 kernel_state = vc4->hang_state;
79 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
82 state = &kernel_state->user_state;
84 /* If the user's array isn't big enough, just return the
85 * required array size.
87 if (get_state->bo_count < state->bo_count) {
88 get_state->bo_count = state->bo_count;
89 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
93 vc4->hang_state = NULL;
94 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
96 /* Save the user's BO pointer, so we don't stomp it with the memcpy. */
97 state->bo = get_state->bo;
98 memcpy(get_state, state, sizeof(*state));
100 bo_state = kcalloc(state->bo_count, sizeof(*bo_state), GFP_KERNEL);
106 for (i = 0; i < state->bo_count; i++) {
107 struct vc4_bo *vc4_bo = to_vc4_bo(kernel_state->bo[i]);
110 ret = drm_gem_handle_create(file_priv, kernel_state->bo[i],
114 state->bo_count = i - 1;
117 bo_state[i].handle = handle;
118 bo_state[i].paddr = vc4_bo->base.paddr;
119 bo_state[i].size = vc4_bo->base.base.size;
122 if (copy_to_user((void __user *)(uintptr_t)get_state->bo,
124 state->bo_count * sizeof(*bo_state)))
131 vc4_free_hang_state(dev, kernel_state);
138 vc4_save_hang_state(struct drm_device *dev)
140 struct vc4_dev *vc4 = to_vc4_dev(dev);
141 struct drm_vc4_get_hang_state *state;
142 struct vc4_hang_state *kernel_state;
143 struct vc4_exec_info *exec[2];
145 unsigned long irqflags;
146 unsigned int i, j, unref_list_count, prev_idx;
148 kernel_state = kcalloc(1, sizeof(*kernel_state), GFP_KERNEL);
152 state = &kernel_state->user_state;
154 spin_lock_irqsave(&vc4->job_lock, irqflags);
155 exec[0] = vc4_first_bin_job(vc4);
156 exec[1] = vc4_first_render_job(vc4);
157 if (!exec[0] && !exec[1]) {
158 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
162 /* Get the bos from both binner and renderer into hang state. */
164 for (i = 0; i < 2; i++) {
168 unref_list_count = 0;
169 list_for_each_entry(bo, &exec[i]->unref_list, unref_head)
171 state->bo_count += exec[i]->bo_count + unref_list_count;
174 kernel_state->bo = kcalloc(state->bo_count,
175 sizeof(*kernel_state->bo), GFP_ATOMIC);
177 if (!kernel_state->bo) {
178 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
183 for (i = 0; i < 2; i++) {
187 for (j = 0; j < exec[i]->bo_count; j++) {
188 drm_gem_object_reference(&exec[i]->bo[j]->base);
189 kernel_state->bo[j + prev_idx] = &exec[i]->bo[j]->base;
192 list_for_each_entry(bo, &exec[i]->unref_list, unref_head) {
193 drm_gem_object_reference(&bo->base.base);
194 kernel_state->bo[j + prev_idx] = &bo->base.base;
201 state->start_bin = exec[0]->ct0ca;
203 state->start_render = exec[1]->ct1ca;
205 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
207 state->ct0ca = V3D_READ(V3D_CTNCA(0));
208 state->ct0ea = V3D_READ(V3D_CTNEA(0));
210 state->ct1ca = V3D_READ(V3D_CTNCA(1));
211 state->ct1ea = V3D_READ(V3D_CTNEA(1));
213 state->ct0cs = V3D_READ(V3D_CTNCS(0));
214 state->ct1cs = V3D_READ(V3D_CTNCS(1));
216 state->ct0ra0 = V3D_READ(V3D_CT00RA0);
217 state->ct1ra0 = V3D_READ(V3D_CT01RA0);
219 state->bpca = V3D_READ(V3D_BPCA);
220 state->bpcs = V3D_READ(V3D_BPCS);
221 state->bpoa = V3D_READ(V3D_BPOA);
222 state->bpos = V3D_READ(V3D_BPOS);
224 state->vpmbase = V3D_READ(V3D_VPMBASE);
226 state->dbge = V3D_READ(V3D_DBGE);
227 state->fdbgo = V3D_READ(V3D_FDBGO);
228 state->fdbgb = V3D_READ(V3D_FDBGB);
229 state->fdbgr = V3D_READ(V3D_FDBGR);
230 state->fdbgs = V3D_READ(V3D_FDBGS);
231 state->errstat = V3D_READ(V3D_ERRSTAT);
233 spin_lock_irqsave(&vc4->job_lock, irqflags);
234 if (vc4->hang_state) {
235 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
236 vc4_free_hang_state(dev, kernel_state);
238 vc4->hang_state = kernel_state;
239 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
244 vc4_reset(struct drm_device *dev)
246 struct vc4_dev *vc4 = to_vc4_dev(dev);
248 DRM_INFO("Resetting GPU.\n");
250 mutex_lock(&vc4->power_lock);
251 if (vc4->power_refcount) {
252 /* Power the device off and back on the by dropping the
253 * reference on runtime PM.
255 pm_runtime_put_sync_suspend(&vc4->v3d->pdev->dev);
256 pm_runtime_get_sync(&vc4->v3d->pdev->dev);
258 mutex_unlock(&vc4->power_lock);
262 /* Rearm the hangcheck -- another job might have been waiting
263 * for our hung one to get kicked off, and vc4_irq_reset()
264 * would have started it.
266 vc4_queue_hangcheck(dev);
270 vc4_reset_work(struct work_struct *work)
272 struct vc4_dev *vc4 =
273 container_of(work, struct vc4_dev, hangcheck.reset_work);
275 vc4_save_hang_state(vc4->dev);
281 vc4_hangcheck_elapsed(unsigned long data)
283 struct drm_device *dev = (struct drm_device *)data;
284 struct vc4_dev *vc4 = to_vc4_dev(dev);
285 uint32_t ct0ca, ct1ca;
286 unsigned long irqflags;
287 struct vc4_exec_info *bin_exec, *render_exec;
289 spin_lock_irqsave(&vc4->job_lock, irqflags);
291 bin_exec = vc4_first_bin_job(vc4);
292 render_exec = vc4_first_render_job(vc4);
294 /* If idle, we can stop watching for hangs. */
295 if (!bin_exec && !render_exec) {
296 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
300 ct0ca = V3D_READ(V3D_CTNCA(0));
301 ct1ca = V3D_READ(V3D_CTNCA(1));
303 /* If we've made any progress in execution, rearm the timer
306 if ((bin_exec && ct0ca != bin_exec->last_ct0ca) ||
307 (render_exec && ct1ca != render_exec->last_ct1ca)) {
309 bin_exec->last_ct0ca = ct0ca;
311 render_exec->last_ct1ca = ct1ca;
312 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
313 vc4_queue_hangcheck(dev);
317 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
319 /* We've gone too long with no progress, reset. This has to
320 * be done from a work struct, since resetting can sleep and
321 * this timer hook isn't allowed to.
323 schedule_work(&vc4->hangcheck.reset_work);
327 submit_cl(struct drm_device *dev, uint32_t thread, uint32_t start, uint32_t end)
329 struct vc4_dev *vc4 = to_vc4_dev(dev);
331 /* Set the current and end address of the control list.
332 * Writing the end register is what starts the job.
334 V3D_WRITE(V3D_CTNCA(thread), start);
335 V3D_WRITE(V3D_CTNEA(thread), end);
339 vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno, uint64_t timeout_ns,
342 struct vc4_dev *vc4 = to_vc4_dev(dev);
344 unsigned long timeout_expire;
347 if (vc4->finished_seqno >= seqno)
353 timeout_expire = jiffies + nsecs_to_jiffies(timeout_ns);
355 trace_vc4_wait_for_seqno_begin(dev, seqno, timeout_ns);
357 prepare_to_wait(&vc4->job_wait_queue, &wait,
358 interruptible ? TASK_INTERRUPTIBLE :
359 TASK_UNINTERRUPTIBLE);
361 if (interruptible && signal_pending(current)) {
366 if (vc4->finished_seqno >= seqno)
369 if (timeout_ns != ~0ull) {
370 if (time_after_eq(jiffies, timeout_expire)) {
374 schedule_timeout(timeout_expire - jiffies);
380 finish_wait(&vc4->job_wait_queue, &wait);
381 trace_vc4_wait_for_seqno_end(dev, seqno);
387 vc4_flush_caches(struct drm_device *dev)
389 struct vc4_dev *vc4 = to_vc4_dev(dev);
391 /* Flush the GPU L2 caches. These caches sit on top of system
392 * L3 (the 128kb or so shared with the CPU), and are
393 * non-allocating in the L3.
395 V3D_WRITE(V3D_L2CACTL,
398 V3D_WRITE(V3D_SLCACTL,
399 VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) |
400 VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC) |
401 VC4_SET_FIELD(0xf, V3D_SLCACTL_UCC) |
402 VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC));
405 /* Sets the registers for the next job to be actually be executed in
408 * The job_lock should be held during this.
411 vc4_submit_next_bin_job(struct drm_device *dev)
413 struct vc4_dev *vc4 = to_vc4_dev(dev);
414 struct vc4_exec_info *exec;
417 exec = vc4_first_bin_job(vc4);
421 vc4_flush_caches(dev);
423 /* Either put the job in the binner if it uses the binner, or
424 * immediately move it to the to-be-rendered queue.
426 if (exec->ct0ca != exec->ct0ea) {
427 submit_cl(dev, 0, exec->ct0ca, exec->ct0ea);
429 vc4_move_job_to_render(dev, exec);
435 vc4_submit_next_render_job(struct drm_device *dev)
437 struct vc4_dev *vc4 = to_vc4_dev(dev);
438 struct vc4_exec_info *exec = vc4_first_render_job(vc4);
443 submit_cl(dev, 1, exec->ct1ca, exec->ct1ea);
447 vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec)
449 struct vc4_dev *vc4 = to_vc4_dev(dev);
450 bool was_empty = list_empty(&vc4->render_job_list);
452 list_move_tail(&exec->head, &vc4->render_job_list);
454 vc4_submit_next_render_job(dev);
458 vc4_update_bo_seqnos(struct vc4_exec_info *exec, uint64_t seqno)
463 for (i = 0; i < exec->bo_count; i++) {
464 bo = to_vc4_bo(&exec->bo[i]->base);
468 list_for_each_entry(bo, &exec->unref_list, unref_head) {
472 for (i = 0; i < exec->rcl_write_bo_count; i++) {
473 bo = to_vc4_bo(&exec->rcl_write_bo[i]->base);
474 bo->write_seqno = seqno;
478 /* Queues a struct vc4_exec_info for execution. If no job is
479 * currently executing, then submits it.
481 * Unlike most GPUs, our hardware only handles one command list at a
482 * time. To queue multiple jobs at once, we'd need to edit the
483 * previous command list to have a jump to the new one at the end, and
484 * then bump the end address. That's a change for a later date,
488 vc4_queue_submit(struct drm_device *dev, struct vc4_exec_info *exec)
490 struct vc4_dev *vc4 = to_vc4_dev(dev);
492 unsigned long irqflags;
494 spin_lock_irqsave(&vc4->job_lock, irqflags);
496 seqno = ++vc4->emit_seqno;
498 vc4_update_bo_seqnos(exec, seqno);
500 list_add_tail(&exec->head, &vc4->bin_job_list);
502 /* If no job was executing, kick ours off. Otherwise, it'll
503 * get started when the previous job's flush done interrupt
506 if (vc4_first_bin_job(vc4) == exec) {
507 vc4_submit_next_bin_job(dev);
508 vc4_queue_hangcheck(dev);
511 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
515 * Looks up a bunch of GEM handles for BOs and stores the array for
516 * use in the command validator that actually writes relocated
517 * addresses pointing to them.
520 vc4_cl_lookup_bos(struct drm_device *dev,
521 struct drm_file *file_priv,
522 struct vc4_exec_info *exec)
524 struct drm_vc4_submit_cl *args = exec->args;
529 exec->bo_count = args->bo_handle_count;
531 if (!exec->bo_count) {
532 /* See comment on bo_index for why we have to check
535 DRM_ERROR("Rendering requires BOs to validate\n");
539 exec->bo = drm_calloc_large(exec->bo_count,
540 sizeof(struct drm_gem_cma_object *));
542 DRM_ERROR("Failed to allocate validated BO pointers\n");
546 handles = drm_malloc_ab(exec->bo_count, sizeof(uint32_t));
549 DRM_ERROR("Failed to allocate incoming GEM handles\n");
553 if (copy_from_user(handles,
554 (void __user *)(uintptr_t)args->bo_handles,
555 exec->bo_count * sizeof(uint32_t))) {
557 DRM_ERROR("Failed to copy in GEM handles\n");
561 spin_lock(&file_priv->table_lock);
562 for (i = 0; i < exec->bo_count; i++) {
563 struct drm_gem_object *bo = idr_find(&file_priv->object_idr,
566 DRM_ERROR("Failed to look up GEM BO %d: %d\n",
569 spin_unlock(&file_priv->table_lock);
572 drm_gem_object_reference(bo);
573 exec->bo[i] = (struct drm_gem_cma_object *)bo;
575 spin_unlock(&file_priv->table_lock);
578 drm_free_large(handles);
583 vc4_get_bcl(struct drm_device *dev, struct vc4_exec_info *exec)
585 struct drm_vc4_submit_cl *args = exec->args;
589 uint32_t bin_offset = 0;
590 uint32_t shader_rec_offset = roundup(bin_offset + args->bin_cl_size,
592 uint32_t uniforms_offset = shader_rec_offset + args->shader_rec_size;
593 uint32_t exec_size = uniforms_offset + args->uniforms_size;
594 uint32_t temp_size = exec_size + (sizeof(struct vc4_shader_state) *
595 args->shader_rec_count);
598 if (shader_rec_offset < args->bin_cl_size ||
599 uniforms_offset < shader_rec_offset ||
600 exec_size < uniforms_offset ||
601 args->shader_rec_count >= (UINT_MAX /
602 sizeof(struct vc4_shader_state)) ||
603 temp_size < exec_size) {
604 DRM_ERROR("overflow in exec arguments\n");
609 /* Allocate space where we'll store the copied in user command lists
610 * and shader records.
612 * We don't just copy directly into the BOs because we need to
613 * read the contents back for validation, and I think the
614 * bo->vaddr is uncached access.
616 temp = drm_malloc_ab(temp_size, 1);
618 DRM_ERROR("Failed to allocate storage for copying "
619 "in bin/render CLs.\n");
623 bin = temp + bin_offset;
624 exec->shader_rec_u = temp + shader_rec_offset;
625 exec->uniforms_u = temp + uniforms_offset;
626 exec->shader_state = temp + exec_size;
627 exec->shader_state_size = args->shader_rec_count;
629 if (copy_from_user(bin,
630 (void __user *)(uintptr_t)args->bin_cl,
631 args->bin_cl_size)) {
636 if (copy_from_user(exec->shader_rec_u,
637 (void __user *)(uintptr_t)args->shader_rec,
638 args->shader_rec_size)) {
643 if (copy_from_user(exec->uniforms_u,
644 (void __user *)(uintptr_t)args->uniforms,
645 args->uniforms_size)) {
650 bo = vc4_bo_create(dev, exec_size, true);
652 DRM_ERROR("Couldn't allocate BO for binning\n");
656 exec->exec_bo = &bo->base;
658 list_add_tail(&to_vc4_bo(&exec->exec_bo->base)->unref_head,
661 exec->ct0ca = exec->exec_bo->paddr + bin_offset;
665 exec->shader_rec_v = exec->exec_bo->vaddr + shader_rec_offset;
666 exec->shader_rec_p = exec->exec_bo->paddr + shader_rec_offset;
667 exec->shader_rec_size = args->shader_rec_size;
669 exec->uniforms_v = exec->exec_bo->vaddr + uniforms_offset;
670 exec->uniforms_p = exec->exec_bo->paddr + uniforms_offset;
671 exec->uniforms_size = args->uniforms_size;
673 ret = vc4_validate_bin_cl(dev,
674 exec->exec_bo->vaddr + bin_offset,
680 ret = vc4_validate_shader_recs(dev, exec);
684 /* Block waiting on any previous rendering into the CS's VBO,
685 * IB, or textures, so that pixels are actually written by the
686 * time we try to read them.
688 ret = vc4_wait_for_seqno(dev, exec->bin_dep_seqno, ~0ull, true);
691 drm_free_large(temp);
696 vc4_complete_exec(struct drm_device *dev, struct vc4_exec_info *exec)
698 struct vc4_dev *vc4 = to_vc4_dev(dev);
702 for (i = 0; i < exec->bo_count; i++)
703 drm_gem_object_unreference_unlocked(&exec->bo[i]->base);
704 drm_free_large(exec->bo);
707 while (!list_empty(&exec->unref_list)) {
708 struct vc4_bo *bo = list_first_entry(&exec->unref_list,
709 struct vc4_bo, unref_head);
710 list_del(&bo->unref_head);
711 drm_gem_object_unreference_unlocked(&bo->base.base);
714 mutex_lock(&vc4->power_lock);
715 if (--vc4->power_refcount == 0) {
716 pm_runtime_mark_last_busy(&vc4->v3d->pdev->dev);
717 pm_runtime_put_autosuspend(&vc4->v3d->pdev->dev);
719 mutex_unlock(&vc4->power_lock);
725 vc4_job_handle_completed(struct vc4_dev *vc4)
727 unsigned long irqflags;
728 struct vc4_seqno_cb *cb, *cb_temp;
730 spin_lock_irqsave(&vc4->job_lock, irqflags);
731 while (!list_empty(&vc4->job_done_list)) {
732 struct vc4_exec_info *exec =
733 list_first_entry(&vc4->job_done_list,
734 struct vc4_exec_info, head);
735 list_del(&exec->head);
737 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
738 vc4_complete_exec(vc4->dev, exec);
739 spin_lock_irqsave(&vc4->job_lock, irqflags);
742 list_for_each_entry_safe(cb, cb_temp, &vc4->seqno_cb_list, work.entry) {
743 if (cb->seqno <= vc4->finished_seqno) {
744 list_del_init(&cb->work.entry);
745 schedule_work(&cb->work);
749 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
752 static void vc4_seqno_cb_work(struct work_struct *work)
754 struct vc4_seqno_cb *cb = container_of(work, struct vc4_seqno_cb, work);
759 int vc4_queue_seqno_cb(struct drm_device *dev,
760 struct vc4_seqno_cb *cb, uint64_t seqno,
761 void (*func)(struct vc4_seqno_cb *cb))
763 struct vc4_dev *vc4 = to_vc4_dev(dev);
765 unsigned long irqflags;
768 INIT_WORK(&cb->work, vc4_seqno_cb_work);
770 spin_lock_irqsave(&vc4->job_lock, irqflags);
771 if (seqno > vc4->finished_seqno) {
773 list_add_tail(&cb->work.entry, &vc4->seqno_cb_list);
775 schedule_work(&cb->work);
777 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
782 /* Scheduled when any job has been completed, this walks the list of
783 * jobs that had completed and unrefs their BOs and frees their exec
787 vc4_job_done_work(struct work_struct *work)
789 struct vc4_dev *vc4 =
790 container_of(work, struct vc4_dev, job_done_work);
792 vc4_job_handle_completed(vc4);
796 vc4_wait_for_seqno_ioctl_helper(struct drm_device *dev,
798 uint64_t *timeout_ns)
800 unsigned long start = jiffies;
801 int ret = vc4_wait_for_seqno(dev, seqno, *timeout_ns, true);
803 if ((ret == -EINTR || ret == -ERESTARTSYS) && *timeout_ns != ~0ull) {
804 uint64_t delta = jiffies_to_nsecs(jiffies - start);
806 if (*timeout_ns >= delta)
807 *timeout_ns -= delta;
814 vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
815 struct drm_file *file_priv)
817 struct drm_vc4_wait_seqno *args = data;
819 return vc4_wait_for_seqno_ioctl_helper(dev, args->seqno,
824 vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
825 struct drm_file *file_priv)
828 struct drm_vc4_wait_bo *args = data;
829 struct drm_gem_object *gem_obj;
835 gem_obj = drm_gem_object_lookup(file_priv, args->handle);
837 DRM_ERROR("Failed to look up GEM BO %d\n", args->handle);
840 bo = to_vc4_bo(gem_obj);
842 ret = vc4_wait_for_seqno_ioctl_helper(dev, bo->seqno,
845 drm_gem_object_unreference_unlocked(gem_obj);
850 * Submits a command list to the VC4.
852 * This is what is called batchbuffer emitting on other hardware.
855 vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
856 struct drm_file *file_priv)
858 struct vc4_dev *vc4 = to_vc4_dev(dev);
859 struct drm_vc4_submit_cl *args = data;
860 struct vc4_exec_info *exec;
863 if ((args->flags & ~VC4_SUBMIT_CL_USE_CLEAR_COLOR) != 0) {
864 DRM_ERROR("Unknown flags: 0x%02x\n", args->flags);
868 exec = kcalloc(1, sizeof(*exec), GFP_KERNEL);
870 DRM_ERROR("malloc failure on exec struct\n");
874 mutex_lock(&vc4->power_lock);
875 if (vc4->power_refcount++ == 0)
876 ret = pm_runtime_get_sync(&vc4->v3d->pdev->dev);
877 mutex_unlock(&vc4->power_lock);
884 INIT_LIST_HEAD(&exec->unref_list);
886 ret = vc4_cl_lookup_bos(dev, file_priv, exec);
890 if (exec->args->bin_cl_size != 0) {
891 ret = vc4_get_bcl(dev, exec);
899 ret = vc4_get_rcl(dev, exec);
903 /* Clear this out of the struct we'll be putting in the queue,
904 * since it's part of our stack.
908 vc4_queue_submit(dev, exec);
910 /* Return the seqno for our job. */
911 args->seqno = vc4->emit_seqno;
916 vc4_complete_exec(vc4->dev, exec);
922 vc4_gem_init(struct drm_device *dev)
924 struct vc4_dev *vc4 = to_vc4_dev(dev);
926 INIT_LIST_HEAD(&vc4->bin_job_list);
927 INIT_LIST_HEAD(&vc4->render_job_list);
928 INIT_LIST_HEAD(&vc4->job_done_list);
929 INIT_LIST_HEAD(&vc4->seqno_cb_list);
930 spin_lock_init(&vc4->job_lock);
932 INIT_WORK(&vc4->hangcheck.reset_work, vc4_reset_work);
933 setup_timer(&vc4->hangcheck.timer,
934 vc4_hangcheck_elapsed,
937 INIT_WORK(&vc4->job_done_work, vc4_job_done_work);
939 mutex_init(&vc4->power_lock);
943 vc4_gem_destroy(struct drm_device *dev)
945 struct vc4_dev *vc4 = to_vc4_dev(dev);
947 /* Waiting for exec to finish would need to be done before
950 WARN_ON(vc4->emit_seqno != vc4->finished_seqno);
952 /* V3D should already have disabled its interrupt and cleared
953 * the overflow allocation registers. Now free the object.
955 if (vc4->overflow_mem) {
956 drm_gem_object_unreference_unlocked(&vc4->overflow_mem->base.base);
957 vc4->overflow_mem = NULL;
961 vc4_free_hang_state(dev, vc4->hang_state);
963 vc4_bo_cache_destroy(dev);