1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016 Broadcom
7 * DOC: VC4 DSI0/DSI1 module
9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
13 * Most Raspberry Pi boards expose DSI1 as their "DISPLAY" connector,
14 * while the compute module brings both DSI0 and DSI1 out.
16 * This driver has been tested for DSI1 video-mode display only
17 * currently, with most of the information necessary for DSI0
21 #include <linux/clk-provider.h>
22 #include <linux/clk.h>
23 #include <linux/completion.h>
24 #include <linux/component.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/dmaengine.h>
27 #include <linux/i2c.h>
29 #include <linux/of_address.h>
30 #include <linux/of_platform.h>
31 #include <linux/pm_runtime.h>
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_bridge.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_mipi_dsi.h>
37 #include <drm/drm_of.h>
38 #include <drm/drm_panel.h>
39 #include <drm/drm_probe_helper.h>
40 #include <drm/drm_simple_kms_helper.h>
45 #define DSI_CMD_FIFO_DEPTH 16
46 #define DSI_PIX_FIFO_DEPTH 256
47 #define DSI_PIX_FIFO_WIDTH 4
49 #define DSI0_CTRL 0x00
51 /* Command packet control. */
52 #define DSI0_TXPKT1C 0x04 /* AKA PKTC */
53 #define DSI1_TXPKT1C 0x04
54 # define DSI_TXPKT1C_TRIG_CMD_MASK VC4_MASK(31, 24)
55 # define DSI_TXPKT1C_TRIG_CMD_SHIFT 24
56 # define DSI_TXPKT1C_CMD_REPEAT_MASK VC4_MASK(23, 10)
57 # define DSI_TXPKT1C_CMD_REPEAT_SHIFT 10
59 # define DSI_TXPKT1C_DISPLAY_NO_MASK VC4_MASK(9, 8)
60 # define DSI_TXPKT1C_DISPLAY_NO_SHIFT 8
61 /* Short, trigger, BTA, or a long packet that fits all in CMDFIFO. */
62 # define DSI_TXPKT1C_DISPLAY_NO_SHORT 0
63 /* Primary display where cmdfifo provides part of the payload and
64 * pixelvalve the rest.
66 # define DSI_TXPKT1C_DISPLAY_NO_PRIMARY 1
67 /* Secondary display where cmdfifo provides part of the payload and
70 # define DSI_TXPKT1C_DISPLAY_NO_SECONDARY 2
72 # define DSI_TXPKT1C_CMD_TX_TIME_MASK VC4_MASK(7, 6)
73 # define DSI_TXPKT1C_CMD_TX_TIME_SHIFT 6
75 # define DSI_TXPKT1C_CMD_CTRL_MASK VC4_MASK(5, 4)
76 # define DSI_TXPKT1C_CMD_CTRL_SHIFT 4
77 /* Command only. Uses TXPKT1H and DISPLAY_NO */
78 # define DSI_TXPKT1C_CMD_CTRL_TX 0
79 /* Command with BTA for either ack or read data. */
80 # define DSI_TXPKT1C_CMD_CTRL_RX 1
81 /* Trigger according to TRIG_CMD */
82 # define DSI_TXPKT1C_CMD_CTRL_TRIG 2
83 /* BTA alone for getting error status after a command, or a TE trigger
84 * without a previous command.
86 # define DSI_TXPKT1C_CMD_CTRL_BTA 3
88 # define DSI_TXPKT1C_CMD_MODE_LP BIT(3)
89 # define DSI_TXPKT1C_CMD_TYPE_LONG BIT(2)
90 # define DSI_TXPKT1C_CMD_TE_EN BIT(1)
91 # define DSI_TXPKT1C_CMD_EN BIT(0)
93 /* Command packet header. */
94 #define DSI0_TXPKT1H 0x08 /* AKA PKTH */
95 #define DSI1_TXPKT1H 0x08
96 # define DSI_TXPKT1H_BC_CMDFIFO_MASK VC4_MASK(31, 24)
97 # define DSI_TXPKT1H_BC_CMDFIFO_SHIFT 24
98 # define DSI_TXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
99 # define DSI_TXPKT1H_BC_PARAM_SHIFT 8
100 # define DSI_TXPKT1H_BC_DT_MASK VC4_MASK(7, 0)
101 # define DSI_TXPKT1H_BC_DT_SHIFT 0
103 #define DSI0_RXPKT1H 0x0c /* AKA RX1_PKTH */
104 #define DSI1_RXPKT1H 0x14
105 # define DSI_RXPKT1H_CRC_ERR BIT(31)
106 # define DSI_RXPKT1H_DET_ERR BIT(30)
107 # define DSI_RXPKT1H_ECC_ERR BIT(29)
108 # define DSI_RXPKT1H_COR_ERR BIT(28)
109 # define DSI_RXPKT1H_INCOMP_PKT BIT(25)
110 # define DSI_RXPKT1H_PKT_TYPE_LONG BIT(24)
111 /* Byte count if DSI_RXPKT1H_PKT_TYPE_LONG */
112 # define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
113 # define DSI_RXPKT1H_BC_PARAM_SHIFT 8
114 /* Short return bytes if !DSI_RXPKT1H_PKT_TYPE_LONG */
115 # define DSI_RXPKT1H_SHORT_1_MASK VC4_MASK(23, 16)
116 # define DSI_RXPKT1H_SHORT_1_SHIFT 16
117 # define DSI_RXPKT1H_SHORT_0_MASK VC4_MASK(15, 8)
118 # define DSI_RXPKT1H_SHORT_0_SHIFT 8
119 # define DSI_RXPKT1H_DT_LP_CMD_MASK VC4_MASK(7, 0)
120 # define DSI_RXPKT1H_DT_LP_CMD_SHIFT 0
122 #define DSI0_RXPKT2H 0x10 /* AKA RX2_PKTH */
123 #define DSI1_RXPKT2H 0x18
124 # define DSI_RXPKT1H_DET_ERR BIT(30)
125 # define DSI_RXPKT1H_ECC_ERR BIT(29)
126 # define DSI_RXPKT1H_COR_ERR BIT(28)
127 # define DSI_RXPKT1H_INCOMP_PKT BIT(25)
128 # define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
129 # define DSI_RXPKT1H_BC_PARAM_SHIFT 8
130 # define DSI_RXPKT1H_DT_MASK VC4_MASK(7, 0)
131 # define DSI_RXPKT1H_DT_SHIFT 0
133 #define DSI0_TXPKT_CMD_FIFO 0x14 /* AKA CMD_DATAF */
134 #define DSI1_TXPKT_CMD_FIFO 0x1c
136 #define DSI0_DISP0_CTRL 0x18
137 # define DSI_DISP0_PIX_CLK_DIV_MASK VC4_MASK(21, 13)
138 # define DSI_DISP0_PIX_CLK_DIV_SHIFT 13
139 # define DSI_DISP0_LP_STOP_CTRL_MASK VC4_MASK(12, 11)
140 # define DSI_DISP0_LP_STOP_CTRL_SHIFT 11
141 # define DSI_DISP0_LP_STOP_DISABLE 0
142 # define DSI_DISP0_LP_STOP_PERLINE 1
143 # define DSI_DISP0_LP_STOP_PERFRAME 2
145 /* Transmit RGB pixels and null packets only during HACTIVE, instead
146 * of going to LP-STOP.
148 # define DSI_DISP_HACTIVE_NULL BIT(10)
149 /* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
150 # define DSI_DISP_VBLP_CTRL BIT(9)
151 /* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
152 # define DSI_DISP_HFP_CTRL BIT(8)
153 /* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
154 # define DSI_DISP_HBP_CTRL BIT(7)
155 # define DSI_DISP0_CHANNEL_MASK VC4_MASK(6, 5)
156 # define DSI_DISP0_CHANNEL_SHIFT 5
157 /* Enables end events for HSYNC/VSYNC, not just start events. */
158 # define DSI_DISP0_ST_END BIT(4)
159 # define DSI_DISP0_PFORMAT_MASK VC4_MASK(3, 2)
160 # define DSI_DISP0_PFORMAT_SHIFT 2
161 # define DSI_PFORMAT_RGB565 0
162 # define DSI_PFORMAT_RGB666_PACKED 1
163 # define DSI_PFORMAT_RGB666 2
164 # define DSI_PFORMAT_RGB888 3
165 /* Default is VIDEO mode. */
166 # define DSI_DISP0_COMMAND_MODE BIT(1)
167 # define DSI_DISP0_ENABLE BIT(0)
169 #define DSI0_DISP1_CTRL 0x1c
170 #define DSI1_DISP1_CTRL 0x2c
171 /* Format of the data written to TXPKT_PIX_FIFO. */
172 # define DSI_DISP1_PFORMAT_MASK VC4_MASK(2, 1)
173 # define DSI_DISP1_PFORMAT_SHIFT 1
174 # define DSI_DISP1_PFORMAT_16BIT 0
175 # define DSI_DISP1_PFORMAT_24BIT 1
176 # define DSI_DISP1_PFORMAT_32BIT_LE 2
177 # define DSI_DISP1_PFORMAT_32BIT_BE 3
179 /* DISP1 is always command mode. */
180 # define DSI_DISP1_ENABLE BIT(0)
182 #define DSI0_TXPKT_PIX_FIFO 0x20 /* AKA PIX_FIFO */
184 #define DSI0_INT_STAT 0x24
185 #define DSI0_INT_EN 0x28
186 # define DSI0_INT_FIFO_ERR BIT(25)
187 # define DSI0_INT_CMDC_DONE_MASK VC4_MASK(24, 23)
188 # define DSI0_INT_CMDC_DONE_SHIFT 23
189 # define DSI0_INT_CMDC_DONE_NO_REPEAT 1
190 # define DSI0_INT_CMDC_DONE_REPEAT 3
191 # define DSI0_INT_PHY_DIR_RTF BIT(22)
192 # define DSI0_INT_PHY_D1_ULPS BIT(21)
193 # define DSI0_INT_PHY_D1_STOP BIT(20)
194 # define DSI0_INT_PHY_RXLPDT BIT(19)
195 # define DSI0_INT_PHY_RXTRIG BIT(18)
196 # define DSI0_INT_PHY_D0_ULPS BIT(17)
197 # define DSI0_INT_PHY_D0_LPDT BIT(16)
198 # define DSI0_INT_PHY_D0_FTR BIT(15)
199 # define DSI0_INT_PHY_D0_STOP BIT(14)
200 /* Signaled when the clock lane enters the given state. */
201 # define DSI0_INT_PHY_CLK_ULPS BIT(13)
202 # define DSI0_INT_PHY_CLK_HS BIT(12)
203 # define DSI0_INT_PHY_CLK_FTR BIT(11)
204 /* Signaled on timeouts */
205 # define DSI0_INT_PR_TO BIT(10)
206 # define DSI0_INT_TA_TO BIT(9)
207 # define DSI0_INT_LPRX_TO BIT(8)
208 # define DSI0_INT_HSTX_TO BIT(7)
209 /* Contention on a line when trying to drive the line low */
210 # define DSI0_INT_ERR_CONT_LP1 BIT(6)
211 # define DSI0_INT_ERR_CONT_LP0 BIT(5)
212 /* Control error: incorrect line state sequence on data lane 0. */
213 # define DSI0_INT_ERR_CONTROL BIT(4)
214 # define DSI0_INT_ERR_SYNC_ESC BIT(3)
215 # define DSI0_INT_RX2_PKT BIT(2)
216 # define DSI0_INT_RX1_PKT BIT(1)
217 # define DSI0_INT_CMD_PKT BIT(0)
219 #define DSI0_INTERRUPTS_ALWAYS_ENABLED (DSI0_INT_ERR_SYNC_ESC | \
220 DSI0_INT_ERR_CONTROL | \
221 DSI0_INT_ERR_CONT_LP0 | \
222 DSI0_INT_ERR_CONT_LP1 | \
228 # define DSI1_INT_PHY_D3_ULPS BIT(30)
229 # define DSI1_INT_PHY_D3_STOP BIT(29)
230 # define DSI1_INT_PHY_D2_ULPS BIT(28)
231 # define DSI1_INT_PHY_D2_STOP BIT(27)
232 # define DSI1_INT_PHY_D1_ULPS BIT(26)
233 # define DSI1_INT_PHY_D1_STOP BIT(25)
234 # define DSI1_INT_PHY_D0_ULPS BIT(24)
235 # define DSI1_INT_PHY_D0_STOP BIT(23)
236 # define DSI1_INT_FIFO_ERR BIT(22)
237 # define DSI1_INT_PHY_DIR_RTF BIT(21)
238 # define DSI1_INT_PHY_RXLPDT BIT(20)
239 # define DSI1_INT_PHY_RXTRIG BIT(19)
240 # define DSI1_INT_PHY_D0_LPDT BIT(18)
241 # define DSI1_INT_PHY_DIR_FTR BIT(17)
243 /* Signaled when the clock lane enters the given state. */
244 # define DSI1_INT_PHY_CLOCK_ULPS BIT(16)
245 # define DSI1_INT_PHY_CLOCK_HS BIT(15)
246 # define DSI1_INT_PHY_CLOCK_STOP BIT(14)
248 /* Signaled on timeouts */
249 # define DSI1_INT_PR_TO BIT(13)
250 # define DSI1_INT_TA_TO BIT(12)
251 # define DSI1_INT_LPRX_TO BIT(11)
252 # define DSI1_INT_HSTX_TO BIT(10)
254 /* Contention on a line when trying to drive the line low */
255 # define DSI1_INT_ERR_CONT_LP1 BIT(9)
256 # define DSI1_INT_ERR_CONT_LP0 BIT(8)
258 /* Control error: incorrect line state sequence on data lane 0. */
259 # define DSI1_INT_ERR_CONTROL BIT(7)
260 /* LPDT synchronization error (bits received not a multiple of 8. */
262 # define DSI1_INT_ERR_SYNC_ESC BIT(6)
263 /* Signaled after receiving an error packet from the display in
264 * response to a read.
266 # define DSI1_INT_RXPKT2 BIT(5)
267 /* Signaled after receiving a packet. The header and optional short
268 * response will be in RXPKT1H, and a long response will be in the
271 # define DSI1_INT_RXPKT1 BIT(4)
272 # define DSI1_INT_TXPKT2_DONE BIT(3)
273 # define DSI1_INT_TXPKT2_END BIT(2)
274 /* Signaled after all repeats of TXPKT1 are transferred. */
275 # define DSI1_INT_TXPKT1_DONE BIT(1)
276 /* Signaled after each TXPKT1 repeat is scheduled. */
277 # define DSI1_INT_TXPKT1_END BIT(0)
279 #define DSI1_INTERRUPTS_ALWAYS_ENABLED (DSI1_INT_ERR_SYNC_ESC | \
280 DSI1_INT_ERR_CONTROL | \
281 DSI1_INT_ERR_CONT_LP0 | \
282 DSI1_INT_ERR_CONT_LP1 | \
288 #define DSI0_STAT 0x2c
289 #define DSI0_HSTX_TO_CNT 0x30
290 #define DSI0_LPRX_TO_CNT 0x34
291 #define DSI0_TA_TO_CNT 0x38
292 #define DSI0_PR_TO_CNT 0x3c
293 #define DSI0_PHYC 0x40
294 # define DSI1_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(25, 20)
295 # define DSI1_PHYC_ESC_CLK_LPDT_SHIFT 20
296 # define DSI1_PHYC_HS_CLK_CONTINUOUS BIT(18)
297 # define DSI0_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(17, 12)
298 # define DSI0_PHYC_ESC_CLK_LPDT_SHIFT 12
299 # define DSI1_PHYC_CLANE_ULPS BIT(17)
300 # define DSI1_PHYC_CLANE_ENABLE BIT(16)
301 # define DSI_PHYC_DLANE3_ULPS BIT(13)
302 # define DSI_PHYC_DLANE3_ENABLE BIT(12)
303 # define DSI0_PHYC_HS_CLK_CONTINUOUS BIT(10)
304 # define DSI0_PHYC_CLANE_ULPS BIT(9)
305 # define DSI_PHYC_DLANE2_ULPS BIT(9)
306 # define DSI0_PHYC_CLANE_ENABLE BIT(8)
307 # define DSI_PHYC_DLANE2_ENABLE BIT(8)
308 # define DSI_PHYC_DLANE1_ULPS BIT(5)
309 # define DSI_PHYC_DLANE1_ENABLE BIT(4)
310 # define DSI_PHYC_DLANE0_FORCE_STOP BIT(2)
311 # define DSI_PHYC_DLANE0_ULPS BIT(1)
312 # define DSI_PHYC_DLANE0_ENABLE BIT(0)
314 #define DSI0_HS_CLT0 0x44
315 #define DSI0_HS_CLT1 0x48
316 #define DSI0_HS_CLT2 0x4c
317 #define DSI0_HS_DLT3 0x50
318 #define DSI0_HS_DLT4 0x54
319 #define DSI0_HS_DLT5 0x58
320 #define DSI0_HS_DLT6 0x5c
321 #define DSI0_HS_DLT7 0x60
323 #define DSI0_PHY_AFEC0 0x64
324 # define DSI0_PHY_AFEC0_DDR2CLK_EN BIT(26)
325 # define DSI0_PHY_AFEC0_DDRCLK_EN BIT(25)
326 # define DSI0_PHY_AFEC0_LATCH_ULPS BIT(24)
327 # define DSI1_PHY_AFEC0_IDR_DLANE3_MASK VC4_MASK(31, 29)
328 # define DSI1_PHY_AFEC0_IDR_DLANE3_SHIFT 29
329 # define DSI1_PHY_AFEC0_IDR_DLANE2_MASK VC4_MASK(28, 26)
330 # define DSI1_PHY_AFEC0_IDR_DLANE2_SHIFT 26
331 # define DSI1_PHY_AFEC0_IDR_DLANE1_MASK VC4_MASK(27, 23)
332 # define DSI1_PHY_AFEC0_IDR_DLANE1_SHIFT 23
333 # define DSI1_PHY_AFEC0_IDR_DLANE0_MASK VC4_MASK(22, 20)
334 # define DSI1_PHY_AFEC0_IDR_DLANE0_SHIFT 20
335 # define DSI1_PHY_AFEC0_IDR_CLANE_MASK VC4_MASK(19, 17)
336 # define DSI1_PHY_AFEC0_IDR_CLANE_SHIFT 17
337 # define DSI0_PHY_AFEC0_ACTRL_DLANE1_MASK VC4_MASK(23, 20)
338 # define DSI0_PHY_AFEC0_ACTRL_DLANE1_SHIFT 20
339 # define DSI0_PHY_AFEC0_ACTRL_DLANE0_MASK VC4_MASK(19, 16)
340 # define DSI0_PHY_AFEC0_ACTRL_DLANE0_SHIFT 16
341 # define DSI0_PHY_AFEC0_ACTRL_CLANE_MASK VC4_MASK(15, 12)
342 # define DSI0_PHY_AFEC0_ACTRL_CLANE_SHIFT 12
343 # define DSI1_PHY_AFEC0_DDR2CLK_EN BIT(16)
344 # define DSI1_PHY_AFEC0_DDRCLK_EN BIT(15)
345 # define DSI1_PHY_AFEC0_LATCH_ULPS BIT(14)
346 # define DSI1_PHY_AFEC0_RESET BIT(13)
347 # define DSI1_PHY_AFEC0_PD BIT(12)
348 # define DSI0_PHY_AFEC0_RESET BIT(11)
349 # define DSI1_PHY_AFEC0_PD_BG BIT(11)
350 # define DSI0_PHY_AFEC0_PD BIT(10)
351 # define DSI1_PHY_AFEC0_PD_DLANE1 BIT(10)
352 # define DSI0_PHY_AFEC0_PD_BG BIT(9)
353 # define DSI1_PHY_AFEC0_PD_DLANE2 BIT(9)
354 # define DSI0_PHY_AFEC0_PD_DLANE1 BIT(8)
355 # define DSI1_PHY_AFEC0_PD_DLANE3 BIT(8)
356 # define DSI_PHY_AFEC0_PTATADJ_MASK VC4_MASK(7, 4)
357 # define DSI_PHY_AFEC0_PTATADJ_SHIFT 4
358 # define DSI_PHY_AFEC0_CTATADJ_MASK VC4_MASK(3, 0)
359 # define DSI_PHY_AFEC0_CTATADJ_SHIFT 0
361 #define DSI0_PHY_AFEC1 0x68
362 # define DSI0_PHY_AFEC1_IDR_DLANE1_MASK VC4_MASK(10, 8)
363 # define DSI0_PHY_AFEC1_IDR_DLANE1_SHIFT 8
364 # define DSI0_PHY_AFEC1_IDR_DLANE0_MASK VC4_MASK(6, 4)
365 # define DSI0_PHY_AFEC1_IDR_DLANE0_SHIFT 4
366 # define DSI0_PHY_AFEC1_IDR_CLANE_MASK VC4_MASK(2, 0)
367 # define DSI0_PHY_AFEC1_IDR_CLANE_SHIFT 0
369 #define DSI0_TST_SEL 0x6c
370 #define DSI0_TST_MON 0x70
372 # define DSI_ID_VALUE 0x00647369
374 #define DSI1_CTRL 0x00
375 # define DSI_CTRL_HS_CLKC_MASK VC4_MASK(15, 14)
376 # define DSI_CTRL_HS_CLKC_SHIFT 14
377 # define DSI_CTRL_HS_CLKC_BYTE 0
378 # define DSI_CTRL_HS_CLKC_DDR2 1
379 # define DSI_CTRL_HS_CLKC_DDR 2
381 # define DSI_CTRL_RX_LPDT_EOT_DISABLE BIT(13)
382 # define DSI_CTRL_LPDT_EOT_DISABLE BIT(12)
383 # define DSI_CTRL_HSDT_EOT_DISABLE BIT(11)
384 # define DSI_CTRL_SOFT_RESET_CFG BIT(10)
385 # define DSI_CTRL_CAL_BYTE BIT(9)
386 # define DSI_CTRL_INV_BYTE BIT(8)
387 # define DSI_CTRL_CLR_LDF BIT(7)
388 # define DSI0_CTRL_CLR_PBCF BIT(6)
389 # define DSI1_CTRL_CLR_RXF BIT(6)
390 # define DSI0_CTRL_CLR_CPBCF BIT(5)
391 # define DSI1_CTRL_CLR_PDF BIT(5)
392 # define DSI0_CTRL_CLR_PDF BIT(4)
393 # define DSI1_CTRL_CLR_CDF BIT(4)
394 # define DSI0_CTRL_CLR_CDF BIT(3)
395 # define DSI0_CTRL_CTRL2 BIT(2)
396 # define DSI1_CTRL_DISABLE_DISP_CRCC BIT(2)
397 # define DSI0_CTRL_CTRL1 BIT(1)
398 # define DSI1_CTRL_DISABLE_DISP_ECCC BIT(1)
399 # define DSI0_CTRL_CTRL0 BIT(0)
400 # define DSI1_CTRL_EN BIT(0)
401 # define DSI0_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
402 DSI0_CTRL_CLR_PBCF | \
403 DSI0_CTRL_CLR_CPBCF | \
404 DSI0_CTRL_CLR_PDF | \
406 # define DSI1_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
407 DSI1_CTRL_CLR_RXF | \
408 DSI1_CTRL_CLR_PDF | \
411 #define DSI1_TXPKT2C 0x0c
412 #define DSI1_TXPKT2H 0x10
413 #define DSI1_TXPKT_PIX_FIFO 0x20
414 #define DSI1_RXPKT_FIFO 0x24
415 #define DSI1_DISP0_CTRL 0x28
416 #define DSI1_INT_STAT 0x30
417 #define DSI1_INT_EN 0x34
418 /* State reporting bits. These mostly behave like INT_STAT, where
419 * writing a 1 clears the bit.
421 #define DSI1_STAT 0x38
422 # define DSI1_STAT_PHY_D3_ULPS BIT(31)
423 # define DSI1_STAT_PHY_D3_STOP BIT(30)
424 # define DSI1_STAT_PHY_D2_ULPS BIT(29)
425 # define DSI1_STAT_PHY_D2_STOP BIT(28)
426 # define DSI1_STAT_PHY_D1_ULPS BIT(27)
427 # define DSI1_STAT_PHY_D1_STOP BIT(26)
428 # define DSI1_STAT_PHY_D0_ULPS BIT(25)
429 # define DSI1_STAT_PHY_D0_STOP BIT(24)
430 # define DSI1_STAT_FIFO_ERR BIT(23)
431 # define DSI1_STAT_PHY_RXLPDT BIT(22)
432 # define DSI1_STAT_PHY_RXTRIG BIT(21)
433 # define DSI1_STAT_PHY_D0_LPDT BIT(20)
434 /* Set when in forward direction */
435 # define DSI1_STAT_PHY_DIR BIT(19)
436 # define DSI1_STAT_PHY_CLOCK_ULPS BIT(18)
437 # define DSI1_STAT_PHY_CLOCK_HS BIT(17)
438 # define DSI1_STAT_PHY_CLOCK_STOP BIT(16)
439 # define DSI1_STAT_PR_TO BIT(15)
440 # define DSI1_STAT_TA_TO BIT(14)
441 # define DSI1_STAT_LPRX_TO BIT(13)
442 # define DSI1_STAT_HSTX_TO BIT(12)
443 # define DSI1_STAT_ERR_CONT_LP1 BIT(11)
444 # define DSI1_STAT_ERR_CONT_LP0 BIT(10)
445 # define DSI1_STAT_ERR_CONTROL BIT(9)
446 # define DSI1_STAT_ERR_SYNC_ESC BIT(8)
447 # define DSI1_STAT_RXPKT2 BIT(7)
448 # define DSI1_STAT_RXPKT1 BIT(6)
449 # define DSI1_STAT_TXPKT2_BUSY BIT(5)
450 # define DSI1_STAT_TXPKT2_DONE BIT(4)
451 # define DSI1_STAT_TXPKT2_END BIT(3)
452 # define DSI1_STAT_TXPKT1_BUSY BIT(2)
453 # define DSI1_STAT_TXPKT1_DONE BIT(1)
454 # define DSI1_STAT_TXPKT1_END BIT(0)
456 #define DSI1_HSTX_TO_CNT 0x3c
457 #define DSI1_LPRX_TO_CNT 0x40
458 #define DSI1_TA_TO_CNT 0x44
459 #define DSI1_PR_TO_CNT 0x48
460 #define DSI1_PHYC 0x4c
462 #define DSI1_HS_CLT0 0x50
463 # define DSI_HS_CLT0_CZERO_MASK VC4_MASK(26, 18)
464 # define DSI_HS_CLT0_CZERO_SHIFT 18
465 # define DSI_HS_CLT0_CPRE_MASK VC4_MASK(17, 9)
466 # define DSI_HS_CLT0_CPRE_SHIFT 9
467 # define DSI_HS_CLT0_CPREP_MASK VC4_MASK(8, 0)
468 # define DSI_HS_CLT0_CPREP_SHIFT 0
470 #define DSI1_HS_CLT1 0x54
471 # define DSI_HS_CLT1_CTRAIL_MASK VC4_MASK(17, 9)
472 # define DSI_HS_CLT1_CTRAIL_SHIFT 9
473 # define DSI_HS_CLT1_CPOST_MASK VC4_MASK(8, 0)
474 # define DSI_HS_CLT1_CPOST_SHIFT 0
476 #define DSI1_HS_CLT2 0x58
477 # define DSI_HS_CLT2_WUP_MASK VC4_MASK(23, 0)
478 # define DSI_HS_CLT2_WUP_SHIFT 0
480 #define DSI1_HS_DLT3 0x5c
481 # define DSI_HS_DLT3_EXIT_MASK VC4_MASK(26, 18)
482 # define DSI_HS_DLT3_EXIT_SHIFT 18
483 # define DSI_HS_DLT3_ZERO_MASK VC4_MASK(17, 9)
484 # define DSI_HS_DLT3_ZERO_SHIFT 9
485 # define DSI_HS_DLT3_PRE_MASK VC4_MASK(8, 0)
486 # define DSI_HS_DLT3_PRE_SHIFT 0
488 #define DSI1_HS_DLT4 0x60
489 # define DSI_HS_DLT4_ANLAT_MASK VC4_MASK(22, 18)
490 # define DSI_HS_DLT4_ANLAT_SHIFT 18
491 # define DSI_HS_DLT4_TRAIL_MASK VC4_MASK(17, 9)
492 # define DSI_HS_DLT4_TRAIL_SHIFT 9
493 # define DSI_HS_DLT4_LPX_MASK VC4_MASK(8, 0)
494 # define DSI_HS_DLT4_LPX_SHIFT 0
496 #define DSI1_HS_DLT5 0x64
497 # define DSI_HS_DLT5_INIT_MASK VC4_MASK(23, 0)
498 # define DSI_HS_DLT5_INIT_SHIFT 0
500 #define DSI1_HS_DLT6 0x68
501 # define DSI_HS_DLT6_TA_GET_MASK VC4_MASK(31, 24)
502 # define DSI_HS_DLT6_TA_GET_SHIFT 24
503 # define DSI_HS_DLT6_TA_SURE_MASK VC4_MASK(23, 16)
504 # define DSI_HS_DLT6_TA_SURE_SHIFT 16
505 # define DSI_HS_DLT6_TA_GO_MASK VC4_MASK(15, 8)
506 # define DSI_HS_DLT6_TA_GO_SHIFT 8
507 # define DSI_HS_DLT6_LP_LPX_MASK VC4_MASK(7, 0)
508 # define DSI_HS_DLT6_LP_LPX_SHIFT 0
510 #define DSI1_HS_DLT7 0x6c
511 # define DSI_HS_DLT7_LP_WUP_MASK VC4_MASK(23, 0)
512 # define DSI_HS_DLT7_LP_WUP_SHIFT 0
514 #define DSI1_PHY_AFEC0 0x70
516 #define DSI1_PHY_AFEC1 0x74
517 # define DSI1_PHY_AFEC1_ACTRL_DLANE3_MASK VC4_MASK(19, 16)
518 # define DSI1_PHY_AFEC1_ACTRL_DLANE3_SHIFT 16
519 # define DSI1_PHY_AFEC1_ACTRL_DLANE2_MASK VC4_MASK(15, 12)
520 # define DSI1_PHY_AFEC1_ACTRL_DLANE2_SHIFT 12
521 # define DSI1_PHY_AFEC1_ACTRL_DLANE1_MASK VC4_MASK(11, 8)
522 # define DSI1_PHY_AFEC1_ACTRL_DLANE1_SHIFT 8
523 # define DSI1_PHY_AFEC1_ACTRL_DLANE0_MASK VC4_MASK(7, 4)
524 # define DSI1_PHY_AFEC1_ACTRL_DLANE0_SHIFT 4
525 # define DSI1_PHY_AFEC1_ACTRL_CLANE_MASK VC4_MASK(3, 0)
526 # define DSI1_PHY_AFEC1_ACTRL_CLANE_SHIFT 0
528 #define DSI1_TST_SEL 0x78
529 #define DSI1_TST_MON 0x7c
530 #define DSI1_PHY_TST1 0x80
531 #define DSI1_PHY_TST2 0x84
532 #define DSI1_PHY_FIFO_STAT 0x88
533 /* Actually, all registers in the range that aren't otherwise claimed
534 * will return the ID.
538 struct vc4_dsi_variant {
539 /* Whether we're on bcm2835's DSI0 or DSI1. */
542 bool broken_axi_workaround;
544 const char *debugfs_name;
545 const struct debugfs_reg32 *regs;
550 /* General DSI hardware state. */
552 struct vc4_encoder encoder;
553 struct mipi_dsi_host dsi_host;
557 struct platform_device *pdev;
559 struct drm_bridge *out_bridge;
560 struct drm_bridge bridge;
564 struct dma_chan *reg_dma_chan;
565 dma_addr_t reg_dma_paddr;
567 dma_addr_t reg_paddr;
569 const struct vc4_dsi_variant *variant;
571 /* DSI channel for the panel we're connected to. */
578 /* Input clock from CPRMAN to the digital PHY, for the DSI
581 struct clk *escape_clock;
583 /* Input clock to the analog PHY, used to generate the DSI bit
586 struct clk *pll_phy_clock;
588 /* HS Clocks generated within the DSI analog PHY. */
589 struct clk_fixed_factor phy_clocks[3];
591 struct clk_hw_onecell_data *clk_onecell;
593 /* Pixel clock output to the pixelvalve, generated from the HS
596 struct clk *pixel_clock;
598 struct completion xfer_completion;
601 struct debugfs_regset32 regset;
604 #define host_to_dsi(host) container_of(host, struct vc4_dsi, dsi_host)
606 static inline struct vc4_dsi *
607 to_vc4_dsi(struct drm_encoder *encoder)
609 return container_of(encoder, struct vc4_dsi, encoder.base);
613 dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val)
615 struct dma_chan *chan = dsi->reg_dma_chan;
616 struct dma_async_tx_descriptor *tx;
620 /* DSI0 should be able to write normally. */
622 writel(val, dsi->regs + offset);
626 *dsi->reg_dma_mem = val;
628 tx = chan->device->device_prep_dma_memcpy(chan,
629 dsi->reg_paddr + offset,
633 DRM_ERROR("Failed to set up DMA register write\n");
637 cookie = tx->tx_submit(tx);
638 ret = dma_submit_error(cookie);
640 DRM_ERROR("Failed to submit DMA: %d\n", ret);
643 ret = dma_sync_wait(chan, cookie);
645 DRM_ERROR("Failed to wait for DMA: %d\n", ret);
648 #define DSI_READ(offset) readl(dsi->regs + (offset))
649 #define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val)
650 #define DSI_PORT_READ(offset) \
651 DSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset)
652 #define DSI_PORT_WRITE(offset, val) \
653 DSI_WRITE(dsi->variant->port ? DSI1_##offset : DSI0_##offset, val)
654 #define DSI_PORT_BIT(bit) (dsi->variant->port ? DSI1_##bit : DSI0_##bit)
656 static inline struct vc4_dsi *
657 bridge_to_vc4_dsi(struct drm_bridge *bridge)
659 return container_of(bridge, struct vc4_dsi, bridge);
662 static const struct debugfs_reg32 dsi0_regs[] = {
663 VC4_REG32(DSI0_CTRL),
664 VC4_REG32(DSI0_STAT),
665 VC4_REG32(DSI0_HSTX_TO_CNT),
666 VC4_REG32(DSI0_LPRX_TO_CNT),
667 VC4_REG32(DSI0_TA_TO_CNT),
668 VC4_REG32(DSI0_PR_TO_CNT),
669 VC4_REG32(DSI0_DISP0_CTRL),
670 VC4_REG32(DSI0_DISP1_CTRL),
671 VC4_REG32(DSI0_INT_STAT),
672 VC4_REG32(DSI0_INT_EN),
673 VC4_REG32(DSI0_PHYC),
674 VC4_REG32(DSI0_HS_CLT0),
675 VC4_REG32(DSI0_HS_CLT1),
676 VC4_REG32(DSI0_HS_CLT2),
677 VC4_REG32(DSI0_HS_DLT3),
678 VC4_REG32(DSI0_HS_DLT4),
679 VC4_REG32(DSI0_HS_DLT5),
680 VC4_REG32(DSI0_HS_DLT6),
681 VC4_REG32(DSI0_HS_DLT7),
682 VC4_REG32(DSI0_PHY_AFEC0),
683 VC4_REG32(DSI0_PHY_AFEC1),
687 static const struct debugfs_reg32 dsi1_regs[] = {
688 VC4_REG32(DSI1_CTRL),
689 VC4_REG32(DSI1_STAT),
690 VC4_REG32(DSI1_HSTX_TO_CNT),
691 VC4_REG32(DSI1_LPRX_TO_CNT),
692 VC4_REG32(DSI1_TA_TO_CNT),
693 VC4_REG32(DSI1_PR_TO_CNT),
694 VC4_REG32(DSI1_DISP0_CTRL),
695 VC4_REG32(DSI1_DISP1_CTRL),
696 VC4_REG32(DSI1_INT_STAT),
697 VC4_REG32(DSI1_INT_EN),
698 VC4_REG32(DSI1_PHYC),
699 VC4_REG32(DSI1_HS_CLT0),
700 VC4_REG32(DSI1_HS_CLT1),
701 VC4_REG32(DSI1_HS_CLT2),
702 VC4_REG32(DSI1_HS_DLT3),
703 VC4_REG32(DSI1_HS_DLT4),
704 VC4_REG32(DSI1_HS_DLT5),
705 VC4_REG32(DSI1_HS_DLT6),
706 VC4_REG32(DSI1_HS_DLT7),
707 VC4_REG32(DSI1_PHY_AFEC0),
708 VC4_REG32(DSI1_PHY_AFEC1),
712 static void vc4_dsi_latch_ulps(struct vc4_dsi *dsi, bool latch)
714 u32 afec0 = DSI_PORT_READ(PHY_AFEC0);
717 afec0 |= DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
719 afec0 &= ~DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
721 DSI_PORT_WRITE(PHY_AFEC0, afec0);
724 /* Enters or exits Ultra Low Power State. */
725 static void vc4_dsi_ulps(struct vc4_dsi *dsi, bool ulps)
727 bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS;
728 u32 phyc_ulps = ((non_continuous ? DSI_PORT_BIT(PHYC_CLANE_ULPS) : 0) |
729 DSI_PHYC_DLANE0_ULPS |
730 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) |
731 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) |
732 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0));
733 u32 stat_ulps = ((non_continuous ? DSI1_STAT_PHY_CLOCK_ULPS : 0) |
734 DSI1_STAT_PHY_D0_ULPS |
735 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) |
736 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) |
737 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0));
738 u32 stat_stop = ((non_continuous ? DSI1_STAT_PHY_CLOCK_STOP : 0) |
739 DSI1_STAT_PHY_D0_STOP |
740 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) |
741 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) |
742 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0));
744 bool ulps_currently_enabled = (DSI_PORT_READ(PHY_AFEC0) &
745 DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS));
747 if (ulps == ulps_currently_enabled)
750 DSI_PORT_WRITE(STAT, stat_ulps);
751 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) | phyc_ulps);
752 ret = wait_for((DSI_PORT_READ(STAT) & stat_ulps) == stat_ulps, 200);
754 dev_warn(&dsi->pdev->dev,
755 "Timeout waiting for DSI ULPS entry: STAT 0x%08x",
756 DSI_PORT_READ(STAT));
757 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
758 vc4_dsi_latch_ulps(dsi, false);
762 /* The DSI module can't be disabled while the module is
763 * generating ULPS state. So, to be able to disable the
764 * module, we have the AFE latch the ULPS state and continue
765 * on to having the module enter STOP.
767 vc4_dsi_latch_ulps(dsi, ulps);
769 DSI_PORT_WRITE(STAT, stat_stop);
770 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
771 ret = wait_for((DSI_PORT_READ(STAT) & stat_stop) == stat_stop, 200);
773 dev_warn(&dsi->pdev->dev,
774 "Timeout waiting for DSI STOP entry: STAT 0x%08x",
775 DSI_PORT_READ(STAT));
776 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
782 dsi_hs_timing(u32 ui_ns, u32 ns, u32 ui)
784 /* The HS timings have to be rounded up to a multiple of 8
785 * because we're using the byte clock.
787 return roundup(ui + DIV_ROUND_UP(ns, ui_ns), 8);
790 /* ESC always runs at 100Mhz. */
791 #define ESC_TIME_NS 10
794 dsi_esc_timing(u32 ns)
796 return DIV_ROUND_UP(ns, ESC_TIME_NS);
799 static void vc4_dsi_bridge_disable(struct drm_bridge *bridge,
800 struct drm_bridge_state *state)
802 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
805 disp0_ctrl = DSI_PORT_READ(DISP0_CTRL);
806 disp0_ctrl &= ~DSI_DISP0_ENABLE;
807 DSI_PORT_WRITE(DISP0_CTRL, disp0_ctrl);
810 static void vc4_dsi_bridge_post_disable(struct drm_bridge *bridge,
811 struct drm_bridge_state *state)
813 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
814 struct device *dev = &dsi->pdev->dev;
816 clk_disable_unprepare(dsi->pll_phy_clock);
817 clk_disable_unprepare(dsi->escape_clock);
818 clk_disable_unprepare(dsi->pixel_clock);
823 /* Extends the mode's blank intervals to handle BCM2835's integer-only
826 * On 2835, PLLD is set to 2Ghz, and may not be changed by the display
827 * driver since most peripherals are hanging off of the PLLD_PER
828 * divider. PLLD_DSI1, which drives our DSI bit clock (and therefore
829 * the pixel clock), only has an integer divider off of DSI.
831 * To get our panel mode to refresh at the expected 60Hz, we need to
832 * extend the horizontal blank time. This means we drive a
833 * higher-than-expected clock rate to the panel, but that's what the
836 static bool vc4_dsi_bridge_mode_fixup(struct drm_bridge *bridge,
837 const struct drm_display_mode *mode,
838 struct drm_display_mode *adjusted_mode)
840 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
841 struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock);
842 unsigned long parent_rate = clk_get_rate(phy_parent);
843 unsigned long pixel_clock_hz = mode->clock * 1000;
844 unsigned long pll_clock = pixel_clock_hz * dsi->divider;
847 /* Find what divider gets us a faster clock than the requested
850 for (divider = 1; divider < 255; divider++) {
851 if (parent_rate / (divider + 1) < pll_clock)
855 /* Now that we've picked a PLL divider, calculate back to its
858 pll_clock = parent_rate / divider;
859 pixel_clock_hz = pll_clock / dsi->divider;
861 adjusted_mode->clock = pixel_clock_hz / 1000;
863 /* Given the new pixel clock, adjust HFP to keep vrefresh the same. */
864 adjusted_mode->htotal = adjusted_mode->clock * mode->htotal /
866 adjusted_mode->hsync_end += adjusted_mode->htotal - mode->htotal;
867 adjusted_mode->hsync_start += adjusted_mode->htotal - mode->htotal;
872 static void vc4_dsi_bridge_pre_enable(struct drm_bridge *bridge,
873 struct drm_bridge_state *old_state)
875 struct drm_atomic_state *state = old_state->base.state;
876 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
877 const struct drm_crtc_state *crtc_state;
878 struct device *dev = &dsi->pdev->dev;
879 const struct drm_display_mode *mode;
880 struct drm_connector *connector;
881 bool debug_dump_regs = false;
882 unsigned long hs_clock;
883 struct drm_crtc *crtc;
885 /* Minimum LP state duration in escape clock cycles. */
886 u32 lpx = dsi_esc_timing(60);
887 unsigned long pixel_clock_hz;
888 unsigned long dsip_clock;
889 unsigned long phy_clock;
892 ret = pm_runtime_resume_and_get(dev);
894 DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->variant->port);
898 if (debug_dump_regs) {
899 struct drm_printer p = drm_info_printer(&dsi->pdev->dev);
900 dev_info(&dsi->pdev->dev, "DSI regs before:\n");
901 drm_print_regset32(&p, &dsi->regset);
905 * Retrieve the CRTC adjusted mode. This requires a little dance to go
906 * from the bridge to the encoder, to the connector and to the CRTC.
908 connector = drm_atomic_get_new_connector_for_encoder(state,
910 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
911 crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
912 mode = &crtc_state->adjusted_mode;
914 pixel_clock_hz = mode->clock * 1000;
916 /* Round up the clk_set_rate() request slightly, since
917 * PLLD_DSI1 is an integer divider and its rate selection will
920 phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
921 ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
923 dev_err(&dsi->pdev->dev,
924 "Failed to set phy clock to %ld: %d\n", phy_clock, ret);
927 /* Reset the DSI and all its fifos. */
929 DSI_CTRL_SOFT_RESET_CFG |
930 DSI_PORT_BIT(CTRL_RESET_FIFOS));
933 DSI_CTRL_HSDT_EOT_DISABLE |
934 DSI_CTRL_RX_LPDT_EOT_DISABLE);
936 /* Clear all stat bits so we see what has happened during enable. */
937 DSI_PORT_WRITE(STAT, DSI_PORT_READ(STAT));
939 /* Set AFE CTR00/CTR1 to release powerdown of analog. */
940 if (dsi->variant->port == 0) {
941 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
942 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ));
945 afec0 |= DSI0_PHY_AFEC0_PD_DLANE1;
947 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO))
948 afec0 |= DSI0_PHY_AFEC0_RESET;
950 DSI_PORT_WRITE(PHY_AFEC0, afec0);
952 /* AFEC reset hold time */
955 DSI_PORT_WRITE(PHY_AFEC1,
956 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) |
957 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) |
958 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE));
960 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
961 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) |
962 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) |
963 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) |
964 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1) |
965 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE2) |
966 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE3));
969 afec0 |= DSI1_PHY_AFEC0_PD_DLANE3;
971 afec0 |= DSI1_PHY_AFEC0_PD_DLANE2;
973 afec0 |= DSI1_PHY_AFEC0_PD_DLANE1;
975 afec0 |= DSI1_PHY_AFEC0_RESET;
977 DSI_PORT_WRITE(PHY_AFEC0, afec0);
979 DSI_PORT_WRITE(PHY_AFEC1, 0);
981 /* AFEC reset hold time */
985 ret = clk_prepare_enable(dsi->escape_clock);
987 DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret);
991 ret = clk_prepare_enable(dsi->pll_phy_clock);
993 DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret);
997 hs_clock = clk_get_rate(dsi->pll_phy_clock);
999 /* Yes, we set the DSI0P/DSI1P pixel clock to the byte rate,
1000 * not the pixel clock rate. DSIxP take from the APHY's byte,
1001 * DDR2, or DDR4 clock (we use byte) and feed into the PV at
1002 * that rate. Separately, a value derived from PIX_CLK_DIV
1003 * and HS_CLKC is fed into the PV to divide down to the actual
1004 * pixel clock for pushing pixels into DSI.
1006 dsip_clock = phy_clock / 8;
1007 ret = clk_set_rate(dsi->pixel_clock, dsip_clock);
1009 dev_err(dev, "Failed to set pixel clock to %ldHz: %d\n",
1013 ret = clk_prepare_enable(dsi->pixel_clock);
1015 DRM_ERROR("Failed to turn on DSI pixel clock: %d\n", ret);
1019 /* How many ns one DSI unit interval is. Note that the clock
1020 * is DDR, so there's an extra divide by 2.
1022 ui_ns = DIV_ROUND_UP(500000000, hs_clock);
1024 DSI_PORT_WRITE(HS_CLT0,
1025 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 262, 0),
1026 DSI_HS_CLT0_CZERO) |
1027 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 0, 8),
1029 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 38, 0),
1030 DSI_HS_CLT0_CPREP));
1032 DSI_PORT_WRITE(HS_CLT1,
1033 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 0),
1034 DSI_HS_CLT1_CTRAIL) |
1035 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 52),
1036 DSI_HS_CLT1_CPOST));
1038 DSI_PORT_WRITE(HS_CLT2,
1039 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000000, 0),
1042 DSI_PORT_WRITE(HS_DLT3,
1043 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 100, 0),
1045 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 105, 6),
1047 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 40, 4),
1050 DSI_PORT_WRITE(HS_DLT4,
1051 VC4_SET_FIELD(dsi_hs_timing(ui_ns, lpx * ESC_TIME_NS, 0),
1053 VC4_SET_FIELD(max(dsi_hs_timing(ui_ns, 0, 8),
1054 dsi_hs_timing(ui_ns, 60, 4)),
1055 DSI_HS_DLT4_TRAIL) |
1056 VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT));
1058 /* T_INIT is how long STOP is driven after power-up to
1059 * indicate to the slave (also coming out of power-up) that
1060 * master init is complete, and should be greater than the
1061 * maximum of two value: T_INIT,MASTER and T_INIT,SLAVE. The
1062 * D-PHY spec gives a minimum 100us for T_INIT,MASTER and
1063 * T_INIT,SLAVE, while allowing protocols on top of it to give
1064 * greater minimums. The vc4 firmware uses an extremely
1065 * conservative 5ms, and we maintain that here.
1067 DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns,
1068 5 * 1000 * 1000, 0),
1071 DSI_PORT_WRITE(HS_DLT6,
1072 VC4_SET_FIELD(lpx * 5, DSI_HS_DLT6_TA_GET) |
1073 VC4_SET_FIELD(lpx, DSI_HS_DLT6_TA_SURE) |
1074 VC4_SET_FIELD(lpx * 4, DSI_HS_DLT6_TA_GO) |
1075 VC4_SET_FIELD(lpx, DSI_HS_DLT6_LP_LPX));
1077 DSI_PORT_WRITE(HS_DLT7,
1078 VC4_SET_FIELD(dsi_esc_timing(1000000),
1079 DSI_HS_DLT7_LP_WUP));
1081 DSI_PORT_WRITE(PHYC,
1082 DSI_PHYC_DLANE0_ENABLE |
1083 (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) |
1084 (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) |
1085 (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) |
1086 DSI_PORT_BIT(PHYC_CLANE_ENABLE) |
1087 ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ?
1088 0 : DSI_PORT_BIT(PHYC_HS_CLK_CONTINUOUS)) |
1089 (dsi->variant->port == 0 ?
1090 VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) :
1091 VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT)));
1093 DSI_PORT_WRITE(CTRL,
1094 DSI_PORT_READ(CTRL) |
1097 /* HS timeout in HS clock cycles: disabled. */
1098 DSI_PORT_WRITE(HSTX_TO_CNT, 0);
1099 /* LP receive timeout in HS clocks. */
1100 DSI_PORT_WRITE(LPRX_TO_CNT, 0xffffff);
1101 /* Bus turnaround timeout */
1102 DSI_PORT_WRITE(TA_TO_CNT, 100000);
1103 /* Display reset sequence timeout */
1104 DSI_PORT_WRITE(PR_TO_CNT, 100000);
1106 /* Set up DISP1 for transferring long command payloads through
1109 DSI_PORT_WRITE(DISP1_CTRL,
1110 VC4_SET_FIELD(DSI_DISP1_PFORMAT_32BIT_LE,
1111 DSI_DISP1_PFORMAT) |
1114 /* Ungate the block. */
1115 if (dsi->variant->port == 0)
1116 DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0);
1118 DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN);
1120 /* Bring AFE out of reset. */
1121 DSI_PORT_WRITE(PHY_AFEC0,
1122 DSI_PORT_READ(PHY_AFEC0) &
1123 ~DSI_PORT_BIT(PHY_AFEC0_RESET));
1125 vc4_dsi_ulps(dsi, false);
1127 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
1128 DSI_PORT_WRITE(DISP0_CTRL,
1129 VC4_SET_FIELD(dsi->divider,
1130 DSI_DISP0_PIX_CLK_DIV) |
1131 VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) |
1132 VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME,
1133 DSI_DISP0_LP_STOP_CTRL) |
1136 DSI_PORT_WRITE(DISP0_CTRL,
1137 DSI_DISP0_COMMAND_MODE);
1141 static void vc4_dsi_bridge_enable(struct drm_bridge *bridge,
1142 struct drm_bridge_state *old_state)
1144 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
1145 bool debug_dump_regs = false;
1148 disp0_ctrl = DSI_PORT_READ(DISP0_CTRL);
1149 disp0_ctrl |= DSI_DISP0_ENABLE;
1150 DSI_PORT_WRITE(DISP0_CTRL, disp0_ctrl);
1152 if (debug_dump_regs) {
1153 struct drm_printer p = drm_info_printer(&dsi->pdev->dev);
1154 dev_info(&dsi->pdev->dev, "DSI regs after:\n");
1155 drm_print_regset32(&p, &dsi->regset);
1159 static int vc4_dsi_bridge_attach(struct drm_bridge *bridge,
1160 enum drm_bridge_attach_flags flags)
1162 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
1164 /* Attach the panel or bridge to the dsi bridge */
1165 return drm_bridge_attach(bridge->encoder, dsi->out_bridge,
1166 &dsi->bridge, flags);
1169 static ssize_t vc4_dsi_host_transfer(struct mipi_dsi_host *host,
1170 const struct mipi_dsi_msg *msg)
1172 struct vc4_dsi *dsi = host_to_dsi(host);
1173 struct mipi_dsi_packet packet;
1174 u32 pkth = 0, pktc = 0;
1176 bool is_long = mipi_dsi_packet_format_is_long(msg->type);
1177 u32 cmd_fifo_len = 0, pix_fifo_len = 0;
1179 mipi_dsi_create_packet(&packet, msg);
1181 pkth |= VC4_SET_FIELD(packet.header[0], DSI_TXPKT1H_BC_DT);
1182 pkth |= VC4_SET_FIELD(packet.header[1] |
1183 (packet.header[2] << 8),
1184 DSI_TXPKT1H_BC_PARAM);
1186 /* Divide data across the various FIFOs we have available.
1187 * The command FIFO takes byte-oriented data, but is of
1188 * limited size. The pixel FIFO (never actually used for
1189 * pixel data in reality) is word oriented, and substantially
1190 * larger. So, we use the pixel FIFO for most of the data,
1191 * sending the residual bytes in the command FIFO at the start.
1193 * With this arrangement, the command FIFO will never get full.
1195 if (packet.payload_length <= 16) {
1196 cmd_fifo_len = packet.payload_length;
1199 cmd_fifo_len = (packet.payload_length %
1200 DSI_PIX_FIFO_WIDTH);
1201 pix_fifo_len = ((packet.payload_length - cmd_fifo_len) /
1202 DSI_PIX_FIFO_WIDTH);
1205 WARN_ON_ONCE(pix_fifo_len >= DSI_PIX_FIFO_DEPTH);
1207 pkth |= VC4_SET_FIELD(cmd_fifo_len, DSI_TXPKT1H_BC_CMDFIFO);
1211 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_RX,
1212 DSI_TXPKT1C_CMD_CTRL);
1214 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_TX,
1215 DSI_TXPKT1C_CMD_CTRL);
1218 for (i = 0; i < cmd_fifo_len; i++)
1219 DSI_PORT_WRITE(TXPKT_CMD_FIFO, packet.payload[i]);
1220 for (i = 0; i < pix_fifo_len; i++) {
1221 const u8 *pix = packet.payload + cmd_fifo_len + i * 4;
1223 DSI_PORT_WRITE(TXPKT_PIX_FIFO,
1230 if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1231 pktc |= DSI_TXPKT1C_CMD_MODE_LP;
1233 pktc |= DSI_TXPKT1C_CMD_TYPE_LONG;
1235 /* Send one copy of the packet. Larger repeats are used for pixel
1236 * data in command mode.
1238 pktc |= VC4_SET_FIELD(1, DSI_TXPKT1C_CMD_REPEAT);
1240 pktc |= DSI_TXPKT1C_CMD_EN;
1242 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SECONDARY,
1243 DSI_TXPKT1C_DISPLAY_NO);
1245 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SHORT,
1246 DSI_TXPKT1C_DISPLAY_NO);
1249 /* Enable the appropriate interrupt for the transfer completion. */
1250 dsi->xfer_result = 0;
1251 reinit_completion(&dsi->xfer_completion);
1252 if (dsi->variant->port == 0) {
1253 DSI_PORT_WRITE(INT_STAT,
1254 DSI0_INT_CMDC_DONE_MASK | DSI1_INT_PHY_DIR_RTF);
1256 DSI_PORT_WRITE(INT_EN, (DSI0_INTERRUPTS_ALWAYS_ENABLED |
1257 DSI0_INT_PHY_DIR_RTF));
1259 DSI_PORT_WRITE(INT_EN,
1260 (DSI0_INTERRUPTS_ALWAYS_ENABLED |
1261 VC4_SET_FIELD(DSI0_INT_CMDC_DONE_NO_REPEAT,
1262 DSI0_INT_CMDC_DONE)));
1265 DSI_PORT_WRITE(INT_STAT,
1266 DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF);
1268 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1269 DSI1_INT_PHY_DIR_RTF));
1271 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1272 DSI1_INT_TXPKT1_DONE));
1276 /* Send the packet. */
1277 DSI_PORT_WRITE(TXPKT1H, pkth);
1278 DSI_PORT_WRITE(TXPKT1C, pktc);
1280 if (!wait_for_completion_timeout(&dsi->xfer_completion,
1281 msecs_to_jiffies(1000))) {
1282 dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout");
1283 dev_err(&dsi->pdev->dev, "instat: 0x%08x\n",
1284 DSI_PORT_READ(INT_STAT));
1287 ret = dsi->xfer_result;
1290 DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED));
1293 goto reset_fifo_and_return;
1295 if (ret == 0 && msg->rx_len) {
1296 u32 rxpkt1h = DSI_PORT_READ(RXPKT1H);
1297 u8 *msg_rx = msg->rx_buf;
1299 if (rxpkt1h & DSI_RXPKT1H_PKT_TYPE_LONG) {
1300 u32 rxlen = VC4_GET_FIELD(rxpkt1h,
1301 DSI_RXPKT1H_BC_PARAM);
1303 if (rxlen != msg->rx_len) {
1304 DRM_ERROR("DSI returned %db, expecting %db\n",
1305 rxlen, (int)msg->rx_len);
1307 goto reset_fifo_and_return;
1310 for (i = 0; i < msg->rx_len; i++)
1311 msg_rx[i] = DSI_READ(DSI1_RXPKT_FIFO);
1313 /* FINISHME: Handle AWER */
1315 msg_rx[0] = VC4_GET_FIELD(rxpkt1h,
1316 DSI_RXPKT1H_SHORT_0);
1317 if (msg->rx_len > 1) {
1318 msg_rx[1] = VC4_GET_FIELD(rxpkt1h,
1319 DSI_RXPKT1H_SHORT_1);
1326 reset_fifo_and_return:
1327 DRM_ERROR("DSI transfer failed, resetting: %d\n", ret);
1329 DSI_PORT_WRITE(TXPKT1C, DSI_PORT_READ(TXPKT1C) & ~DSI_TXPKT1C_CMD_EN);
1331 DSI_PORT_WRITE(CTRL,
1332 DSI_PORT_READ(CTRL) |
1333 DSI_PORT_BIT(CTRL_RESET_FIFOS));
1335 DSI_PORT_WRITE(TXPKT1C, 0);
1336 DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED));
1340 static const struct component_ops vc4_dsi_ops;
1341 static int vc4_dsi_host_attach(struct mipi_dsi_host *host,
1342 struct mipi_dsi_device *device)
1344 struct vc4_dsi *dsi = host_to_dsi(host);
1347 dsi->lanes = device->lanes;
1348 dsi->channel = device->channel;
1349 dsi->mode_flags = device->mode_flags;
1351 switch (device->format) {
1352 case MIPI_DSI_FMT_RGB888:
1353 dsi->format = DSI_PFORMAT_RGB888;
1354 dsi->divider = 24 / dsi->lanes;
1356 case MIPI_DSI_FMT_RGB666:
1357 dsi->format = DSI_PFORMAT_RGB666;
1358 dsi->divider = 24 / dsi->lanes;
1360 case MIPI_DSI_FMT_RGB666_PACKED:
1361 dsi->format = DSI_PFORMAT_RGB666_PACKED;
1362 dsi->divider = 18 / dsi->lanes;
1364 case MIPI_DSI_FMT_RGB565:
1365 dsi->format = DSI_PFORMAT_RGB565;
1366 dsi->divider = 16 / dsi->lanes;
1369 dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n",
1374 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1375 dev_err(&dsi->pdev->dev,
1376 "Only VIDEO mode panels supported currently.\n");
1380 drm_bridge_add(&dsi->bridge);
1382 ret = component_add(&dsi->pdev->dev, &vc4_dsi_ops);
1384 drm_bridge_remove(&dsi->bridge);
1391 static int vc4_dsi_host_detach(struct mipi_dsi_host *host,
1392 struct mipi_dsi_device *device)
1394 struct vc4_dsi *dsi = host_to_dsi(host);
1396 component_del(&dsi->pdev->dev, &vc4_dsi_ops);
1397 drm_bridge_remove(&dsi->bridge);
1401 static const struct mipi_dsi_host_ops vc4_dsi_host_ops = {
1402 .attach = vc4_dsi_host_attach,
1403 .detach = vc4_dsi_host_detach,
1404 .transfer = vc4_dsi_host_transfer,
1407 static const struct drm_bridge_funcs vc4_dsi_bridge_funcs = {
1408 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1409 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1410 .atomic_reset = drm_atomic_helper_bridge_reset,
1411 .atomic_pre_enable = vc4_dsi_bridge_pre_enable,
1412 .atomic_enable = vc4_dsi_bridge_enable,
1413 .atomic_disable = vc4_dsi_bridge_disable,
1414 .atomic_post_disable = vc4_dsi_bridge_post_disable,
1415 .attach = vc4_dsi_bridge_attach,
1416 .mode_fixup = vc4_dsi_bridge_mode_fixup,
1419 static int vc4_dsi_late_register(struct drm_encoder *encoder)
1421 struct drm_device *drm = encoder->dev;
1422 struct vc4_dsi *dsi = to_vc4_dsi(encoder);
1425 ret = vc4_debugfs_add_regset32(drm->primary, dsi->variant->debugfs_name,
1433 static const struct drm_encoder_funcs vc4_dsi_encoder_funcs = {
1434 .late_register = vc4_dsi_late_register,
1437 static const struct vc4_dsi_variant bcm2711_dsi1_variant = {
1439 .debugfs_name = "dsi1_regs",
1441 .nregs = ARRAY_SIZE(dsi1_regs),
1444 static const struct vc4_dsi_variant bcm2835_dsi0_variant = {
1446 .debugfs_name = "dsi0_regs",
1448 .nregs = ARRAY_SIZE(dsi0_regs),
1451 static const struct vc4_dsi_variant bcm2835_dsi1_variant = {
1453 .broken_axi_workaround = true,
1454 .debugfs_name = "dsi1_regs",
1456 .nregs = ARRAY_SIZE(dsi1_regs),
1459 static const struct of_device_id vc4_dsi_dt_match[] = {
1460 { .compatible = "brcm,bcm2711-dsi1", &bcm2711_dsi1_variant },
1461 { .compatible = "brcm,bcm2835-dsi0", &bcm2835_dsi0_variant },
1462 { .compatible = "brcm,bcm2835-dsi1", &bcm2835_dsi1_variant },
1466 static void dsi_handle_error(struct vc4_dsi *dsi,
1467 irqreturn_t *ret, u32 stat, u32 bit,
1473 DRM_ERROR("DSI%d: %s error\n", dsi->variant->port, type);
1478 * Initial handler for port 1 where we need the reg_dma workaround.
1479 * The register DMA writes sleep, so we can't do it in the top half.
1480 * Instead we use IRQF_ONESHOT so that the IRQ gets disabled in the
1481 * parent interrupt contrller until our interrupt thread is done.
1483 static irqreturn_t vc4_dsi_irq_defer_to_thread_handler(int irq, void *data)
1485 struct vc4_dsi *dsi = data;
1486 u32 stat = DSI_PORT_READ(INT_STAT);
1491 return IRQ_WAKE_THREAD;
1495 * Normal IRQ handler for port 0, or the threaded IRQ handler for port
1496 * 1 where we need the reg_dma workaround.
1498 static irqreturn_t vc4_dsi_irq_handler(int irq, void *data)
1500 struct vc4_dsi *dsi = data;
1501 u32 stat = DSI_PORT_READ(INT_STAT);
1502 irqreturn_t ret = IRQ_NONE;
1504 DSI_PORT_WRITE(INT_STAT, stat);
1506 dsi_handle_error(dsi, &ret, stat,
1507 DSI_PORT_BIT(INT_ERR_SYNC_ESC), "LPDT sync");
1508 dsi_handle_error(dsi, &ret, stat,
1509 DSI_PORT_BIT(INT_ERR_CONTROL), "data lane 0 sequence");
1510 dsi_handle_error(dsi, &ret, stat,
1511 DSI_PORT_BIT(INT_ERR_CONT_LP0), "LP0 contention");
1512 dsi_handle_error(dsi, &ret, stat,
1513 DSI_PORT_BIT(INT_ERR_CONT_LP1), "LP1 contention");
1514 dsi_handle_error(dsi, &ret, stat,
1515 DSI_PORT_BIT(INT_HSTX_TO), "HSTX timeout");
1516 dsi_handle_error(dsi, &ret, stat,
1517 DSI_PORT_BIT(INT_LPRX_TO), "LPRX timeout");
1518 dsi_handle_error(dsi, &ret, stat,
1519 DSI_PORT_BIT(INT_TA_TO), "turnaround timeout");
1520 dsi_handle_error(dsi, &ret, stat,
1521 DSI_PORT_BIT(INT_PR_TO), "peripheral reset timeout");
1523 if (stat & ((dsi->variant->port ? DSI1_INT_TXPKT1_DONE :
1524 DSI0_INT_CMDC_DONE_MASK) |
1525 DSI_PORT_BIT(INT_PHY_DIR_RTF))) {
1526 complete(&dsi->xfer_completion);
1528 } else if (stat & DSI_PORT_BIT(INT_HSTX_TO)) {
1529 complete(&dsi->xfer_completion);
1530 dsi->xfer_result = -ETIMEDOUT;
1538 * vc4_dsi_init_phy_clocks - Exposes clocks generated by the analog
1539 * PHY that are consumed by CPRMAN (clk-bcm2835.c).
1543 vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi)
1545 struct device *dev = &dsi->pdev->dev;
1546 const char *parent_name = __clk_get_name(dsi->pll_phy_clock);
1547 static const struct {
1557 dsi->clk_onecell = devm_kzalloc(dev,
1558 sizeof(*dsi->clk_onecell) +
1559 ARRAY_SIZE(phy_clocks) *
1560 sizeof(struct clk_hw *),
1562 if (!dsi->clk_onecell)
1564 dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks);
1566 for (i = 0; i < ARRAY_SIZE(phy_clocks); i++) {
1567 struct clk_fixed_factor *fix = &dsi->phy_clocks[i];
1568 struct clk_init_data init;
1572 snprintf(clk_name, sizeof(clk_name),
1573 "dsi%u_%s", dsi->variant->port, phy_clocks[i].name);
1575 /* We just use core fixed factor clock ops for the PHY
1576 * clocks. The clocks are actually gated by the
1577 * PHY_AFEC0_DDRCLK_EN bits, which we should be
1578 * setting if we use the DDR/DDR2 clocks. However,
1579 * vc4_dsi_encoder_enable() is setting up both AFEC0,
1580 * setting both our parent DSI PLL's rate and this
1581 * clock's rate, so it knows if DDR/DDR2 are going to
1582 * be used and could enable the gates itself.
1585 fix->div = phy_clocks[i].div;
1586 fix->hw.init = &init;
1588 memset(&init, 0, sizeof(init));
1589 init.parent_names = &parent_name;
1590 init.num_parents = 1;
1591 init.name = clk_name;
1592 init.ops = &clk_fixed_factor_ops;
1594 ret = devm_clk_hw_register(dev, &fix->hw);
1598 dsi->clk_onecell->hws[i] = &fix->hw;
1601 return of_clk_add_hw_provider(dev->of_node,
1602 of_clk_hw_onecell_get,
1606 static void vc4_dsi_dma_mem_release(void *ptr)
1608 struct vc4_dsi *dsi = ptr;
1609 struct device *dev = &dsi->pdev->dev;
1611 dma_free_coherent(dev, 4, dsi->reg_dma_mem, dsi->reg_dma_paddr);
1612 dsi->reg_dma_mem = NULL;
1615 static void vc4_dsi_dma_chan_release(void *ptr)
1617 struct vc4_dsi *dsi = ptr;
1619 dma_release_channel(dsi->reg_dma_chan);
1620 dsi->reg_dma_chan = NULL;
1623 static void vc4_dsi_release(struct kref *kref)
1625 struct vc4_dsi *dsi =
1626 container_of(kref, struct vc4_dsi, kref);
1631 static void vc4_dsi_get(struct vc4_dsi *dsi)
1633 kref_get(&dsi->kref);
1636 static void vc4_dsi_put(struct vc4_dsi *dsi)
1638 kref_put(&dsi->kref, &vc4_dsi_release);
1641 static void vc4_dsi_release_action(struct drm_device *drm, void *ptr)
1643 struct vc4_dsi *dsi = ptr;
1648 static int vc4_dsi_bind(struct device *dev, struct device *master, void *data)
1650 struct platform_device *pdev = to_platform_device(dev);
1651 struct drm_device *drm = dev_get_drvdata(master);
1652 struct vc4_dsi *dsi = dev_get_drvdata(dev);
1653 const struct of_device_id *match;
1654 struct drm_encoder *encoder = &dsi->encoder.base;
1659 ret = drmm_add_action_or_reset(drm, vc4_dsi_release_action, dsi);
1663 match = of_match_device(vc4_dsi_dt_match, dev);
1667 dsi->variant = match->data;
1668 dsi->encoder.type = dsi->variant->port ?
1669 VC4_ENCODER_TYPE_DSI1 : VC4_ENCODER_TYPE_DSI0;
1671 dsi->regs = vc4_ioremap_regs(pdev, 0);
1672 if (IS_ERR(dsi->regs))
1673 return PTR_ERR(dsi->regs);
1675 dsi->regset.base = dsi->regs;
1676 dsi->regset.regs = dsi->variant->regs;
1677 dsi->regset.nregs = dsi->variant->nregs;
1679 if (DSI_PORT_READ(ID) != DSI_ID_VALUE) {
1680 dev_err(dev, "Port returned 0x%08x for ID instead of 0x%08x\n",
1681 DSI_PORT_READ(ID), DSI_ID_VALUE);
1685 /* DSI1 on BCM2835/6/7 has a broken AXI slave that doesn't respond to
1686 * writes from the ARM. It does handle writes from the DMA engine,
1687 * so set up a channel for talking to it.
1689 if (dsi->variant->broken_axi_workaround) {
1690 dma_cap_mask_t dma_mask;
1692 dsi->reg_dma_mem = dma_alloc_coherent(dev, 4,
1693 &dsi->reg_dma_paddr,
1695 if (!dsi->reg_dma_mem) {
1696 DRM_ERROR("Failed to get DMA memory\n");
1700 ret = devm_add_action_or_reset(dev, vc4_dsi_dma_mem_release, dsi);
1704 dma_cap_zero(dma_mask);
1705 dma_cap_set(DMA_MEMCPY, dma_mask);
1707 dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask);
1708 if (IS_ERR(dsi->reg_dma_chan)) {
1709 ret = PTR_ERR(dsi->reg_dma_chan);
1710 if (ret != -EPROBE_DEFER)
1711 DRM_ERROR("Failed to get DMA channel: %d\n",
1716 ret = devm_add_action_or_reset(dev, vc4_dsi_dma_chan_release, dsi);
1720 /* Get the physical address of the device's registers. The
1721 * struct resource for the regs gives us the bus address
1724 dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node,
1728 init_completion(&dsi->xfer_completion);
1729 /* At startup enable error-reporting interrupts and nothing else. */
1730 DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1731 /* Clear any existing interrupt state. */
1732 DSI_PORT_WRITE(INT_STAT, DSI_PORT_READ(INT_STAT));
1734 if (dsi->reg_dma_mem)
1735 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
1736 vc4_dsi_irq_defer_to_thread_handler,
1737 vc4_dsi_irq_handler,
1741 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1742 vc4_dsi_irq_handler, 0, "vc4 dsi", dsi);
1744 if (ret != -EPROBE_DEFER)
1745 dev_err(dev, "Failed to get interrupt: %d\n", ret);
1749 dsi->escape_clock = devm_clk_get(dev, "escape");
1750 if (IS_ERR(dsi->escape_clock)) {
1751 ret = PTR_ERR(dsi->escape_clock);
1752 if (ret != -EPROBE_DEFER)
1753 dev_err(dev, "Failed to get escape clock: %d\n", ret);
1757 dsi->pll_phy_clock = devm_clk_get(dev, "phy");
1758 if (IS_ERR(dsi->pll_phy_clock)) {
1759 ret = PTR_ERR(dsi->pll_phy_clock);
1760 if (ret != -EPROBE_DEFER)
1761 dev_err(dev, "Failed to get phy clock: %d\n", ret);
1765 dsi->pixel_clock = devm_clk_get(dev, "pixel");
1766 if (IS_ERR(dsi->pixel_clock)) {
1767 ret = PTR_ERR(dsi->pixel_clock);
1768 if (ret != -EPROBE_DEFER)
1769 dev_err(dev, "Failed to get pixel clock: %d\n", ret);
1773 dsi->out_bridge = drmm_of_get_bridge(drm, dev->of_node, 0, 0);
1774 if (IS_ERR(dsi->out_bridge))
1775 return PTR_ERR(dsi->out_bridge);
1777 /* The esc clock rate is supposed to always be 100Mhz. */
1778 ret = clk_set_rate(dsi->escape_clock, 100 * 1000000);
1780 dev_err(dev, "Failed to set esc clock: %d\n", ret);
1784 ret = vc4_dsi_init_phy_clocks(dsi);
1788 ret = drmm_encoder_init(drm, encoder,
1789 &vc4_dsi_encoder_funcs,
1790 DRM_MODE_ENCODER_DSI,
1795 ret = devm_pm_runtime_enable(dev);
1799 ret = drm_bridge_attach(encoder, &dsi->bridge, NULL, 0);
1801 dev_err(dev, "bridge attach failed: %d\n", ret);
1808 static const struct component_ops vc4_dsi_ops = {
1809 .bind = vc4_dsi_bind,
1812 static int vc4_dsi_dev_probe(struct platform_device *pdev)
1814 struct device *dev = &pdev->dev;
1815 struct vc4_dsi *dsi;
1817 dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
1820 dev_set_drvdata(dev, dsi);
1822 kref_init(&dsi->kref);
1824 dsi->bridge.funcs = &vc4_dsi_bridge_funcs;
1825 dsi->bridge.of_node = dev->of_node;
1826 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
1829 dsi->dsi_host.ops = &vc4_dsi_host_ops;
1830 dsi->dsi_host.dev = dev;
1831 mipi_dsi_host_register(&dsi->dsi_host);
1836 static int vc4_dsi_dev_remove(struct platform_device *pdev)
1838 struct device *dev = &pdev->dev;
1839 struct vc4_dsi *dsi = dev_get_drvdata(dev);
1841 mipi_dsi_host_unregister(&dsi->dsi_host);
1847 struct platform_driver vc4_dsi_driver = {
1848 .probe = vc4_dsi_dev_probe,
1849 .remove = vc4_dsi_dev_remove,
1852 .of_match_table = vc4_dsi_dt_match,