1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2015 Broadcom
8 #include <linux/delay.h>
9 #include <linux/refcount.h>
10 #include <linux/uaccess.h>
12 #include <drm/drm_atomic.h>
13 #include <drm/drm_debugfs.h>
14 #include <drm/drm_device.h>
15 #include <drm/drm_encoder.h>
16 #include <drm/drm_gem_cma_helper.h>
17 #include <drm/drm_managed.h>
18 #include <drm/drm_mm.h>
19 #include <drm/drm_modeset_lock.h>
21 #include "uapi/drm/vc4_drm.h"
24 struct drm_gem_object;
26 /* Don't forget to update vc4_bo.c: bo_type_names[] when adding to
29 enum vc4_kernel_bo_type {
30 /* Any kernel allocation (gem_create_object hook) before it
31 * gets another type set.
35 VC4_BO_TYPE_V3D_SHADER,
40 VC4_BO_TYPE_KERNEL_CACHE,
44 /* Performance monitor object. The perform lifetime is controlled by userspace
45 * using perfmon related ioctls. A perfmon can be attached to a submit_cl
46 * request, and when this is the case, HW perf counters will be activated just
47 * before the submit_cl is submitted to the GPU and disabled when the job is
48 * done. This way, only events related to a specific job will be counted.
51 /* Tracks the number of users of the perfmon, when this counter reaches
52 * zero the perfmon is destroyed.
56 /* Number of counters activated in this perfmon instance
57 * (should be less than DRM_VC4_MAX_PERF_COUNTERS).
61 /* Events counted by the HW perf counters. */
62 u8 events[DRM_VC4_MAX_PERF_COUNTERS];
64 /* Storage for counter values. Counters are incremented by the HW
65 * perf counter values every time the perfmon is attached to a GPU job.
66 * This way, perfmon users don't have to retrieve the results after
67 * each job if they want to track events covering several submissions.
68 * Note that counter values can't be reset, but you can fake a reset by
69 * destroying the perfmon and creating a new one.
75 struct drm_device base;
85 struct vc4_hang_state *hang_state;
87 /* The kernel-space BO cache. Tracks buffers that have been
88 * unreferenced by all other users (refcounts of 0!) but not
89 * yet freed, so we can do cheap allocations.
92 /* Array of list heads for entries in the BO cache,
93 * based on number of pages, so we can do O(1) lookups
94 * in the cache when allocating.
96 struct list_head *size_list;
97 uint32_t size_list_size;
99 /* List of all BOs in the cache, ordered by age, so we
100 * can do O(1) lookups when trying to free old
103 struct list_head time_list;
104 struct work_struct time_work;
105 struct timer_list time_timer;
115 /* Protects bo_cache and bo_labels. */
116 struct mutex bo_lock;
118 /* Purgeable BO pool. All BOs in this pool can have their memory
119 * reclaimed if the driver is unable to allocate new BOs. We also
120 * keep stats related to the purge mechanism here.
123 struct list_head list;
126 unsigned int purged_num;
131 uint64_t dma_fence_context;
133 /* Sequence number for the last job queued in bin_job_list.
134 * Starts at 0 (no jobs emitted).
138 /* Sequence number for the last completed job on the GPU.
139 * Starts at 0 (no jobs completed).
141 uint64_t finished_seqno;
143 /* List of all struct vc4_exec_info for jobs to be executed in
144 * the binner. The first job in the list is the one currently
145 * programmed into ct0ca for execution.
147 struct list_head bin_job_list;
149 /* List of all struct vc4_exec_info for jobs that have
150 * completed binning and are ready for rendering. The first
151 * job in the list is the one currently programmed into ct1ca
154 struct list_head render_job_list;
156 /* List of the finished vc4_exec_infos waiting to be freed by
159 struct list_head job_done_list;
160 /* Spinlock used to synchronize the job_list and seqno
161 * accesses between the IRQ handler and GEM ioctls.
164 wait_queue_head_t job_wait_queue;
165 struct work_struct job_done_work;
167 /* Used to track the active perfmon if any. Access to this field is
168 * protected by job_lock.
170 struct vc4_perfmon *active_perfmon;
172 /* List of struct vc4_seqno_cb for callbacks to be made from a
173 * workqueue when the given seqno is passed.
175 struct list_head seqno_cb_list;
177 /* The memory used for storing binner tile alloc, tile state,
178 * and overflow memory allocations. This is freed when V3D
181 struct vc4_bo *bin_bo;
183 /* Size of blocks allocated within bin_bo. */
184 uint32_t bin_alloc_size;
186 /* Bitmask of the bin_alloc_size chunks in bin_bo that are
189 uint32_t bin_alloc_used;
191 /* Bitmask of the current bin_alloc used for overflow memory. */
192 uint32_t bin_alloc_overflow;
194 /* Incremented when an underrun error happened after an atomic commit.
195 * This is particularly useful to detect when a specific modeset is too
196 * demanding in term of memory or HVS bandwidth which is hard to guess
197 * at atomic check time.
201 struct work_struct overflow_mem_work;
205 /* Set to true when the load tracker is supported. */
206 bool load_tracker_available;
208 /* Set to true when the load tracker is active. */
209 bool load_tracker_enabled;
211 /* Mutex controlling the power refcount. */
212 struct mutex power_lock;
215 struct timer_list timer;
216 struct work_struct reset_work;
219 struct drm_modeset_lock ctm_state_lock;
220 struct drm_private_obj ctm_manager;
221 struct drm_private_obj hvs_channels;
222 struct drm_private_obj load_tracker;
224 /* List of vc4_debugfs_info_entry for adding to debugfs once
225 * the minor is available (after drm_dev_register()).
227 struct list_head debugfs_list;
229 /* Mutex for binner bo allocation. */
230 struct mutex bin_bo_lock;
231 /* Reference count for our binner bo. */
232 struct kref bin_bo_kref;
235 static inline struct vc4_dev *
236 to_vc4_dev(struct drm_device *dev)
238 return container_of(dev, struct vc4_dev, base);
242 struct drm_gem_cma_object base;
244 /* seqno of the last job to render using this BO. */
247 /* seqno of the last job to use the RCL to write to this BO.
249 * Note that this doesn't include binner overflow memory
252 uint64_t write_seqno;
256 /* List entry for the BO's position in either
257 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
259 struct list_head unref_head;
261 /* Time in jiffies when the BO was put in vc4->bo_cache. */
262 unsigned long free_time;
264 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
265 struct list_head size_head;
267 /* Struct for shader validation state, if created by
268 * DRM_IOCTL_VC4_CREATE_SHADER_BO.
270 struct vc4_validated_shader_info *validated_shader;
272 /* One of enum vc4_kernel_bo_type, or VC4_BO_TYPE_COUNT + i
273 * for user-allocated labels.
277 /* Count the number of active users. This is needed to determine
278 * whether we can move the BO to the purgeable list or not (when the BO
279 * is used by the GPU or the display engine we can't purge it).
283 /* Store purgeable/purged state here */
285 struct mutex madv_lock;
288 static inline struct vc4_bo *
289 to_vc4_bo(struct drm_gem_object *bo)
291 return container_of(to_drm_gem_cma_obj(bo), struct vc4_bo, base);
295 struct dma_fence base;
296 struct drm_device *dev;
297 /* vc4 seqno for signaled() test */
301 static inline struct vc4_fence *
302 to_vc4_fence(struct dma_fence *fence)
304 return container_of(fence, struct vc4_fence, base);
307 struct vc4_seqno_cb {
308 struct work_struct work;
310 void (*func)(struct vc4_seqno_cb *cb);
315 struct platform_device *pdev;
318 struct debugfs_regset32 regset;
322 struct platform_device *pdev;
326 struct clk *core_clk;
328 /* Memory manager for CRTCs to allocate space in the display
329 * list. Units are dwords.
331 struct drm_mm dlist_mm;
332 /* Memory manager for the LBM memory used by HVS scaling. */
333 struct drm_mm lbm_mm;
336 struct drm_mm_node mitchell_netravali_filter;
338 struct debugfs_regset32 regset;
340 /* HVS version 5 flag, therefore requires updated dlist structures */
345 struct drm_plane base;
348 static inline struct vc4_plane *
349 to_vc4_plane(struct drm_plane *plane)
351 return container_of(plane, struct vc4_plane, base);
354 enum vc4_scaling_mode {
360 struct vc4_plane_state {
361 struct drm_plane_state base;
362 /* System memory copy of the display list for this element, computed
363 * at atomic_check time.
366 u32 dlist_size; /* Number of dwords allocated for the display list */
367 u32 dlist_count; /* Number of used dwords in the display list. */
369 /* Offset in the dlist to various words, for pageflip or
377 /* Offset where the plane's dlist was last stored in the
378 * hardware at vc4_crtc_atomic_flush() time.
380 u32 __iomem *hw_dlist;
382 /* Clipped coordinates of the plane on the display. */
383 int crtc_x, crtc_y, crtc_w, crtc_h;
384 /* Clipped area being scanned from in the FB. */
387 u32 src_w[2], src_h[2];
389 /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
390 enum vc4_scaling_mode x_scaling[2], y_scaling[2];
394 /* Offset to start scanning out from the start of the plane's
399 /* Our allocation in LBM for temporary storage during scaling. */
400 struct drm_mm_node lbm;
402 /* Set when the plane has per-pixel alpha content or does not cover
403 * the entire screen. This is a hint to the CRTC that it might need
404 * to enable background color fill.
408 /* Mark the dlist as initialized. Useful to avoid initializing it twice
409 * when async update is not possible.
411 bool dlist_initialized;
413 /* Load of this plane on the HVS block. The load is expressed in HVS
418 /* Memory bandwidth needed for this plane. This is expressed in
424 static inline struct vc4_plane_state *
425 to_vc4_plane_state(struct drm_plane_state *state)
427 return container_of(state, struct vc4_plane_state, base);
430 enum vc4_encoder_type {
431 VC4_ENCODER_TYPE_NONE,
432 VC4_ENCODER_TYPE_HDMI0,
433 VC4_ENCODER_TYPE_HDMI1,
434 VC4_ENCODER_TYPE_VEC,
435 VC4_ENCODER_TYPE_DSI0,
436 VC4_ENCODER_TYPE_DSI1,
437 VC4_ENCODER_TYPE_SMI,
438 VC4_ENCODER_TYPE_DPI,
442 struct drm_encoder base;
443 enum vc4_encoder_type type;
446 void (*pre_crtc_configure)(struct drm_encoder *encoder, struct drm_atomic_state *state);
447 void (*pre_crtc_enable)(struct drm_encoder *encoder, struct drm_atomic_state *state);
448 void (*post_crtc_enable)(struct drm_encoder *encoder, struct drm_atomic_state *state);
450 void (*post_crtc_disable)(struct drm_encoder *encoder, struct drm_atomic_state *state);
451 void (*post_crtc_powerdown)(struct drm_encoder *encoder, struct drm_atomic_state *state);
454 static inline struct vc4_encoder *
455 to_vc4_encoder(struct drm_encoder *encoder)
457 return container_of(encoder, struct vc4_encoder, base);
460 struct vc4_crtc_data {
461 /* Bitmask of channels (FIFOs) of the HVS that the output can source from */
462 unsigned int hvs_available_channels;
464 /* Which output of the HVS this pixelvalve sources from. */
469 struct vc4_crtc_data base;
471 /* Depth of the PixelValve FIFO in bytes */
472 unsigned int fifo_depth;
474 /* Number of pixels output per clock period */
477 enum vc4_encoder_type encoder_types[4];
478 const char *debugfs_name;
483 struct drm_crtc base;
484 struct platform_device *pdev;
485 const struct vc4_crtc_data *data;
488 /* Timestamp at start of vblank irq - unaffected by lock delays. */
495 struct drm_pending_vblank_event *event;
497 struct debugfs_regset32 regset;
500 * @feeds_txp: True if the CRTC feeds our writeback controller.
505 static inline struct vc4_crtc *
506 to_vc4_crtc(struct drm_crtc *crtc)
508 return container_of(crtc, struct vc4_crtc, base);
511 static inline const struct vc4_crtc_data *
512 vc4_crtc_to_vc4_crtc_data(const struct vc4_crtc *crtc)
517 static inline const struct vc4_pv_data *
518 vc4_crtc_to_vc4_pv_data(const struct vc4_crtc *crtc)
520 const struct vc4_crtc_data *data = vc4_crtc_to_vc4_crtc_data(crtc);
522 return container_of(data, struct vc4_pv_data, base);
525 struct vc4_crtc_state {
526 struct drm_crtc_state base;
527 /* Dlist area for this CRTC configuration. */
528 struct drm_mm_node mm;
530 unsigned int assigned_channel;
539 /* Transitional state below, only valid during atomic commits */
543 #define VC4_HVS_CHANNEL_DISABLED ((unsigned int)-1)
545 static inline struct vc4_crtc_state *
546 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
548 return container_of(crtc_state, struct vc4_crtc_state, base);
551 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
552 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
553 #define HVS_READ(offset) readl(vc4->hvs->regs + offset)
554 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
556 #define VC4_REG32(reg) { .name = #reg, .offset = reg }
558 struct vc4_exec_info {
559 /* Sequence number for this bin/render job. */
562 /* Latest write_seqno of any BO that binning depends on. */
563 uint64_t bin_dep_seqno;
565 struct dma_fence *fence;
567 /* Last current addresses the hardware was processing when the
568 * hangcheck timer checked on us.
570 uint32_t last_ct0ca, last_ct1ca;
572 /* Kernel-space copy of the ioctl arguments */
573 struct drm_vc4_submit_cl *args;
575 /* This is the array of BOs that were looked up at the start of exec.
576 * Command validation will use indices into this array.
578 struct drm_gem_cma_object **bo;
581 /* List of BOs that are being written by the RCL. Other than
582 * the binner temporary storage, this is all the BOs written
585 struct drm_gem_cma_object *rcl_write_bo[4];
586 uint32_t rcl_write_bo_count;
588 /* Pointers for our position in vc4->job_list */
589 struct list_head head;
591 /* List of other BOs used in the job that need to be released
592 * once the job is complete.
594 struct list_head unref_list;
596 /* Current unvalidated indices into @bo loaded by the non-hardware
597 * VC4_PACKET_GEM_HANDLES.
599 uint32_t bo_index[2];
601 /* This is the BO where we store the validated command lists, shader
602 * records, and uniforms.
604 struct drm_gem_cma_object *exec_bo;
607 * This tracks the per-shader-record state (packet 64) that
608 * determines the length of the shader record and the offset
609 * it's expected to be found at. It gets read in from the
612 struct vc4_shader_state {
614 /* Maximum vertex index referenced by any primitive using this
620 /** How many shader states the user declared they were using. */
621 uint32_t shader_state_size;
622 /** How many shader state records the validator has seen. */
623 uint32_t shader_state_count;
625 bool found_tile_binning_mode_config_packet;
626 bool found_start_tile_binning_packet;
627 bool found_increment_semaphore_packet;
629 uint8_t bin_tiles_x, bin_tiles_y;
630 /* Physical address of the start of the tile alloc array
631 * (where each tile's binned CL will start)
633 uint32_t tile_alloc_offset;
634 /* Bitmask of which binner slots are freed when this job completes. */
638 * Computed addresses pointing into exec_bo where we start the
639 * bin thread (ct0) and render thread (ct1).
641 uint32_t ct0ca, ct0ea;
642 uint32_t ct1ca, ct1ea;
644 /* Pointer to the unvalidated bin CL (if present). */
647 /* Pointers to the shader recs. These paddr gets incremented as CL
648 * packets are relocated in validate_gl_shader_state, and the vaddrs
649 * (u and v) get incremented and size decremented as the shader recs
650 * themselves are validated.
654 uint32_t shader_rec_p;
655 uint32_t shader_rec_size;
657 /* Pointers to the uniform data. These pointers are incremented, and
658 * size decremented, as each batch of uniforms is uploaded.
663 uint32_t uniforms_size;
665 /* Pointer to a performance monitor object if the user requested it,
668 struct vc4_perfmon *perfmon;
670 /* Whether the exec has taken a reference to the binner BO, which should
671 * happen with a VC4_PACKET_TILE_BINNING_MODE_CONFIG packet.
676 /* Per-open file private data. Any driver-specific resource that has to be
677 * released when the DRM file is closed should be placed here.
688 static inline struct vc4_exec_info *
689 vc4_first_bin_job(struct vc4_dev *vc4)
691 return list_first_entry_or_null(&vc4->bin_job_list,
692 struct vc4_exec_info, head);
695 static inline struct vc4_exec_info *
696 vc4_first_render_job(struct vc4_dev *vc4)
698 return list_first_entry_or_null(&vc4->render_job_list,
699 struct vc4_exec_info, head);
702 static inline struct vc4_exec_info *
703 vc4_last_render_job(struct vc4_dev *vc4)
705 if (list_empty(&vc4->render_job_list))
707 return list_last_entry(&vc4->render_job_list,
708 struct vc4_exec_info, head);
712 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
715 * This will be used at draw time to relocate the reference to the texture
716 * contents in p0, and validate that the offset combined with
717 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
718 * Note that the hardware treats unprovided config parameters as 0, so not all
719 * of them need to be set up for every texure sample, and we'll store ~0 as
720 * the offset to mark the unused ones.
722 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
723 * Setup") for definitions of the texture parameters.
725 struct vc4_texture_sample_info {
727 uint32_t p_offset[4];
731 * struct vc4_validated_shader_info - information about validated shaders that
732 * needs to be used from command list validation.
734 * For a given shader, each time a shader state record references it, we need
735 * to verify that the shader doesn't read more uniforms than the shader state
736 * record's uniform BO pointer can provide, and we need to apply relocations
737 * and validate the shader state record's uniforms that define the texture
740 struct vc4_validated_shader_info {
741 uint32_t uniforms_size;
742 uint32_t uniforms_src_size;
743 uint32_t num_texture_samples;
744 struct vc4_texture_sample_info *texture_samples;
746 uint32_t num_uniform_addr_offsets;
747 uint32_t *uniform_addr_offsets;
753 * __wait_for - magic wait macro
755 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
756 * important that we check the condition again after having timed out, since the
757 * timeout could be due to preemption or similar and we've never had a chance to
758 * check the condition before the timeout.
760 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
761 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
762 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
766 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
768 /* Guarantee COND check prior to timeout */ \
775 ret__ = -ETIMEDOUT; \
778 usleep_range(wait__, wait__ * 2); \
779 if (wait__ < (Wmax)) \
785 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
787 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
790 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
791 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
792 bool from_cache, enum vc4_kernel_bo_type type);
793 int vc4_dumb_create(struct drm_file *file_priv,
794 struct drm_device *dev,
795 struct drm_mode_create_dumb *args);
796 int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
797 struct drm_file *file_priv);
798 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
799 struct drm_file *file_priv);
800 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
801 struct drm_file *file_priv);
802 int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
803 struct drm_file *file_priv);
804 int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
805 struct drm_file *file_priv);
806 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
807 struct drm_file *file_priv);
808 int vc4_label_bo_ioctl(struct drm_device *dev, void *data,
809 struct drm_file *file_priv);
810 int vc4_bo_cache_init(struct drm_device *dev);
811 int vc4_bo_inc_usecnt(struct vc4_bo *bo);
812 void vc4_bo_dec_usecnt(struct vc4_bo *bo);
813 void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo);
814 void vc4_bo_remove_from_purgeable_pool(struct vc4_bo *bo);
817 extern struct platform_driver vc4_crtc_driver;
818 int vc4_crtc_disable_at_boot(struct drm_crtc *crtc);
819 int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
820 const struct drm_crtc_funcs *crtc_funcs,
821 const struct drm_crtc_helper_funcs *crtc_helper_funcs);
822 void vc4_crtc_destroy(struct drm_crtc *crtc);
823 int vc4_page_flip(struct drm_crtc *crtc,
824 struct drm_framebuffer *fb,
825 struct drm_pending_vblank_event *event,
827 struct drm_modeset_acquire_ctx *ctx);
828 struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc);
829 void vc4_crtc_destroy_state(struct drm_crtc *crtc,
830 struct drm_crtc_state *state);
831 void vc4_crtc_reset(struct drm_crtc *crtc);
832 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc);
833 void vc4_crtc_get_margins(struct drm_crtc_state *state,
834 unsigned int *left, unsigned int *right,
835 unsigned int *top, unsigned int *bottom);
838 void vc4_debugfs_init(struct drm_minor *minor);
839 #ifdef CONFIG_DEBUG_FS
840 void vc4_debugfs_add_file(struct drm_device *drm,
841 const char *filename,
842 int (*show)(struct seq_file*, void*),
844 void vc4_debugfs_add_regset32(struct drm_device *drm,
845 const char *filename,
846 struct debugfs_regset32 *regset);
848 static inline void vc4_debugfs_add_file(struct drm_device *drm,
849 const char *filename,
850 int (*show)(struct seq_file*, void*),
855 static inline void vc4_debugfs_add_regset32(struct drm_device *drm,
856 const char *filename,
857 struct debugfs_regset32 *regset)
863 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
866 extern struct platform_driver vc4_dpi_driver;
869 extern struct platform_driver vc4_dsi_driver;
872 extern const struct dma_fence_ops vc4_fence_ops;
875 int vc4_gem_init(struct drm_device *dev);
876 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
877 struct drm_file *file_priv);
878 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
879 struct drm_file *file_priv);
880 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
881 struct drm_file *file_priv);
882 void vc4_submit_next_bin_job(struct drm_device *dev);
883 void vc4_submit_next_render_job(struct drm_device *dev);
884 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
885 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
886 uint64_t timeout_ns, bool interruptible);
887 void vc4_job_handle_completed(struct vc4_dev *vc4);
888 int vc4_queue_seqno_cb(struct drm_device *dev,
889 struct vc4_seqno_cb *cb, uint64_t seqno,
890 void (*func)(struct vc4_seqno_cb *cb));
891 int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data,
892 struct drm_file *file_priv);
895 extern struct platform_driver vc4_hdmi_driver;
898 extern struct platform_driver vc4_vec_driver;
901 extern struct platform_driver vc4_txp_driver;
904 void vc4_irq_enable(struct drm_device *dev);
905 void vc4_irq_disable(struct drm_device *dev);
906 int vc4_irq_install(struct drm_device *dev, int irq);
907 void vc4_irq_uninstall(struct drm_device *dev);
908 void vc4_irq_reset(struct drm_device *dev);
911 extern struct platform_driver vc4_hvs_driver;
912 void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int output);
913 int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output);
914 int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state);
915 void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state);
916 void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state);
917 void vc4_hvs_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state);
918 void vc4_hvs_dump_state(struct drm_device *dev);
919 void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel);
920 void vc4_hvs_mask_underrun(struct drm_device *dev, int channel);
923 int vc4_kms_load(struct drm_device *dev);
926 struct drm_plane *vc4_plane_init(struct drm_device *dev,
927 enum drm_plane_type type);
928 int vc4_plane_create_additional_planes(struct drm_device *dev);
929 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
930 u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
931 void vc4_plane_async_set_fb(struct drm_plane *plane,
932 struct drm_framebuffer *fb);
935 extern struct platform_driver vc4_v3d_driver;
936 extern const struct of_device_id vc4_v3d_dt_match[];
937 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4);
938 int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used);
939 void vc4_v3d_bin_bo_put(struct vc4_dev *vc4);
940 int vc4_v3d_pm_get(struct vc4_dev *vc4);
941 void vc4_v3d_pm_put(struct vc4_dev *vc4);
945 vc4_validate_bin_cl(struct drm_device *dev,
948 struct vc4_exec_info *exec);
951 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
953 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
956 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
958 bool vc4_check_tex_size(struct vc4_exec_info *exec,
959 struct drm_gem_cma_object *fbo,
960 uint32_t offset, uint8_t tiling_format,
961 uint32_t width, uint32_t height, uint8_t cpp);
963 /* vc4_validate_shader.c */
964 struct vc4_validated_shader_info *
965 vc4_validate_shader(struct drm_gem_cma_object *shader_obj);
968 void vc4_perfmon_get(struct vc4_perfmon *perfmon);
969 void vc4_perfmon_put(struct vc4_perfmon *perfmon);
970 void vc4_perfmon_start(struct vc4_dev *vc4, struct vc4_perfmon *perfmon);
971 void vc4_perfmon_stop(struct vc4_dev *vc4, struct vc4_perfmon *perfmon,
973 struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id);
974 void vc4_perfmon_open_file(struct vc4_file *vc4file);
975 void vc4_perfmon_close_file(struct vc4_file *vc4file);
976 int vc4_perfmon_create_ioctl(struct drm_device *dev, void *data,
977 struct drm_file *file_priv);
978 int vc4_perfmon_destroy_ioctl(struct drm_device *dev, void *data,
979 struct drm_file *file_priv);
980 int vc4_perfmon_get_values_ioctl(struct drm_device *dev, void *data,
981 struct drm_file *file_priv);
983 #endif /* _VC4_DRV_H_ */