1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2015 Broadcom
8 #include <linux/delay.h>
9 #include <linux/refcount.h>
10 #include <linux/uaccess.h>
12 #include <drm/drm_atomic.h>
13 #include <drm/drm_debugfs.h>
14 #include <drm/drm_device.h>
15 #include <drm/drm_encoder.h>
16 #include <drm/drm_gem_cma_helper.h>
17 #include <drm/drm_managed.h>
18 #include <drm/drm_mm.h>
19 #include <drm/drm_modeset_lock.h>
21 #include "uapi/drm/vc4_drm.h"
25 struct drm_gem_object;
27 /* Don't forget to update vc4_bo.c: bo_type_names[] when adding to
30 enum vc4_kernel_bo_type {
31 /* Any kernel allocation (gem_create_object hook) before it
32 * gets another type set.
36 VC4_BO_TYPE_V3D_SHADER,
41 VC4_BO_TYPE_KERNEL_CACHE,
45 /* Performance monitor object. The perform lifetime is controlled by userspace
46 * using perfmon related ioctls. A perfmon can be attached to a submit_cl
47 * request, and when this is the case, HW perf counters will be activated just
48 * before the submit_cl is submitted to the GPU and disabled when the job is
49 * done. This way, only events related to a specific job will be counted.
54 /* Tracks the number of users of the perfmon, when this counter reaches
55 * zero the perfmon is destroyed.
59 /* Number of counters activated in this perfmon instance
60 * (should be less than DRM_VC4_MAX_PERF_COUNTERS).
64 /* Events counted by the HW perf counters. */
65 u8 events[DRM_VC4_MAX_PERF_COUNTERS];
67 /* Storage for counter values. Counters are incremented by the HW
68 * perf counter values every time the perfmon is attached to a GPU job.
69 * This way, perfmon users don't have to retrieve the results after
70 * each job if they want to track events covering several submissions.
71 * Note that counter values can't be reset, but you can fake a reset by
72 * destroying the perfmon and creating a new one.
78 struct drm_device base;
85 struct rpi_firmware *firmware;
92 struct vc4_fkms *fkms;
94 struct vc4_hang_state *hang_state;
96 /* The kernel-space BO cache. Tracks buffers that have been
97 * unreferenced by all other users (refcounts of 0!) but not
98 * yet freed, so we can do cheap allocations.
100 struct vc4_bo_cache {
101 /* Array of list heads for entries in the BO cache,
102 * based on number of pages, so we can do O(1) lookups
103 * in the cache when allocating.
105 struct list_head *size_list;
106 uint32_t size_list_size;
108 /* List of all BOs in the cache, ordered by age, so we
109 * can do O(1) lookups when trying to free old
112 struct list_head time_list;
113 struct work_struct time_work;
114 struct timer_list time_timer;
124 /* Protects bo_cache and bo_labels. */
125 struct mutex bo_lock;
127 /* Purgeable BO pool. All BOs in this pool can have their memory
128 * reclaimed if the driver is unable to allocate new BOs. We also
129 * keep stats related to the purge mechanism here.
132 struct list_head list;
135 unsigned int purged_num;
140 uint64_t dma_fence_context;
142 /* Sequence number for the last job queued in bin_job_list.
143 * Starts at 0 (no jobs emitted).
147 /* Sequence number for the last completed job on the GPU.
148 * Starts at 0 (no jobs completed).
150 uint64_t finished_seqno;
152 /* List of all struct vc4_exec_info for jobs to be executed in
153 * the binner. The first job in the list is the one currently
154 * programmed into ct0ca for execution.
156 struct list_head bin_job_list;
158 /* List of all struct vc4_exec_info for jobs that have
159 * completed binning and are ready for rendering. The first
160 * job in the list is the one currently programmed into ct1ca
163 struct list_head render_job_list;
165 /* List of the finished vc4_exec_infos waiting to be freed by
168 struct list_head job_done_list;
169 /* Spinlock used to synchronize the job_list and seqno
170 * accesses between the IRQ handler and GEM ioctls.
173 wait_queue_head_t job_wait_queue;
174 struct work_struct job_done_work;
176 /* Used to track the active perfmon if any. Access to this field is
177 * protected by job_lock.
179 struct vc4_perfmon *active_perfmon;
181 /* List of struct vc4_seqno_cb for callbacks to be made from a
182 * workqueue when the given seqno is passed.
184 struct list_head seqno_cb_list;
186 /* The memory used for storing binner tile alloc, tile state,
187 * and overflow memory allocations. This is freed when V3D
190 struct vc4_bo *bin_bo;
192 /* Size of blocks allocated within bin_bo. */
193 uint32_t bin_alloc_size;
195 /* Bitmask of the bin_alloc_size chunks in bin_bo that are
198 uint32_t bin_alloc_used;
200 /* Bitmask of the current bin_alloc used for overflow memory. */
201 uint32_t bin_alloc_overflow;
203 /* Incremented when an underrun error happened after an atomic commit.
204 * This is particularly useful to detect when a specific modeset is too
205 * demanding in term of memory or HVS bandwidth which is hard to guess
206 * at atomic check time.
210 struct work_struct overflow_mem_work;
214 /* Set to true when the load tracker is active. */
215 bool load_tracker_enabled;
217 /* Mutex controlling the power refcount. */
218 struct mutex power_lock;
221 struct timer_list timer;
222 struct work_struct reset_work;
225 struct drm_modeset_lock ctm_state_lock;
226 struct drm_private_obj ctm_manager;
227 struct drm_private_obj hvs_channels;
228 struct drm_private_obj load_tracker;
230 /* List of vc4_debugfs_info_entry for adding to debugfs once
231 * the minor is available (after drm_dev_register()).
233 struct list_head debugfs_list;
235 /* Mutex for binner bo allocation. */
236 struct mutex bin_bo_lock;
237 /* Reference count for our binner bo. */
238 struct kref bin_bo_kref;
241 static inline struct vc4_dev *
242 to_vc4_dev(struct drm_device *dev)
244 return container_of(dev, struct vc4_dev, base);
248 struct drm_gem_cma_object base;
250 /* seqno of the last job to render using this BO. */
253 /* seqno of the last job to use the RCL to write to this BO.
255 * Note that this doesn't include binner overflow memory
258 uint64_t write_seqno;
262 /* List entry for the BO's position in either
263 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
265 struct list_head unref_head;
267 /* Time in jiffies when the BO was put in vc4->bo_cache. */
268 unsigned long free_time;
270 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
271 struct list_head size_head;
273 /* Struct for shader validation state, if created by
274 * DRM_IOCTL_VC4_CREATE_SHADER_BO.
276 struct vc4_validated_shader_info *validated_shader;
278 /* One of enum vc4_kernel_bo_type, or VC4_BO_TYPE_COUNT + i
279 * for user-allocated labels.
283 /* Count the number of active users. This is needed to determine
284 * whether we can move the BO to the purgeable list or not (when the BO
285 * is used by the GPU or the display engine we can't purge it).
289 /* Store purgeable/purged state here */
291 struct mutex madv_lock;
294 static inline struct vc4_bo *
295 to_vc4_bo(struct drm_gem_object *bo)
297 return container_of(to_drm_gem_cma_obj(bo), struct vc4_bo, base);
301 struct dma_fence base;
302 struct drm_device *dev;
303 /* vc4 seqno for signaled() test */
307 static inline struct vc4_fence *
308 to_vc4_fence(struct dma_fence *fence)
310 return container_of(fence, struct vc4_fence, base);
313 struct vc4_seqno_cb {
314 struct work_struct work;
316 void (*func)(struct vc4_seqno_cb *cb);
321 struct platform_device *pdev;
324 struct debugfs_regset32 regset;
329 struct platform_device *pdev;
333 struct clk *core_clk;
335 /* Memory manager for CRTCs to allocate space in the display
336 * list. Units are dwords.
338 struct drm_mm dlist_mm;
339 /* Memory manager for the LBM memory used by HVS scaling. */
340 struct drm_mm lbm_mm;
343 struct drm_mm_node mitchell_netravali_filter;
345 struct debugfs_regset32 regset;
348 * Even if HDMI0 on the RPi4 can output modes requiring a pixel
349 * rate higher than 297MHz, it needs some adjustments in the
350 * config.txt file to be able to do so and thus won't always be
353 bool vc5_hdmi_enable_scrambling;
356 * 4096x2160@60 requires a core overclock to work, so register
357 * whether that is sufficient.
359 bool vc5_hdmi_enable_4096by2160;
363 struct drm_plane base;
366 static inline struct vc4_plane *
367 to_vc4_plane(struct drm_plane *plane)
369 return container_of(plane, struct vc4_plane, base);
372 enum vc4_scaling_mode {
378 struct vc4_plane_state {
379 struct drm_plane_state base;
380 /* System memory copy of the display list for this element, computed
381 * at atomic_check time.
384 u32 dlist_size; /* Number of dwords allocated for the display list */
385 u32 dlist_count; /* Number of used dwords in the display list. */
387 /* Offset in the dlist to various words, for pageflip or
395 /* Offset where the plane's dlist was last stored in the
396 * hardware at vc4_crtc_atomic_flush() time.
398 u32 __iomem *hw_dlist;
400 /* Clipped coordinates of the plane on the display. */
401 int crtc_x, crtc_y, crtc_w, crtc_h;
402 /* Clipped area being scanned from in the FB in u16.16 format */
405 u32 src_w[2], src_h[2];
407 /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
408 enum vc4_scaling_mode x_scaling[2], y_scaling[2];
412 /* Offset to start scanning out from the start of the plane's
417 /* Our allocation in LBM for temporary storage during scaling. */
418 struct drm_mm_node lbm;
420 /* Set when the plane has per-pixel alpha content or does not cover
421 * the entire screen. This is a hint to the CRTC that it might need
422 * to enable background color fill.
426 /* Mark the dlist as initialized. Useful to avoid initializing it twice
427 * when async update is not possible.
429 bool dlist_initialized;
431 /* Load of this plane on the HVS block. The load is expressed in HVS
436 /* Memory bandwidth needed for this plane. This is expressed in
442 static inline struct vc4_plane_state *
443 to_vc4_plane_state(struct drm_plane_state *state)
445 return container_of(state, struct vc4_plane_state, base);
448 enum vc4_encoder_type {
449 VC4_ENCODER_TYPE_NONE,
450 VC4_ENCODER_TYPE_HDMI0,
451 VC4_ENCODER_TYPE_HDMI1,
452 VC4_ENCODER_TYPE_VEC,
453 VC4_ENCODER_TYPE_DSI0,
454 VC4_ENCODER_TYPE_DSI1,
455 VC4_ENCODER_TYPE_SMI,
456 VC4_ENCODER_TYPE_DPI,
460 struct drm_encoder base;
461 enum vc4_encoder_type type;
464 void (*pre_crtc_configure)(struct drm_encoder *encoder, struct drm_atomic_state *state);
465 void (*pre_crtc_enable)(struct drm_encoder *encoder, struct drm_atomic_state *state);
466 void (*post_crtc_enable)(struct drm_encoder *encoder, struct drm_atomic_state *state);
468 void (*post_crtc_disable)(struct drm_encoder *encoder, struct drm_atomic_state *state);
469 void (*post_crtc_powerdown)(struct drm_encoder *encoder, struct drm_atomic_state *state);
472 static inline struct vc4_encoder *
473 to_vc4_encoder(struct drm_encoder *encoder)
475 return container_of(encoder, struct vc4_encoder, base);
478 struct vc4_crtc_data {
479 /* Bitmask of channels (FIFOs) of the HVS that the output can source from */
480 unsigned int hvs_available_channels;
482 /* Which output of the HVS this pixelvalve sources from. */
487 struct vc4_crtc_data base;
489 /* Depth of the PixelValve FIFO in bytes */
490 unsigned int fifo_depth;
492 /* Number of pixels output per clock period */
495 enum vc4_encoder_type encoder_types[4];
496 const char *debugfs_name;
500 struct vc5_gamma_entry {
505 #define VC5_HVS_SET_GAMMA_ENTRY(x, c, g) (struct vc5_gamma_entry){ \
506 .x_c_terms = VC4_SET_FIELD((x), SCALER5_DSPGAMMA_OFF_X) | \
507 VC4_SET_FIELD((c), SCALER5_DSPGAMMA_OFF_C), \
512 struct drm_crtc base;
513 struct platform_device *pdev;
514 const struct vc4_crtc_data *data;
517 /* Timestamp at start of vblank irq - unaffected by lock delays. */
521 struct { /* VC4 gamma LUT */
526 struct { /* VC5 gamma PWL entries */
527 struct vc5_gamma_entry pwl_r[SCALER5_DSPGAMMA_NUM_POINTS];
528 struct vc5_gamma_entry pwl_g[SCALER5_DSPGAMMA_NUM_POINTS];
529 struct vc5_gamma_entry pwl_b[SCALER5_DSPGAMMA_NUM_POINTS];
530 struct vc5_gamma_entry pwl_a[SCALER5_DSPGAMMA_NUM_POINTS];
534 struct drm_pending_vblank_event *event;
536 struct debugfs_regset32 regset;
539 * @feeds_txp: True if the CRTC feeds our writeback controller.
544 * @irq_lock: Spinlock protecting the resources shared between
545 * the atomic code and our vblank handler.
550 * @current_dlist: Start offset of the display list currently
551 * set in the HVS for that CRTC. Protected by @irq_lock, and
552 * copied in vc4_hvs_update_dlist() for the CRTC interrupt
553 * handler to have access to that value.
555 unsigned int current_dlist;
558 * @current_hvs_channel: HVS channel currently assigned to the
559 * CRTC. Protected by @irq_lock, and copied in
560 * vc4_hvs_atomic_begin() for the CRTC interrupt handler to have
561 * access to that value.
563 unsigned int current_hvs_channel;
566 static inline struct vc4_crtc *
567 to_vc4_crtc(struct drm_crtc *crtc)
569 return container_of(crtc, struct vc4_crtc, base);
572 static inline const struct vc4_crtc_data *
573 vc4_crtc_to_vc4_crtc_data(const struct vc4_crtc *crtc)
578 static inline const struct vc4_pv_data *
579 vc4_crtc_to_vc4_pv_data(const struct vc4_crtc *crtc)
581 const struct vc4_crtc_data *data = vc4_crtc_to_vc4_crtc_data(crtc);
583 return container_of(data, struct vc4_pv_data, base);
586 struct drm_connector *vc4_get_crtc_connector(struct drm_crtc *crtc,
587 struct drm_crtc_state *state);
589 struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc,
590 struct drm_crtc_state *state);
592 struct vc4_crtc_state {
593 struct drm_crtc_state base;
594 /* Dlist area for this CRTC configuration. */
595 struct drm_mm_node mm;
597 unsigned int assigned_channel;
599 struct drm_connector_tv_margins margins;
601 unsigned long hvs_load;
603 /* Transitional state below, only valid during atomic commits */
607 #define VC4_HVS_CHANNEL_DISABLED ((unsigned int)-1)
609 static inline struct vc4_crtc_state *
610 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
612 return container_of(crtc_state, struct vc4_crtc_state, base);
615 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
616 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
617 #define HVS_READ(offset) readl(hvs->regs + offset)
618 #define HVS_WRITE(offset, val) writel(val, hvs->regs + offset)
620 #define VC4_REG32(reg) { .name = #reg, .offset = reg }
622 struct vc4_exec_info {
625 /* Sequence number for this bin/render job. */
628 /* Latest write_seqno of any BO that binning depends on. */
629 uint64_t bin_dep_seqno;
631 struct dma_fence *fence;
633 /* Last current addresses the hardware was processing when the
634 * hangcheck timer checked on us.
636 uint32_t last_ct0ca, last_ct1ca;
638 /* Kernel-space copy of the ioctl arguments */
639 struct drm_vc4_submit_cl *args;
641 /* This is the array of BOs that were looked up at the start of exec.
642 * Command validation will use indices into this array.
644 struct drm_gem_cma_object **bo;
647 /* List of BOs that are being written by the RCL. Other than
648 * the binner temporary storage, this is all the BOs written
651 struct drm_gem_cma_object *rcl_write_bo[4];
652 uint32_t rcl_write_bo_count;
654 /* Pointers for our position in vc4->job_list */
655 struct list_head head;
657 /* List of other BOs used in the job that need to be released
658 * once the job is complete.
660 struct list_head unref_list;
662 /* Current unvalidated indices into @bo loaded by the non-hardware
663 * VC4_PACKET_GEM_HANDLES.
665 uint32_t bo_index[2];
667 /* This is the BO where we store the validated command lists, shader
668 * records, and uniforms.
670 struct drm_gem_cma_object *exec_bo;
673 * This tracks the per-shader-record state (packet 64) that
674 * determines the length of the shader record and the offset
675 * it's expected to be found at. It gets read in from the
678 struct vc4_shader_state {
680 /* Maximum vertex index referenced by any primitive using this
686 /** How many shader states the user declared they were using. */
687 uint32_t shader_state_size;
688 /** How many shader state records the validator has seen. */
689 uint32_t shader_state_count;
691 bool found_tile_binning_mode_config_packet;
692 bool found_start_tile_binning_packet;
693 bool found_increment_semaphore_packet;
695 uint8_t bin_tiles_x, bin_tiles_y;
696 /* Physical address of the start of the tile alloc array
697 * (where each tile's binned CL will start)
699 uint32_t tile_alloc_offset;
700 /* Bitmask of which binner slots are freed when this job completes. */
704 * Computed addresses pointing into exec_bo where we start the
705 * bin thread (ct0) and render thread (ct1).
707 uint32_t ct0ca, ct0ea;
708 uint32_t ct1ca, ct1ea;
710 /* Pointer to the unvalidated bin CL (if present). */
713 /* Pointers to the shader recs. These paddr gets incremented as CL
714 * packets are relocated in validate_gl_shader_state, and the vaddrs
715 * (u and v) get incremented and size decremented as the shader recs
716 * themselves are validated.
720 uint32_t shader_rec_p;
721 uint32_t shader_rec_size;
723 /* Pointers to the uniform data. These pointers are incremented, and
724 * size decremented, as each batch of uniforms is uploaded.
729 uint32_t uniforms_size;
731 /* Pointer to a performance monitor object if the user requested it,
734 struct vc4_perfmon *perfmon;
736 /* Whether the exec has taken a reference to the binner BO, which should
737 * happen with a VC4_PACKET_TILE_BINNING_MODE_CONFIG packet.
742 /* Per-open file private data. Any driver-specific resource that has to be
743 * released when the DRM file is closed should be placed here.
756 static inline struct vc4_exec_info *
757 vc4_first_bin_job(struct vc4_dev *vc4)
759 return list_first_entry_or_null(&vc4->bin_job_list,
760 struct vc4_exec_info, head);
763 static inline struct vc4_exec_info *
764 vc4_first_render_job(struct vc4_dev *vc4)
766 return list_first_entry_or_null(&vc4->render_job_list,
767 struct vc4_exec_info, head);
770 static inline struct vc4_exec_info *
771 vc4_last_render_job(struct vc4_dev *vc4)
773 if (list_empty(&vc4->render_job_list))
775 return list_last_entry(&vc4->render_job_list,
776 struct vc4_exec_info, head);
780 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
783 * This will be used at draw time to relocate the reference to the texture
784 * contents in p0, and validate that the offset combined with
785 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
786 * Note that the hardware treats unprovided config parameters as 0, so not all
787 * of them need to be set up for every texure sample, and we'll store ~0 as
788 * the offset to mark the unused ones.
790 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
791 * Setup") for definitions of the texture parameters.
793 struct vc4_texture_sample_info {
795 uint32_t p_offset[4];
799 * struct vc4_validated_shader_info - information about validated shaders that
800 * needs to be used from command list validation.
802 * For a given shader, each time a shader state record references it, we need
803 * to verify that the shader doesn't read more uniforms than the shader state
804 * record's uniform BO pointer can provide, and we need to apply relocations
805 * and validate the shader state record's uniforms that define the texture
808 struct vc4_validated_shader_info {
809 uint32_t uniforms_size;
810 uint32_t uniforms_src_size;
811 uint32_t num_texture_samples;
812 struct vc4_texture_sample_info *texture_samples;
814 uint32_t num_uniform_addr_offsets;
815 uint32_t *uniform_addr_offsets;
821 * __wait_for - magic wait macro
823 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
824 * important that we check the condition again after having timed out, since the
825 * timeout could be due to preemption or similar and we've never had a chance to
826 * check the condition before the timeout.
828 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
829 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
830 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
834 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
836 /* Guarantee COND check prior to timeout */ \
843 ret__ = -ETIMEDOUT; \
846 usleep_range(wait__, wait__ * 2); \
847 if (wait__ < (Wmax)) \
853 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
855 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
858 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
859 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
860 bool from_cache, enum vc4_kernel_bo_type type);
861 int vc4_bo_dumb_create(struct drm_file *file_priv,
862 struct drm_device *dev,
863 struct drm_mode_create_dumb *args);
864 int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
865 struct drm_file *file_priv);
866 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
867 struct drm_file *file_priv);
868 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
869 struct drm_file *file_priv);
870 int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
871 struct drm_file *file_priv);
872 int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
873 struct drm_file *file_priv);
874 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
875 struct drm_file *file_priv);
876 int vc4_label_bo_ioctl(struct drm_device *dev, void *data,
877 struct drm_file *file_priv);
878 int vc4_bo_cache_init(struct drm_device *dev);
879 int vc4_bo_inc_usecnt(struct vc4_bo *bo);
880 void vc4_bo_dec_usecnt(struct vc4_bo *bo);
881 void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo);
882 void vc4_bo_remove_from_purgeable_pool(struct vc4_bo *bo);
885 extern struct platform_driver vc4_crtc_driver;
886 int vc4_crtc_disable_at_boot(struct drm_crtc *crtc);
887 int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
888 const struct drm_crtc_funcs *crtc_funcs,
889 const struct drm_crtc_helper_funcs *crtc_helper_funcs);
890 void vc4_crtc_destroy(struct drm_crtc *crtc);
891 int vc4_page_flip(struct drm_crtc *crtc,
892 struct drm_framebuffer *fb,
893 struct drm_pending_vblank_event *event,
895 struct drm_modeset_acquire_ctx *ctx);
896 struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc);
897 void vc4_crtc_destroy_state(struct drm_crtc *crtc,
898 struct drm_crtc_state *state);
899 void vc4_crtc_reset(struct drm_crtc *crtc);
900 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc);
901 void vc4_crtc_get_margins(struct drm_crtc_state *state,
902 unsigned int *left, unsigned int *right,
903 unsigned int *top, unsigned int *bottom);
906 void vc4_debugfs_init(struct drm_minor *minor);
907 #ifdef CONFIG_DEBUG_FS
908 void vc4_debugfs_add_file(struct drm_device *drm,
909 const char *filename,
910 int (*show)(struct seq_file*, void*),
912 void vc4_debugfs_add_regset32(struct drm_device *drm,
913 const char *filename,
914 struct debugfs_regset32 *regset);
916 static inline void vc4_debugfs_add_file(struct drm_device *drm,
917 const char *filename,
918 int (*show)(struct seq_file*, void*),
923 static inline void vc4_debugfs_add_regset32(struct drm_device *drm,
924 const char *filename,
925 struct debugfs_regset32 *regset)
931 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
932 int vc4_dumb_fixup_args(struct drm_mode_create_dumb *args);
935 extern struct platform_driver vc4_dpi_driver;
938 extern struct platform_driver vc4_dsi_driver;
941 extern const struct dma_fence_ops vc4_fence_ops;
943 /* vc4_firmware_kms.c */
944 extern struct platform_driver vc4_firmware_kms_driver;
947 int vc4_gem_init(struct drm_device *dev);
948 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
949 struct drm_file *file_priv);
950 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
951 struct drm_file *file_priv);
952 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
953 struct drm_file *file_priv);
954 void vc4_submit_next_bin_job(struct drm_device *dev);
955 void vc4_submit_next_render_job(struct drm_device *dev);
956 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
957 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
958 uint64_t timeout_ns, bool interruptible);
959 void vc4_job_handle_completed(struct vc4_dev *vc4);
960 int vc4_queue_seqno_cb(struct drm_device *dev,
961 struct vc4_seqno_cb *cb, uint64_t seqno,
962 void (*func)(struct vc4_seqno_cb *cb));
963 int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data,
964 struct drm_file *file_priv);
967 extern struct platform_driver vc4_hdmi_driver;
970 extern struct platform_driver vc4_vec_driver;
973 extern struct platform_driver vc4_txp_driver;
976 void vc4_irq_enable(struct drm_device *dev);
977 void vc4_irq_disable(struct drm_device *dev);
978 int vc4_irq_install(struct drm_device *dev, int irq);
979 void vc4_irq_uninstall(struct drm_device *dev);
980 void vc4_irq_reset(struct drm_device *dev);
983 extern struct platform_driver vc4_hvs_driver;
984 void vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int output);
985 int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output);
986 u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo);
987 int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state);
988 void vc4_hvs_atomic_begin(struct drm_crtc *crtc, struct drm_atomic_state *state);
989 void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state);
990 void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state);
991 void vc4_hvs_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state);
992 void vc4_hvs_dump_state(struct vc4_hvs *hvs);
993 void vc4_hvs_unmask_underrun(struct vc4_hvs *hvs, int channel);
994 void vc4_hvs_mask_underrun(struct vc4_hvs *hvs, int channel);
997 int vc4_kms_load(struct drm_device *dev);
1000 struct drm_plane *vc4_plane_init(struct drm_device *dev,
1001 enum drm_plane_type type);
1002 int vc4_plane_create_additional_planes(struct drm_device *dev);
1003 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
1004 u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
1005 void vc4_plane_async_set_fb(struct drm_plane *plane,
1006 struct drm_framebuffer *fb);
1009 extern struct platform_driver vc4_v3d_driver;
1010 extern const struct of_device_id vc4_v3d_dt_match[];
1011 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4);
1012 int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used);
1013 void vc4_v3d_bin_bo_put(struct vc4_dev *vc4);
1014 int vc4_v3d_pm_get(struct vc4_dev *vc4);
1015 void vc4_v3d_pm_put(struct vc4_dev *vc4);
1017 /* vc4_validate.c */
1019 vc4_validate_bin_cl(struct drm_device *dev,
1022 struct vc4_exec_info *exec);
1025 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
1027 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
1030 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
1032 bool vc4_check_tex_size(struct vc4_exec_info *exec,
1033 struct drm_gem_cma_object *fbo,
1034 uint32_t offset, uint8_t tiling_format,
1035 uint32_t width, uint32_t height, uint8_t cpp);
1037 /* vc4_validate_shader.c */
1038 struct vc4_validated_shader_info *
1039 vc4_validate_shader(struct drm_gem_cma_object *shader_obj);
1042 void vc4_perfmon_get(struct vc4_perfmon *perfmon);
1043 void vc4_perfmon_put(struct vc4_perfmon *perfmon);
1044 void vc4_perfmon_start(struct vc4_dev *vc4, struct vc4_perfmon *perfmon);
1045 void vc4_perfmon_stop(struct vc4_dev *vc4, struct vc4_perfmon *perfmon,
1047 struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id);
1048 void vc4_perfmon_open_file(struct vc4_file *vc4file);
1049 void vc4_perfmon_close_file(struct vc4_file *vc4file);
1050 int vc4_perfmon_create_ioctl(struct drm_device *dev, void *data,
1051 struct drm_file *file_priv);
1052 int vc4_perfmon_destroy_ioctl(struct drm_device *dev, void *data,
1053 struct drm_file *file_priv);
1054 int vc4_perfmon_get_values_ioctl(struct drm_device *dev, void *data,
1055 struct drm_file *file_priv);
1057 #endif /* _VC4_DRV_H_ */