1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2015 Broadcom
8 #include <linux/delay.h>
9 #include <linux/refcount.h>
10 #include <linux/uaccess.h>
12 #include <drm/drm_atomic.h>
13 #include <drm/drm_debugfs.h>
14 #include <drm/drm_device.h>
15 #include <drm/drm_encoder.h>
16 #include <drm/drm_gem_cma_helper.h>
17 #include <drm/drm_managed.h>
18 #include <drm/drm_mm.h>
19 #include <drm/drm_modeset_lock.h>
21 #include "uapi/drm/vc4_drm.h"
25 struct drm_gem_object;
27 /* Don't forget to update vc4_bo.c: bo_type_names[] when adding to
30 enum vc4_kernel_bo_type {
31 /* Any kernel allocation (gem_create_object hook) before it
32 * gets another type set.
36 VC4_BO_TYPE_V3D_SHADER,
41 VC4_BO_TYPE_KERNEL_CACHE,
45 /* Performance monitor object. The perform lifetime is controlled by userspace
46 * using perfmon related ioctls. A perfmon can be attached to a submit_cl
47 * request, and when this is the case, HW perf counters will be activated just
48 * before the submit_cl is submitted to the GPU and disabled when the job is
49 * done. This way, only events related to a specific job will be counted.
52 /* Tracks the number of users of the perfmon, when this counter reaches
53 * zero the perfmon is destroyed.
57 /* Number of counters activated in this perfmon instance
58 * (should be less than DRM_VC4_MAX_PERF_COUNTERS).
62 /* Events counted by the HW perf counters. */
63 u8 events[DRM_VC4_MAX_PERF_COUNTERS];
65 /* Storage for counter values. Counters are incremented by the HW
66 * perf counter values every time the perfmon is attached to a GPU job.
67 * This way, perfmon users don't have to retrieve the results after
68 * each job if they want to track events covering several submissions.
69 * Note that counter values can't be reset, but you can fake a reset by
70 * destroying the perfmon and creating a new one.
76 struct drm_device base;
81 struct rpi_firmware *firmware;
88 struct vc4_fkms *fkms;
90 struct vc4_hang_state *hang_state;
92 /* The kernel-space BO cache. Tracks buffers that have been
93 * unreferenced by all other users (refcounts of 0!) but not
94 * yet freed, so we can do cheap allocations.
97 /* Array of list heads for entries in the BO cache,
98 * based on number of pages, so we can do O(1) lookups
99 * in the cache when allocating.
101 struct list_head *size_list;
102 uint32_t size_list_size;
104 /* List of all BOs in the cache, ordered by age, so we
105 * can do O(1) lookups when trying to free old
108 struct list_head time_list;
109 struct work_struct time_work;
110 struct timer_list time_timer;
120 /* Protects bo_cache and bo_labels. */
121 struct mutex bo_lock;
123 /* Purgeable BO pool. All BOs in this pool can have their memory
124 * reclaimed if the driver is unable to allocate new BOs. We also
125 * keep stats related to the purge mechanism here.
128 struct list_head list;
131 unsigned int purged_num;
136 uint64_t dma_fence_context;
138 /* Sequence number for the last job queued in bin_job_list.
139 * Starts at 0 (no jobs emitted).
143 /* Sequence number for the last completed job on the GPU.
144 * Starts at 0 (no jobs completed).
146 uint64_t finished_seqno;
148 /* List of all struct vc4_exec_info for jobs to be executed in
149 * the binner. The first job in the list is the one currently
150 * programmed into ct0ca for execution.
152 struct list_head bin_job_list;
154 /* List of all struct vc4_exec_info for jobs that have
155 * completed binning and are ready for rendering. The first
156 * job in the list is the one currently programmed into ct1ca
159 struct list_head render_job_list;
161 /* List of the finished vc4_exec_infos waiting to be freed by
164 struct list_head job_done_list;
165 /* Spinlock used to synchronize the job_list and seqno
166 * accesses between the IRQ handler and GEM ioctls.
169 wait_queue_head_t job_wait_queue;
170 struct work_struct job_done_work;
172 /* Used to track the active perfmon if any. Access to this field is
173 * protected by job_lock.
175 struct vc4_perfmon *active_perfmon;
177 /* List of struct vc4_seqno_cb for callbacks to be made from a
178 * workqueue when the given seqno is passed.
180 struct list_head seqno_cb_list;
182 /* The memory used for storing binner tile alloc, tile state,
183 * and overflow memory allocations. This is freed when V3D
186 struct vc4_bo *bin_bo;
188 /* Size of blocks allocated within bin_bo. */
189 uint32_t bin_alloc_size;
191 /* Bitmask of the bin_alloc_size chunks in bin_bo that are
194 uint32_t bin_alloc_used;
196 /* Bitmask of the current bin_alloc used for overflow memory. */
197 uint32_t bin_alloc_overflow;
199 /* Incremented when an underrun error happened after an atomic commit.
200 * This is particularly useful to detect when a specific modeset is too
201 * demanding in term of memory or HVS bandwidth which is hard to guess
202 * at atomic check time.
206 struct work_struct overflow_mem_work;
210 /* Set to true when the load tracker is active. */
211 bool load_tracker_enabled;
213 /* Mutex controlling the power refcount. */
214 struct mutex power_lock;
217 struct timer_list timer;
218 struct work_struct reset_work;
221 struct drm_modeset_lock ctm_state_lock;
222 struct drm_private_obj ctm_manager;
223 struct drm_private_obj hvs_channels;
224 struct drm_private_obj load_tracker;
226 /* List of vc4_debugfs_info_entry for adding to debugfs once
227 * the minor is available (after drm_dev_register()).
229 struct list_head debugfs_list;
231 /* Mutex for binner bo allocation. */
232 struct mutex bin_bo_lock;
233 /* Reference count for our binner bo. */
234 struct kref bin_bo_kref;
237 static inline struct vc4_dev *
238 to_vc4_dev(struct drm_device *dev)
240 return container_of(dev, struct vc4_dev, base);
244 struct drm_gem_cma_object base;
246 /* seqno of the last job to render using this BO. */
249 /* seqno of the last job to use the RCL to write to this BO.
251 * Note that this doesn't include binner overflow memory
254 uint64_t write_seqno;
258 /* List entry for the BO's position in either
259 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
261 struct list_head unref_head;
263 /* Time in jiffies when the BO was put in vc4->bo_cache. */
264 unsigned long free_time;
266 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
267 struct list_head size_head;
269 /* Struct for shader validation state, if created by
270 * DRM_IOCTL_VC4_CREATE_SHADER_BO.
272 struct vc4_validated_shader_info *validated_shader;
274 /* One of enum vc4_kernel_bo_type, or VC4_BO_TYPE_COUNT + i
275 * for user-allocated labels.
279 /* Count the number of active users. This is needed to determine
280 * whether we can move the BO to the purgeable list or not (when the BO
281 * is used by the GPU or the display engine we can't purge it).
285 /* Store purgeable/purged state here */
287 struct mutex madv_lock;
290 static inline struct vc4_bo *
291 to_vc4_bo(struct drm_gem_object *bo)
293 return container_of(to_drm_gem_cma_obj(bo), struct vc4_bo, base);
297 struct dma_fence base;
298 struct drm_device *dev;
299 /* vc4 seqno for signaled() test */
303 static inline struct vc4_fence *
304 to_vc4_fence(struct dma_fence *fence)
306 return container_of(fence, struct vc4_fence, base);
309 struct vc4_seqno_cb {
310 struct work_struct work;
312 void (*func)(struct vc4_seqno_cb *cb);
317 struct platform_device *pdev;
320 struct debugfs_regset32 regset;
324 struct platform_device *pdev;
328 struct clk *core_clk;
330 /* Memory manager for CRTCs to allocate space in the display
331 * list. Units are dwords.
333 struct drm_mm dlist_mm;
334 /* Memory manager for the LBM memory used by HVS scaling. */
335 struct drm_mm lbm_mm;
338 struct drm_mm_node mitchell_netravali_filter;
340 struct debugfs_regset32 regset;
342 /* HVS version 5 flag, therefore requires updated dlist structures */
347 struct drm_plane base;
350 static inline struct vc4_plane *
351 to_vc4_plane(struct drm_plane *plane)
353 return container_of(plane, struct vc4_plane, base);
356 enum vc4_scaling_mode {
362 struct vc4_plane_state {
363 struct drm_plane_state base;
364 /* System memory copy of the display list for this element, computed
365 * at atomic_check time.
368 u32 dlist_size; /* Number of dwords allocated for the display list */
369 u32 dlist_count; /* Number of used dwords in the display list. */
371 /* Offset in the dlist to various words, for pageflip or
379 /* Offset where the plane's dlist was last stored in the
380 * hardware at vc4_crtc_atomic_flush() time.
382 u32 __iomem *hw_dlist;
384 /* Clipped coordinates of the plane on the display. */
385 int crtc_x, crtc_y, crtc_w, crtc_h;
386 /* Clipped area being scanned from in the FB in u16.16 format */
389 u32 src_w[2], src_h[2];
391 /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
392 enum vc4_scaling_mode x_scaling[2], y_scaling[2];
396 /* Offset to start scanning out from the start of the plane's
401 /* Our allocation in LBM for temporary storage during scaling. */
402 struct drm_mm_node lbm;
404 /* Set when the plane has per-pixel alpha content or does not cover
405 * the entire screen. This is a hint to the CRTC that it might need
406 * to enable background color fill.
410 /* Mark the dlist as initialized. Useful to avoid initializing it twice
411 * when async update is not possible.
413 bool dlist_initialized;
415 /* Load of this plane on the HVS block. The load is expressed in HVS
420 /* Memory bandwidth needed for this plane. This is expressed in
426 static inline struct vc4_plane_state *
427 to_vc4_plane_state(struct drm_plane_state *state)
429 return container_of(state, struct vc4_plane_state, base);
432 enum vc4_encoder_type {
433 VC4_ENCODER_TYPE_NONE,
434 VC4_ENCODER_TYPE_HDMI0,
435 VC4_ENCODER_TYPE_HDMI1,
436 VC4_ENCODER_TYPE_VEC,
437 VC4_ENCODER_TYPE_DSI0,
438 VC4_ENCODER_TYPE_DSI1,
439 VC4_ENCODER_TYPE_SMI,
440 VC4_ENCODER_TYPE_DPI,
444 struct drm_encoder base;
445 enum vc4_encoder_type type;
448 void (*pre_crtc_configure)(struct drm_encoder *encoder, struct drm_atomic_state *state);
449 void (*pre_crtc_enable)(struct drm_encoder *encoder, struct drm_atomic_state *state);
450 void (*post_crtc_enable)(struct drm_encoder *encoder, struct drm_atomic_state *state);
452 void (*post_crtc_disable)(struct drm_encoder *encoder, struct drm_atomic_state *state);
453 void (*post_crtc_powerdown)(struct drm_encoder *encoder, struct drm_atomic_state *state);
456 static inline struct vc4_encoder *
457 to_vc4_encoder(struct drm_encoder *encoder)
459 return container_of(encoder, struct vc4_encoder, base);
462 struct vc4_crtc_data {
463 /* Bitmask of channels (FIFOs) of the HVS that the output can source from */
464 unsigned int hvs_available_channels;
466 /* Which output of the HVS this pixelvalve sources from. */
471 struct vc4_crtc_data base;
473 /* Depth of the PixelValve FIFO in bytes */
474 unsigned int fifo_depth;
476 /* Number of pixels output per clock period */
479 enum vc4_encoder_type encoder_types[4];
480 const char *debugfs_name;
484 struct vc5_gamma_entry {
489 #define VC5_HVS_SET_GAMMA_ENTRY(x, c, g) (struct vc5_gamma_entry){ \
490 .x_c_terms = VC4_SET_FIELD((x), SCALER5_DSPGAMMA_OFF_X) | \
491 VC4_SET_FIELD((c), SCALER5_DSPGAMMA_OFF_C), \
496 struct drm_crtc base;
497 struct platform_device *pdev;
498 const struct vc4_crtc_data *data;
501 /* Timestamp at start of vblank irq - unaffected by lock delays. */
505 struct { /* VC4 gamma LUT */
510 struct { /* VC5 gamma PWL entries */
511 struct vc5_gamma_entry pwl_r[SCALER5_DSPGAMMA_NUM_POINTS];
512 struct vc5_gamma_entry pwl_g[SCALER5_DSPGAMMA_NUM_POINTS];
513 struct vc5_gamma_entry pwl_b[SCALER5_DSPGAMMA_NUM_POINTS];
514 struct vc5_gamma_entry pwl_a[SCALER5_DSPGAMMA_NUM_POINTS];
518 struct drm_pending_vblank_event *event;
520 struct debugfs_regset32 regset;
523 * @feeds_txp: True if the CRTC feeds our writeback controller.
528 * @irq_lock: Spinlock protecting the resources shared between
529 * the atomic code and our vblank handler.
534 * @current_dlist: Start offset of the display list currently
535 * set in the HVS for that CRTC. Protected by @irq_lock, and
536 * copied in vc4_hvs_update_dlist() for the CRTC interrupt
537 * handler to have access to that value.
539 unsigned int current_dlist;
542 * @current_hvs_channel: HVS channel currently assigned to the
543 * CRTC. Protected by @irq_lock, and copied in
544 * vc4_hvs_atomic_begin() for the CRTC interrupt handler to have
545 * access to that value.
547 unsigned int current_hvs_channel;
550 static inline struct vc4_crtc *
551 to_vc4_crtc(struct drm_crtc *crtc)
553 return container_of(crtc, struct vc4_crtc, base);
556 static inline const struct vc4_crtc_data *
557 vc4_crtc_to_vc4_crtc_data(const struct vc4_crtc *crtc)
562 static inline const struct vc4_pv_data *
563 vc4_crtc_to_vc4_pv_data(const struct vc4_crtc *crtc)
565 const struct vc4_crtc_data *data = vc4_crtc_to_vc4_crtc_data(crtc);
567 return container_of(data, struct vc4_pv_data, base);
570 struct drm_connector *vc4_get_crtc_connector(struct drm_crtc *crtc,
571 struct drm_crtc_state *state);
573 struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc,
574 struct drm_crtc_state *state);
576 struct vc4_crtc_state {
577 struct drm_crtc_state base;
578 /* Dlist area for this CRTC configuration. */
579 struct drm_mm_node mm;
581 unsigned int assigned_channel;
583 struct drm_connector_tv_margins margins;
585 unsigned long hvs_load;
587 /* Transitional state below, only valid during atomic commits */
591 #define VC4_HVS_CHANNEL_DISABLED ((unsigned int)-1)
593 static inline struct vc4_crtc_state *
594 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
596 return container_of(crtc_state, struct vc4_crtc_state, base);
599 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
600 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
601 #define HVS_READ(offset) readl(hvs->regs + offset)
602 #define HVS_WRITE(offset, val) writel(val, hvs->regs + offset)
604 #define VC4_REG32(reg) { .name = #reg, .offset = reg }
606 struct vc4_exec_info {
607 /* Sequence number for this bin/render job. */
610 /* Latest write_seqno of any BO that binning depends on. */
611 uint64_t bin_dep_seqno;
613 struct dma_fence *fence;
615 /* Last current addresses the hardware was processing when the
616 * hangcheck timer checked on us.
618 uint32_t last_ct0ca, last_ct1ca;
620 /* Kernel-space copy of the ioctl arguments */
621 struct drm_vc4_submit_cl *args;
623 /* This is the array of BOs that were looked up at the start of exec.
624 * Command validation will use indices into this array.
626 struct drm_gem_cma_object **bo;
629 /* List of BOs that are being written by the RCL. Other than
630 * the binner temporary storage, this is all the BOs written
633 struct drm_gem_cma_object *rcl_write_bo[4];
634 uint32_t rcl_write_bo_count;
636 /* Pointers for our position in vc4->job_list */
637 struct list_head head;
639 /* List of other BOs used in the job that need to be released
640 * once the job is complete.
642 struct list_head unref_list;
644 /* Current unvalidated indices into @bo loaded by the non-hardware
645 * VC4_PACKET_GEM_HANDLES.
647 uint32_t bo_index[2];
649 /* This is the BO where we store the validated command lists, shader
650 * records, and uniforms.
652 struct drm_gem_cma_object *exec_bo;
655 * This tracks the per-shader-record state (packet 64) that
656 * determines the length of the shader record and the offset
657 * it's expected to be found at. It gets read in from the
660 struct vc4_shader_state {
662 /* Maximum vertex index referenced by any primitive using this
668 /** How many shader states the user declared they were using. */
669 uint32_t shader_state_size;
670 /** How many shader state records the validator has seen. */
671 uint32_t shader_state_count;
673 bool found_tile_binning_mode_config_packet;
674 bool found_start_tile_binning_packet;
675 bool found_increment_semaphore_packet;
677 uint8_t bin_tiles_x, bin_tiles_y;
678 /* Physical address of the start of the tile alloc array
679 * (where each tile's binned CL will start)
681 uint32_t tile_alloc_offset;
682 /* Bitmask of which binner slots are freed when this job completes. */
686 * Computed addresses pointing into exec_bo where we start the
687 * bin thread (ct0) and render thread (ct1).
689 uint32_t ct0ca, ct0ea;
690 uint32_t ct1ca, ct1ea;
692 /* Pointer to the unvalidated bin CL (if present). */
695 /* Pointers to the shader recs. These paddr gets incremented as CL
696 * packets are relocated in validate_gl_shader_state, and the vaddrs
697 * (u and v) get incremented and size decremented as the shader recs
698 * themselves are validated.
702 uint32_t shader_rec_p;
703 uint32_t shader_rec_size;
705 /* Pointers to the uniform data. These pointers are incremented, and
706 * size decremented, as each batch of uniforms is uploaded.
711 uint32_t uniforms_size;
713 /* Pointer to a performance monitor object if the user requested it,
716 struct vc4_perfmon *perfmon;
718 /* Whether the exec has taken a reference to the binner BO, which should
719 * happen with a VC4_PACKET_TILE_BINNING_MODE_CONFIG packet.
724 /* Per-open file private data. Any driver-specific resource that has to be
725 * released when the DRM file is closed should be placed here.
736 static inline struct vc4_exec_info *
737 vc4_first_bin_job(struct vc4_dev *vc4)
739 return list_first_entry_or_null(&vc4->bin_job_list,
740 struct vc4_exec_info, head);
743 static inline struct vc4_exec_info *
744 vc4_first_render_job(struct vc4_dev *vc4)
746 return list_first_entry_or_null(&vc4->render_job_list,
747 struct vc4_exec_info, head);
750 static inline struct vc4_exec_info *
751 vc4_last_render_job(struct vc4_dev *vc4)
753 if (list_empty(&vc4->render_job_list))
755 return list_last_entry(&vc4->render_job_list,
756 struct vc4_exec_info, head);
760 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
763 * This will be used at draw time to relocate the reference to the texture
764 * contents in p0, and validate that the offset combined with
765 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
766 * Note that the hardware treats unprovided config parameters as 0, so not all
767 * of them need to be set up for every texure sample, and we'll store ~0 as
768 * the offset to mark the unused ones.
770 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
771 * Setup") for definitions of the texture parameters.
773 struct vc4_texture_sample_info {
775 uint32_t p_offset[4];
779 * struct vc4_validated_shader_info - information about validated shaders that
780 * needs to be used from command list validation.
782 * For a given shader, each time a shader state record references it, we need
783 * to verify that the shader doesn't read more uniforms than the shader state
784 * record's uniform BO pointer can provide, and we need to apply relocations
785 * and validate the shader state record's uniforms that define the texture
788 struct vc4_validated_shader_info {
789 uint32_t uniforms_size;
790 uint32_t uniforms_src_size;
791 uint32_t num_texture_samples;
792 struct vc4_texture_sample_info *texture_samples;
794 uint32_t num_uniform_addr_offsets;
795 uint32_t *uniform_addr_offsets;
801 * __wait_for - magic wait macro
803 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
804 * important that we check the condition again after having timed out, since the
805 * timeout could be due to preemption or similar and we've never had a chance to
806 * check the condition before the timeout.
808 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
809 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
810 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
814 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
816 /* Guarantee COND check prior to timeout */ \
823 ret__ = -ETIMEDOUT; \
826 usleep_range(wait__, wait__ * 2); \
827 if (wait__ < (Wmax)) \
833 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
835 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
838 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
839 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
840 bool from_cache, enum vc4_kernel_bo_type type);
841 int vc4_dumb_create(struct drm_file *file_priv,
842 struct drm_device *dev,
843 struct drm_mode_create_dumb *args);
844 int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
845 struct drm_file *file_priv);
846 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
847 struct drm_file *file_priv);
848 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
849 struct drm_file *file_priv);
850 int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
851 struct drm_file *file_priv);
852 int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
853 struct drm_file *file_priv);
854 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
855 struct drm_file *file_priv);
856 int vc4_label_bo_ioctl(struct drm_device *dev, void *data,
857 struct drm_file *file_priv);
858 int vc4_bo_cache_init(struct drm_device *dev);
859 int vc4_bo_inc_usecnt(struct vc4_bo *bo);
860 void vc4_bo_dec_usecnt(struct vc4_bo *bo);
861 void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo);
862 void vc4_bo_remove_from_purgeable_pool(struct vc4_bo *bo);
865 extern struct platform_driver vc4_crtc_driver;
866 int vc4_crtc_disable_at_boot(struct drm_crtc *crtc);
867 int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
868 const struct drm_crtc_funcs *crtc_funcs,
869 const struct drm_crtc_helper_funcs *crtc_helper_funcs);
870 void vc4_crtc_destroy(struct drm_crtc *crtc);
871 int vc4_page_flip(struct drm_crtc *crtc,
872 struct drm_framebuffer *fb,
873 struct drm_pending_vblank_event *event,
875 struct drm_modeset_acquire_ctx *ctx);
876 struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc);
877 void vc4_crtc_destroy_state(struct drm_crtc *crtc,
878 struct drm_crtc_state *state);
879 void vc4_crtc_reset(struct drm_crtc *crtc);
880 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc);
881 void vc4_crtc_get_margins(struct drm_crtc_state *state,
882 unsigned int *left, unsigned int *right,
883 unsigned int *top, unsigned int *bottom);
886 void vc4_debugfs_init(struct drm_minor *minor);
887 #ifdef CONFIG_DEBUG_FS
888 void vc4_debugfs_add_file(struct drm_device *drm,
889 const char *filename,
890 int (*show)(struct seq_file*, void*),
892 void vc4_debugfs_add_regset32(struct drm_device *drm,
893 const char *filename,
894 struct debugfs_regset32 *regset);
896 static inline void vc4_debugfs_add_file(struct drm_device *drm,
897 const char *filename,
898 int (*show)(struct seq_file*, void*),
903 static inline void vc4_debugfs_add_regset32(struct drm_device *drm,
904 const char *filename,
905 struct debugfs_regset32 *regset)
911 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
914 extern struct platform_driver vc4_dpi_driver;
917 extern struct platform_driver vc4_dsi_driver;
920 extern const struct dma_fence_ops vc4_fence_ops;
922 /* vc4_firmware_kms.c */
923 extern struct platform_driver vc4_firmware_kms_driver;
926 int vc4_gem_init(struct drm_device *dev);
927 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
928 struct drm_file *file_priv);
929 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
930 struct drm_file *file_priv);
931 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
932 struct drm_file *file_priv);
933 void vc4_submit_next_bin_job(struct drm_device *dev);
934 void vc4_submit_next_render_job(struct drm_device *dev);
935 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
936 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
937 uint64_t timeout_ns, bool interruptible);
938 void vc4_job_handle_completed(struct vc4_dev *vc4);
939 int vc4_queue_seqno_cb(struct drm_device *dev,
940 struct vc4_seqno_cb *cb, uint64_t seqno,
941 void (*func)(struct vc4_seqno_cb *cb));
942 int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data,
943 struct drm_file *file_priv);
946 extern struct platform_driver vc4_hdmi_driver;
949 extern struct platform_driver vc4_vec_driver;
952 extern struct platform_driver vc4_txp_driver;
955 void vc4_irq_enable(struct drm_device *dev);
956 void vc4_irq_disable(struct drm_device *dev);
957 int vc4_irq_install(struct drm_device *dev, int irq);
958 void vc4_irq_uninstall(struct drm_device *dev);
959 void vc4_irq_reset(struct drm_device *dev);
962 extern struct platform_driver vc4_hvs_driver;
963 void vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int output);
964 int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output);
965 u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo);
966 int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state);
967 void vc4_hvs_atomic_begin(struct drm_crtc *crtc, struct drm_atomic_state *state);
968 void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state);
969 void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state);
970 void vc4_hvs_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state);
971 void vc4_hvs_dump_state(struct vc4_hvs *hvs);
972 void vc4_hvs_unmask_underrun(struct vc4_hvs *hvs, int channel);
973 void vc4_hvs_mask_underrun(struct vc4_hvs *hvs, int channel);
976 int vc4_kms_load(struct drm_device *dev);
979 struct drm_plane *vc4_plane_init(struct drm_device *dev,
980 enum drm_plane_type type);
981 int vc4_plane_create_additional_planes(struct drm_device *dev);
982 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
983 u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
984 void vc4_plane_async_set_fb(struct drm_plane *plane,
985 struct drm_framebuffer *fb);
988 extern struct platform_driver vc4_v3d_driver;
989 extern const struct of_device_id vc4_v3d_dt_match[];
990 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4);
991 int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used);
992 void vc4_v3d_bin_bo_put(struct vc4_dev *vc4);
993 int vc4_v3d_pm_get(struct vc4_dev *vc4);
994 void vc4_v3d_pm_put(struct vc4_dev *vc4);
998 vc4_validate_bin_cl(struct drm_device *dev,
1001 struct vc4_exec_info *exec);
1004 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
1006 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
1009 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
1011 bool vc4_check_tex_size(struct vc4_exec_info *exec,
1012 struct drm_gem_cma_object *fbo,
1013 uint32_t offset, uint8_t tiling_format,
1014 uint32_t width, uint32_t height, uint8_t cpp);
1016 /* vc4_validate_shader.c */
1017 struct vc4_validated_shader_info *
1018 vc4_validate_shader(struct drm_gem_cma_object *shader_obj);
1021 void vc4_perfmon_get(struct vc4_perfmon *perfmon);
1022 void vc4_perfmon_put(struct vc4_perfmon *perfmon);
1023 void vc4_perfmon_start(struct vc4_dev *vc4, struct vc4_perfmon *perfmon);
1024 void vc4_perfmon_stop(struct vc4_dev *vc4, struct vc4_perfmon *perfmon,
1026 struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id);
1027 void vc4_perfmon_open_file(struct vc4_file *vc4file);
1028 void vc4_perfmon_close_file(struct vc4_file *vc4file);
1029 int vc4_perfmon_create_ioctl(struct drm_device *dev, void *data,
1030 struct drm_file *file_priv);
1031 int vc4_perfmon_destroy_ioctl(struct drm_device *dev, void *data,
1032 struct drm_file *file_priv);
1033 int vc4_perfmon_get_values_ioctl(struct drm_device *dev, void *data,
1034 struct drm_file *file_priv);
1036 #endif /* _VC4_DRV_H_ */