1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2015 Broadcom
8 #include <linux/delay.h>
9 #include <linux/refcount.h>
10 #include <linux/uaccess.h>
12 #include <drm/drm_atomic.h>
13 #include <drm/drm_debugfs.h>
14 #include <drm/drm_device.h>
15 #include <drm/drm_encoder.h>
16 #include <drm/drm_gem_cma_helper.h>
17 #include <drm/drm_managed.h>
18 #include <drm/drm_mm.h>
19 #include <drm/drm_modeset_lock.h>
21 #include "uapi/drm/vc4_drm.h"
24 struct drm_gem_object;
26 /* Don't forget to update vc4_bo.c: bo_type_names[] when adding to
29 enum vc4_kernel_bo_type {
30 /* Any kernel allocation (gem_create_object hook) before it
31 * gets another type set.
35 VC4_BO_TYPE_V3D_SHADER,
40 VC4_BO_TYPE_KERNEL_CACHE,
44 /* Performance monitor object. The perform lifetime is controlled by userspace
45 * using perfmon related ioctls. A perfmon can be attached to a submit_cl
46 * request, and when this is the case, HW perf counters will be activated just
47 * before the submit_cl is submitted to the GPU and disabled when the job is
48 * done. This way, only events related to a specific job will be counted.
51 /* Tracks the number of users of the perfmon, when this counter reaches
52 * zero the perfmon is destroyed.
56 /* Number of counters activated in this perfmon instance
57 * (should be less than DRM_VC4_MAX_PERF_COUNTERS).
61 /* Events counted by the HW perf counters. */
62 u8 events[DRM_VC4_MAX_PERF_COUNTERS];
64 /* Storage for counter values. Counters are incremented by the HW
65 * perf counter values every time the perfmon is attached to a GPU job.
66 * This way, perfmon users don't have to retrieve the results after
67 * each job if they want to track events covering several submissions.
68 * Note that counter values can't be reset, but you can fake a reset by
69 * destroying the perfmon and creating a new one.
75 struct drm_device base;
80 struct rpi_firmware *firmware;
87 struct vc4_fkms *fkms;
89 struct vc4_hang_state *hang_state;
91 /* The kernel-space BO cache. Tracks buffers that have been
92 * unreferenced by all other users (refcounts of 0!) but not
93 * yet freed, so we can do cheap allocations.
96 /* Array of list heads for entries in the BO cache,
97 * based on number of pages, so we can do O(1) lookups
98 * in the cache when allocating.
100 struct list_head *size_list;
101 uint32_t size_list_size;
103 /* List of all BOs in the cache, ordered by age, so we
104 * can do O(1) lookups when trying to free old
107 struct list_head time_list;
108 struct work_struct time_work;
109 struct timer_list time_timer;
119 /* Protects bo_cache and bo_labels. */
120 struct mutex bo_lock;
122 /* Purgeable BO pool. All BOs in this pool can have their memory
123 * reclaimed if the driver is unable to allocate new BOs. We also
124 * keep stats related to the purge mechanism here.
127 struct list_head list;
130 unsigned int purged_num;
135 uint64_t dma_fence_context;
137 /* Sequence number for the last job queued in bin_job_list.
138 * Starts at 0 (no jobs emitted).
142 /* Sequence number for the last completed job on the GPU.
143 * Starts at 0 (no jobs completed).
145 uint64_t finished_seqno;
147 /* List of all struct vc4_exec_info for jobs to be executed in
148 * the binner. The first job in the list is the one currently
149 * programmed into ct0ca for execution.
151 struct list_head bin_job_list;
153 /* List of all struct vc4_exec_info for jobs that have
154 * completed binning and are ready for rendering. The first
155 * job in the list is the one currently programmed into ct1ca
158 struct list_head render_job_list;
160 /* List of the finished vc4_exec_infos waiting to be freed by
163 struct list_head job_done_list;
164 /* Spinlock used to synchronize the job_list and seqno
165 * accesses between the IRQ handler and GEM ioctls.
168 wait_queue_head_t job_wait_queue;
169 struct work_struct job_done_work;
171 /* Used to track the active perfmon if any. Access to this field is
172 * protected by job_lock.
174 struct vc4_perfmon *active_perfmon;
176 /* List of struct vc4_seqno_cb for callbacks to be made from a
177 * workqueue when the given seqno is passed.
179 struct list_head seqno_cb_list;
181 /* The memory used for storing binner tile alloc, tile state,
182 * and overflow memory allocations. This is freed when V3D
185 struct vc4_bo *bin_bo;
187 /* Size of blocks allocated within bin_bo. */
188 uint32_t bin_alloc_size;
190 /* Bitmask of the bin_alloc_size chunks in bin_bo that are
193 uint32_t bin_alloc_used;
195 /* Bitmask of the current bin_alloc used for overflow memory. */
196 uint32_t bin_alloc_overflow;
198 /* Incremented when an underrun error happened after an atomic commit.
199 * This is particularly useful to detect when a specific modeset is too
200 * demanding in term of memory or HVS bandwidth which is hard to guess
201 * at atomic check time.
205 struct work_struct overflow_mem_work;
209 /* Set to true when the load tracker is active. */
210 bool load_tracker_enabled;
212 /* Mutex controlling the power refcount. */
213 struct mutex power_lock;
216 struct timer_list timer;
217 struct work_struct reset_work;
220 struct drm_modeset_lock ctm_state_lock;
221 struct drm_private_obj ctm_manager;
222 struct drm_private_obj hvs_channels;
223 struct drm_private_obj load_tracker;
225 /* List of vc4_debugfs_info_entry for adding to debugfs once
226 * the minor is available (after drm_dev_register()).
228 struct list_head debugfs_list;
230 /* Mutex for binner bo allocation. */
231 struct mutex bin_bo_lock;
232 /* Reference count for our binner bo. */
233 struct kref bin_bo_kref;
236 static inline struct vc4_dev *
237 to_vc4_dev(struct drm_device *dev)
239 return container_of(dev, struct vc4_dev, base);
243 struct drm_gem_cma_object base;
245 /* seqno of the last job to render using this BO. */
248 /* seqno of the last job to use the RCL to write to this BO.
250 * Note that this doesn't include binner overflow memory
253 uint64_t write_seqno;
257 /* List entry for the BO's position in either
258 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
260 struct list_head unref_head;
262 /* Time in jiffies when the BO was put in vc4->bo_cache. */
263 unsigned long free_time;
265 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
266 struct list_head size_head;
268 /* Struct for shader validation state, if created by
269 * DRM_IOCTL_VC4_CREATE_SHADER_BO.
271 struct vc4_validated_shader_info *validated_shader;
273 /* One of enum vc4_kernel_bo_type, or VC4_BO_TYPE_COUNT + i
274 * for user-allocated labels.
278 /* Count the number of active users. This is needed to determine
279 * whether we can move the BO to the purgeable list or not (when the BO
280 * is used by the GPU or the display engine we can't purge it).
284 /* Store purgeable/purged state here */
286 struct mutex madv_lock;
289 static inline struct vc4_bo *
290 to_vc4_bo(struct drm_gem_object *bo)
292 return container_of(to_drm_gem_cma_obj(bo), struct vc4_bo, base);
296 struct dma_fence base;
297 struct drm_device *dev;
298 /* vc4 seqno for signaled() test */
302 static inline struct vc4_fence *
303 to_vc4_fence(struct dma_fence *fence)
305 return container_of(fence, struct vc4_fence, base);
308 struct vc4_seqno_cb {
309 struct work_struct work;
311 void (*func)(struct vc4_seqno_cb *cb);
316 struct platform_device *pdev;
319 struct debugfs_regset32 regset;
323 struct platform_device *pdev;
327 struct clk *core_clk;
328 struct clk_request *core_req;
330 /* Memory manager for CRTCs to allocate space in the display
331 * list. Units are dwords.
333 struct drm_mm dlist_mm;
334 /* Memory manager for the LBM memory used by HVS scaling. */
335 struct drm_mm lbm_mm;
338 struct drm_mm_node mitchell_netravali_filter;
340 struct debugfs_regset32 regset;
342 /* HVS version 5 flag, therefore requires updated dlist structures */
347 struct drm_plane base;
350 static inline struct vc4_plane *
351 to_vc4_plane(struct drm_plane *plane)
353 return container_of(plane, struct vc4_plane, base);
356 enum vc4_scaling_mode {
362 struct vc4_plane_state {
363 struct drm_plane_state base;
364 /* System memory copy of the display list for this element, computed
365 * at atomic_check time.
368 u32 dlist_size; /* Number of dwords allocated for the display list */
369 u32 dlist_count; /* Number of used dwords in the display list. */
371 /* Offset in the dlist to various words, for pageflip or
379 /* Offset where the plane's dlist was last stored in the
380 * hardware at vc4_crtc_atomic_flush() time.
382 u32 __iomem *hw_dlist;
384 /* Clipped coordinates of the plane on the display. */
385 int crtc_x, crtc_y, crtc_w, crtc_h;
386 /* Clipped area being scanned from in the FB. */
389 u32 src_w[2], src_h[2];
391 /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
392 enum vc4_scaling_mode x_scaling[2], y_scaling[2];
396 /* Offset to start scanning out from the start of the plane's
401 /* Our allocation in LBM for temporary storage during scaling. */
402 struct drm_mm_node lbm;
404 /* Set when the plane has per-pixel alpha content or does not cover
405 * the entire screen. This is a hint to the CRTC that it might need
406 * to enable background color fill.
410 /* Mark the dlist as initialized. Useful to avoid initializing it twice
411 * when async update is not possible.
413 bool dlist_initialized;
415 /* Load of this plane on the HVS block. The load is expressed in HVS
420 /* Memory bandwidth needed for this plane. This is expressed in
426 static inline struct vc4_plane_state *
427 to_vc4_plane_state(struct drm_plane_state *state)
429 return container_of(state, struct vc4_plane_state, base);
432 enum vc4_encoder_type {
433 VC4_ENCODER_TYPE_NONE,
434 VC4_ENCODER_TYPE_HDMI0,
435 VC4_ENCODER_TYPE_HDMI1,
436 VC4_ENCODER_TYPE_VEC,
437 VC4_ENCODER_TYPE_DSI0,
438 VC4_ENCODER_TYPE_DSI1,
439 VC4_ENCODER_TYPE_SMI,
440 VC4_ENCODER_TYPE_DPI,
444 struct drm_encoder base;
445 enum vc4_encoder_type type;
448 void (*pre_crtc_configure)(struct drm_encoder *encoder, struct drm_atomic_state *state);
449 void (*pre_crtc_enable)(struct drm_encoder *encoder, struct drm_atomic_state *state);
450 void (*post_crtc_enable)(struct drm_encoder *encoder, struct drm_atomic_state *state);
452 void (*post_crtc_disable)(struct drm_encoder *encoder, struct drm_atomic_state *state);
453 void (*post_crtc_powerdown)(struct drm_encoder *encoder, struct drm_atomic_state *state);
456 static inline struct vc4_encoder *
457 to_vc4_encoder(struct drm_encoder *encoder)
459 return container_of(encoder, struct vc4_encoder, base);
462 struct vc4_crtc_data {
463 /* Bitmask of channels (FIFOs) of the HVS that the output can source from */
464 unsigned int hvs_available_channels;
466 /* Which output of the HVS this pixelvalve sources from. */
471 struct vc4_crtc_data base;
473 /* Depth of the PixelValve FIFO in bytes */
474 unsigned int fifo_depth;
476 /* Number of pixels output per clock period */
479 enum vc4_encoder_type encoder_types[4];
480 const char *debugfs_name;
485 struct drm_crtc base;
486 struct platform_device *pdev;
487 const struct vc4_crtc_data *data;
490 /* Timestamp at start of vblank irq - unaffected by lock delays. */
497 struct drm_pending_vblank_event *event;
499 struct debugfs_regset32 regset;
502 * @feeds_txp: True if the CRTC feeds our writeback controller.
507 * @irq_lock: Spinlock protecting the resources shared between
508 * the atomic code and our vblank handler.
513 * @current_dlist: Start offset of the display list currently
514 * set in the HVS for that CRTC. Protected by @irq_lock, and
515 * copied in vc4_hvs_update_dlist() for the CRTC interrupt
516 * handler to have access to that value.
518 unsigned int current_dlist;
521 * @current_hvs_channel: HVS channel currently assigned to the
522 * CRTC. Protected by @irq_lock, and copied in
523 * vc4_hvs_atomic_begin() for the CRTC interrupt handler to have
524 * access to that value.
526 unsigned int current_hvs_channel;
529 static inline struct vc4_crtc *
530 to_vc4_crtc(struct drm_crtc *crtc)
532 return container_of(crtc, struct vc4_crtc, base);
535 static inline const struct vc4_crtc_data *
536 vc4_crtc_to_vc4_crtc_data(const struct vc4_crtc *crtc)
541 static inline const struct vc4_pv_data *
542 vc4_crtc_to_vc4_pv_data(const struct vc4_crtc *crtc)
544 const struct vc4_crtc_data *data = vc4_crtc_to_vc4_crtc_data(crtc);
546 return container_of(data, struct vc4_pv_data, base);
549 struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc,
550 struct drm_crtc_state *state);
552 struct vc4_crtc_state {
553 struct drm_crtc_state base;
554 /* Dlist area for this CRTC configuration. */
555 struct drm_mm_node mm;
557 unsigned int assigned_channel;
566 unsigned long hvs_load;
568 /* Transitional state below, only valid during atomic commits */
572 #define VC4_HVS_CHANNEL_DISABLED ((unsigned int)-1)
574 static inline struct vc4_crtc_state *
575 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
577 return container_of(crtc_state, struct vc4_crtc_state, base);
580 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
581 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
582 #define HVS_READ(offset) readl(vc4->hvs->regs + offset)
583 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
585 #define VC4_REG32(reg) { .name = #reg, .offset = reg }
587 struct vc4_exec_info {
588 /* Sequence number for this bin/render job. */
591 /* Latest write_seqno of any BO that binning depends on. */
592 uint64_t bin_dep_seqno;
594 struct dma_fence *fence;
596 /* Last current addresses the hardware was processing when the
597 * hangcheck timer checked on us.
599 uint32_t last_ct0ca, last_ct1ca;
601 /* Kernel-space copy of the ioctl arguments */
602 struct drm_vc4_submit_cl *args;
604 /* This is the array of BOs that were looked up at the start of exec.
605 * Command validation will use indices into this array.
607 struct drm_gem_cma_object **bo;
610 /* List of BOs that are being written by the RCL. Other than
611 * the binner temporary storage, this is all the BOs written
614 struct drm_gem_cma_object *rcl_write_bo[4];
615 uint32_t rcl_write_bo_count;
617 /* Pointers for our position in vc4->job_list */
618 struct list_head head;
620 /* List of other BOs used in the job that need to be released
621 * once the job is complete.
623 struct list_head unref_list;
625 /* Current unvalidated indices into @bo loaded by the non-hardware
626 * VC4_PACKET_GEM_HANDLES.
628 uint32_t bo_index[2];
630 /* This is the BO where we store the validated command lists, shader
631 * records, and uniforms.
633 struct drm_gem_cma_object *exec_bo;
636 * This tracks the per-shader-record state (packet 64) that
637 * determines the length of the shader record and the offset
638 * it's expected to be found at. It gets read in from the
641 struct vc4_shader_state {
643 /* Maximum vertex index referenced by any primitive using this
649 /** How many shader states the user declared they were using. */
650 uint32_t shader_state_size;
651 /** How many shader state records the validator has seen. */
652 uint32_t shader_state_count;
654 bool found_tile_binning_mode_config_packet;
655 bool found_start_tile_binning_packet;
656 bool found_increment_semaphore_packet;
658 uint8_t bin_tiles_x, bin_tiles_y;
659 /* Physical address of the start of the tile alloc array
660 * (where each tile's binned CL will start)
662 uint32_t tile_alloc_offset;
663 /* Bitmask of which binner slots are freed when this job completes. */
667 * Computed addresses pointing into exec_bo where we start the
668 * bin thread (ct0) and render thread (ct1).
670 uint32_t ct0ca, ct0ea;
671 uint32_t ct1ca, ct1ea;
673 /* Pointer to the unvalidated bin CL (if present). */
676 /* Pointers to the shader recs. These paddr gets incremented as CL
677 * packets are relocated in validate_gl_shader_state, and the vaddrs
678 * (u and v) get incremented and size decremented as the shader recs
679 * themselves are validated.
683 uint32_t shader_rec_p;
684 uint32_t shader_rec_size;
686 /* Pointers to the uniform data. These pointers are incremented, and
687 * size decremented, as each batch of uniforms is uploaded.
692 uint32_t uniforms_size;
694 /* Pointer to a performance monitor object if the user requested it,
697 struct vc4_perfmon *perfmon;
699 /* Whether the exec has taken a reference to the binner BO, which should
700 * happen with a VC4_PACKET_TILE_BINNING_MODE_CONFIG packet.
705 /* Per-open file private data. Any driver-specific resource that has to be
706 * released when the DRM file is closed should be placed here.
717 static inline struct vc4_exec_info *
718 vc4_first_bin_job(struct vc4_dev *vc4)
720 return list_first_entry_or_null(&vc4->bin_job_list,
721 struct vc4_exec_info, head);
724 static inline struct vc4_exec_info *
725 vc4_first_render_job(struct vc4_dev *vc4)
727 return list_first_entry_or_null(&vc4->render_job_list,
728 struct vc4_exec_info, head);
731 static inline struct vc4_exec_info *
732 vc4_last_render_job(struct vc4_dev *vc4)
734 if (list_empty(&vc4->render_job_list))
736 return list_last_entry(&vc4->render_job_list,
737 struct vc4_exec_info, head);
741 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
744 * This will be used at draw time to relocate the reference to the texture
745 * contents in p0, and validate that the offset combined with
746 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
747 * Note that the hardware treats unprovided config parameters as 0, so not all
748 * of them need to be set up for every texure sample, and we'll store ~0 as
749 * the offset to mark the unused ones.
751 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
752 * Setup") for definitions of the texture parameters.
754 struct vc4_texture_sample_info {
756 uint32_t p_offset[4];
760 * struct vc4_validated_shader_info - information about validated shaders that
761 * needs to be used from command list validation.
763 * For a given shader, each time a shader state record references it, we need
764 * to verify that the shader doesn't read more uniforms than the shader state
765 * record's uniform BO pointer can provide, and we need to apply relocations
766 * and validate the shader state record's uniforms that define the texture
769 struct vc4_validated_shader_info {
770 uint32_t uniforms_size;
771 uint32_t uniforms_src_size;
772 uint32_t num_texture_samples;
773 struct vc4_texture_sample_info *texture_samples;
775 uint32_t num_uniform_addr_offsets;
776 uint32_t *uniform_addr_offsets;
782 * __wait_for - magic wait macro
784 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
785 * important that we check the condition again after having timed out, since the
786 * timeout could be due to preemption or similar and we've never had a chance to
787 * check the condition before the timeout.
789 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
790 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
791 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
795 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
797 /* Guarantee COND check prior to timeout */ \
804 ret__ = -ETIMEDOUT; \
807 usleep_range(wait__, wait__ * 2); \
808 if (wait__ < (Wmax)) \
814 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
816 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
819 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
820 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
821 bool from_cache, enum vc4_kernel_bo_type type);
822 int vc4_dumb_create(struct drm_file *file_priv,
823 struct drm_device *dev,
824 struct drm_mode_create_dumb *args);
825 int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
826 struct drm_file *file_priv);
827 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
828 struct drm_file *file_priv);
829 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
830 struct drm_file *file_priv);
831 int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
832 struct drm_file *file_priv);
833 int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
834 struct drm_file *file_priv);
835 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
836 struct drm_file *file_priv);
837 int vc4_label_bo_ioctl(struct drm_device *dev, void *data,
838 struct drm_file *file_priv);
839 int vc4_bo_cache_init(struct drm_device *dev);
840 int vc4_bo_inc_usecnt(struct vc4_bo *bo);
841 void vc4_bo_dec_usecnt(struct vc4_bo *bo);
842 void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo);
843 void vc4_bo_remove_from_purgeable_pool(struct vc4_bo *bo);
846 extern struct platform_driver vc4_crtc_driver;
847 int vc4_crtc_disable_at_boot(struct drm_crtc *crtc);
848 int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
849 const struct drm_crtc_funcs *crtc_funcs,
850 const struct drm_crtc_helper_funcs *crtc_helper_funcs);
851 void vc4_crtc_destroy(struct drm_crtc *crtc);
852 int vc4_page_flip(struct drm_crtc *crtc,
853 struct drm_framebuffer *fb,
854 struct drm_pending_vblank_event *event,
856 struct drm_modeset_acquire_ctx *ctx);
857 struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc);
858 void vc4_crtc_destroy_state(struct drm_crtc *crtc,
859 struct drm_crtc_state *state);
860 void vc4_crtc_reset(struct drm_crtc *crtc);
861 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc);
862 void vc4_crtc_get_margins(struct drm_crtc_state *state,
863 unsigned int *left, unsigned int *right,
864 unsigned int *top, unsigned int *bottom);
867 void vc4_debugfs_init(struct drm_minor *minor);
868 #ifdef CONFIG_DEBUG_FS
869 void vc4_debugfs_add_file(struct drm_device *drm,
870 const char *filename,
871 int (*show)(struct seq_file*, void*),
873 void vc4_debugfs_add_regset32(struct drm_device *drm,
874 const char *filename,
875 struct debugfs_regset32 *regset);
877 static inline void vc4_debugfs_add_file(struct drm_device *drm,
878 const char *filename,
879 int (*show)(struct seq_file*, void*),
884 static inline void vc4_debugfs_add_regset32(struct drm_device *drm,
885 const char *filename,
886 struct debugfs_regset32 *regset)
892 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
895 extern struct platform_driver vc4_dpi_driver;
898 extern struct platform_driver vc4_dsi_driver;
901 extern const struct dma_fence_ops vc4_fence_ops;
903 /* vc4_firmware_kms.c */
904 extern struct platform_driver vc4_firmware_kms_driver;
907 int vc4_gem_init(struct drm_device *dev);
908 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
909 struct drm_file *file_priv);
910 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
911 struct drm_file *file_priv);
912 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
913 struct drm_file *file_priv);
914 void vc4_submit_next_bin_job(struct drm_device *dev);
915 void vc4_submit_next_render_job(struct drm_device *dev);
916 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
917 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
918 uint64_t timeout_ns, bool interruptible);
919 void vc4_job_handle_completed(struct vc4_dev *vc4);
920 int vc4_queue_seqno_cb(struct drm_device *dev,
921 struct vc4_seqno_cb *cb, uint64_t seqno,
922 void (*func)(struct vc4_seqno_cb *cb));
923 int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data,
924 struct drm_file *file_priv);
927 extern struct platform_driver vc4_hdmi_driver;
930 extern struct platform_driver vc4_vec_driver;
933 extern struct platform_driver vc4_txp_driver;
936 void vc4_irq_enable(struct drm_device *dev);
937 void vc4_irq_disable(struct drm_device *dev);
938 int vc4_irq_install(struct drm_device *dev, int irq);
939 void vc4_irq_uninstall(struct drm_device *dev);
940 void vc4_irq_reset(struct drm_device *dev);
943 extern struct platform_driver vc4_hvs_driver;
944 void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int output);
945 int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output);
946 int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state);
947 void vc4_hvs_atomic_begin(struct drm_crtc *crtc, struct drm_atomic_state *state);
948 void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state);
949 void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state);
950 void vc4_hvs_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state);
951 void vc4_hvs_dump_state(struct drm_device *dev);
952 void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel);
953 void vc4_hvs_mask_underrun(struct drm_device *dev, int channel);
956 int vc4_kms_load(struct drm_device *dev);
959 struct drm_plane *vc4_plane_init(struct drm_device *dev,
960 enum drm_plane_type type);
961 int vc4_plane_create_additional_planes(struct drm_device *dev);
962 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
963 u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
964 void vc4_plane_async_set_fb(struct drm_plane *plane,
965 struct drm_framebuffer *fb);
968 extern struct platform_driver vc4_v3d_driver;
969 extern const struct of_device_id vc4_v3d_dt_match[];
970 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4);
971 int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used);
972 void vc4_v3d_bin_bo_put(struct vc4_dev *vc4);
973 int vc4_v3d_pm_get(struct vc4_dev *vc4);
974 void vc4_v3d_pm_put(struct vc4_dev *vc4);
978 vc4_validate_bin_cl(struct drm_device *dev,
981 struct vc4_exec_info *exec);
984 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
986 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
989 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
991 bool vc4_check_tex_size(struct vc4_exec_info *exec,
992 struct drm_gem_cma_object *fbo,
993 uint32_t offset, uint8_t tiling_format,
994 uint32_t width, uint32_t height, uint8_t cpp);
996 /* vc4_validate_shader.c */
997 struct vc4_validated_shader_info *
998 vc4_validate_shader(struct drm_gem_cma_object *shader_obj);
1001 void vc4_perfmon_get(struct vc4_perfmon *perfmon);
1002 void vc4_perfmon_put(struct vc4_perfmon *perfmon);
1003 void vc4_perfmon_start(struct vc4_dev *vc4, struct vc4_perfmon *perfmon);
1004 void vc4_perfmon_stop(struct vc4_dev *vc4, struct vc4_perfmon *perfmon,
1006 struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id);
1007 void vc4_perfmon_open_file(struct vc4_file *vc4file);
1008 void vc4_perfmon_close_file(struct vc4_file *vc4file);
1009 int vc4_perfmon_create_ioctl(struct drm_device *dev, void *data,
1010 struct drm_file *file_priv);
1011 int vc4_perfmon_destroy_ioctl(struct drm_device *dev, void *data,
1012 struct drm_file *file_priv);
1013 int vc4_perfmon_get_values_ioctl(struct drm_device *dev, void *data,
1014 struct drm_file *file_priv);
1016 #endif /* _VC4_DRV_H_ */