1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2015 Broadcom
8 #include <linux/delay.h>
9 #include <linux/refcount.h>
10 #include <linux/uaccess.h>
12 #include <drm/drm_atomic.h>
13 #include <drm/drm_debugfs.h>
14 #include <drm/drm_device.h>
15 #include <drm/drm_encoder.h>
16 #include <drm/drm_gem_cma_helper.h>
17 #include <drm/drm_mm.h>
18 #include <drm/drm_modeset_lock.h>
20 #include "uapi/drm/vc4_drm.h"
23 struct drm_gem_object;
25 /* Don't forget to update vc4_bo.c: bo_type_names[] when adding to
28 enum vc4_kernel_bo_type {
29 /* Any kernel allocation (gem_create_object hook) before it
30 * gets another type set.
34 VC4_BO_TYPE_V3D_SHADER,
39 VC4_BO_TYPE_KERNEL_CACHE,
43 /* Performance monitor object. The perform lifetime is controlled by userspace
44 * using perfmon related ioctls. A perfmon can be attached to a submit_cl
45 * request, and when this is the case, HW perf counters will be activated just
46 * before the submit_cl is submitted to the GPU and disabled when the job is
47 * done. This way, only events related to a specific job will be counted.
50 /* Tracks the number of users of the perfmon, when this counter reaches
51 * zero the perfmon is destroyed.
55 /* Number of counters activated in this perfmon instance
56 * (should be less than DRM_VC4_MAX_PERF_COUNTERS).
60 /* Events counted by the HW perf counters. */
61 u8 events[DRM_VC4_MAX_PERF_COUNTERS];
63 /* Storage for counter values. Counters are incremented by the HW
64 * perf counter values every time the perfmon is attached to a GPU job.
65 * This way, perfmon users don't have to retrieve the results after
66 * each job if they want to track events covering several submissions.
67 * Note that counter values can't be reset, but you can fake a reset by
68 * destroying the perfmon and creating a new one.
74 struct drm_device *dev;
77 struct rpi_firmware *firmware;
85 struct vc4_fkms *fkms;
87 struct vc4_hang_state *hang_state;
89 /* The kernel-space BO cache. Tracks buffers that have been
90 * unreferenced by all other users (refcounts of 0!) but not
91 * yet freed, so we can do cheap allocations.
94 /* Array of list heads for entries in the BO cache,
95 * based on number of pages, so we can do O(1) lookups
96 * in the cache when allocating.
98 struct list_head *size_list;
99 uint32_t size_list_size;
101 /* List of all BOs in the cache, ordered by age, so we
102 * can do O(1) lookups when trying to free old
105 struct list_head time_list;
106 struct work_struct time_work;
107 struct timer_list time_timer;
117 /* Protects bo_cache and bo_labels. */
118 struct mutex bo_lock;
120 /* Purgeable BO pool. All BOs in this pool can have their memory
121 * reclaimed if the driver is unable to allocate new BOs. We also
122 * keep stats related to the purge mechanism here.
125 struct list_head list;
128 unsigned int purged_num;
133 uint64_t dma_fence_context;
135 /* Sequence number for the last job queued in bin_job_list.
136 * Starts at 0 (no jobs emitted).
140 /* Sequence number for the last completed job on the GPU.
141 * Starts at 0 (no jobs completed).
143 uint64_t finished_seqno;
145 /* List of all struct vc4_exec_info for jobs to be executed in
146 * the binner. The first job in the list is the one currently
147 * programmed into ct0ca for execution.
149 struct list_head bin_job_list;
151 /* List of all struct vc4_exec_info for jobs that have
152 * completed binning and are ready for rendering. The first
153 * job in the list is the one currently programmed into ct1ca
156 struct list_head render_job_list;
158 /* List of the finished vc4_exec_infos waiting to be freed by
161 struct list_head job_done_list;
162 /* Spinlock used to synchronize the job_list and seqno
163 * accesses between the IRQ handler and GEM ioctls.
166 wait_queue_head_t job_wait_queue;
167 struct work_struct job_done_work;
169 /* Used to track the active perfmon if any. Access to this field is
170 * protected by job_lock.
172 struct vc4_perfmon *active_perfmon;
174 /* List of struct vc4_seqno_cb for callbacks to be made from a
175 * workqueue when the given seqno is passed.
177 struct list_head seqno_cb_list;
179 /* The memory used for storing binner tile alloc, tile state,
180 * and overflow memory allocations. This is freed when V3D
183 struct vc4_bo *bin_bo;
185 /* Size of blocks allocated within bin_bo. */
186 uint32_t bin_alloc_size;
188 /* Bitmask of the bin_alloc_size chunks in bin_bo that are
191 uint32_t bin_alloc_used;
193 /* Bitmask of the current bin_alloc used for overflow memory. */
194 uint32_t bin_alloc_overflow;
196 /* Incremented when an underrun error happened after an atomic commit.
197 * This is particularly useful to detect when a specific modeset is too
198 * demanding in term of memory or HVS bandwidth which is hard to guess
199 * at atomic check time.
203 struct work_struct overflow_mem_work;
207 /* Set to true when the load tracker is supported. */
208 bool load_tracker_available;
210 /* Set to true when the load tracker is active. */
211 bool load_tracker_enabled;
213 /* Mutex controlling the power refcount. */
214 struct mutex power_lock;
217 struct timer_list timer;
218 struct work_struct reset_work;
221 struct semaphore async_modeset;
223 struct drm_modeset_lock ctm_state_lock;
224 struct drm_private_obj ctm_manager;
225 struct drm_private_obj load_tracker;
227 /* List of vc4_debugfs_info_entry for adding to debugfs once
228 * the minor is available (after drm_dev_register()).
230 struct list_head debugfs_list;
233 static inline struct vc4_dev *
234 to_vc4_dev(struct drm_device *dev)
236 return (struct vc4_dev *)dev->dev_private;
240 struct drm_gem_cma_object base;
242 /* seqno of the last job to render using this BO. */
245 /* seqno of the last job to use the RCL to write to this BO.
247 * Note that this doesn't include binner overflow memory
250 uint64_t write_seqno;
254 /* List entry for the BO's position in either
255 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
257 struct list_head unref_head;
259 /* Time in jiffies when the BO was put in vc4->bo_cache. */
260 unsigned long free_time;
262 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
263 struct list_head size_head;
265 /* Struct for shader validation state, if created by
266 * DRM_IOCTL_VC4_CREATE_SHADER_BO.
268 struct vc4_validated_shader_info *validated_shader;
270 /* One of enum vc4_kernel_bo_type, or VC4_BO_TYPE_COUNT + i
271 * for user-allocated labels.
275 /* Count the number of active users. This is needed to determine
276 * whether we can move the BO to the purgeable list or not (when the BO
277 * is used by the GPU or the display engine we can't purge it).
281 /* Store purgeable/purged state here */
283 struct mutex madv_lock;
286 static inline struct vc4_bo *
287 to_vc4_bo(struct drm_gem_object *bo)
289 return (struct vc4_bo *)bo;
293 struct dma_fence base;
294 struct drm_device *dev;
295 /* vc4 seqno for signaled() test */
299 static inline struct vc4_fence *
300 to_vc4_fence(struct dma_fence *fence)
302 return (struct vc4_fence *)fence;
305 struct vc4_seqno_cb {
306 struct work_struct work;
308 void (*func)(struct vc4_seqno_cb *cb);
313 struct platform_device *pdev;
316 struct debugfs_regset32 regset;
320 struct platform_device *pdev;
324 struct clk *core_clk;
326 /* Memory manager for CRTCs to allocate space in the display
327 * list. Units are dwords.
329 struct drm_mm dlist_mm;
330 /* Memory manager for the LBM memory used by HVS scaling. */
331 struct drm_mm lbm_mm;
334 struct drm_mm_node mitchell_netravali_filter;
336 struct debugfs_regset32 regset;
338 /* HVS version 5 flag, therefore requires updated dlist structures */
343 struct drm_plane base;
346 static inline struct vc4_plane *
347 to_vc4_plane(struct drm_plane *plane)
349 return (struct vc4_plane *)plane;
352 enum vc4_scaling_mode {
358 struct vc4_plane_state {
359 struct drm_plane_state base;
360 /* System memory copy of the display list for this element, computed
361 * at atomic_check time.
364 u32 dlist_size; /* Number of dwords allocated for the display list */
365 u32 dlist_count; /* Number of used dwords in the display list. */
367 /* Offset in the dlist to various words, for pageflip or
375 /* Offset where the plane's dlist was last stored in the
376 * hardware at vc4_crtc_atomic_flush() time.
378 u32 __iomem *hw_dlist;
380 /* Clipped coordinates of the plane on the display. */
381 int crtc_x, crtc_y, crtc_w, crtc_h;
382 /* Clipped area being scanned from in the FB. */
385 u32 src_w[2], src_h[2];
387 /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
388 enum vc4_scaling_mode x_scaling[2], y_scaling[2];
392 /* Offset to start scanning out from the start of the plane's
397 /* Our allocation in LBM for temporary storage during scaling. */
398 struct drm_mm_node lbm;
400 /* Set when the plane has per-pixel alpha content or does not cover
401 * the entire screen. This is a hint to the CRTC that it might need
402 * to enable background color fill.
406 /* Mark the dlist as initialized. Useful to avoid initializing it twice
407 * when async update is not possible.
409 bool dlist_initialized;
411 /* Load of this plane on the HVS block. The load is expressed in HVS
416 /* Memory bandwidth needed for this plane. This is expressed in
422 static inline struct vc4_plane_state *
423 to_vc4_plane_state(struct drm_plane_state *state)
425 return (struct vc4_plane_state *)state;
428 enum vc4_encoder_type {
429 VC4_ENCODER_TYPE_NONE,
430 VC4_ENCODER_TYPE_HDMI0,
431 VC4_ENCODER_TYPE_HDMI1,
432 VC4_ENCODER_TYPE_VEC,
433 VC4_ENCODER_TYPE_DSI0,
434 VC4_ENCODER_TYPE_DSI1,
435 VC4_ENCODER_TYPE_SMI,
436 VC4_ENCODER_TYPE_DPI,
440 struct drm_encoder base;
441 enum vc4_encoder_type type;
444 void (*pre_crtc_configure)(struct drm_encoder *encoder);
445 void (*pre_crtc_enable)(struct drm_encoder *encoder);
446 void (*post_crtc_enable)(struct drm_encoder *encoder);
448 void (*post_crtc_disable)(struct drm_encoder *encoder);
449 void (*post_crtc_powerdown)(struct drm_encoder *encoder);
452 static inline struct vc4_encoder *
453 to_vc4_encoder(struct drm_encoder *encoder)
455 return container_of(encoder, struct vc4_encoder, base);
458 struct vc4_crtc_data {
459 /* Depth of the PixelValve FIFO in bytes */
460 unsigned int fifo_depth;
462 /* Which channels of the HVS can the output source from */
463 unsigned int hvs_available_channels;
465 /* Which output of the HVS this pixelvalve sources from. */
468 /* Number of pixels output per clock period */
471 enum vc4_encoder_type encoder_types[4];
472 const char *debugfs_name;
476 struct drm_crtc base;
477 struct platform_device *pdev;
478 const struct vc4_crtc_data *data;
481 /* Timestamp at start of vblank irq - unaffected by lock delays. */
488 struct drm_pending_vblank_event *event;
490 struct debugfs_regset32 regset;
493 static inline struct vc4_crtc *
494 to_vc4_crtc(struct drm_crtc *crtc)
496 return (struct vc4_crtc *)crtc;
499 struct vc4_crtc_state {
500 struct drm_crtc_state base;
501 /* Dlist area for this CRTC configuration. */
502 struct drm_mm_node mm;
505 unsigned int assigned_channel;
514 #define VC4_HVS_CHANNEL_DISABLED ((unsigned int) -1)
516 static inline struct vc4_crtc_state *
517 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
519 return (struct vc4_crtc_state *)crtc_state;
522 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
523 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
524 #define HVS_READ(offset) readl(vc4->hvs->regs + offset)
525 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
527 #define VC4_REG32(reg) { .name = #reg, .offset = reg }
529 struct vc4_exec_info {
530 /* Sequence number for this bin/render job. */
533 /* Latest write_seqno of any BO that binning depends on. */
534 uint64_t bin_dep_seqno;
536 struct dma_fence *fence;
538 /* Last current addresses the hardware was processing when the
539 * hangcheck timer checked on us.
541 uint32_t last_ct0ca, last_ct1ca;
543 /* Kernel-space copy of the ioctl arguments */
544 struct drm_vc4_submit_cl *args;
546 /* This is the array of BOs that were looked up at the start of exec.
547 * Command validation will use indices into this array.
549 struct drm_gem_cma_object **bo;
552 /* List of BOs that are being written by the RCL. Other than
553 * the binner temporary storage, this is all the BOs written
556 struct drm_gem_cma_object *rcl_write_bo[4];
557 uint32_t rcl_write_bo_count;
559 /* Pointers for our position in vc4->job_list */
560 struct list_head head;
562 /* List of other BOs used in the job that need to be released
563 * once the job is complete.
565 struct list_head unref_list;
567 /* Current unvalidated indices into @bo loaded by the non-hardware
568 * VC4_PACKET_GEM_HANDLES.
570 uint32_t bo_index[2];
572 /* This is the BO where we store the validated command lists, shader
573 * records, and uniforms.
575 struct drm_gem_cma_object *exec_bo;
578 * This tracks the per-shader-record state (packet 64) that
579 * determines the length of the shader record and the offset
580 * it's expected to be found at. It gets read in from the
583 struct vc4_shader_state {
585 /* Maximum vertex index referenced by any primitive using this
591 /** How many shader states the user declared they were using. */
592 uint32_t shader_state_size;
593 /** How many shader state records the validator has seen. */
594 uint32_t shader_state_count;
596 bool found_tile_binning_mode_config_packet;
597 bool found_start_tile_binning_packet;
598 bool found_increment_semaphore_packet;
600 uint8_t bin_tiles_x, bin_tiles_y;
601 /* Physical address of the start of the tile alloc array
602 * (where each tile's binned CL will start)
604 uint32_t tile_alloc_offset;
605 /* Bitmask of which binner slots are freed when this job completes. */
609 * Computed addresses pointing into exec_bo where we start the
610 * bin thread (ct0) and render thread (ct1).
612 uint32_t ct0ca, ct0ea;
613 uint32_t ct1ca, ct1ea;
615 /* Pointer to the unvalidated bin CL (if present). */
618 /* Pointers to the shader recs. These paddr gets incremented as CL
619 * packets are relocated in validate_gl_shader_state, and the vaddrs
620 * (u and v) get incremented and size decremented as the shader recs
621 * themselves are validated.
625 uint32_t shader_rec_p;
626 uint32_t shader_rec_size;
628 /* Pointers to the uniform data. These pointers are incremented, and
629 * size decremented, as each batch of uniforms is uploaded.
634 uint32_t uniforms_size;
636 /* Pointer to a performance monitor object if the user requested it,
639 struct vc4_perfmon *perfmon;
642 struct drm_vc4_file_private {
647 /* Per-open file private data. Any driver-specific resource that has to be
648 * released when the DRM file is closed should be placed here.
655 struct drm_vc4_file_private priv;
658 static inline struct vc4_exec_info *
659 vc4_first_bin_job(struct vc4_dev *vc4)
661 return list_first_entry_or_null(&vc4->bin_job_list,
662 struct vc4_exec_info, head);
665 static inline struct vc4_exec_info *
666 vc4_first_render_job(struct vc4_dev *vc4)
668 return list_first_entry_or_null(&vc4->render_job_list,
669 struct vc4_exec_info, head);
672 static inline struct vc4_exec_info *
673 vc4_last_render_job(struct vc4_dev *vc4)
675 if (list_empty(&vc4->render_job_list))
677 return list_last_entry(&vc4->render_job_list,
678 struct vc4_exec_info, head);
682 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
685 * This will be used at draw time to relocate the reference to the texture
686 * contents in p0, and validate that the offset combined with
687 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
688 * Note that the hardware treats unprovided config parameters as 0, so not all
689 * of them need to be set up for every texure sample, and we'll store ~0 as
690 * the offset to mark the unused ones.
692 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
693 * Setup") for definitions of the texture parameters.
695 struct vc4_texture_sample_info {
697 uint32_t p_offset[4];
701 * struct vc4_validated_shader_info - information about validated shaders that
702 * needs to be used from command list validation.
704 * For a given shader, each time a shader state record references it, we need
705 * to verify that the shader doesn't read more uniforms than the shader state
706 * record's uniform BO pointer can provide, and we need to apply relocations
707 * and validate the shader state record's uniforms that define the texture
710 struct vc4_validated_shader_info {
711 uint32_t uniforms_size;
712 uint32_t uniforms_src_size;
713 uint32_t num_texture_samples;
714 struct vc4_texture_sample_info *texture_samples;
716 uint32_t num_uniform_addr_offsets;
717 uint32_t *uniform_addr_offsets;
723 * _wait_for - magic (register) wait macro
725 * Does the right thing for modeset paths when run under kdgb or similar atomic
726 * contexts. Note that it's important that we check the condition again after
727 * having timed out, since the timeout could be due to preemption or similar and
728 * we've never had a chance to check the condition before the timeout.
730 #define _wait_for(COND, MS, W) ({ \
731 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
734 if (time_after(jiffies, timeout__)) { \
736 ret__ = -ETIMEDOUT; \
739 if (W && drm_can_sleep()) { \
748 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
751 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
752 void vc4_free_object(struct drm_gem_object *gem_obj);
753 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
754 bool from_cache, enum vc4_kernel_bo_type type);
755 int vc4_dumb_create(struct drm_file *file_priv,
756 struct drm_device *dev,
757 struct drm_mode_create_dumb *args);
758 struct dma_buf *vc4_prime_export(struct drm_gem_object *obj, int flags);
759 int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
760 struct drm_file *file_priv);
761 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
762 struct drm_file *file_priv);
763 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
764 struct drm_file *file_priv);
765 int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
766 struct drm_file *file_priv);
767 int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
768 struct drm_file *file_priv);
769 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
770 struct drm_file *file_priv);
771 int vc4_label_bo_ioctl(struct drm_device *dev, void *data,
772 struct drm_file *file_priv);
773 vm_fault_t vc4_fault(struct vm_fault *vmf);
774 int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
775 int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
776 struct drm_gem_object *vc4_prime_import_sg_table(struct drm_device *dev,
777 struct dma_buf_attachment *attach,
778 struct sg_table *sgt);
779 void *vc4_prime_vmap(struct drm_gem_object *obj);
780 int vc4_bo_cache_init(struct drm_device *dev);
781 void vc4_bo_cache_destroy(struct drm_device *dev);
782 int vc4_bo_inc_usecnt(struct vc4_bo *bo);
783 void vc4_bo_dec_usecnt(struct vc4_bo *bo);
784 void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo);
785 void vc4_bo_remove_from_purgeable_pool(struct vc4_bo *bo);
788 extern struct platform_driver vc4_crtc_driver;
789 bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
790 bool in_vblank_irq, int *vpos, int *hpos,
791 ktime_t *stime, ktime_t *etime,
792 const struct drm_display_mode *mode);
793 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc);
794 void vc4_crtc_txp_armed(struct drm_crtc_state *state);
795 void vc4_crtc_get_margins(struct drm_crtc_state *state,
796 unsigned int *right, unsigned int *left,
797 unsigned int *top, unsigned int *bottom);
800 int vc4_debugfs_init(struct drm_minor *minor);
801 #ifdef CONFIG_DEBUG_FS
802 void vc4_debugfs_add_file(struct drm_device *drm,
803 const char *filename,
804 int (*show)(struct seq_file*, void*),
806 void vc4_debugfs_add_regset32(struct drm_device *drm,
807 const char *filename,
808 struct debugfs_regset32 *regset);
810 static inline void vc4_debugfs_add_file(struct drm_device *drm,
811 const char *filename,
812 int (*show)(struct seq_file*, void*),
817 static inline void vc4_debugfs_add_regset32(struct drm_device *drm,
818 const char *filename,
819 struct debugfs_regset32 *regset)
825 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
828 extern struct platform_driver vc4_dpi_driver;
831 extern struct platform_driver vc4_dsi_driver;
834 extern const struct dma_fence_ops vc4_fence_ops;
836 /* vc4_firmware_kms.c */
837 extern struct platform_driver vc4_firmware_kms_driver;
840 void vc4_gem_init(struct drm_device *dev);
841 void vc4_gem_destroy(struct drm_device *dev);
842 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
843 struct drm_file *file_priv);
844 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
845 struct drm_file *file_priv);
846 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
847 struct drm_file *file_priv);
848 void vc4_submit_next_bin_job(struct drm_device *dev);
849 void vc4_submit_next_render_job(struct drm_device *dev);
850 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
851 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
852 uint64_t timeout_ns, bool interruptible);
853 void vc4_job_handle_completed(struct vc4_dev *vc4);
854 int vc4_queue_seqno_cb(struct drm_device *dev,
855 struct vc4_seqno_cb *cb, uint64_t seqno,
856 void (*func)(struct vc4_seqno_cb *cb));
857 int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data,
858 struct drm_file *file_priv);
861 extern struct platform_driver vc4_hdmi_driver;
864 extern struct platform_driver vc4_vec_driver;
867 extern struct platform_driver vc4_txp_driver;
870 irqreturn_t vc4_irq(int irq, void *arg);
871 void vc4_irq_preinstall(struct drm_device *dev);
872 int vc4_irq_postinstall(struct drm_device *dev);
873 void vc4_irq_uninstall(struct drm_device *dev);
874 void vc4_irq_reset(struct drm_device *dev);
877 extern struct platform_driver vc4_hvs_driver;
878 void vc4_hvs_dump_state(struct drm_device *dev);
879 void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel);
880 void vc4_hvs_mask_underrun(struct drm_device *dev, int channel);
883 int vc4_kms_load(struct drm_device *dev);
886 struct drm_plane *vc4_plane_init(struct drm_device *dev,
887 enum drm_plane_type type);
888 int vc4_plane_create_additional_planes(struct drm_device *dev);
889 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
890 u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
891 void vc4_plane_async_set_fb(struct drm_plane *plane,
892 struct drm_framebuffer *fb);
895 extern struct platform_driver vc4_v3d_driver;
896 extern const struct of_device_id vc4_v3d_dt_match[];
897 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4);
898 int vc4_v3d_pm_get(struct vc4_dev *vc4);
899 void vc4_v3d_pm_put(struct vc4_dev *vc4);
903 vc4_validate_bin_cl(struct drm_device *dev,
906 struct vc4_exec_info *exec);
909 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
911 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
914 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
916 bool vc4_check_tex_size(struct vc4_exec_info *exec,
917 struct drm_gem_cma_object *fbo,
918 uint32_t offset, uint8_t tiling_format,
919 uint32_t width, uint32_t height, uint8_t cpp);
921 /* vc4_validate_shader.c */
922 struct vc4_validated_shader_info *
923 vc4_validate_shader(struct drm_gem_cma_object *shader_obj);
925 int vc4_debugfs_gem_info(struct seq_file *m, void *data);
926 int vc4_drm_gem_prime_fd_to_handle(struct drm_device *dev,
927 struct drm_file *file_priv, int prime_fd, uint32_t *handle);
930 void vc4_perfmon_get(struct vc4_perfmon *perfmon);
931 void vc4_perfmon_put(struct vc4_perfmon *perfmon);
932 void vc4_perfmon_start(struct vc4_dev *vc4, struct vc4_perfmon *perfmon);
933 void vc4_perfmon_stop(struct vc4_dev *vc4, struct vc4_perfmon *perfmon,
935 struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id);
936 void vc4_perfmon_open_file(struct vc4_file *vc4file);
937 void vc4_perfmon_close_file(struct vc4_file *vc4file);
938 int vc4_perfmon_create_ioctl(struct drm_device *dev, void *data,
939 struct drm_file *file_priv);
940 int vc4_perfmon_destroy_ioctl(struct drm_device *dev, void *data,
941 struct drm_file *file_priv);
942 int vc4_perfmon_get_values_ioctl(struct drm_device *dev, void *data,
943 struct drm_file *file_priv);
945 #endif /* _VC4_DRV_H_ */