2 * Copyright (C) 2015 Broadcom
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/reservation.h>
11 #include <drm/drm_encoder.h>
12 #include <drm/drm_gem_cma_helper.h>
13 #include <drm/drm_atomic.h>
15 #include "uapi/drm/vc4_drm.h"
17 /* Don't forget to update vc4_bo.c: bo_type_names[] when adding to
20 enum vc4_kernel_bo_type {
21 /* Any kernel allocation (gem_create_object hook) before it
22 * gets another type set.
26 VC4_BO_TYPE_V3D_SHADER,
31 VC4_BO_TYPE_KERNEL_CACHE,
35 /* Performance monitor object. The perform lifetime is controlled by userspace
36 * using perfmon related ioctls. A perfmon can be attached to a submit_cl
37 * request, and when this is the case, HW perf counters will be activated just
38 * before the submit_cl is submitted to the GPU and disabled when the job is
39 * done. This way, only events related to a specific job will be counted.
42 /* Tracks the number of users of the perfmon, when this counter reaches
43 * zero the perfmon is destroyed.
47 /* Number of counters activated in this perfmon instance
48 * (should be less than DRM_VC4_MAX_PERF_COUNTERS).
52 /* Events counted by the HW perf counters. */
53 u8 events[DRM_VC4_MAX_PERF_COUNTERS];
55 /* Storage for counter values. Counters are incremented by the HW
56 * perf counter values every time the perfmon is attached to a GPU job.
57 * This way, perfmon users don't have to retrieve the results after
58 * each job if they want to track events covering several submissions.
59 * Note that counter values can't be reset, but you can fake a reset by
60 * destroying the perfmon and creating a new one.
66 struct drm_device *dev;
68 struct vc4_hdmi *hdmi;
75 struct vc4_hang_state *hang_state;
77 /* The kernel-space BO cache. Tracks buffers that have been
78 * unreferenced by all other users (refcounts of 0!) but not
79 * yet freed, so we can do cheap allocations.
82 /* Array of list heads for entries in the BO cache,
83 * based on number of pages, so we can do O(1) lookups
84 * in the cache when allocating.
86 struct list_head *size_list;
87 uint32_t size_list_size;
89 /* List of all BOs in the cache, ordered by age, so we
90 * can do O(1) lookups when trying to free old
93 struct list_head time_list;
94 struct work_struct time_work;
95 struct timer_list time_timer;
105 /* Protects bo_cache and bo_labels. */
106 struct mutex bo_lock;
108 /* Purgeable BO pool. All BOs in this pool can have their memory
109 * reclaimed if the driver is unable to allocate new BOs. We also
110 * keep stats related to the purge mechanism here.
113 struct list_head list;
116 unsigned int purged_num;
121 uint64_t dma_fence_context;
123 /* Sequence number for the last job queued in bin_job_list.
124 * Starts at 0 (no jobs emitted).
128 /* Sequence number for the last completed job on the GPU.
129 * Starts at 0 (no jobs completed).
131 uint64_t finished_seqno;
133 /* List of all struct vc4_exec_info for jobs to be executed in
134 * the binner. The first job in the list is the one currently
135 * programmed into ct0ca for execution.
137 struct list_head bin_job_list;
139 /* List of all struct vc4_exec_info for jobs that have
140 * completed binning and are ready for rendering. The first
141 * job in the list is the one currently programmed into ct1ca
144 struct list_head render_job_list;
146 /* List of the finished vc4_exec_infos waiting to be freed by
149 struct list_head job_done_list;
150 /* Spinlock used to synchronize the job_list and seqno
151 * accesses between the IRQ handler and GEM ioctls.
154 wait_queue_head_t job_wait_queue;
155 struct work_struct job_done_work;
157 /* Used to track the active perfmon if any. Access to this field is
158 * protected by job_lock.
160 struct vc4_perfmon *active_perfmon;
162 /* List of struct vc4_seqno_cb for callbacks to be made from a
163 * workqueue when the given seqno is passed.
165 struct list_head seqno_cb_list;
167 /* The memory used for storing binner tile alloc, tile state,
168 * and overflow memory allocations. This is freed when V3D
171 struct vc4_bo *bin_bo;
173 /* Size of blocks allocated within bin_bo. */
174 uint32_t bin_alloc_size;
176 /* Bitmask of the bin_alloc_size chunks in bin_bo that are
179 uint32_t bin_alloc_used;
181 /* Bitmask of the current bin_alloc used for overflow memory. */
182 uint32_t bin_alloc_overflow;
184 struct work_struct overflow_mem_work;
188 /* Mutex controlling the power refcount. */
189 struct mutex power_lock;
192 struct timer_list timer;
193 struct work_struct reset_work;
196 struct semaphore async_modeset;
198 struct drm_modeset_lock ctm_state_lock;
199 struct drm_private_obj ctm_manager;
202 static inline struct vc4_dev *
203 to_vc4_dev(struct drm_device *dev)
205 return (struct vc4_dev *)dev->dev_private;
209 struct drm_gem_cma_object base;
211 /* seqno of the last job to render using this BO. */
214 /* seqno of the last job to use the RCL to write to this BO.
216 * Note that this doesn't include binner overflow memory
219 uint64_t write_seqno;
223 /* List entry for the BO's position in either
224 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
226 struct list_head unref_head;
228 /* Time in jiffies when the BO was put in vc4->bo_cache. */
229 unsigned long free_time;
231 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
232 struct list_head size_head;
234 /* Struct for shader validation state, if created by
235 * DRM_IOCTL_VC4_CREATE_SHADER_BO.
237 struct vc4_validated_shader_info *validated_shader;
239 /* normally (resv == &_resv) except for imported bo's */
240 struct reservation_object *resv;
241 struct reservation_object _resv;
243 /* One of enum vc4_kernel_bo_type, or VC4_BO_TYPE_COUNT + i
244 * for user-allocated labels.
248 /* Count the number of active users. This is needed to determine
249 * whether we can move the BO to the purgeable list or not (when the BO
250 * is used by the GPU or the display engine we can't purge it).
254 /* Store purgeable/purged state here */
256 struct mutex madv_lock;
259 static inline struct vc4_bo *
260 to_vc4_bo(struct drm_gem_object *bo)
262 return (struct vc4_bo *)bo;
266 struct dma_fence base;
267 struct drm_device *dev;
268 /* vc4 seqno for signaled() test */
272 static inline struct vc4_fence *
273 to_vc4_fence(struct dma_fence *fence)
275 return (struct vc4_fence *)fence;
278 struct vc4_seqno_cb {
279 struct work_struct work;
281 void (*func)(struct vc4_seqno_cb *cb);
286 struct platform_device *pdev;
292 struct platform_device *pdev;
296 /* Memory manager for CRTCs to allocate space in the display
297 * list. Units are dwords.
299 struct drm_mm dlist_mm;
300 /* Memory manager for the LBM memory used by HVS scaling. */
301 struct drm_mm lbm_mm;
304 struct drm_mm_node mitchell_netravali_filter;
308 struct drm_plane base;
311 static inline struct vc4_plane *
312 to_vc4_plane(struct drm_plane *plane)
314 return (struct vc4_plane *)plane;
317 enum vc4_scaling_mode {
323 struct vc4_plane_state {
324 struct drm_plane_state base;
325 /* System memory copy of the display list for this element, computed
326 * at atomic_check time.
329 u32 dlist_size; /* Number of dwords allocated for the display list */
330 u32 dlist_count; /* Number of used dwords in the display list. */
332 /* Offset in the dlist to various words, for pageflip or
339 /* Offset where the plane's dlist was last stored in the
340 * hardware at vc4_crtc_atomic_flush() time.
342 u32 __iomem *hw_dlist;
344 /* Clipped coordinates of the plane on the display. */
345 int crtc_x, crtc_y, crtc_w, crtc_h;
346 /* Clipped area being scanned from in the FB. */
349 u32 src_w[2], src_h[2];
351 /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
352 enum vc4_scaling_mode x_scaling[2], y_scaling[2];
356 /* Offset to start scanning out from the start of the plane's
361 /* Our allocation in LBM for temporary storage during scaling. */
362 struct drm_mm_node lbm;
364 /* Set when the plane has per-pixel alpha content or does not cover
365 * the entire screen. This is a hint to the CRTC that it might need
366 * to enable background color fill.
371 static inline struct vc4_plane_state *
372 to_vc4_plane_state(struct drm_plane_state *state)
374 return (struct vc4_plane_state *)state;
377 enum vc4_encoder_type {
378 VC4_ENCODER_TYPE_NONE,
379 VC4_ENCODER_TYPE_HDMI,
380 VC4_ENCODER_TYPE_VEC,
381 VC4_ENCODER_TYPE_DSI0,
382 VC4_ENCODER_TYPE_DSI1,
383 VC4_ENCODER_TYPE_SMI,
384 VC4_ENCODER_TYPE_DPI,
388 struct drm_encoder base;
389 enum vc4_encoder_type type;
393 static inline struct vc4_encoder *
394 to_vc4_encoder(struct drm_encoder *encoder)
396 return container_of(encoder, struct vc4_encoder, base);
399 struct vc4_crtc_data {
400 /* Which channel of the HVS this pixelvalve sources from. */
403 enum vc4_encoder_type encoder_types[4];
407 struct drm_crtc base;
408 const struct vc4_crtc_data *data;
411 /* Timestamp at start of vblank irq - unaffected by lock delays. */
414 /* Which HVS channel we're using for our CRTC. */
420 /* Size in pixels of the COB memory allocated to this CRTC. */
423 struct drm_pending_vblank_event *event;
426 static inline struct vc4_crtc *
427 to_vc4_crtc(struct drm_crtc *crtc)
429 return (struct vc4_crtc *)crtc;
432 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
433 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
434 #define HVS_READ(offset) readl(vc4->hvs->regs + offset)
435 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
437 struct vc4_exec_info {
438 /* Sequence number for this bin/render job. */
441 /* Latest write_seqno of any BO that binning depends on. */
442 uint64_t bin_dep_seqno;
444 struct dma_fence *fence;
446 /* Last current addresses the hardware was processing when the
447 * hangcheck timer checked on us.
449 uint32_t last_ct0ca, last_ct1ca;
451 /* Kernel-space copy of the ioctl arguments */
452 struct drm_vc4_submit_cl *args;
454 /* This is the array of BOs that were looked up at the start of exec.
455 * Command validation will use indices into this array.
457 struct drm_gem_cma_object **bo;
460 /* List of BOs that are being written by the RCL. Other than
461 * the binner temporary storage, this is all the BOs written
464 struct drm_gem_cma_object *rcl_write_bo[4];
465 uint32_t rcl_write_bo_count;
467 /* Pointers for our position in vc4->job_list */
468 struct list_head head;
470 /* List of other BOs used in the job that need to be released
471 * once the job is complete.
473 struct list_head unref_list;
475 /* Current unvalidated indices into @bo loaded by the non-hardware
476 * VC4_PACKET_GEM_HANDLES.
478 uint32_t bo_index[2];
480 /* This is the BO where we store the validated command lists, shader
481 * records, and uniforms.
483 struct drm_gem_cma_object *exec_bo;
486 * This tracks the per-shader-record state (packet 64) that
487 * determines the length of the shader record and the offset
488 * it's expected to be found at. It gets read in from the
491 struct vc4_shader_state {
493 /* Maximum vertex index referenced by any primitive using this
499 /** How many shader states the user declared they were using. */
500 uint32_t shader_state_size;
501 /** How many shader state records the validator has seen. */
502 uint32_t shader_state_count;
504 bool found_tile_binning_mode_config_packet;
505 bool found_start_tile_binning_packet;
506 bool found_increment_semaphore_packet;
508 uint8_t bin_tiles_x, bin_tiles_y;
509 /* Physical address of the start of the tile alloc array
510 * (where each tile's binned CL will start)
512 uint32_t tile_alloc_offset;
513 /* Bitmask of which binner slots are freed when this job completes. */
517 * Computed addresses pointing into exec_bo where we start the
518 * bin thread (ct0) and render thread (ct1).
520 uint32_t ct0ca, ct0ea;
521 uint32_t ct1ca, ct1ea;
523 /* Pointer to the unvalidated bin CL (if present). */
526 /* Pointers to the shader recs. These paddr gets incremented as CL
527 * packets are relocated in validate_gl_shader_state, and the vaddrs
528 * (u and v) get incremented and size decremented as the shader recs
529 * themselves are validated.
533 uint32_t shader_rec_p;
534 uint32_t shader_rec_size;
536 /* Pointers to the uniform data. These pointers are incremented, and
537 * size decremented, as each batch of uniforms is uploaded.
542 uint32_t uniforms_size;
544 /* Pointer to a performance monitor object if the user requested it,
547 struct vc4_perfmon *perfmon;
550 /* Per-open file private data. Any driver-specific resource that has to be
551 * released when the DRM file is closed should be placed here.
560 static inline struct vc4_exec_info *
561 vc4_first_bin_job(struct vc4_dev *vc4)
563 return list_first_entry_or_null(&vc4->bin_job_list,
564 struct vc4_exec_info, head);
567 static inline struct vc4_exec_info *
568 vc4_first_render_job(struct vc4_dev *vc4)
570 return list_first_entry_or_null(&vc4->render_job_list,
571 struct vc4_exec_info, head);
574 static inline struct vc4_exec_info *
575 vc4_last_render_job(struct vc4_dev *vc4)
577 if (list_empty(&vc4->render_job_list))
579 return list_last_entry(&vc4->render_job_list,
580 struct vc4_exec_info, head);
584 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
587 * This will be used at draw time to relocate the reference to the texture
588 * contents in p0, and validate that the offset combined with
589 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
590 * Note that the hardware treats unprovided config parameters as 0, so not all
591 * of them need to be set up for every texure sample, and we'll store ~0 as
592 * the offset to mark the unused ones.
594 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
595 * Setup") for definitions of the texture parameters.
597 struct vc4_texture_sample_info {
599 uint32_t p_offset[4];
603 * struct vc4_validated_shader_info - information about validated shaders that
604 * needs to be used from command list validation.
606 * For a given shader, each time a shader state record references it, we need
607 * to verify that the shader doesn't read more uniforms than the shader state
608 * record's uniform BO pointer can provide, and we need to apply relocations
609 * and validate the shader state record's uniforms that define the texture
612 struct vc4_validated_shader_info {
613 uint32_t uniforms_size;
614 uint32_t uniforms_src_size;
615 uint32_t num_texture_samples;
616 struct vc4_texture_sample_info *texture_samples;
618 uint32_t num_uniform_addr_offsets;
619 uint32_t *uniform_addr_offsets;
625 * _wait_for - magic (register) wait macro
627 * Does the right thing for modeset paths when run under kdgb or similar atomic
628 * contexts. Note that it's important that we check the condition again after
629 * having timed out, since the timeout could be due to preemption or similar and
630 * we've never had a chance to check the condition before the timeout.
632 #define _wait_for(COND, MS, W) ({ \
633 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
636 if (time_after(jiffies, timeout__)) { \
638 ret__ = -ETIMEDOUT; \
641 if (W && drm_can_sleep()) { \
650 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
653 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
654 void vc4_free_object(struct drm_gem_object *gem_obj);
655 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
656 bool from_cache, enum vc4_kernel_bo_type type);
657 int vc4_dumb_create(struct drm_file *file_priv,
658 struct drm_device *dev,
659 struct drm_mode_create_dumb *args);
660 struct dma_buf *vc4_prime_export(struct drm_device *dev,
661 struct drm_gem_object *obj, int flags);
662 int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
663 struct drm_file *file_priv);
664 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
665 struct drm_file *file_priv);
666 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
667 struct drm_file *file_priv);
668 int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
669 struct drm_file *file_priv);
670 int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
671 struct drm_file *file_priv);
672 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
673 struct drm_file *file_priv);
674 int vc4_label_bo_ioctl(struct drm_device *dev, void *data,
675 struct drm_file *file_priv);
676 int vc4_fault(struct vm_fault *vmf);
677 int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
678 struct reservation_object *vc4_prime_res_obj(struct drm_gem_object *obj);
679 int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
680 struct drm_gem_object *vc4_prime_import_sg_table(struct drm_device *dev,
681 struct dma_buf_attachment *attach,
682 struct sg_table *sgt);
683 void *vc4_prime_vmap(struct drm_gem_object *obj);
684 int vc4_bo_cache_init(struct drm_device *dev);
685 void vc4_bo_cache_destroy(struct drm_device *dev);
686 int vc4_bo_stats_debugfs(struct seq_file *m, void *arg);
687 int vc4_bo_inc_usecnt(struct vc4_bo *bo);
688 void vc4_bo_dec_usecnt(struct vc4_bo *bo);
689 void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo);
690 void vc4_bo_remove_from_purgeable_pool(struct vc4_bo *bo);
693 extern struct platform_driver vc4_crtc_driver;
694 int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg);
695 bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
696 bool in_vblank_irq, int *vpos, int *hpos,
697 ktime_t *stime, ktime_t *etime,
698 const struct drm_display_mode *mode);
701 int vc4_debugfs_init(struct drm_minor *minor);
704 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
707 extern struct platform_driver vc4_dpi_driver;
708 int vc4_dpi_debugfs_regs(struct seq_file *m, void *unused);
711 extern struct platform_driver vc4_dsi_driver;
712 int vc4_dsi_debugfs_regs(struct seq_file *m, void *unused);
715 extern const struct dma_fence_ops vc4_fence_ops;
718 void vc4_gem_init(struct drm_device *dev);
719 void vc4_gem_destroy(struct drm_device *dev);
720 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
721 struct drm_file *file_priv);
722 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
723 struct drm_file *file_priv);
724 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
725 struct drm_file *file_priv);
726 void vc4_submit_next_bin_job(struct drm_device *dev);
727 void vc4_submit_next_render_job(struct drm_device *dev);
728 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
729 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
730 uint64_t timeout_ns, bool interruptible);
731 void vc4_job_handle_completed(struct vc4_dev *vc4);
732 int vc4_queue_seqno_cb(struct drm_device *dev,
733 struct vc4_seqno_cb *cb, uint64_t seqno,
734 void (*func)(struct vc4_seqno_cb *cb));
735 int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data,
736 struct drm_file *file_priv);
739 extern struct platform_driver vc4_hdmi_driver;
740 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused);
743 extern struct platform_driver vc4_vec_driver;
744 int vc4_vec_debugfs_regs(struct seq_file *m, void *unused);
747 irqreturn_t vc4_irq(int irq, void *arg);
748 void vc4_irq_preinstall(struct drm_device *dev);
749 int vc4_irq_postinstall(struct drm_device *dev);
750 void vc4_irq_uninstall(struct drm_device *dev);
751 void vc4_irq_reset(struct drm_device *dev);
754 extern struct platform_driver vc4_hvs_driver;
755 void vc4_hvs_dump_state(struct drm_device *dev);
756 int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused);
759 int vc4_kms_load(struct drm_device *dev);
762 struct drm_plane *vc4_plane_init(struct drm_device *dev,
763 enum drm_plane_type type);
764 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
765 u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
766 void vc4_plane_async_set_fb(struct drm_plane *plane,
767 struct drm_framebuffer *fb);
770 extern struct platform_driver vc4_v3d_driver;
771 int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused);
772 int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused);
773 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4);
777 vc4_validate_bin_cl(struct drm_device *dev,
780 struct vc4_exec_info *exec);
783 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
785 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
788 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
790 bool vc4_check_tex_size(struct vc4_exec_info *exec,
791 struct drm_gem_cma_object *fbo,
792 uint32_t offset, uint8_t tiling_format,
793 uint32_t width, uint32_t height, uint8_t cpp);
795 /* vc4_validate_shader.c */
796 struct vc4_validated_shader_info *
797 vc4_validate_shader(struct drm_gem_cma_object *shader_obj);
800 void vc4_perfmon_get(struct vc4_perfmon *perfmon);
801 void vc4_perfmon_put(struct vc4_perfmon *perfmon);
802 void vc4_perfmon_start(struct vc4_dev *vc4, struct vc4_perfmon *perfmon);
803 void vc4_perfmon_stop(struct vc4_dev *vc4, struct vc4_perfmon *perfmon,
805 struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id);
806 void vc4_perfmon_open_file(struct vc4_file *vc4file);
807 void vc4_perfmon_close_file(struct vc4_file *vc4file);
808 int vc4_perfmon_create_ioctl(struct drm_device *dev, void *data,
809 struct drm_file *file_priv);
810 int vc4_perfmon_destroy_ioctl(struct drm_device *dev, void *data,
811 struct drm_file *file_priv);
812 int vc4_perfmon_get_values_ioctl(struct drm_device *dev, void *data,
813 struct drm_file *file_priv);