2 * Copyright (C) 2015 Broadcom
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/mm_types.h>
10 #include <linux/reservation.h>
12 #include <drm/drm_encoder.h>
13 #include <drm/drm_gem_cma_helper.h>
14 #include <drm/drm_atomic.h>
15 #include <drm/drm_syncobj.h>
17 #include "uapi/drm/vc4_drm.h"
19 /* Don't forget to update vc4_bo.c: bo_type_names[] when adding to
22 enum vc4_kernel_bo_type {
23 /* Any kernel allocation (gem_create_object hook) before it
24 * gets another type set.
28 VC4_BO_TYPE_V3D_SHADER,
33 VC4_BO_TYPE_KERNEL_CACHE,
37 /* Performance monitor object. The perform lifetime is controlled by userspace
38 * using perfmon related ioctls. A perfmon can be attached to a submit_cl
39 * request, and when this is the case, HW perf counters will be activated just
40 * before the submit_cl is submitted to the GPU and disabled when the job is
41 * done. This way, only events related to a specific job will be counted.
44 /* Tracks the number of users of the perfmon, when this counter reaches
45 * zero the perfmon is destroyed.
49 /* Number of counters activated in this perfmon instance
50 * (should be less than DRM_VC4_MAX_PERF_COUNTERS).
54 /* Events counted by the HW perf counters. */
55 u8 events[DRM_VC4_MAX_PERF_COUNTERS];
57 /* Storage for counter values. Counters are incremented by the HW
58 * perf counter values every time the perfmon is attached to a GPU job.
59 * This way, perfmon users don't have to retrieve the results after
60 * each job if they want to track events covering several submissions.
61 * Note that counter values can't be reset, but you can fake a reset by
62 * destroying the perfmon and creating a new one.
68 struct drm_device *dev;
71 struct rpi_firmware *firmware;
73 struct vc4_hdmi *hdmi;
80 struct vc4_fkms *fkms;
82 struct vc4_hang_state *hang_state;
84 /* The kernel-space BO cache. Tracks buffers that have been
85 * unreferenced by all other users (refcounts of 0!) but not
86 * yet freed, so we can do cheap allocations.
89 /* Array of list heads for entries in the BO cache,
90 * based on number of pages, so we can do O(1) lookups
91 * in the cache when allocating.
93 struct list_head *size_list;
94 uint32_t size_list_size;
96 /* List of all BOs in the cache, ordered by age, so we
97 * can do O(1) lookups when trying to free old
100 struct list_head time_list;
101 struct work_struct time_work;
102 struct timer_list time_timer;
112 /* Protects bo_cache and bo_labels. */
113 struct mutex bo_lock;
115 /* Purgeable BO pool. All BOs in this pool can have their memory
116 * reclaimed if the driver is unable to allocate new BOs. We also
117 * keep stats related to the purge mechanism here.
120 struct list_head list;
123 unsigned int purged_num;
128 uint64_t dma_fence_context;
130 /* Sequence number for the last job queued in bin_job_list.
131 * Starts at 0 (no jobs emitted).
135 /* Sequence number for the last completed job on the GPU.
136 * Starts at 0 (no jobs completed).
138 uint64_t finished_seqno;
140 /* List of all struct vc4_exec_info for jobs to be executed in
141 * the binner. The first job in the list is the one currently
142 * programmed into ct0ca for execution.
144 struct list_head bin_job_list;
146 /* List of all struct vc4_exec_info for jobs that have
147 * completed binning and are ready for rendering. The first
148 * job in the list is the one currently programmed into ct1ca
151 struct list_head render_job_list;
153 /* List of the finished vc4_exec_infos waiting to be freed by
156 struct list_head job_done_list;
157 /* Spinlock used to synchronize the job_list and seqno
158 * accesses between the IRQ handler and GEM ioctls.
161 wait_queue_head_t job_wait_queue;
162 struct work_struct job_done_work;
164 /* Used to track the active perfmon if any. Access to this field is
165 * protected by job_lock.
167 struct vc4_perfmon *active_perfmon;
169 /* List of struct vc4_seqno_cb for callbacks to be made from a
170 * workqueue when the given seqno is passed.
172 struct list_head seqno_cb_list;
174 /* The memory used for storing binner tile alloc, tile state,
175 * and overflow memory allocations. This is freed when V3D
178 struct vc4_bo *bin_bo;
180 /* Size of blocks allocated within bin_bo. */
181 uint32_t bin_alloc_size;
183 /* Bitmask of the bin_alloc_size chunks in bin_bo that are
186 uint32_t bin_alloc_used;
188 /* Bitmask of the current bin_alloc used for overflow memory. */
189 uint32_t bin_alloc_overflow;
191 struct work_struct overflow_mem_work;
195 /* Mutex controlling the power refcount. */
196 struct mutex power_lock;
199 struct timer_list timer;
200 struct work_struct reset_work;
203 struct semaphore async_modeset;
205 struct drm_modeset_lock ctm_state_lock;
206 struct drm_private_obj ctm_manager;
209 static inline struct vc4_dev *
210 to_vc4_dev(struct drm_device *dev)
212 return (struct vc4_dev *)dev->dev_private;
216 struct drm_gem_cma_object base;
218 /* seqno of the last job to render using this BO. */
221 /* seqno of the last job to use the RCL to write to this BO.
223 * Note that this doesn't include binner overflow memory
226 uint64_t write_seqno;
230 /* List entry for the BO's position in either
231 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
233 struct list_head unref_head;
235 /* Time in jiffies when the BO was put in vc4->bo_cache. */
236 unsigned long free_time;
238 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
239 struct list_head size_head;
241 /* Struct for shader validation state, if created by
242 * DRM_IOCTL_VC4_CREATE_SHADER_BO.
244 struct vc4_validated_shader_info *validated_shader;
246 /* normally (resv == &_resv) except for imported bo's */
247 struct reservation_object *resv;
248 struct reservation_object _resv;
250 /* One of enum vc4_kernel_bo_type, or VC4_BO_TYPE_COUNT + i
251 * for user-allocated labels.
255 /* Count the number of active users. This is needed to determine
256 * whether we can move the BO to the purgeable list or not (when the BO
257 * is used by the GPU or the display engine we can't purge it).
261 /* Store purgeable/purged state here */
263 struct mutex madv_lock;
266 static inline struct vc4_bo *
267 to_vc4_bo(struct drm_gem_object *bo)
269 return (struct vc4_bo *)bo;
273 struct dma_fence base;
274 struct drm_device *dev;
275 /* vc4 seqno for signaled() test */
279 static inline struct vc4_fence *
280 to_vc4_fence(struct dma_fence *fence)
282 return (struct vc4_fence *)fence;
285 struct vc4_seqno_cb {
286 struct work_struct work;
288 void (*func)(struct vc4_seqno_cb *cb);
293 struct platform_device *pdev;
299 struct platform_device *pdev;
303 /* Memory manager for CRTCs to allocate space in the display
304 * list. Units are dwords.
306 struct drm_mm dlist_mm;
307 /* Memory manager for the LBM memory used by HVS scaling. */
308 struct drm_mm lbm_mm;
311 struct drm_mm_node mitchell_netravali_filter;
315 struct drm_plane base;
318 static inline struct vc4_plane *
319 to_vc4_plane(struct drm_plane *plane)
321 return (struct vc4_plane *)plane;
324 enum vc4_scaling_mode {
330 struct vc4_plane_state {
331 struct drm_plane_state base;
332 /* System memory copy of the display list for this element, computed
333 * at atomic_check time.
336 u32 dlist_size; /* Number of dwords allocated for the display list */
337 u32 dlist_count; /* Number of used dwords in the display list. */
339 /* Offset in the dlist to various words, for pageflip or
346 /* Offset where the plane's dlist was last stored in the
347 * hardware at vc4_crtc_atomic_flush() time.
349 u32 __iomem *hw_dlist;
351 /* Clipped coordinates of the plane on the display. */
352 int crtc_x, crtc_y, crtc_w, crtc_h;
353 /* Clipped area being scanned from in the FB. */
356 u32 src_w[2], src_h[2];
358 /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
359 enum vc4_scaling_mode x_scaling[2], y_scaling[2];
363 /* Offset to start scanning out from the start of the plane's
368 /* Our allocation in LBM for temporary storage during scaling. */
369 struct drm_mm_node lbm;
371 /* Set when the plane has per-pixel alpha content or does not cover
372 * the entire screen. This is a hint to the CRTC that it might need
373 * to enable background color fill.
378 static inline struct vc4_plane_state *
379 to_vc4_plane_state(struct drm_plane_state *state)
381 return (struct vc4_plane_state *)state;
384 enum vc4_encoder_type {
385 VC4_ENCODER_TYPE_NONE,
386 VC4_ENCODER_TYPE_HDMI,
387 VC4_ENCODER_TYPE_VEC,
388 VC4_ENCODER_TYPE_DSI0,
389 VC4_ENCODER_TYPE_DSI1,
390 VC4_ENCODER_TYPE_SMI,
391 VC4_ENCODER_TYPE_DPI,
395 struct drm_encoder base;
396 enum vc4_encoder_type type;
400 static inline struct vc4_encoder *
401 to_vc4_encoder(struct drm_encoder *encoder)
403 return container_of(encoder, struct vc4_encoder, base);
406 struct vc4_crtc_data {
407 /* Which channel of the HVS this pixelvalve sources from. */
410 enum vc4_encoder_type encoder_types[4];
414 struct drm_crtc base;
415 const struct vc4_crtc_data *data;
418 /* Timestamp at start of vblank irq - unaffected by lock delays. */
421 /* Which HVS channel we're using for our CRTC. */
427 /* Size in pixels of the COB memory allocated to this CRTC. */
430 struct drm_pending_vblank_event *event;
433 static inline struct vc4_crtc *
434 to_vc4_crtc(struct drm_crtc *crtc)
436 return (struct vc4_crtc *)crtc;
439 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
440 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
441 #define HVS_READ(offset) readl(vc4->hvs->regs + offset)
442 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
444 struct vc4_exec_info {
445 /* Sequence number for this bin/render job. */
448 /* Latest write_seqno of any BO that binning depends on. */
449 uint64_t bin_dep_seqno;
451 struct dma_fence *fence;
453 /* Last current addresses the hardware was processing when the
454 * hangcheck timer checked on us.
456 uint32_t last_ct0ca, last_ct1ca;
458 /* Kernel-space copy of the ioctl arguments */
459 struct drm_vc4_submit_cl *args;
461 /* This is the array of BOs that were looked up at the start of exec.
462 * Command validation will use indices into this array.
464 struct drm_gem_cma_object **bo;
467 /* List of BOs that are being written by the RCL. Other than
468 * the binner temporary storage, this is all the BOs written
471 struct drm_gem_cma_object *rcl_write_bo[4];
472 uint32_t rcl_write_bo_count;
474 /* Pointers for our position in vc4->job_list */
475 struct list_head head;
477 /* List of other BOs used in the job that need to be released
478 * once the job is complete.
480 struct list_head unref_list;
482 /* Current unvalidated indices into @bo loaded by the non-hardware
483 * VC4_PACKET_GEM_HANDLES.
485 uint32_t bo_index[2];
487 /* This is the BO where we store the validated command lists, shader
488 * records, and uniforms.
490 struct drm_gem_cma_object *exec_bo;
493 * This tracks the per-shader-record state (packet 64) that
494 * determines the length of the shader record and the offset
495 * it's expected to be found at. It gets read in from the
498 struct vc4_shader_state {
500 /* Maximum vertex index referenced by any primitive using this
506 /** How many shader states the user declared they were using. */
507 uint32_t shader_state_size;
508 /** How many shader state records the validator has seen. */
509 uint32_t shader_state_count;
511 bool found_tile_binning_mode_config_packet;
512 bool found_start_tile_binning_packet;
513 bool found_increment_semaphore_packet;
515 uint8_t bin_tiles_x, bin_tiles_y;
516 /* Physical address of the start of the tile alloc array
517 * (where each tile's binned CL will start)
519 uint32_t tile_alloc_offset;
520 /* Bitmask of which binner slots are freed when this job completes. */
524 * Computed addresses pointing into exec_bo where we start the
525 * bin thread (ct0) and render thread (ct1).
527 uint32_t ct0ca, ct0ea;
528 uint32_t ct1ca, ct1ea;
530 /* Pointer to the unvalidated bin CL (if present). */
533 /* Pointers to the shader recs. These paddr gets incremented as CL
534 * packets are relocated in validate_gl_shader_state, and the vaddrs
535 * (u and v) get incremented and size decremented as the shader recs
536 * themselves are validated.
540 uint32_t shader_rec_p;
541 uint32_t shader_rec_size;
543 /* Pointers to the uniform data. These pointers are incremented, and
544 * size decremented, as each batch of uniforms is uploaded.
549 uint32_t uniforms_size;
551 /* Pointer to a performance monitor object if the user requested it,
554 struct vc4_perfmon *perfmon;
557 struct drm_vc4_file_private {
562 /* Per-open file private data. Any driver-specific resource that has to be
563 * released when the DRM file is closed should be placed here.
570 struct drm_vc4_file_private priv;
573 static inline struct vc4_exec_info *
574 vc4_first_bin_job(struct vc4_dev *vc4)
576 return list_first_entry_or_null(&vc4->bin_job_list,
577 struct vc4_exec_info, head);
580 static inline struct vc4_exec_info *
581 vc4_first_render_job(struct vc4_dev *vc4)
583 return list_first_entry_or_null(&vc4->render_job_list,
584 struct vc4_exec_info, head);
587 static inline struct vc4_exec_info *
588 vc4_last_render_job(struct vc4_dev *vc4)
590 if (list_empty(&vc4->render_job_list))
592 return list_last_entry(&vc4->render_job_list,
593 struct vc4_exec_info, head);
597 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
600 * This will be used at draw time to relocate the reference to the texture
601 * contents in p0, and validate that the offset combined with
602 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
603 * Note that the hardware treats unprovided config parameters as 0, so not all
604 * of them need to be set up for every texure sample, and we'll store ~0 as
605 * the offset to mark the unused ones.
607 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
608 * Setup") for definitions of the texture parameters.
610 struct vc4_texture_sample_info {
612 uint32_t p_offset[4];
616 * struct vc4_validated_shader_info - information about validated shaders that
617 * needs to be used from command list validation.
619 * For a given shader, each time a shader state record references it, we need
620 * to verify that the shader doesn't read more uniforms than the shader state
621 * record's uniform BO pointer can provide, and we need to apply relocations
622 * and validate the shader state record's uniforms that define the texture
625 struct vc4_validated_shader_info {
626 uint32_t uniforms_size;
627 uint32_t uniforms_src_size;
628 uint32_t num_texture_samples;
629 struct vc4_texture_sample_info *texture_samples;
631 uint32_t num_uniform_addr_offsets;
632 uint32_t *uniform_addr_offsets;
638 * _wait_for - magic (register) wait macro
640 * Does the right thing for modeset paths when run under kdgb or similar atomic
641 * contexts. Note that it's important that we check the condition again after
642 * having timed out, since the timeout could be due to preemption or similar and
643 * we've never had a chance to check the condition before the timeout.
645 #define _wait_for(COND, MS, W) ({ \
646 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
649 if (time_after(jiffies, timeout__)) { \
651 ret__ = -ETIMEDOUT; \
654 if (W && drm_can_sleep()) { \
663 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
666 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
667 void vc4_free_object(struct drm_gem_object *gem_obj);
668 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
669 bool from_cache, enum vc4_kernel_bo_type type);
670 int vc4_dumb_create(struct drm_file *file_priv,
671 struct drm_device *dev,
672 struct drm_mode_create_dumb *args);
673 struct dma_buf *vc4_prime_export(struct drm_device *dev,
674 struct drm_gem_object *obj, int flags);
675 int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
676 struct drm_file *file_priv);
677 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
678 struct drm_file *file_priv);
679 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
680 struct drm_file *file_priv);
681 int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
682 struct drm_file *file_priv);
683 int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
684 struct drm_file *file_priv);
685 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
686 struct drm_file *file_priv);
687 int vc4_label_bo_ioctl(struct drm_device *dev, void *data,
688 struct drm_file *file_priv);
689 vm_fault_t vc4_fault(struct vm_fault *vmf);
690 int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
691 struct reservation_object *vc4_prime_res_obj(struct drm_gem_object *obj);
692 int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
693 struct drm_gem_object *vc4_prime_import_sg_table(struct drm_device *dev,
694 struct dma_buf_attachment *attach,
695 struct sg_table *sgt);
696 void *vc4_prime_vmap(struct drm_gem_object *obj);
697 int vc4_bo_cache_init(struct drm_device *dev);
698 void vc4_bo_cache_destroy(struct drm_device *dev);
699 int vc4_bo_stats_debugfs(struct seq_file *m, void *arg);
700 int vc4_bo_inc_usecnt(struct vc4_bo *bo);
701 void vc4_bo_dec_usecnt(struct vc4_bo *bo);
702 void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo);
703 void vc4_bo_remove_from_purgeable_pool(struct vc4_bo *bo);
706 extern struct platform_driver vc4_crtc_driver;
707 int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg);
708 bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
709 bool in_vblank_irq, int *vpos, int *hpos,
710 ktime_t *stime, ktime_t *etime,
711 const struct drm_display_mode *mode);
712 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc);
713 void vc4_crtc_txp_armed(struct drm_crtc_state *state);
714 void vc4_crtc_get_margins(struct drm_crtc_state *state,
715 unsigned int *right, unsigned int *left,
716 unsigned int *top, unsigned int *bottom);
719 int vc4_debugfs_init(struct drm_minor *minor);
722 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
725 extern struct platform_driver vc4_dpi_driver;
726 int vc4_dpi_debugfs_regs(struct seq_file *m, void *unused);
729 extern struct platform_driver vc4_dsi_driver;
730 int vc4_dsi_debugfs_regs(struct seq_file *m, void *unused);
733 extern const struct dma_fence_ops vc4_fence_ops;
735 /* vc4_firmware_kms.c */
736 extern struct platform_driver vc4_firmware_kms_driver;
739 void vc4_gem_init(struct drm_device *dev);
740 void vc4_gem_destroy(struct drm_device *dev);
741 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
742 struct drm_file *file_priv);
743 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
744 struct drm_file *file_priv);
745 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
746 struct drm_file *file_priv);
747 void vc4_submit_next_bin_job(struct drm_device *dev);
748 void vc4_submit_next_render_job(struct drm_device *dev);
749 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
750 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
751 uint64_t timeout_ns, bool interruptible);
752 void vc4_job_handle_completed(struct vc4_dev *vc4);
753 int vc4_queue_seqno_cb(struct drm_device *dev,
754 struct vc4_seqno_cb *cb, uint64_t seqno,
755 void (*func)(struct vc4_seqno_cb *cb));
756 int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data,
757 struct drm_file *file_priv);
760 extern struct platform_driver vc4_hdmi_driver;
761 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused);
764 extern struct platform_driver vc4_vec_driver;
765 int vc4_vec_debugfs_regs(struct seq_file *m, void *unused);
768 extern struct platform_driver vc4_txp_driver;
769 int vc4_txp_debugfs_regs(struct seq_file *m, void *unused);
772 irqreturn_t vc4_irq(int irq, void *arg);
773 void vc4_irq_preinstall(struct drm_device *dev);
774 int vc4_irq_postinstall(struct drm_device *dev);
775 void vc4_irq_uninstall(struct drm_device *dev);
776 void vc4_irq_reset(struct drm_device *dev);
779 extern struct platform_driver vc4_hvs_driver;
780 void vc4_hvs_dump_state(struct drm_device *dev);
781 int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused);
784 int vc4_kms_load(struct drm_device *dev);
787 struct drm_plane *vc4_plane_init(struct drm_device *dev,
788 enum drm_plane_type type);
789 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
790 u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
791 void vc4_plane_async_set_fb(struct drm_plane *plane,
792 struct drm_framebuffer *fb);
795 extern struct platform_driver vc4_v3d_driver;
796 int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused);
797 int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused);
798 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4);
802 vc4_validate_bin_cl(struct drm_device *dev,
805 struct vc4_exec_info *exec);
808 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
810 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
813 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
815 bool vc4_check_tex_size(struct vc4_exec_info *exec,
816 struct drm_gem_cma_object *fbo,
817 uint32_t offset, uint8_t tiling_format,
818 uint32_t width, uint32_t height, uint8_t cpp);
820 /* vc4_validate_shader.c */
821 struct vc4_validated_shader_info *
822 vc4_validate_shader(struct drm_gem_cma_object *shader_obj);
824 int vc4_debugfs_gem_info(struct seq_file *m, void *data);
825 int vc4_drm_gem_prime_fd_to_handle(struct drm_device *dev,
826 struct drm_file *file_priv, int prime_fd, uint32_t *handle);
829 void vc4_perfmon_get(struct vc4_perfmon *perfmon);
830 void vc4_perfmon_put(struct vc4_perfmon *perfmon);
831 void vc4_perfmon_start(struct vc4_dev *vc4, struct vc4_perfmon *perfmon);
832 void vc4_perfmon_stop(struct vc4_dev *vc4, struct vc4_perfmon *perfmon,
834 struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id);
835 void vc4_perfmon_open_file(struct vc4_file *vc4file);
836 void vc4_perfmon_close_file(struct vc4_file *vc4file);
837 int vc4_perfmon_create_ioctl(struct drm_device *dev, void *data,
838 struct drm_file *file_priv);
839 int vc4_perfmon_destroy_ioctl(struct drm_device *dev, void *data,
840 struct drm_file *file_priv);
841 int vc4_perfmon_get_values_ioctl(struct drm_device *dev, void *data,
842 struct drm_file *file_priv);