drivers/gpu/drm/vc4/vc4_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 CRTC module
   8  *
   9  * In VC4, the Pixel Valve is what most closely corresponds to the
  10  * DRM's concept of a CRTC.  The PV generates video timings from the
  11  * encoder's clock plus its configuration.  It pulls scaled pixels from
  12  * the HVS at that timing, and feeds it to the encoder.
  13  *
  14  * However, the DRM CRTC also collects the configuration of all the
  15  * DRM planes attached to it.  As a result, the CRTC is also
  16  * responsible for writing the display list for the HVS channel that
  17  * the CRTC will use.
  18  *
  19  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  20  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  21  * image domain can feed either HDMI or the SDTV controller.  The
  22  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  23  * SDTV, etc.) according to which output type is chosen in the mux.
  24  *
  25  * For power management, the pixel valve's registers are all clocked
  26  * by the AXI clock, while the timings and FIFOs make use of the
  27  * output-specific clock.  Since the encoders also directly consume
  28  * the CPRMAN clocks, and know what timings they need, they are the
  29  * ones that set the clock.
  30  */
  31
  32 #include <linux/clk.h>
  33 #include <linux/component.h>
  34 #include <linux/of_device.h>
  35 #include <linux/pm_runtime.h>
  36
  37 #include <drm/drm_atomic.h>
  38 #include <drm/drm_atomic_helper.h>
  39 #include <drm/drm_atomic_uapi.h>
  40 #include <drm/drm_fb_cma_helper.h>
  41 #include <drm/drm_print.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/drm_vblank.h>
  44
  45 #include "vc4_drv.h"
  46 #include "vc4_hdmi.h"
  47 #include "vc4_regs.h"
  48
  49 #define HVS_FIFO_LATENCY_PIX    6
  50
  51 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  52 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
  53
  54 static const struct debugfs_reg32 crtc_regs[] = {
  55         VC4_REG32(PV_CONTROL),
  56         VC4_REG32(PV_V_CONTROL),
  57         VC4_REG32(PV_VSYNCD_EVEN),
  58         VC4_REG32(PV_HORZA),
  59         VC4_REG32(PV_HORZB),
  60         VC4_REG32(PV_VERTA),
  61         VC4_REG32(PV_VERTB),
  62         VC4_REG32(PV_VERTA_EVEN),
  63         VC4_REG32(PV_VERTB_EVEN),
  64         VC4_REG32(PV_INTEN),
  65         VC4_REG32(PV_INTSTAT),
  66         VC4_REG32(PV_STAT),
  67         VC4_REG32(PV_HACT_ACT),
  68 };
  69
  70 static unsigned int
  71 vc4_crtc_get_cob_allocation(struct vc4_dev *vc4, unsigned int channel)
  72 {
  73         struct vc4_hvs *hvs = vc4->hvs;
  74         u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel));
  75         /* Top/base are supposed to be 4-pixel aligned, but the
  76          * Raspberry Pi firmware fills the low bits (which are
  77          * presumably ignored).
  78          */
  79         u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
  80         u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
  81
  82         return top - base + 4;
  83 }
  84
  85 static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
  86                                           bool in_vblank_irq,
  87                                           int *vpos, int *hpos,
  88                                           ktime_t *stime, ktime_t *etime,
  89                                           const struct drm_display_mode *mode)
  90 {
  91         struct drm_device *dev = crtc->dev;
  92         struct vc4_dev *vc4 = to_vc4_dev(dev);
  93         struct vc4_hvs *hvs = vc4->hvs;
  94         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  95         struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
  96         unsigned int cob_size;
  97         u32 val;
  98         int fifo_lines;
  99         int vblank_lines;
 100         bool ret = false;
 101
 102         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 103
 104         /* Get optional system timestamp before query. */
 105         if (stime)
 106                 *stime = ktime_get();
 107
 108         /*
 109          * Read vertical scanline which is currently composed for our
 110          * pixelvalve by the HVS, and also the scaler status.
 111          */
 112         val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel));
 113
 114         /* Get optional system timestamp after query. */
 115         if (etime)
 116                 *etime = ktime_get();
 117
 118         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 119
 120         /* Vertical position of hvs composed scanline. */
 121         *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
 122         *hpos = 0;
 123
 124         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 125                 *vpos /= 2;
 126
 127                 /* Use hpos to correct for field offset in interlaced mode. */
 128                 if (vc4_hvs_get_fifo_frame_count(hvs, vc4_crtc_state->assigned_channel) % 2)
 129                         *hpos += mode->crtc_htotal / 2;
 130         }
 131
 132         cob_size = vc4_crtc_get_cob_allocation(vc4, vc4_crtc_state->assigned_channel);
 133         /* This is the offset we need for translating hvs -> pv scanout pos. */
 134         fifo_lines = cob_size / mode->crtc_hdisplay;
 135
 136         if (fifo_lines > 0)
 137                 ret = true;
 138
 139         /* HVS more than fifo_lines into frame for compositing? */
 140         if (*vpos > fifo_lines) {
 141                 /*
 142                  * We are in active scanout and can get some meaningful results
 143                  * from HVS. The actual PV scanout can not trail behind more
 144                  * than fifo_lines as that is the fifo's capacity. Assume that
 145                  * in active scanout the HVS and PV work in lockstep wrt. HVS
 146                  * refilling the fifo and PV consuming from the fifo, ie.
 147                  * whenever the PV consumes and frees up a scanline in the
 148                  * fifo, the HVS will immediately refill it, therefore
 149                  * incrementing vpos. Therefore we choose HVS read position -
 150                  * fifo size in scanlines as a estimate of the real scanout
 151                  * position of the PV.
 152                  */
 153                 *vpos -= fifo_lines + 1;
 154
 155                 return ret;
 156         }
 157
 158         /*
 159          * Less: This happens when we are in vblank and the HVS, after getting
 160          * the VSTART restart signal from the PV, just started refilling its
 161          * fifo with new lines from the top-most lines of the new framebuffers.
 162          * The PV does not scan out in vblank, so does not remove lines from
 163          * the fifo, so the fifo will be full quickly and the HVS has to pause.
 164          * We can't get meaningful readings wrt. scanline position of the PV
 165          * and need to make things up in a approximative but consistent way.
 166          */
 167         vblank_lines = mode->vtotal - mode->vdisplay;
 168
 169         if (in_vblank_irq) {
 170                 /*
 171                  * Assume the irq handler got called close to first
 172                  * line of vblank, so PV has about a full vblank
 173                  * scanlines to go, and as a base timestamp use the
 174                  * one taken at entry into vblank irq handler, so it
 175                  * is not affected by random delays due to lock
 176                  * contention on event_lock or vblank_time lock in
 177                  * the core.
 178                  */
 179                 *vpos = -vblank_lines;
 180
 181                 if (stime)
 182                         *stime = vc4_crtc->t_vblank;
 183                 if (etime)
 184                         *etime = vc4_crtc->t_vblank;
 185
 186                 /*
 187                  * If the HVS fifo is not yet full then we know for certain
 188                  * we are at the very beginning of vblank, as the hvs just
 189                  * started refilling, and the stime and etime timestamps
 190                  * truly correspond to start of vblank.
 191                  *
 192                  * Unfortunately there's no way to report this to upper levels
 193                  * and make it more useful.
 194                  */
 195         } else {
 196                 /*
 197                  * No clue where we are inside vblank. Return a vpos of zero,
 198                  * which will cause calling code to just return the etime
 199                  * timestamp uncorrected. At least this is no worse than the
 200                  * standard fallback.
 201                  */
 202                 *vpos = 0;
 203         }
 204
 205         return ret;
 206 }
 207
 208 void vc4_crtc_destroy(struct drm_crtc *crtc)
 209 {
 210         drm_crtc_cleanup(crtc);
 211 }
 212
 213 static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
 214 {
 215         const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);
 216         const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
 217         struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev);
 218         u32 fifo_len_bytes = pv_data->fifo_depth;
 219
 220         /*
 221          * Pixels are pulled from the HVS if the number of bytes is
 222          * lower than the FIFO full level.
 223          *
 224          * The latency of the pixel fetch mechanism is 6 pixels, so we
 225          * need to convert those 6 pixels in bytes, depending on the
 226          * format, and then subtract that from the length of the FIFO
 227          * to make sure we never end up in a situation where the FIFO
 228          * is full.
 229          */
 230         switch (format) {
 231         case PV_CONTROL_FORMAT_DSIV_16:
 232         case PV_CONTROL_FORMAT_DSIC_16:
 233                 return fifo_len_bytes - 2 * HVS_FIFO_LATENCY_PIX;
 234         case PV_CONTROL_FORMAT_DSIV_18:
 235                 return fifo_len_bytes - 14;
 236         case PV_CONTROL_FORMAT_24:
 237         case PV_CONTROL_FORMAT_DSIV_24:
 238         default:
 239                 /*
 240                  * For some reason, the pixelvalve4 doesn't work with
 241                  * the usual formula and will only work with 32.
 242                  */
 243                 if (crtc_data->hvs_output == 5)
 244                         return 32;
 245
 246                 /*
 247                  * It looks like in some situations, we will overflow
 248                  * the PixelValve FIFO (with the bit 10 of PV stat being
 249                  * set) and stall the HVS / PV, eventually resulting in
 250                  * a page flip timeout.
 251                  *
 252                  * Displaying the video overlay during a playback with
 253                  * Kodi on an RPi3 seems to be a great solution with a
 254                  * failure rate around 50%.
 255                  *
 256                  * Removing 1 from the FIFO full level however
 257                  * seems to completely remove that issue.
 258                  */
 259                 if (!vc4->is_vc5)
 260                         return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1;
 261
 262                 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
 263         }
 264 }
 265
 266 static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc,
 267                                              u32 format)
 268 {
 269         u32 level = vc4_get_fifo_full_level(vc4_crtc, format);
 270         u32 ret = 0;
 271
 272         ret |= VC4_SET_FIELD((level >> 6),
 273                              PV5_CONTROL_FIFO_LEVEL_HIGH);
 274
 275         return ret | VC4_SET_FIELD(level & 0x3f,
 276                                    PV_CONTROL_FIFO_LEVEL);
 277 }
 278
 279 /*
 280  * Returns the encoder attached to the CRTC.
 281  *
 282  * VC4 can only scan out to one encoder at a time, while the DRM core
 283  * allows drivers to push pixels to more than one encoder from the
 284  * same CRTC.
 285  */
 286 struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc,
 287                                          struct drm_crtc_state *state)
 288 {
 289         struct drm_encoder *encoder;
 290
 291         WARN_ON(hweight32(state->encoder_mask) > 1);
 292
 293         drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask)
 294                 return encoder;
 295
 296         return NULL;
 297 }
 298
 299 #define drm_for_each_connector_mask(connector, dev, connector_mask) \
 300         list_for_each_entry((connector), &(dev)->mode_config.connector_list, head) \
 301                 for_each_if ((connector_mask) & drm_connector_mask(connector))
 302
 303 struct drm_connector *vc4_get_crtc_connector(struct drm_crtc *crtc,
 304                                              struct drm_crtc_state *state)
 305 {
 306         struct drm_connector *connector;
 307
 308         WARN_ON(hweight32(state->connector_mask) > 1);
 309
 310         drm_for_each_connector_mask(connector, crtc->dev, state->connector_mask)
 311                 return connector;
 312
 313         return NULL;
 314 }
 315
 316 static void vc4_crtc_pixelvalve_reset(struct drm_crtc *crtc)
 317 {
 318         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 319
 320         /* The PV needs to be disabled before it can be flushed */
 321         CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);
 322         CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR);
 323 }
 324
 325 static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encoder,
 326                                struct drm_atomic_state *state)
 327 {
 328         struct drm_device *dev = crtc->dev;
 329         struct vc4_dev *vc4 = to_vc4_dev(dev);
 330         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 331         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 332         const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
 333         struct drm_crtc_state *crtc_state = crtc->state;
 334         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 335         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 336         bool is_hdmi = vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0 ||
 337                        vc4_encoder->type == VC4_ENCODER_TYPE_HDMI1;
 338         u32 pixel_rep = ((mode->flags & DRM_MODE_FLAG_DBLCLK) && !is_hdmi) ? 2 : 1;
 339         bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
 340                        vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
 341         bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1;
 342         bool is_vec = vc4_encoder->type == VC4_ENCODER_TYPE_VEC;
 343         u32 format = is_dsi1 ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
 344         u8 ppc = pv_data->pixels_per_clock;
 345
 346         u16 vert_bp = mode->crtc_vtotal - mode->crtc_vsync_end;
 347         u16 vert_sync = mode->crtc_vsync_end - mode->crtc_vsync_start;
 348         u16 vert_fp = mode->crtc_vsync_start - mode->crtc_vdisplay;
 349
 350         bool debug_dump_regs = false;
 351
 352         if (debug_dump_regs) {
 353                 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
 354                 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
 355                          drm_crtc_index(crtc));
 356                 drm_print_regset32(&p, &vc4_crtc->regset);
 357         }
 358
 359         vc4_crtc_pixelvalve_reset(crtc);
 360
 361         CRTC_WRITE(PV_HORZA,
 362                    VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
 363                                  PV_HORZA_HBP) |
 364                    VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc,
 365                                  PV_HORZA_HSYNC));
 366
 367         CRTC_WRITE(PV_HORZB,
 368                    VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc,
 369                                  PV_HORZB_HFP) |
 370                    VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,
 371                                  PV_HORZB_HACTIVE));
 372
 373         if (interlace) {
 374                 bool odd_field_first = false;
 375                 u32 field_delay = mode->htotal * pixel_rep / (2 * ppc);
 376                 u16 vert_bp_even = vert_bp;
 377                 u16 vert_fp_even = vert_fp;
 378
 379                 if (is_vec) {
 380                         /* VEC (composite output) */
 381                         ++field_delay;
 382                         if (mode->htotal == 858) {
 383                                 /* 525-line mode (NTSC or PAL-M) */
 384                                 odd_field_first = true;
 385                         }
 386                 }
 387
 388                 if (odd_field_first)
 389                         ++vert_fp_even;
 390                 else
 391                         ++vert_bp;
 392
 393                 CRTC_WRITE(PV_VERTA_EVEN,
 394                            VC4_SET_FIELD(vert_bp_even, PV_VERTA_VBP) |
 395                            VC4_SET_FIELD(vert_sync, PV_VERTA_VSYNC));
 396                 CRTC_WRITE(PV_VERTB_EVEN,
 397                            VC4_SET_FIELD(vert_fp_even, PV_VERTB_VFP) |
 398                            VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 399
 400                 /* We set up first field even mode for HDMI and VEC's PAL.
 401                  * For NTSC, we need first field odd.
 402                  */
 403                 CRTC_WRITE(PV_V_CONTROL,
 404                            PV_VCONTROL_CONTINUOUS |
 405                            (is_dsi ? PV_VCONTROL_DSI : 0) |
 406                            PV_VCONTROL_INTERLACE |
 407                            (odd_field_first
 408                                    ? PV_VCONTROL_ODD_FIRST
 409                                    : VC4_SET_FIELD(field_delay,
 410                                                    PV_VCONTROL_ODD_DELAY)));
 411                 CRTC_WRITE(PV_VSYNCD_EVEN,
 412                            (odd_field_first ? field_delay : 0));
 413         } else {
 414                 CRTC_WRITE(PV_V_CONTROL,
 415                            PV_VCONTROL_CONTINUOUS |
 416                            (is_dsi ? PV_VCONTROL_DSI : 0));
 417                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
 418         }
 419
 420         CRTC_WRITE(PV_VERTA,
 421                    VC4_SET_FIELD(vert_bp, PV_VERTA_VBP) |
 422                    VC4_SET_FIELD(vert_sync, PV_VERTA_VSYNC));
 423         CRTC_WRITE(PV_VERTB,
 424                    VC4_SET_FIELD(vert_fp, PV_VERTB_VFP) |
 425                    VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 426
 427         if (is_dsi)
 428                 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
 429
 430         if (vc4->is_vc5)
 431                 CRTC_WRITE(PV_MUX_CFG,
 432                            VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP,
 433                                          PV_MUX_CFG_RGB_PIXEL_MUX_MODE));
 434
 435         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR |
 436                    vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |
 437                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 438                    VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
 439                    PV_CONTROL_CLR_AT_START |
 440                    PV_CONTROL_TRIGGER_UNDERFLOW |
 441                    PV_CONTROL_WAIT_HSTART |
 442                    VC4_SET_FIELD(vc4_encoder->clock_select,
 443                                  PV_CONTROL_CLK_SELECT));
 444
 445         if (debug_dump_regs) {
 446                 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
 447                 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
 448                          drm_crtc_index(crtc));
 449                 drm_print_regset32(&p, &vc4_crtc->regset);
 450         }
 451 }
 452
 453 static void require_hvs_enabled(struct drm_device *dev)
 454 {
 455         struct vc4_dev *vc4 = to_vc4_dev(dev);
 456         struct vc4_hvs *hvs = vc4->hvs;
 457
 458         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 459                      SCALER_DISPCTRL_ENABLE);
 460 }
 461
 462 static int vc4_crtc_disable(struct drm_crtc *crtc,
 463                             struct drm_encoder *encoder,
 464                             struct drm_atomic_state *state,
 465                             unsigned int channel)
 466 {
 467         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 468         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 469         struct drm_device *dev = crtc->dev;
 470         struct vc4_dev *vc4 = to_vc4_dev(dev);
 471         int ret;
 472
 473         CRTC_WRITE(PV_V_CONTROL,
 474                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 475         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 476         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 477
 478         /*
 479          * This delay is needed to avoid to get a pixel stuck in an
 480          * unflushable FIFO between the pixelvalve and the HDMI
 481          * controllers on the BCM2711.
 482          *
 483          * Timing is fairly sensitive here, so mdelay is the safest
 484          * approach.
 485          *
 486          * If it was to be reworked, the stuck pixel happens on a
 487          * BCM2711 when changing mode with a good probability, so a
 488          * script that changes mode on a regular basis should trigger
 489          * the bug after less than 10 attempts. It manifests itself with
 490          * every pixels being shifted by one to the right, and thus the
 491          * last pixel of a line actually being displayed as the first
 492          * pixel on the next line.
 493          */
 494         mdelay(20);
 495
 496         if (vc4_encoder && vc4_encoder->post_crtc_disable)
 497                 vc4_encoder->post_crtc_disable(encoder, state);
 498
 499         vc4_crtc_pixelvalve_reset(crtc);
 500         vc4_hvs_stop_channel(vc4->hvs, channel);
 501
 502         if (vc4_encoder && vc4_encoder->post_crtc_powerdown)
 503                 vc4_encoder->post_crtc_powerdown(encoder, state);
 504
 505         return 0;
 506 }
 507
 508 static struct drm_encoder *vc4_crtc_get_encoder_by_type(struct drm_crtc *crtc,
 509                                                         enum vc4_encoder_type type)
 510 {
 511         struct drm_encoder *encoder;
 512
 513         drm_for_each_encoder(encoder, crtc->dev) {
 514                 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 515
 516                 if (vc4_encoder->type == type)
 517                         return encoder;
 518         }
 519
 520         return NULL;
 521 }
 522
 523 int vc4_crtc_disable_at_boot(struct drm_crtc *crtc)
 524 {
 525         struct drm_device *drm = crtc->dev;
 526         struct vc4_dev *vc4 = to_vc4_dev(drm);
 527         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 528         enum vc4_encoder_type encoder_type;
 529         const struct vc4_pv_data *pv_data;
 530         struct drm_encoder *encoder;
 531         struct vc4_hdmi *vc4_hdmi;
 532         unsigned encoder_sel;
 533         int channel;
 534         int ret;
 535
 536         if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
 537                                       "brcm,bcm2711-pixelvalve2") ||
 538               of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
 539                                       "brcm,bcm2711-pixelvalve4")))
 540                 return 0;
 541
 542         if (!(CRTC_READ(PV_CONTROL) & PV_CONTROL_EN))
 543                 return 0;
 544
 545         if (!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN))
 546                 return 0;
 547
 548         channel = vc4_hvs_get_fifo_from_output(vc4->hvs, vc4_crtc->data->hvs_output);
 549         if (channel < 0)
 550                 return 0;
 551
 552         encoder_sel = VC4_GET_FIELD(CRTC_READ(PV_CONTROL), PV_CONTROL_CLK_SELECT);
 553         if (WARN_ON(encoder_sel != 0))
 554                 return 0;
 555
 556         pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
 557         encoder_type = pv_data->encoder_types[encoder_sel];
 558         encoder = vc4_crtc_get_encoder_by_type(crtc, encoder_type);
 559         if (WARN_ON(!encoder))
 560                 return 0;
 561
 562         vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 563         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
 564         if (ret)
 565                 return ret;
 566
 567         ret = vc4_crtc_disable(crtc, encoder, NULL, channel);
 568         if (ret)
 569                 return ret;
 570
 571         /*
 572          * post_crtc_powerdown will have called pm_runtime_put, so we
 573          * don't need it here otherwise we'll get the reference counting
 574          * wrong.
 575          */
 576
 577         return 0;
 578 }
 579
 580 static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
 581                                     struct drm_atomic_state *state)
 582 {
 583         struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
 584                                                                          crtc);
 585         struct vc4_crtc_state *old_vc4_state = to_vc4_crtc_state(old_state);
 586         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, old_state);
 587         struct drm_device *dev = crtc->dev;
 588
 589         drm_dbg(dev, "Disabling CRTC %s (%u) connected to Encoder %s (%u)",
 590                 crtc->name, crtc->base.id, encoder->name, encoder->base.id);
 591
 592         require_hvs_enabled(dev);
 593
 594         /* Disable vblank irq handling before crtc is disabled. */
 595         drm_crtc_vblank_off(crtc);
 596
 597         vc4_crtc_disable(crtc, encoder, state, old_vc4_state->assigned_channel);
 598
 599         /*
 600          * Make sure we issue a vblank event after disabling the CRTC if
 601          * someone was waiting it.
 602          */
 603         if (crtc->state->event) {
 604                 unsigned long flags;
 605
 606                 spin_lock_irqsave(&dev->event_lock, flags);
 607                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 608                 crtc->state->event = NULL;
 609                 spin_unlock_irqrestore(&dev->event_lock, flags);
 610         }
 611 }
 612
 613 static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
 614                                    struct drm_atomic_state *state)
 615 {
 616         struct drm_crtc_state *new_state = drm_atomic_get_new_crtc_state(state,
 617                                                                          crtc);
 618         struct drm_device *dev = crtc->dev;
 619         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 620         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, new_state);
 621         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 622
 623         drm_dbg(dev, "Enabling CRTC %s (%u) connected to Encoder %s (%u)",
 624                 crtc->name, crtc->base.id, encoder->name, encoder->base.id);
 625
 626         require_hvs_enabled(dev);
 627
 628         /* Enable vblank irq handling before crtc is started otherwise
 629          * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
 630          */
 631         drm_crtc_vblank_on(crtc);
 632
 633         vc4_hvs_atomic_enable(crtc, state);
 634
 635         if (vc4_encoder->pre_crtc_configure)
 636                 vc4_encoder->pre_crtc_configure(encoder, state);
 637
 638         vc4_crtc_config_pv(crtc, encoder, state);
 639
 640         CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);
 641
 642         if (vc4_encoder->pre_crtc_enable)
 643                 vc4_encoder->pre_crtc_enable(encoder, state);
 644
 645         /* When feeding the transposer block the pixelvalve is unneeded and
 646          * should not be enabled.
 647          */
 648         CRTC_WRITE(PV_V_CONTROL,
 649                    CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 650
 651         if (vc4_encoder->post_crtc_enable)
 652                 vc4_encoder->post_crtc_enable(encoder, state);
 653 }
 654
 655 static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
 656                                                 const struct drm_display_mode *mode)
 657 {
 658         /* Do not allow doublescan modes from user space */
 659         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 660                 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
 661                               crtc->base.id);
 662                 return MODE_NO_DBLESCAN;
 663         }
 664
 665         return MODE_OK;
 666 }
 667
 668 void vc4_crtc_get_margins(struct drm_crtc_state *state,
 669                           unsigned int *left, unsigned int *right,
 670                           unsigned int *top, unsigned int *bottom)
 671 {
 672         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 673         struct drm_connector_state *conn_state;
 674         struct drm_connector *conn;
 675         int i;
 676
 677         *left = vc4_state->margins.left;
 678         *right = vc4_state->margins.right;
 679         *top = vc4_state->margins.top;
 680         *bottom = vc4_state->margins.bottom;
 681
 682         /* We have to interate over all new connector states because
 683          * vc4_crtc_get_margins() might be called before
 684          * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state
 685          * might be outdated.
 686          */
 687         for_each_new_connector_in_state(state->state, conn, conn_state, i) {
 688                 if (conn_state->crtc != state->crtc)
 689                         continue;
 690
 691                 *left = conn_state->tv.margins.left;
 692                 *right = conn_state->tv.margins.right;
 693                 *top = conn_state->tv.margins.top;
 694                 *bottom = conn_state->tv.margins.bottom;
 695                 break;
 696         }
 697 }
 698
 699 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 700                                  struct drm_atomic_state *state)
 701 {
 702         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 703                                                                           crtc);
 704         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 705         struct drm_connector *conn;
 706         struct drm_connector_state *conn_state;
 707         struct drm_encoder *encoder;
 708         int ret, i;
 709
 710         ret = vc4_hvs_atomic_check(crtc, state);
 711         if (ret)
 712                 return ret;
 713
 714         encoder = vc4_get_crtc_encoder(crtc, crtc_state);
 715         if (encoder) {
 716                 const struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 717                 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 718
 719                 mode = &crtc_state->adjusted_mode;
 720                 if (vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0) {
 721                         vc4_state->hvs_load = max(mode->clock * mode->hdisplay / mode->htotal + 1000,
 722                                                   mode->clock * 9 / 10) * 1000;
 723                 } else {
 724                         vc4_state->hvs_load = mode->clock * 1000;
 725                 }
 726         }
 727
 728         for_each_new_connector_in_state(state, conn, conn_state,
 729                                         i) {
 730                 if (conn_state->crtc != crtc)
 731                         continue;
 732
 733                 if (memcmp(&vc4_state->margins, &conn_state->tv.margins,
 734                            sizeof(vc4_state->margins))) {
 735                         memcpy(&vc4_state->margins, &conn_state->tv.margins,
 736                                sizeof(vc4_state->margins));
 737
 738                         /* Need to force the dlist entries for all planes to be
 739                          * updated so that the dest rectangles are changed.
 740                          */
 741                         crtc_state->zpos_changed = true;
 742                 }
 743                 break;
 744         }
 745
 746         return 0;
 747 }
 748
 749 static int vc4_enable_vblank(struct drm_crtc *crtc)
 750 {
 751         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 752
 753         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 754
 755         return 0;
 756 }
 757
 758 static void vc4_disable_vblank(struct drm_crtc *crtc)
 759 {
 760         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 761
 762         CRTC_WRITE(PV_INTEN, 0);
 763 }
 764
 765 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 766 {
 767         struct drm_crtc *crtc = &vc4_crtc->base;
 768         struct drm_device *dev = crtc->dev;
 769         struct vc4_dev *vc4 = to_vc4_dev(dev);
 770         struct vc4_hvs *hvs = vc4->hvs;
 771         u32 chan = vc4_crtc->current_hvs_channel;
 772         unsigned long flags;
 773
 774         spin_lock_irqsave(&dev->event_lock, flags);
 775         spin_lock(&vc4_crtc->irq_lock);
 776         if (vc4_crtc->event &&
 777             (vc4_crtc->current_dlist == HVS_READ(SCALER_DISPLACTX(chan)) ||
 778              vc4_crtc->feeds_txp)) {
 779                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 780                 vc4_crtc->event = NULL;
 781                 drm_crtc_vblank_put(crtc);
 782
 783                 /* Wait for the page flip to unmask the underrun to ensure that
 784                  * the display list was updated by the hardware. Before that
 785                  * happens, the HVS will be using the previous display list with
 786                  * the CRTC and encoder already reconfigured, leading to
 787                  * underruns. This can be seen when reconfiguring the CRTC.
 788                  */
 789                 vc4_hvs_unmask_underrun(hvs, chan);
 790         }
 791         spin_unlock(&vc4_crtc->irq_lock);
 792         spin_unlock_irqrestore(&dev->event_lock, flags);
 793 }
 794
 795 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
 796 {
 797         crtc->t_vblank = ktime_get();
 798         drm_crtc_handle_vblank(&crtc->base);
 799         vc4_crtc_handle_page_flip(crtc);
 800 }
 801
 802 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 803 {
 804         struct vc4_crtc *vc4_crtc = data;
 805         u32 stat = CRTC_READ(PV_INTSTAT);
 806         irqreturn_t ret = IRQ_NONE;
 807
 808         if (stat & PV_INT_VFP_START) {
 809                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 810                 vc4_crtc_handle_vblank(vc4_crtc);
 811                 ret = IRQ_HANDLED;
 812         }
 813
 814         return ret;
 815 }
 816
 817 struct vc4_async_flip_state {
 818         struct drm_crtc *crtc;
 819         struct drm_framebuffer *fb;
 820         struct drm_framebuffer *old_fb;
 821         struct drm_pending_vblank_event *event;
 822
 823         union {
 824                 struct dma_fence_cb fence;
 825                 struct vc4_seqno_cb seqno;
 826         } cb;
 827 };
 828
 829 /* Called when the V3D execution for the BO being flipped to is done, so that
 830  * we can actually update the plane's address to point to it.
 831  */
 832 static void
 833 vc4_async_page_flip_complete(struct vc4_async_flip_state *flip_state)
 834 {
 835         struct drm_crtc *crtc = flip_state->crtc;
 836         struct drm_device *dev = crtc->dev;
 837         struct drm_plane *plane = crtc->primary;
 838
 839         vc4_plane_async_set_fb(plane, flip_state->fb);
 840         if (flip_state->event) {
 841                 unsigned long flags;
 842
 843                 spin_lock_irqsave(&dev->event_lock, flags);
 844                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 845                 spin_unlock_irqrestore(&dev->event_lock, flags);
 846         }
 847
 848         drm_crtc_vblank_put(crtc);
 849         drm_framebuffer_put(flip_state->fb);
 850
 851         if (flip_state->old_fb)
 852                 drm_framebuffer_put(flip_state->old_fb);
 853
 854         kfree(flip_state);
 855 }
 856
 857 static void vc4_async_page_flip_seqno_complete(struct vc4_seqno_cb *cb)
 858 {
 859         struct vc4_async_flip_state *flip_state =
 860                 container_of(cb, struct vc4_async_flip_state, cb.seqno);
 861         struct vc4_bo *bo = NULL;
 862
 863         if (flip_state->old_fb) {
 864                 struct drm_gem_cma_object *cma_bo =
 865                         drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
 866                 bo = to_vc4_bo(&cma_bo->base);
 867         }
 868
 869         vc4_async_page_flip_complete(flip_state);
 870
 871         /*
 872          * Decrement the BO usecnt in order to keep the inc/dec
 873          * calls balanced when the planes are updated through
 874          * the async update path.
 875          *
 876          * FIXME: we should move to generic async-page-flip when
 877          * it's available, so that we can get rid of this
 878          * hand-made cleanup_fb() logic.
 879          */
 880         if (bo)
 881                 vc4_bo_dec_usecnt(bo);
 882 }
 883
 884 static void vc4_async_page_flip_fence_complete(struct dma_fence *fence,
 885                                                struct dma_fence_cb *cb)
 886 {
 887         struct vc4_async_flip_state *flip_state =
 888                 container_of(cb, struct vc4_async_flip_state, cb.fence);
 889
 890         vc4_async_page_flip_complete(flip_state);
 891         dma_fence_put(fence);
 892 }
 893
 894 static int vc4_async_set_fence_cb(struct drm_device *dev,
 895                                   struct vc4_async_flip_state *flip_state)
 896 {
 897         struct drm_framebuffer *fb = flip_state->fb;
 898         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 899         struct vc4_dev *vc4 = to_vc4_dev(dev);
 900         struct dma_fence *fence;
 901
 902         if (!vc4->is_vc5) {
 903                 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 904
 905                 return vc4_queue_seqno_cb(dev, &flip_state->cb.seqno, bo->seqno,
 906                                           vc4_async_page_flip_seqno_complete);
 907         }
 908
 909         fence = dma_fence_get(dma_resv_excl_fence(cma_bo->base.resv));
 910         if (dma_fence_add_callback(fence, &flip_state->cb.fence,
 911                                    vc4_async_page_flip_fence_complete))
 912                 vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence);
 913
 914         return 0;
 915 }
 916
 917 static int
 918 vc4_async_page_flip_common(struct drm_crtc *crtc,
 919                            struct drm_framebuffer *fb,
 920                            struct drm_pending_vblank_event *event,
 921                            uint32_t flags)
 922 {
 923         struct drm_device *dev = crtc->dev;
 924         struct drm_plane *plane = crtc->primary;
 925         struct vc4_async_flip_state *flip_state;
 926
 927         flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 928         if (!flip_state)
 929                 return -ENOMEM;
 930
 931         drm_framebuffer_get(fb);
 932         flip_state->fb = fb;
 933         flip_state->crtc = crtc;
 934         flip_state->event = event;
 935
 936         /* Save the current FB before it's replaced by the new one in
 937          * drm_atomic_set_fb_for_plane(). We'll need the old FB in
 938          * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
 939          * it consistent.
 940          * FIXME: we should move to generic async-page-flip when it's
 941          * available, so that we can get rid of this hand-made cleanup_fb()
 942          * logic.
 943          */
 944         flip_state->old_fb = plane->state->fb;
 945         if (flip_state->old_fb)
 946                 drm_framebuffer_get(flip_state->old_fb);
 947
 948         WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 949
 950         /* Immediately update the plane's legacy fb pointer, so that later
 951          * modeset prep sees the state that will be present when the semaphore
 952          * is released.
 953          */
 954         drm_atomic_set_fb_for_plane(plane->state, fb);
 955
 956         vc4_async_set_fence_cb(dev, flip_state);
 957
 958         /* Driver takes ownership of state on successful async commit. */
 959         return 0;
 960 }
 961
 962 /* Implements async (non-vblank-synced) page flips.
 963  *
 964  * The page flip ioctl needs to return immediately, so we grab the
 965  * modeset semaphore on the pipe, and queue the address update for
 966  * when V3D is done with the BO being flipped to.
 967  */
 968 static int vc4_async_page_flip(struct drm_crtc *crtc,
 969                                struct drm_framebuffer *fb,
 970                                struct drm_pending_vblank_event *event,
 971                                uint32_t flags)
 972 {
 973         struct drm_device *dev = crtc->dev;
 974         struct vc4_dev *vc4 = to_vc4_dev(dev);
 975         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 976         struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 977         int ret;
 978
 979         if (WARN_ON_ONCE(vc4->is_vc5))
 980                 return -ENODEV;
 981
 982         /*
 983          * Increment the BO usecnt here, so that we never end up with an
 984          * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
 985          * plane is later updated through the non-async path.
 986          *
 987          * FIXME: we should move to generic async-page-flip when
 988          * it's available, so that we can get rid of this
 989          * hand-made prepare_fb() logic.
 990          */
 991         ret = vc4_bo_inc_usecnt(bo);
 992         if (ret)
 993                 return ret;
 994
 995         ret = vc4_async_page_flip_common(crtc, fb, event, flags);
 996         if (ret) {
 997                 vc4_bo_dec_usecnt(bo);
 998                 return ret;
 999         }
1000
1001         return 0;
1002 }
1003
1004 static int vc5_async_page_flip(struct drm_crtc *crtc,
1005                                struct drm_framebuffer *fb,
1006                                struct drm_pending_vblank_event *event,
1007                                uint32_t flags)
1008 {
1009         return vc4_async_page_flip_common(crtc, fb, event, flags);
1010 }
1011
1012 int vc4_page_flip(struct drm_crtc *crtc,
1013                   struct drm_framebuffer *fb,
1014                   struct drm_pending_vblank_event *event,
1015                   uint32_t flags,
1016                   struct drm_modeset_acquire_ctx *ctx)
1017 {
1018         if (flags & DRM_MODE_PAGE_FLIP_ASYNC) {
1019                 struct drm_device *dev = crtc->dev;
1020                 struct vc4_dev *vc4 = to_vc4_dev(dev);
1021
1022                 if (vc4->is_vc5)
1023                         return vc5_async_page_flip(crtc, fb, event, flags);
1024                 else
1025                         return vc4_async_page_flip(crtc, fb, event, flags);
1026         } else {
1027                 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
1028         }
1029 }
1030
1031 struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
1032 {
1033         struct vc4_crtc_state *vc4_state, *old_vc4_state;
1034
1035         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
1036         if (!vc4_state)
1037                 return NULL;
1038
1039         old_vc4_state = to_vc4_crtc_state(crtc->state);
1040         vc4_state->margins = old_vc4_state->margins;
1041         vc4_state->assigned_channel = old_vc4_state->assigned_channel;
1042
1043         __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
1044         return &vc4_state->base;
1045 }
1046
1047 void vc4_crtc_destroy_state(struct drm_crtc *crtc,
1048                             struct drm_crtc_state *state)
1049 {
1050         struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
1051         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
1052
1053         if (drm_mm_node_allocated(&vc4_state->mm)) {
1054                 unsigned long flags;
1055
1056                 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
1057                 drm_mm_remove_node(&vc4_state->mm);
1058                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
1059
1060         }
1061
1062         drm_atomic_helper_crtc_destroy_state(crtc, state);
1063 }
1064
1065 void vc4_crtc_reset(struct drm_crtc *crtc)
1066 {
1067         struct vc4_crtc_state *vc4_crtc_state;
1068
1069         if (crtc->state)
1070                 vc4_crtc_destroy_state(crtc, crtc->state);
1071
1072         vc4_crtc_state = kzalloc(sizeof(*vc4_crtc_state), GFP_KERNEL);
1073         if (!vc4_crtc_state) {
1074                 crtc->state = NULL;
1075                 return;
1076         }
1077
1078         vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
1079         __drm_atomic_helper_crtc_reset(crtc, &vc4_crtc_state->base);
1080 }
1081
1082 static const struct drm_crtc_funcs vc4_crtc_funcs = {
1083         .set_config = drm_atomic_helper_set_config,
1084         .destroy = vc4_crtc_destroy,
1085         .page_flip = vc4_page_flip,
1086         .set_property = NULL,
1087         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
1088         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
1089         .reset = vc4_crtc_reset,
1090         .atomic_duplicate_state = vc4_crtc_duplicate_state,
1091         .atomic_destroy_state = vc4_crtc_destroy_state,
1092         .enable_vblank = vc4_enable_vblank,
1093         .disable_vblank = vc4_disable_vblank,
1094         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1095 };
1096
1097 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
1098         .mode_valid = vc4_crtc_mode_valid,
1099         .atomic_check = vc4_crtc_atomic_check,
1100         .atomic_begin = vc4_hvs_atomic_begin,
1101         .atomic_flush = vc4_hvs_atomic_flush,
1102         .atomic_enable = vc4_crtc_atomic_enable,
1103         .atomic_disable = vc4_crtc_atomic_disable,
1104         .get_scanout_position = vc4_crtc_get_scanout_position,
1105 };
1106
1107 static const struct vc4_pv_data bcm2835_pv0_data = {
1108         .base = {
1109                 .hvs_available_channels = BIT(0),
1110                 .hvs_output = 0,
1111         },
1112         .debugfs_name = "crtc0_regs",
1113         .fifo_depth = 64,
1114         .pixels_per_clock = 1,
1115         .encoder_types = {
1116                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
1117                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
1118         },
1119 };
1120
1121 static const struct vc4_pv_data bcm2835_pv1_data = {
1122         .base = {
1123                 .hvs_available_channels = BIT(2),
1124                 .hvs_output = 2,
1125         },
1126         .debugfs_name = "crtc1_regs",
1127         .fifo_depth = 64,
1128         .pixels_per_clock = 1,
1129         .encoder_types = {
1130                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
1131                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
1132         },
1133 };
1134
1135 static const struct vc4_pv_data bcm2835_pv2_data = {
1136         .base = {
1137                 .hvs_available_channels = BIT(1),
1138                 .hvs_output = 1,
1139         },
1140         .debugfs_name = "crtc2_regs",
1141         .fifo_depth = 64,
1142         .pixels_per_clock = 1,
1143         .encoder_types = {
1144                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI0,
1145                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1146         },
1147 };
1148
1149 static const struct vc4_pv_data bcm2711_pv0_data = {
1150         .base = {
1151                 .hvs_available_channels = BIT(0),
1152                 .hvs_output = 0,
1153         },
1154         .debugfs_name = "crtc0_regs",
1155         .fifo_depth = 64,
1156         .pixels_per_clock = 1,
1157         .encoder_types = {
1158                 [0] = VC4_ENCODER_TYPE_DSI0,
1159                 [1] = VC4_ENCODER_TYPE_DPI,
1160         },
1161 };
1162
1163 static const struct vc4_pv_data bcm2711_pv1_data = {
1164         .base = {
1165                 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1166                 .hvs_output = 3,
1167         },
1168         .debugfs_name = "crtc1_regs",
1169         .fifo_depth = 64,
1170         .pixels_per_clock = 1,
1171         .encoder_types = {
1172                 [0] = VC4_ENCODER_TYPE_DSI1,
1173                 [1] = VC4_ENCODER_TYPE_SMI,
1174         },
1175 };
1176
1177 static const struct vc4_pv_data bcm2711_pv2_data = {
1178         .base = {
1179                 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1180                 .hvs_output = 4,
1181         },
1182         .debugfs_name = "crtc2_regs",
1183         .fifo_depth = 256,
1184         .pixels_per_clock = 2,
1185         .encoder_types = {
1186                 [0] = VC4_ENCODER_TYPE_HDMI0,
1187         },
1188 };
1189
1190 static const struct vc4_pv_data bcm2711_pv3_data = {
1191         .base = {
1192                 .hvs_available_channels = BIT(1),
1193                 .hvs_output = 1,
1194         },
1195         .debugfs_name = "crtc3_regs",
1196         .fifo_depth = 64,
1197         .pixels_per_clock = 1,
1198         .encoder_types = {
1199                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1200         },
1201 };
1202
1203 static const struct vc4_pv_data bcm2711_pv4_data = {
1204         .base = {
1205                 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1206                 .hvs_output = 5,
1207         },
1208         .debugfs_name = "crtc4_regs",
1209         .fifo_depth = 64,
1210         .pixels_per_clock = 2,
1211         .encoder_types = {
1212                 [0] = VC4_ENCODER_TYPE_HDMI1,
1213         },
1214 };
1215
1216 static const struct of_device_id vc4_crtc_dt_match[] = {
1217         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
1218         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
1219         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },
1220         { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data },
1221         { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data },
1222         { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
1223         { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
1224         { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
1225         {}
1226 };
1227
1228 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1229                                         struct drm_crtc *crtc)
1230 {
1231         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1232         const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
1233         const enum vc4_encoder_type *encoder_types = pv_data->encoder_types;
1234         struct drm_encoder *encoder;
1235
1236         drm_for_each_encoder(encoder, drm) {
1237                 struct vc4_encoder *vc4_encoder;
1238                 int i;
1239
1240                 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
1241                         continue;
1242
1243                 vc4_encoder = to_vc4_encoder(encoder);
1244                 for (i = 0; i < ARRAY_SIZE(pv_data->encoder_types); i++) {
1245                         if (vc4_encoder->type == encoder_types[i]) {
1246                                 vc4_encoder->clock_select = i;
1247                                 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1248                                 break;
1249                         }
1250                 }
1251         }
1252 }
1253
1254 int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
1255                   const struct drm_crtc_funcs *crtc_funcs,
1256                   const struct drm_crtc_helper_funcs *crtc_helper_funcs)
1257 {
1258         struct vc4_dev *vc4 = to_vc4_dev(drm);
1259         struct drm_crtc *crtc = &vc4_crtc->base;
1260         struct drm_plane *primary_plane;
1261         unsigned int i;
1262
1263         /* For now, we create just the primary and the legacy cursor
1264          * planes.  We should be able to stack more planes on easily,
1265          * but to do that we would need to compute the bandwidth
1266          * requirement of the plane configuration, and reject ones
1267          * that will take too much.
1268          */
1269         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
1270         if (IS_ERR(primary_plane)) {
1271                 dev_err(drm->dev, "failed to construct primary plane\n");
1272                 return PTR_ERR(primary_plane);
1273         }
1274
1275         spin_lock_init(&vc4_crtc->irq_lock);
1276         drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1277                                   crtc_funcs, NULL);
1278         drm_crtc_helper_add(crtc, crtc_helper_funcs);
1279
1280         if (!vc4->is_vc5) {
1281                 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1282                 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
1283         }
1284
1285
1286         if (!vc4->is_vc5) {
1287                 /* We support CTM, but only for one CRTC at a time. It's therefore
1288                  * implemented as private driver state in vc4_kms, not here.
1289                  */
1290                 drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
1291
1292                 /* Initialize the VC4 gamma LUTs */
1293                 for (i = 0; i < crtc->gamma_size; i++) {
1294                         vc4_crtc->lut_r[i] = i;
1295                         vc4_crtc->lut_g[i] = i;
1296                         vc4_crtc->lut_b[i] = i;
1297                 }
1298         } else {
1299                 /* Initialize the VC5 gamma PWL entries. Assume 12-bit pipeline,
1300                  * evenly spread over full range.
1301                  */
1302                 for (i = 0; i < SCALER5_DSPGAMMA_NUM_POINTS; i++) {
1303                         vc4_crtc->pwl_r[i] =
1304                                 VC5_HVS_SET_GAMMA_ENTRY(i << 8, i << 12, 1 << 8);
1305                         vc4_crtc->pwl_g[i] =
1306                                 VC5_HVS_SET_GAMMA_ENTRY(i << 8, i << 12, 1 << 8);
1307                         vc4_crtc->pwl_b[i] =
1308                                 VC5_HVS_SET_GAMMA_ENTRY(i << 8, i << 12, 1 << 8);
1309                         vc4_crtc->pwl_a[i] =
1310                                 VC5_HVS_SET_GAMMA_ENTRY(i << 8, i << 12, 1 << 8);
1311                 }
1312         }
1313
1314         return 0;
1315 }
1316
1317 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1318 {
1319         struct platform_device *pdev = to_platform_device(dev);
1320         struct drm_device *drm = dev_get_drvdata(master);
1321         const struct vc4_pv_data *pv_data;
1322         struct vc4_crtc *vc4_crtc;
1323         struct drm_crtc *crtc;
1324         struct drm_plane *destroy_plane, *temp;
1325         int ret;
1326
1327         vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
1328         if (!vc4_crtc)
1329                 return -ENOMEM;
1330         crtc = &vc4_crtc->base;
1331
1332         pv_data = of_device_get_match_data(dev);
1333         if (!pv_data)
1334                 return -ENODEV;
1335         vc4_crtc->data = &pv_data->base;
1336         vc4_crtc->pdev = pdev;
1337
1338         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1339         if (IS_ERR(vc4_crtc->regs))
1340                 return PTR_ERR(vc4_crtc->regs);
1341
1342         vc4_crtc->regset.base = vc4_crtc->regs;
1343         vc4_crtc->regset.regs = crtc_regs;
1344         vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);
1345
1346         ret = vc4_crtc_init(drm, vc4_crtc,
1347                             &vc4_crtc_funcs, &vc4_crtc_helper_funcs);
1348         if (ret)
1349                 return ret;
1350         vc4_set_crtc_possible_masks(drm, crtc);
1351
1352         CRTC_WRITE(PV_INTEN, 0);
1353         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1354         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1355                                vc4_crtc_irq_handler,
1356                                IRQF_SHARED,
1357                                "vc4 crtc", vc4_crtc);
1358         if (ret)
1359                 goto err_destroy_planes;
1360
1361         platform_set_drvdata(pdev, vc4_crtc);
1362
1363         vc4_debugfs_add_regset32(drm, pv_data->debugfs_name,
1364                                  &vc4_crtc->regset);
1365
1366         return 0;
1367
1368 err_destroy_planes:
1369         list_for_each_entry_safe(destroy_plane, temp,
1370                                  &drm->mode_config.plane_list, head) {
1371                 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc))
1372                     destroy_plane->funcs->destroy(destroy_plane);
1373         }
1374
1375         return ret;
1376 }
1377
1378 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1379                             void *data)
1380 {
1381         struct platform_device *pdev = to_platform_device(dev);
1382         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1383
1384         vc4_crtc_destroy(&vc4_crtc->base);
1385
1386         CRTC_WRITE(PV_INTEN, 0);
1387
1388         platform_set_drvdata(pdev, NULL);
1389 }
1390
1391 static const struct component_ops vc4_crtc_ops = {
1392         .bind   = vc4_crtc_bind,
1393         .unbind = vc4_crtc_unbind,
1394 };
1395
1396 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1397 {
1398         return component_add(&pdev->dev, &vc4_crtc_ops);
1399 }
1400
1401 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1402 {
1403         component_del(&pdev->dev, &vc4_crtc_ops);
1404         return 0;
1405 }
1406
1407 struct platform_driver vc4_crtc_driver = {
1408         .probe = vc4_crtc_dev_probe,
1409         .remove = vc4_crtc_dev_remove,
1410         .driver = {
1411                 .name = "vc4_crtc",
1412                 .of_match_table = vc4_crtc_dt_match,
1413         },
1414 };