drivers/gpu/drm/vc4/vc4_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 CRTC module
   8  *
   9  * In VC4, the Pixel Valve is what most closely corresponds to the
  10  * DRM's concept of a CRTC.  The PV generates video timings from the
  11  * encoder's clock plus its configuration.  It pulls scaled pixels from
  12  * the HVS at that timing, and feeds it to the encoder.
  13  *
  14  * However, the DRM CRTC also collects the configuration of all the
  15  * DRM planes attached to it.  As a result, the CRTC is also
  16  * responsible for writing the display list for the HVS channel that
  17  * the CRTC will use.
  18  *
  19  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  20  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  21  * image domain can feed either HDMI or the SDTV controller.  The
  22  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  23  * SDTV, etc.) according to which output type is chosen in the mux.
  24  *
  25  * For power management, the pixel valve's registers are all clocked
  26  * by the AXI clock, while the timings and FIFOs make use of the
  27  * output-specific clock.  Since the encoders also directly consume
  28  * the CPRMAN clocks, and know what timings they need, they are the
  29  * ones that set the clock.
  30  */
  31
  32 #include <linux/clk.h>
  33 #include <linux/component.h>
  34 #include <linux/of_device.h>
  35
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_atomic_uapi.h>
  39 #include <drm/drm_fb_cma_helper.h>
  40 #include <drm/drm_print.h>
  41 #include <drm/drm_probe_helper.h>
  42 #include <drm/drm_vblank.h>
  43
  44 #include "vc4_drv.h"
  45 #include "vc4_regs.h"
  46
  47 #define HVS_FIFO_LATENCY_PIX    6
  48
  49 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  50 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
  51
  52 static const struct debugfs_reg32 crtc_regs[] = {
  53         VC4_REG32(PV_CONTROL),
  54         VC4_REG32(PV_V_CONTROL),
  55         VC4_REG32(PV_VSYNCD_EVEN),
  56         VC4_REG32(PV_HORZA),
  57         VC4_REG32(PV_HORZB),
  58         VC4_REG32(PV_VERTA),
  59         VC4_REG32(PV_VERTB),
  60         VC4_REG32(PV_VERTA_EVEN),
  61         VC4_REG32(PV_VERTB_EVEN),
  62         VC4_REG32(PV_INTEN),
  63         VC4_REG32(PV_INTSTAT),
  64         VC4_REG32(PV_STAT),
  65         VC4_REG32(PV_HACT_ACT),
  66 };
  67
  68 static unsigned int
  69 vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc, unsigned int channel)
  70 {
  71         struct drm_device *drm = vc4_crtc->base.dev;
  72         struct vc4_dev *vc4 = to_vc4_dev(drm);
  73
  74         u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel));
  75         /* Top/base are supposed to be 4-pixel aligned, but the
  76          * Raspberry Pi firmware fills the low bits (which are
  77          * presumably ignored).
  78          */
  79         u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
  80         u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
  81
  82         return top - base + 4;
  83 }
  84
  85 bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
  86                              bool in_vblank_irq, int *vpos, int *hpos,
  87                              ktime_t *stime, ktime_t *etime,
  88                              const struct drm_display_mode *mode)
  89 {
  90         struct vc4_dev *vc4 = to_vc4_dev(dev);
  91         struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
  92         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  93         struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
  94         unsigned int cob_size;
  95         u32 val;
  96         int fifo_lines;
  97         int vblank_lines;
  98         bool ret = false;
  99
 100         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 101
 102         /* Get optional system timestamp before query. */
 103         if (stime)
 104                 *stime = ktime_get();
 105
 106         /*
 107          * Read vertical scanline which is currently composed for our
 108          * pixelvalve by the HVS, and also the scaler status.
 109          */
 110         val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel));
 111
 112         /* Get optional system timestamp after query. */
 113         if (etime)
 114                 *etime = ktime_get();
 115
 116         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 117
 118         /* Vertical position of hvs composed scanline. */
 119         *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
 120         *hpos = 0;
 121
 122         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 123                 *vpos /= 2;
 124
 125                 /* Use hpos to correct for field offset in interlaced mode. */
 126                 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
 127                         *hpos += mode->crtc_htotal / 2;
 128         }
 129
 130         cob_size = vc4_crtc_get_cob_allocation(vc4_crtc, vc4_crtc_state->assigned_channel);
 131         /* This is the offset we need for translating hvs -> pv scanout pos. */
 132         fifo_lines = cob_size / mode->crtc_hdisplay;
 133
 134         if (fifo_lines > 0)
 135                 ret = true;
 136
 137         /* HVS more than fifo_lines into frame for compositing? */
 138         if (*vpos > fifo_lines) {
 139                 /*
 140                  * We are in active scanout and can get some meaningful results
 141                  * from HVS. The actual PV scanout can not trail behind more
 142                  * than fifo_lines as that is the fifo's capacity. Assume that
 143                  * in active scanout the HVS and PV work in lockstep wrt. HVS
 144                  * refilling the fifo and PV consuming from the fifo, ie.
 145                  * whenever the PV consumes and frees up a scanline in the
 146                  * fifo, the HVS will immediately refill it, therefore
 147                  * incrementing vpos. Therefore we choose HVS read position -
 148                  * fifo size in scanlines as a estimate of the real scanout
 149                  * position of the PV.
 150                  */
 151                 *vpos -= fifo_lines + 1;
 152
 153                 return ret;
 154         }
 155
 156         /*
 157          * Less: This happens when we are in vblank and the HVS, after getting
 158          * the VSTART restart signal from the PV, just started refilling its
 159          * fifo with new lines from the top-most lines of the new framebuffers.
 160          * The PV does not scan out in vblank, so does not remove lines from
 161          * the fifo, so the fifo will be full quickly and the HVS has to pause.
 162          * We can't get meaningful readings wrt. scanline position of the PV
 163          * and need to make things up in a approximative but consistent way.
 164          */
 165         vblank_lines = mode->vtotal - mode->vdisplay;
 166
 167         if (in_vblank_irq) {
 168                 /*
 169                  * Assume the irq handler got called close to first
 170                  * line of vblank, so PV has about a full vblank
 171                  * scanlines to go, and as a base timestamp use the
 172                  * one taken at entry into vblank irq handler, so it
 173                  * is not affected by random delays due to lock
 174                  * contention on event_lock or vblank_time lock in
 175                  * the core.
 176                  */
 177                 *vpos = -vblank_lines;
 178
 179                 if (stime)
 180                         *stime = vc4_crtc->t_vblank;
 181                 if (etime)
 182                         *etime = vc4_crtc->t_vblank;
 183
 184                 /*
 185                  * If the HVS fifo is not yet full then we know for certain
 186                  * we are at the very beginning of vblank, as the hvs just
 187                  * started refilling, and the stime and etime timestamps
 188                  * truly correspond to start of vblank.
 189                  *
 190                  * Unfortunately there's no way to report this to upper levels
 191                  * and make it more useful.
 192                  */
 193         } else {
 194                 /*
 195                  * No clue where we are inside vblank. Return a vpos of zero,
 196                  * which will cause calling code to just return the etime
 197                  * timestamp uncorrected. At least this is no worse than the
 198                  * standard fallback.
 199                  */
 200                 *vpos = 0;
 201         }
 202
 203         return ret;
 204 }
 205
 206 static void vc4_crtc_destroy(struct drm_crtc *crtc)
 207 {
 208         drm_crtc_cleanup(crtc);
 209 }
 210
 211 static void
 212 vc4_crtc_lut_load(struct drm_crtc *crtc)
 213 {
 214         struct drm_device *dev = crtc->dev;
 215         struct vc4_dev *vc4 = to_vc4_dev(dev);
 216         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 217         struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
 218         u32 i;
 219
 220         /* The LUT memory is laid out with each HVS channel in order,
 221          * each of which takes 256 writes for R, 256 for G, then 256
 222          * for B.
 223          */
 224         HVS_WRITE(SCALER_GAMADDR,
 225                   SCALER_GAMADDR_AUTOINC |
 226                   (vc4_crtc_state->assigned_channel * 3 * crtc->gamma_size));
 227
 228         for (i = 0; i < crtc->gamma_size; i++)
 229                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
 230         for (i = 0; i < crtc->gamma_size; i++)
 231                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
 232         for (i = 0; i < crtc->gamma_size; i++)
 233                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
 234 }
 235
 236 static void
 237 vc4_crtc_update_gamma_lut(struct drm_crtc *crtc)
 238 {
 239         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 240         struct drm_color_lut *lut = crtc->state->gamma_lut->data;
 241         u32 length = drm_color_lut_size(crtc->state->gamma_lut);
 242         u32 i;
 243
 244         for (i = 0; i < length; i++) {
 245                 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8);
 246                 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8);
 247                 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);
 248         }
 249
 250         vc4_crtc_lut_load(crtc);
 251 }
 252
 253 static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
 254 {
 255         u32 fifo_len_bytes = vc4_crtc->data->fifo_depth;
 256
 257         /*
 258          * Pixels are pulled from the HVS if the number of bytes is
 259          * lower than the FIFO full level.
 260          *
 261          * The latency of the pixel fetch mechanism is 6 pixels, so we
 262          * need to convert those 6 pixels in bytes, depending on the
 263          * format, and then substract that from the length of the FIFO
 264          * to make sure we never end up in a situation where the FIFO
 265          * is full.
 266          */
 267         switch (format) {
 268         case PV_CONTROL_FORMAT_DSIV_16:
 269         case PV_CONTROL_FORMAT_DSIC_16:
 270                 return fifo_len_bytes - 2 * HVS_FIFO_LATENCY_PIX;
 271         case PV_CONTROL_FORMAT_DSIV_18:
 272                 return fifo_len_bytes - 14;
 273         case PV_CONTROL_FORMAT_24:
 274         case PV_CONTROL_FORMAT_DSIV_24:
 275         default:
 276                 /*
 277                  * For some reason, the pixelvalve4 doesn't work with
 278                  * the usual formula and will only work with 32.
 279                  */
 280                 if (vc4_crtc->data->hvs_output == 5)
 281                         return 32;
 282
 283                 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
 284         }
 285 }
 286
 287 static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc,
 288                                              u32 format)
 289 {
 290         u32 level = vc4_get_fifo_full_level(vc4_crtc, format);
 291         u32 ret = 0;
 292
 293         if (level > 0x3f)
 294                 ret |= VC4_SET_FIELD((level >> 6) & 0x3,
 295                                      PV5_CONTROL_FIFO_LEVEL_HIGH);
 296
 297         return ret | VC4_SET_FIELD(level & 0x3f,
 298                                    PV_CONTROL_FIFO_LEVEL);
 299 }
 300
 301 /*
 302  * Returns the encoder attached to the CRTC.
 303  *
 304  * VC4 can only scan out to one encoder at a time, while the DRM core
 305  * allows drivers to push pixels to more than one encoder from the
 306  * same CRTC.
 307  */
 308 static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
 309 {
 310         struct drm_connector *connector;
 311         struct drm_connector_list_iter conn_iter;
 312
 313         drm_connector_list_iter_begin(crtc->dev, &conn_iter);
 314         drm_for_each_connector_iter(connector, &conn_iter) {
 315                 if (connector->state->crtc == crtc) {
 316                         drm_connector_list_iter_end(&conn_iter);
 317                         return connector->encoder;
 318                 }
 319         }
 320         drm_connector_list_iter_end(&conn_iter);
 321
 322         return NULL;
 323 }
 324
 325 static void vc4_crtc_config_pv(struct drm_crtc *crtc)
 326 {
 327         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
 328         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 329         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 330         struct drm_crtc_state *state = crtc->state;
 331         struct drm_display_mode *mode = &state->adjusted_mode;
 332         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 333         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 334         bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
 335                        vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
 336         u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
 337         u8 ppc = vc4_crtc->data->pixels_per_clock;
 338
 339         /* Reset the PV fifo. */
 340         CRTC_WRITE(PV_CONTROL, 0);
 341         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
 342         CRTC_WRITE(PV_CONTROL, 0);
 343
 344         CRTC_WRITE(PV_MUX_CFG,
 345                    VC4_SET_FIELD(8, PV_MUX_CFG_RGB_PIXEL_MUX_MODE));
 346
 347         CRTC_WRITE(PV_HORZA,
 348                    VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
 349                                  PV_HORZA_HBP) |
 350                    VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc,
 351                                  PV_HORZA_HSYNC));
 352
 353         CRTC_WRITE(PV_HORZB,
 354                    VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc,
 355                                  PV_HORZB_HFP) |
 356                    VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,
 357                                  PV_HORZB_HACTIVE));
 358
 359         CRTC_WRITE(PV_VERTA,
 360                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 361                                  PV_VERTA_VBP) |
 362                    VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 363                                  PV_VERTA_VSYNC));
 364         CRTC_WRITE(PV_VERTB,
 365                    VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 366                                  PV_VERTB_VFP) |
 367                    VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 368
 369         if (interlace) {
 370                 CRTC_WRITE(PV_VERTA_EVEN,
 371                            VC4_SET_FIELD(mode->crtc_vtotal -
 372                                          mode->crtc_vsync_end - 1,
 373                                          PV_VERTA_VBP) |
 374                            VC4_SET_FIELD(mode->crtc_vsync_end -
 375                                          mode->crtc_vsync_start,
 376                                          PV_VERTA_VSYNC));
 377                 CRTC_WRITE(PV_VERTB_EVEN,
 378                            VC4_SET_FIELD(mode->crtc_vsync_start -
 379                                          mode->crtc_vdisplay,
 380                                          PV_VERTB_VFP) |
 381                            VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 382
 383                 /* We set up first field even mode for HDMI.  VEC's
 384                  * NTSC mode would want first field odd instead, once
 385                  * we support it (to do so, set ODD_FIRST and put the
 386                  * delay in VSYNCD_EVEN instead).
 387                  */
 388                 CRTC_WRITE(PV_V_CONTROL,
 389                            PV_VCONTROL_CONTINUOUS |
 390                            (is_dsi ? PV_VCONTROL_DSI : 0) |
 391                            PV_VCONTROL_INTERLACE |
 392                            VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
 393                                          PV_VCONTROL_ODD_DELAY));
 394                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
 395         } else {
 396                 CRTC_WRITE(PV_V_CONTROL,
 397                            PV_VCONTROL_CONTINUOUS |
 398                            (is_dsi ? PV_VCONTROL_DSI : 0));
 399         }
 400
 401         CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
 402
 403         CRTC_WRITE(PV_CONTROL,
 404                    vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |
 405                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 406                    VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
 407                    PV_CONTROL_CLR_AT_START |
 408                    PV_CONTROL_TRIGGER_UNDERFLOW |
 409                    PV_CONTROL_WAIT_HSTART |
 410                    VC4_SET_FIELD(vc4_encoder->clock_select,
 411                                  PV_CONTROL_CLK_SELECT));
 412 }
 413
 414 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
 415 {
 416         struct drm_device *dev = crtc->dev;
 417         struct vc4_dev *vc4 = to_vc4_dev(dev);
 418         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 419         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 420         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 421         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 422         bool debug_dump_regs = false;
 423
 424         if (debug_dump_regs) {
 425                 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
 426                 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
 427                          drm_crtc_index(crtc));
 428                 drm_print_regset32(&p, &vc4_crtc->regset);
 429         }
 430
 431         if (vc4_crtc->data->hvs_output == 2) {
 432                 u32 dispctrl;
 433                 u32 dsp3_mux;
 434
 435                 /*
 436                  * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
 437                  * FIFO X'.
 438                  * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
 439                  *
 440                  * DSP3 is connected to FIFO2 unless the transposer is
 441                  * enabled. In this case, FIFO 2 is directly accessed by the
 442                  * TXP IP, and we need to disable the FIFO2 -> pixelvalve1
 443                  * route.
 444                  */
 445                 if (vc4_state->feed_txp)
 446                         dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
 447                 else
 448                         dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
 449
 450                 dispctrl = HVS_READ(SCALER_DISPCTRL) &
 451                            ~SCALER_DISPCTRL_DSP3_MUX_MASK;
 452                 HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
 453         }
 454
 455         if (!vc4_state->feed_txp)
 456                 vc4_crtc_config_pv(crtc);
 457
 458         HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel),
 459                   SCALER_DISPBKGND_AUTOHS |
 460                   ((!vc4->hvs->hvs5) ? SCALER_DISPBKGND_GAMMA : 0) |
 461                   (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
 462
 463         /* Reload the LUT, since the SRAMs would have been disabled if
 464          * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
 465          */
 466         vc4_crtc_lut_load(crtc);
 467
 468         if (debug_dump_regs) {
 469                 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
 470                 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
 471                          drm_crtc_index(crtc));
 472                 drm_print_regset32(&p, &vc4_crtc->regset);
 473         }
 474 }
 475
 476 static void require_hvs_enabled(struct drm_device *dev)
 477 {
 478         struct vc4_dev *vc4 = to_vc4_dev(dev);
 479
 480         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 481                      SCALER_DISPCTRL_ENABLE);
 482 }
 483
 484 static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
 485                                     struct drm_crtc_state *old_state)
 486 {
 487         struct drm_device *dev = crtc->dev;
 488         struct vc4_dev *vc4 = to_vc4_dev(dev);
 489         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 490         struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(old_state);
 491         u32 chan = vc4_crtc_state->assigned_channel;
 492         int ret;
 493         require_hvs_enabled(dev);
 494
 495         /* Disable vblank irq handling before crtc is disabled. */
 496         drm_crtc_vblank_off(crtc);
 497
 498         CRTC_WRITE(PV_V_CONTROL,
 499                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 500         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 501         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 502
 503         CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);
 504
 505         if (HVS_READ(SCALER_DISPCTRLX(chan)) &
 506             SCALER_DISPCTRLX_ENABLE) {
 507                 HVS_WRITE(SCALER_DISPCTRLX(chan),
 508                           SCALER_DISPCTRLX_RESET);
 509
 510                 /* While the docs say that reset is self-clearing, it
 511                  * seems it doesn't actually.
 512                  */
 513                 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
 514         }
 515
 516         /* Once we leave, the scaler should be disabled and its fifo empty. */
 517
 518         WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
 519
 520         WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
 521                                    SCALER_DISPSTATX_MODE) !=
 522                      SCALER_DISPSTATX_MODE_DISABLED);
 523
 524         WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
 525                       (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
 526                      SCALER_DISPSTATX_EMPTY);
 527
 528         /*
 529          * Make sure we issue a vblank event after disabling the CRTC if
 530          * someone was waiting it.
 531          */
 532         if (crtc->state->event) {
 533                 unsigned long flags;
 534
 535                 spin_lock_irqsave(&dev->event_lock, flags);
 536                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 537                 crtc->state->event = NULL;
 538                 spin_unlock_irqrestore(&dev->event_lock, flags);
 539         }
 540 }
 541
 542 void vc4_crtc_txp_armed(struct drm_crtc_state *state)
 543 {
 544         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 545
 546         vc4_state->txp_armed = true;
 547 }
 548
 549 static void vc4_crtc_update_dlist(struct drm_crtc *crtc)
 550 {
 551         struct drm_device *dev = crtc->dev;
 552         struct vc4_dev *vc4 = to_vc4_dev(dev);
 553         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 554         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 555
 556         if (crtc->state->event) {
 557                 unsigned long flags;
 558
 559                 crtc->state->event->pipe = drm_crtc_index(crtc);
 560
 561                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 562
 563                 spin_lock_irqsave(&dev->event_lock, flags);
 564
 565                 if (!vc4_state->feed_txp || vc4_state->txp_armed) {
 566                         vc4_crtc->event = crtc->state->event;
 567                         crtc->state->event = NULL;
 568                 }
 569
 570                 HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
 571                           vc4_state->mm.start);
 572
 573                 spin_unlock_irqrestore(&dev->event_lock, flags);
 574         } else {
 575                 HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
 576                           vc4_state->mm.start);
 577         }
 578 }
 579
 580 static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
 581                                    struct drm_crtc_state *old_state)
 582 {
 583         struct drm_device *dev = crtc->dev;
 584         struct vc4_dev *vc4 = to_vc4_dev(dev);
 585         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 586         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 587         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 588         u32 dispctrl;
 589
 590         require_hvs_enabled(dev);
 591
 592         /* Reset the PV fifo. */
 593         CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) |
 594                    PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
 595
 596         /* Enable vblank irq handling before crtc is started otherwise
 597          * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
 598          */
 599         drm_crtc_vblank_on(crtc);
 600         vc4_crtc_update_dlist(crtc);
 601
 602         /* Turn on the scaler, which will wait for vstart to start
 603          * compositing.
 604          * When feeding the transposer, we should operate in oneshot
 605          * mode.
 606          */
 607         dispctrl = SCALER_DISPCTRLX_ENABLE;
 608
 609         if (!vc4->hvs->hvs5)
 610                 dispctrl |= VC4_SET_FIELD(mode->hdisplay,
 611                                           SCALER_DISPCTRLX_WIDTH) |
 612                             VC4_SET_FIELD(mode->vdisplay,
 613                                           SCALER_DISPCTRLX_HEIGHT) |
 614                             (vc4_state->feed_txp ?
 615                                         SCALER_DISPCTRLX_ONESHOT : 0);
 616         else
 617                 dispctrl |= VC4_SET_FIELD(mode->hdisplay,
 618                                           SCALER5_DISPCTRLX_WIDTH) |
 619                             VC4_SET_FIELD(mode->vdisplay,
 620                                           SCALER5_DISPCTRLX_HEIGHT) |
 621                             (vc4_state->feed_txp ?
 622                                         SCALER5_DISPCTRLX_ONESHOT : 0);
 623
 624         HVS_WRITE(SCALER_DISPCTRLX(vc4_state->assigned_channel), dispctrl);
 625
 626         /* When feeding the transposer block the pixelvalve is unneeded and
 627          * should not be enabled.
 628          */
 629         if (!vc4_state->feed_txp)
 630                 CRTC_WRITE(PV_V_CONTROL,
 631                            CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 632 }
 633
 634 static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
 635                                                 const struct drm_display_mode *mode)
 636 {
 637         /* Do not allow doublescan modes from user space */
 638         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 639                 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
 640                               crtc->base.id);
 641                 return MODE_NO_DBLESCAN;
 642         }
 643
 644         return MODE_OK;
 645 }
 646
 647 void vc4_crtc_get_margins(struct drm_crtc_state *state,
 648                           unsigned int *left, unsigned int *right,
 649                           unsigned int *top, unsigned int *bottom)
 650 {
 651         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 652         struct drm_connector_state *conn_state;
 653         struct drm_connector *conn;
 654         int i;
 655
 656         *left = vc4_state->margins.left;
 657         *right = vc4_state->margins.right;
 658         *top = vc4_state->margins.top;
 659         *bottom = vc4_state->margins.bottom;
 660
 661         /* We have to interate over all new connector states because
 662          * vc4_crtc_get_margins() might be called before
 663          * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state
 664          * might be outdated.
 665          */
 666         for_each_new_connector_in_state(state->state, conn, conn_state, i) {
 667                 if (conn_state->crtc != state->crtc)
 668                         continue;
 669
 670                 *left = conn_state->tv.margins.left;
 671                 *right = conn_state->tv.margins.right;
 672                 *top = conn_state->tv.margins.top;
 673                 *bottom = conn_state->tv.margins.bottom;
 674                 break;
 675         }
 676 }
 677
 678 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 679                                  struct drm_crtc_state *state)
 680 {
 681         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 682         struct drm_device *dev = crtc->dev;
 683         struct vc4_dev *vc4 = to_vc4_dev(dev);
 684         struct drm_plane *plane;
 685         unsigned long flags;
 686         const struct drm_plane_state *plane_state;
 687         struct drm_connector *conn;
 688         struct drm_connector_state *conn_state;
 689         u32 dlist_count = 0;
 690         int ret, i;
 691
 692         /* The pixelvalve can only feed one encoder (and encoders are
 693          * 1:1 with connectors.)
 694          */
 695         if (hweight32(state->connector_mask) > 1)
 696                 return -EINVAL;
 697
 698         drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
 699                 dlist_count += vc4_plane_dlist_size(plane_state);
 700
 701         dlist_count++; /* Account for SCALER_CTL0_END. */
 702
 703         spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 704         ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
 705                                  dlist_count);
 706         spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 707         if (ret)
 708                 return ret;
 709
 710         for_each_new_connector_in_state(state->state, conn, conn_state, i) {
 711                 if (conn_state->crtc != crtc)
 712                         continue;
 713
 714                 /* The writeback connector is implemented using the transposer
 715                  * block which is directly taking its data from the HVS FIFO.
 716                  */
 717                 if (conn->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) {
 718                         state->no_vblank = true;
 719                         vc4_state->feed_txp = true;
 720                 } else {
 721                         state->no_vblank = false;
 722                         vc4_state->feed_txp = false;
 723                 }
 724
 725                 vc4_state->margins.left = conn_state->tv.margins.left;
 726                 vc4_state->margins.right = conn_state->tv.margins.right;
 727                 vc4_state->margins.top = conn_state->tv.margins.top;
 728                 vc4_state->margins.bottom = conn_state->tv.margins.bottom;
 729                 break;
 730         }
 731
 732         return 0;
 733 }
 734
 735 static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
 736                                   struct drm_crtc_state *old_state)
 737 {
 738         struct drm_device *dev = crtc->dev;
 739         struct vc4_dev *vc4 = to_vc4_dev(dev);
 740         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 741         struct drm_plane *plane;
 742         struct vc4_plane_state *vc4_plane_state;
 743         bool debug_dump_regs = false;
 744         bool enable_bg_fill = false;
 745         u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
 746         u32 __iomem *dlist_next = dlist_start;
 747
 748         if (debug_dump_regs) {
 749                 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
 750                 vc4_hvs_dump_state(dev);
 751         }
 752
 753         /* Copy all the active planes' dlist contents to the hardware dlist. */
 754         drm_atomic_crtc_for_each_plane(plane, crtc) {
 755                 /* Is this the first active plane? */
 756                 if (dlist_next == dlist_start) {
 757                         /* We need to enable background fill when a plane
 758                          * could be alpha blending from the background, i.e.
 759                          * where no other plane is underneath. It suffices to
 760                          * consider the first active plane here since we set
 761                          * needs_bg_fill such that either the first plane
 762                          * already needs it or all planes on top blend from
 763                          * the first or a lower plane.
 764                          */
 765                         vc4_plane_state = to_vc4_plane_state(plane->state);
 766                         enable_bg_fill = vc4_plane_state->needs_bg_fill;
 767                 }
 768
 769                 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
 770         }
 771
 772         writel(SCALER_CTL0_END, dlist_next);
 773         dlist_next++;
 774
 775         WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
 776
 777         if (enable_bg_fill)
 778                 /* This sets a black background color fill, as is the case
 779                  * with other DRM drivers.
 780                  */
 781                 HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel),
 782                           HVS_READ(SCALER_DISPBKGNDX(vc4_state->assigned_channel)) |
 783                           SCALER_DISPBKGND_FILL);
 784
 785         /* Only update DISPLIST if the CRTC was already running and is not
 786          * being disabled.
 787          * vc4_crtc_enable() takes care of updating the dlist just after
 788          * re-enabling VBLANK interrupts and before enabling the engine.
 789          * If the CRTC is being disabled, there's no point in updating this
 790          * information.
 791          */
 792         if (crtc->state->active && old_state->active)
 793                 vc4_crtc_update_dlist(crtc);
 794
 795         if (crtc->state->color_mgmt_changed) {
 796                 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_state->assigned_channel));
 797
 798                 if (crtc->state->gamma_lut) {
 799                         vc4_crtc_update_gamma_lut(crtc);
 800                         dispbkgndx |= SCALER_DISPBKGND_GAMMA;
 801                 } else {
 802                         /* Unsetting DISPBKGND_GAMMA skips the gamma lut step
 803                          * in hardware, which is the same as a linear lut that
 804                          * DRM expects us to use in absence of a user lut.
 805                          */
 806                         dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
 807                 }
 808                 HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel), dispbkgndx);
 809         }
 810
 811         if (debug_dump_regs) {
 812                 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
 813                 vc4_hvs_dump_state(dev);
 814         }
 815 }
 816
 817 static int vc4_enable_vblank(struct drm_crtc *crtc)
 818 {
 819         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 820
 821         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 822
 823         return 0;
 824 }
 825
 826 static void vc4_disable_vblank(struct drm_crtc *crtc)
 827 {
 828         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 829
 830         CRTC_WRITE(PV_INTEN, 0);
 831 }
 832
 833 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 834 {
 835         struct drm_crtc *crtc = &vc4_crtc->base;
 836         struct drm_device *dev = crtc->dev;
 837         struct vc4_dev *vc4 = to_vc4_dev(dev);
 838         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 839         u32 chan = vc4_state->assigned_channel;
 840         unsigned long flags;
 841
 842         spin_lock_irqsave(&dev->event_lock, flags);
 843         if (vc4_crtc->event &&
 844             (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)) ||
 845              vc4_state->feed_txp)) {
 846                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 847                 vc4_crtc->event = NULL;
 848                 drm_crtc_vblank_put(crtc);
 849
 850                 /* Wait for the page flip to unmask the underrun to ensure that
 851                  * the display list was updated by the hardware. Before that
 852                  * happens, the HVS will be using the previous display list with
 853                  * the CRTC and encoder already reconfigured, leading to
 854                  * underruns. This can be seen when reconfiguring the CRTC.
 855                  */
 856                 if (vc4->hvs)
 857                         vc4_hvs_unmask_underrun(dev, chan);
 858         }
 859         spin_unlock_irqrestore(&dev->event_lock, flags);
 860 }
 861
 862 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
 863 {
 864         crtc->t_vblank = ktime_get();
 865         drm_crtc_handle_vblank(&crtc->base);
 866         vc4_crtc_handle_page_flip(crtc);
 867 }
 868
 869 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 870 {
 871         struct vc4_crtc *vc4_crtc = data;
 872         u32 stat = CRTC_READ(PV_INTSTAT);
 873         irqreturn_t ret = IRQ_NONE;
 874
 875         if (stat & PV_INT_VFP_START) {
 876                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 877                 vc4_crtc_handle_vblank(vc4_crtc);
 878                 ret = IRQ_HANDLED;
 879         }
 880
 881         return ret;
 882 }
 883
 884 struct vc4_async_flip_state {
 885         struct drm_crtc *crtc;
 886         struct drm_framebuffer *fb;
 887         struct drm_framebuffer *old_fb;
 888         struct drm_pending_vblank_event *event;
 889
 890         struct vc4_seqno_cb cb;
 891 };
 892
 893 /* Called when the V3D execution for the BO being flipped to is done, so that
 894  * we can actually update the plane's address to point to it.
 895  */
 896 static void
 897 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
 898 {
 899         struct vc4_async_flip_state *flip_state =
 900                 container_of(cb, struct vc4_async_flip_state, cb);
 901         struct drm_crtc *crtc = flip_state->crtc;
 902         struct drm_device *dev = crtc->dev;
 903         struct vc4_dev *vc4 = to_vc4_dev(dev);
 904         struct drm_plane *plane = crtc->primary;
 905
 906         vc4_plane_async_set_fb(plane, flip_state->fb);
 907         if (flip_state->event) {
 908                 unsigned long flags;
 909
 910                 spin_lock_irqsave(&dev->event_lock, flags);
 911                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 912                 spin_unlock_irqrestore(&dev->event_lock, flags);
 913         }
 914
 915         drm_crtc_vblank_put(crtc);
 916         drm_framebuffer_put(flip_state->fb);
 917
 918         /* Decrement the BO usecnt in order to keep the inc/dec calls balanced
 919          * when the planes are updated through the async update path.
 920          * FIXME: we should move to generic async-page-flip when it's
 921          * available, so that we can get rid of this hand-made cleanup_fb()
 922          * logic.
 923          */
 924         if (flip_state->old_fb) {
 925                 struct drm_gem_cma_object *cma_bo;
 926                 struct vc4_bo *bo;
 927
 928                 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
 929                 bo = to_vc4_bo(&cma_bo->base);
 930                 vc4_bo_dec_usecnt(bo);
 931                 drm_framebuffer_put(flip_state->old_fb);
 932         }
 933
 934         kfree(flip_state);
 935
 936         up(&vc4->async_modeset);
 937 }
 938
 939 /* Implements async (non-vblank-synced) page flips.
 940  *
 941  * The page flip ioctl needs to return immediately, so we grab the
 942  * modeset semaphore on the pipe, and queue the address update for
 943  * when V3D is done with the BO being flipped to.
 944  */
 945 static int vc4_async_page_flip(struct drm_crtc *crtc,
 946                                struct drm_framebuffer *fb,
 947                                struct drm_pending_vblank_event *event,
 948                                uint32_t flags)
 949 {
 950         struct drm_device *dev = crtc->dev;
 951         struct vc4_dev *vc4 = to_vc4_dev(dev);
 952         struct drm_plane *plane = crtc->primary;
 953         int ret = 0;
 954         struct vc4_async_flip_state *flip_state;
 955         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 956         struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 957
 958         /* Increment the BO usecnt here, so that we never end up with an
 959          * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
 960          * plane is later updated through the non-async path.
 961          * FIXME: we should move to generic async-page-flip when it's
 962          * available, so that we can get rid of this hand-made prepare_fb()
 963          * logic.
 964          */
 965         ret = vc4_bo_inc_usecnt(bo);
 966         if (ret)
 967                 return ret;
 968
 969         flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 970         if (!flip_state) {
 971                 vc4_bo_dec_usecnt(bo);
 972                 return -ENOMEM;
 973         }
 974
 975         drm_framebuffer_get(fb);
 976         flip_state->fb = fb;
 977         flip_state->crtc = crtc;
 978         flip_state->event = event;
 979
 980         /* Make sure all other async modesetes have landed. */
 981         ret = down_interruptible(&vc4->async_modeset);
 982         if (ret) {
 983                 drm_framebuffer_put(fb);
 984                 vc4_bo_dec_usecnt(bo);
 985                 kfree(flip_state);
 986                 return ret;
 987         }
 988
 989         /* Save the current FB before it's replaced by the new one in
 990          * drm_atomic_set_fb_for_plane(). We'll need the old FB in
 991          * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
 992          * it consistent.
 993          * FIXME: we should move to generic async-page-flip when it's
 994          * available, so that we can get rid of this hand-made cleanup_fb()
 995          * logic.
 996          */
 997         flip_state->old_fb = plane->state->fb;
 998         if (flip_state->old_fb)
 999                 drm_framebuffer_get(flip_state->old_fb);
1000
1001         WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1002
1003         /* Immediately update the plane's legacy fb pointer, so that later
1004          * modeset prep sees the state that will be present when the semaphore
1005          * is released.
1006          */
1007         drm_atomic_set_fb_for_plane(plane->state, fb);
1008
1009         vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
1010                            vc4_async_page_flip_complete);
1011
1012         /* Driver takes ownership of state on successful async commit. */
1013         return 0;
1014 }
1015
1016 static int vc4_page_flip(struct drm_crtc *crtc,
1017                          struct drm_framebuffer *fb,
1018                          struct drm_pending_vblank_event *event,
1019                          uint32_t flags,
1020                          struct drm_modeset_acquire_ctx *ctx)
1021 {
1022         if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
1023                 return vc4_async_page_flip(crtc, fb, event, flags);
1024         else
1025                 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
1026 }
1027
1028 static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
1029 {
1030         struct vc4_crtc_state *vc4_state, *old_vc4_state;
1031
1032         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
1033         if (!vc4_state)
1034                 return NULL;
1035
1036         old_vc4_state = to_vc4_crtc_state(crtc->state);
1037         vc4_state->feed_txp = old_vc4_state->feed_txp;
1038         vc4_state->margins = old_vc4_state->margins;
1039         vc4_state->assigned_channel = old_vc4_state->assigned_channel;
1040
1041         __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
1042         return &vc4_state->base;
1043 }
1044
1045 static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
1046                                    struct drm_crtc_state *state)
1047 {
1048         struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
1049         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
1050
1051         if (vc4_state->mm.allocated) {
1052                 unsigned long flags;
1053
1054                 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
1055                 drm_mm_remove_node(&vc4_state->mm);
1056                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
1057
1058         }
1059
1060         drm_atomic_helper_crtc_destroy_state(crtc, state);
1061 }
1062
1063 static void
1064 vc4_crtc_reset(struct drm_crtc *crtc)
1065 {
1066         if (crtc->state)
1067                 vc4_crtc_destroy_state(crtc, crtc->state);
1068
1069         crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL);
1070         if (crtc->state)
1071                 crtc->state->crtc = crtc;
1072 }
1073
1074 static const struct drm_crtc_funcs vc4_crtc_funcs = {
1075         .set_config = drm_atomic_helper_set_config,
1076         .destroy = vc4_crtc_destroy,
1077         .page_flip = vc4_page_flip,
1078         .set_property = NULL,
1079         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
1080         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
1081         .reset = vc4_crtc_reset,
1082         .atomic_duplicate_state = vc4_crtc_duplicate_state,
1083         .atomic_destroy_state = vc4_crtc_destroy_state,
1084         .gamma_set = drm_atomic_helper_legacy_gamma_set,
1085         .enable_vblank = vc4_enable_vblank,
1086         .disable_vblank = vc4_disable_vblank,
1087 };
1088
1089 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
1090         .mode_set_nofb = vc4_crtc_mode_set_nofb,
1091         .mode_valid = vc4_crtc_mode_valid,
1092         .atomic_check = vc4_crtc_atomic_check,
1093         .atomic_flush = vc4_crtc_atomic_flush,
1094         .atomic_enable = vc4_crtc_atomic_enable,
1095         .atomic_disable = vc4_crtc_atomic_disable,
1096 };
1097
1098 static const struct vc4_crtc_data bcm2835_pv0_data = {
1099         .hvs_available_channels = BIT(0),
1100         .hvs_output = 0,
1101         .debugfs_name = "crtc0_regs",
1102         .fifo_depth = 64,
1103         .pixels_per_clock = 1,
1104         .encoder_types = {
1105                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
1106                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
1107         },
1108 };
1109
1110 static const struct vc4_crtc_data bcm2835_pv1_data = {
1111         .hvs_available_channels = BIT(2),
1112         .hvs_output = 2,
1113         .debugfs_name = "crtc1_regs",
1114         .fifo_depth = 64,
1115         .pixels_per_clock = 1,
1116         .encoder_types = {
1117                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
1118                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
1119         },
1120 };
1121
1122 static const struct vc4_crtc_data bcm2835_pv2_data = {
1123         .hvs_available_channels = BIT(1),
1124         .hvs_output = 1,
1125         .debugfs_name = "crtc2_regs",
1126         .fifo_depth = 64,
1127         .pixels_per_clock = 1,
1128         .encoder_types = {
1129                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI0,
1130                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1131         },
1132 };
1133
1134 static const struct vc4_crtc_data bcm2711_pv0_data = {
1135         .debugfs_name = "crtc0_regs",
1136         .hvs_available_channels = BIT(0),
1137         .hvs_output = 0,
1138         .fifo_depth = 64,
1139         .pixels_per_clock = 1,
1140         .encoder_types = {
1141                 [0] = VC4_ENCODER_TYPE_DSI0,
1142                 [1] = VC4_ENCODER_TYPE_DPI,
1143         },
1144 };
1145
1146 static const struct vc4_crtc_data bcm2711_pv1_data = {
1147         .debugfs_name = "crtc1_regs",
1148         .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1149         .hvs_output = 3,
1150         .fifo_depth = 64,
1151         .pixels_per_clock = 1,
1152         .encoder_types = {
1153                 [0] = VC4_ENCODER_TYPE_DSI1,
1154                 [1] = VC4_ENCODER_TYPE_SMI,
1155         },
1156 };
1157
1158 static const struct vc4_crtc_data bcm2711_pv2_data = {
1159         .debugfs_name = "crtc2_regs",
1160         .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1161         .hvs_output = 4,
1162         .fifo_depth = 256,
1163         .pixels_per_clock = 2,
1164         .encoder_types = {
1165                 [0] = VC4_ENCODER_TYPE_HDMI0,
1166         },
1167 };
1168
1169 static const struct vc4_crtc_data bcm2711_pv3_data = {
1170         .debugfs_name = "crtc3_regs",
1171         .hvs_available_channels = BIT(1),
1172         .hvs_output = 1,
1173         .fifo_depth = 64,
1174         .pixels_per_clock = 1,
1175         .encoder_types = {
1176                 [0] = VC4_ENCODER_TYPE_VEC,
1177         },
1178 };
1179
1180 static const struct vc4_crtc_data bcm2711_pv4_data = {
1181         .debugfs_name = "crtc4_regs",
1182         .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1183         .hvs_output = 5,
1184         .fifo_depth = 64,
1185         .pixels_per_clock = 2,
1186         .encoder_types = {
1187                 [0] = VC4_ENCODER_TYPE_HDMI1,
1188         },
1189 };
1190
1191 static const struct of_device_id vc4_crtc_dt_match[] = {
1192         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
1193         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
1194         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },
1195         { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data },
1196         { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data },
1197         { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
1198         { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
1199         { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
1200         {}
1201 };
1202
1203 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1204                                         struct drm_crtc *crtc)
1205 {
1206         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1207         const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
1208         const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
1209         struct drm_encoder *encoder;
1210
1211         drm_for_each_encoder(encoder, drm) {
1212                 struct vc4_encoder *vc4_encoder;
1213                 int i;
1214
1215                 /* HVS FIFO2 can feed the TXP IP. */
1216                 if (crtc_data->hvs_output == 2 &&
1217                     encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) {
1218                         encoder->possible_crtcs |= drm_crtc_mask(crtc);
1219                         continue;
1220                 }
1221
1222                 vc4_encoder = to_vc4_encoder(encoder);
1223                 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
1224                         if (vc4_encoder->type == encoder_types[i]) {
1225                                 vc4_encoder->clock_select = i;
1226                                 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1227                                 break;
1228                         }
1229                 }
1230         }
1231 }
1232
1233 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1234 {
1235         struct platform_device *pdev = to_platform_device(dev);
1236         struct drm_device *drm = dev_get_drvdata(master);
1237         struct vc4_dev *vc4 = to_vc4_dev(drm);
1238         struct vc4_crtc *vc4_crtc;
1239         struct drm_crtc *crtc;
1240         struct drm_plane *primary_plane, *destroy_plane, *temp;
1241         const struct of_device_id *match;
1242         int ret, i;
1243
1244         vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
1245         if (!vc4_crtc)
1246                 return -ENOMEM;
1247         crtc = &vc4_crtc->base;
1248
1249         match = of_match_device(vc4_crtc_dt_match, dev);
1250         if (!match)
1251                 return -ENODEV;
1252         vc4_crtc->data = match->data;
1253         vc4_crtc->pdev = pdev;
1254
1255         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1256         if (IS_ERR(vc4_crtc->regs))
1257                 return PTR_ERR(vc4_crtc->regs);
1258
1259         vc4_crtc->regset.base = vc4_crtc->regs;
1260         vc4_crtc->regset.regs = crtc_regs;
1261         vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);
1262
1263         /* For now, we create just the primary and the legacy cursor
1264          * planes.  We should be able to stack more planes on easily,
1265          * but to do that we would need to compute the bandwidth
1266          * requirement of the plane configuration, and reject ones
1267          * that will take too much.
1268          */
1269         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
1270         if (IS_ERR(primary_plane)) {
1271                 dev_err(dev, "failed to construct primary plane\n");
1272                 ret = PTR_ERR(primary_plane);
1273                 goto err;
1274         }
1275
1276         drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1277                                   &vc4_crtc_funcs, NULL);
1278         drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
1279
1280         if (!vc4->hvs->hvs5) {
1281                 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1282
1283                 /* We support CTM, but only for one CRTC at a
1284                  * time. It's therefore implemented as private driver
1285                  * state in vc4_kms, not here.
1286                  */
1287                 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
1288         }
1289
1290         CRTC_WRITE(PV_INTEN, 0);
1291         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1292         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1293                                vc4_crtc_irq_handler,
1294                                IRQF_SHARED,
1295                                "vc4 crtc", vc4_crtc);
1296         if (ret)
1297                 goto err_destroy_planes;
1298
1299         vc4_set_crtc_possible_masks(drm, crtc);
1300
1301         for (i = 0; i < crtc->gamma_size; i++) {
1302                 vc4_crtc->lut_r[i] = i;
1303                 vc4_crtc->lut_g[i] = i;
1304                 vc4_crtc->lut_b[i] = i;
1305         }
1306
1307         platform_set_drvdata(pdev, vc4_crtc);
1308
1309         vc4_debugfs_add_regset32(drm, vc4_crtc->data->debugfs_name,
1310                                  &vc4_crtc->regset);
1311
1312         return 0;
1313
1314 err_destroy_planes:
1315         list_for_each_entry_safe(destroy_plane, temp,
1316                                  &drm->mode_config.plane_list, head) {
1317                 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc))
1318                     destroy_plane->funcs->destroy(destroy_plane);
1319         }
1320 err:
1321         return ret;
1322 }
1323
1324 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1325                             void *data)
1326 {
1327         struct platform_device *pdev = to_platform_device(dev);
1328         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1329
1330         vc4_crtc_destroy(&vc4_crtc->base);
1331
1332         CRTC_WRITE(PV_INTEN, 0);
1333
1334         platform_set_drvdata(pdev, NULL);
1335 }
1336
1337 static const struct component_ops vc4_crtc_ops = {
1338         .bind   = vc4_crtc_bind,
1339         .unbind = vc4_crtc_unbind,
1340 };
1341
1342 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1343 {
1344         return component_add(&pdev->dev, &vc4_crtc_ops);
1345 }
1346
1347 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1348 {
1349         component_del(&pdev->dev, &vc4_crtc_ops);
1350         return 0;
1351 }
1352
1353 struct platform_driver vc4_crtc_driver = {
1354         .probe = vc4_crtc_dev_probe,
1355         .remove = vc4_crtc_dev_remove,
1356         .driver = {
1357                 .name = "vc4_crtc",
1358                 .of_match_table = vc4_crtc_dt_match,
1359         },
1360 };