1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2014-2018 Broadcom */
4 #include <linux/device.h>
5 #include <linux/dma-mapping.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/reset.h>
11 #include <linux/sched/signal.h>
12 #include <linux/uaccess.h>
14 #include <drm/drm_syncobj.h>
15 #include <uapi/drm/v3d_drm.h>
19 #include "v3d_trace.h"
22 v3d_init_core(struct v3d_dev *v3d, int core)
24 /* Set OVRTMUOUT, which means that the texture sampler uniform
25 * configuration's tmu output type field is used, instead of
26 * using the hardware default behavior based on the texture
27 * type. If you want the default behavior, you can still put
28 * "2" in the indirect texture state's output_type field.
31 V3D_CORE_WRITE(core, V3D_CTL_MISCCFG, V3D_MISCCFG_OVRTMUOUT);
33 /* Whenever we flush the L2T cache, we always want to flush
36 V3D_CORE_WRITE(core, V3D_CTL_L2TFLSTA, 0);
37 V3D_CORE_WRITE(core, V3D_CTL_L2TFLEND, ~0);
40 /* Sets invariant state for the HW. */
42 v3d_init_hw_state(struct v3d_dev *v3d)
44 v3d_init_core(v3d, 0);
48 v3d_idle_axi(struct v3d_dev *v3d, int core)
50 V3D_CORE_WRITE(core, V3D_GMP_CFG, V3D_GMP_CFG_STOP_REQ);
52 if (wait_for((V3D_CORE_READ(core, V3D_GMP_STATUS) &
53 (V3D_GMP_STATUS_RD_COUNT_MASK |
54 V3D_GMP_STATUS_WR_COUNT_MASK |
55 V3D_GMP_STATUS_CFG_BUSY)) == 0, 100)) {
56 DRM_ERROR("Failed to wait for safe GMP shutdown\n");
61 v3d_idle_gca(struct v3d_dev *v3d)
66 V3D_GCA_WRITE(V3D_GCA_SAFE_SHUTDOWN, V3D_GCA_SAFE_SHUTDOWN_EN);
68 if (wait_for((V3D_GCA_READ(V3D_GCA_SAFE_SHUTDOWN_ACK) &
69 V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED) ==
70 V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED, 100)) {
71 DRM_ERROR("Failed to wait for safe GCA shutdown\n");
76 v3d_reset_by_bridge(struct v3d_dev *v3d)
78 int version = V3D_BRIDGE_READ(V3D_TOP_GR_BRIDGE_REVISION);
80 if (V3D_GET_FIELD(version, V3D_TOP_GR_BRIDGE_MAJOR) == 2) {
81 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0,
82 V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT);
83 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_0, 0);
85 /* GFXH-1383: The SW_INIT may cause a stray write to address 0
86 * of the unit, so reset it to its power-on value here.
88 V3D_WRITE(V3D_HUB_AXICFG, V3D_HUB_AXICFG_MAX_LEN_MASK);
90 WARN_ON_ONCE(V3D_GET_FIELD(version,
91 V3D_TOP_GR_BRIDGE_MAJOR) != 7);
92 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1,
93 V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT);
94 V3D_BRIDGE_WRITE(V3D_TOP_GR_BRIDGE_SW_INIT_1, 0);
99 v3d_reset_v3d(struct v3d_dev *v3d)
102 reset_control_reset(v3d->reset);
104 v3d_reset_by_bridge(v3d);
106 v3d_init_hw_state(v3d);
110 v3d_reset(struct v3d_dev *v3d)
112 struct drm_device *dev = &v3d->drm;
114 DRM_DEV_ERROR(dev->dev, "Resetting GPU for hang.\n");
115 DRM_DEV_ERROR(dev->dev, "V3D_ERR_STAT: 0x%08x\n",
116 V3D_CORE_READ(0, V3D_ERR_STAT));
117 trace_v3d_reset_begin(dev);
119 /* XXX: only needed for safe powerdown, not reset. */
121 v3d_idle_axi(v3d, 0);
126 v3d_mmu_set_page_table(v3d);
129 v3d_perfmon_stop(v3d, v3d->active_perfmon, false);
131 trace_v3d_reset_end(dev);
135 v3d_flush_l3(struct v3d_dev *v3d)
138 u32 gca_ctrl = V3D_GCA_READ(V3D_GCA_CACHE_CTRL);
140 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL,
141 gca_ctrl | V3D_GCA_CACHE_CTRL_FLUSH);
144 V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL,
145 gca_ctrl & ~V3D_GCA_CACHE_CTRL_FLUSH);
150 /* Invalidates the (read-only) L2C cache. This was the L2 cache for
151 * uniforms and instructions on V3D 3.2.
154 v3d_invalidate_l2c(struct v3d_dev *v3d, int core)
159 V3D_CORE_WRITE(core, V3D_CTL_L2CACTL,
164 /* Invalidates texture L2 cachelines */
166 v3d_flush_l2t(struct v3d_dev *v3d, int core)
168 /* While there is a busy bit (V3D_L2TCACTL_L2TFLS), we don't
169 * need to wait for completion before dispatching the job --
170 * L2T accesses will be stalled until the flush has completed.
171 * However, we do need to make sure we don't try to trigger a
172 * new flush while the L2_CLEAN queue is trying to
173 * synchronously clean after a job.
175 mutex_lock(&v3d->cache_clean_lock);
176 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL,
177 V3D_L2TCACTL_L2TFLS |
178 V3D_SET_FIELD(V3D_L2TCACTL_FLM_FLUSH, V3D_L2TCACTL_FLM));
179 mutex_unlock(&v3d->cache_clean_lock);
182 /* Cleans texture L1 and L2 cachelines (writing back dirty data).
184 * For cleaning, which happens from the CACHE_CLEAN queue after CSD has
185 * executed, we need to make sure that the clean is done before
186 * signaling job completion. So, we synchronously wait before
187 * returning, and we make sure that L2 invalidates don't happen in the
188 * meantime to confuse our are-we-done checks.
191 v3d_clean_caches(struct v3d_dev *v3d)
193 struct drm_device *dev = &v3d->drm;
196 trace_v3d_cache_clean_begin(dev);
198 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF);
199 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
200 V3D_L2TCACTL_TMUWCF), 100)) {
201 DRM_ERROR("Timeout waiting for TMU write combiner flush\n");
204 mutex_lock(&v3d->cache_clean_lock);
205 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL,
206 V3D_L2TCACTL_L2TFLS |
207 V3D_SET_FIELD(V3D_L2TCACTL_FLM_CLEAN, V3D_L2TCACTL_FLM));
209 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
210 V3D_L2TCACTL_L2TFLS), 100)) {
211 DRM_ERROR("Timeout waiting for L2T clean\n");
214 mutex_unlock(&v3d->cache_clean_lock);
216 trace_v3d_cache_clean_end(dev);
219 /* Invalidates the slice caches. These are read-only caches. */
221 v3d_invalidate_slices(struct v3d_dev *v3d, int core)
223 V3D_CORE_WRITE(core, V3D_CTL_SLCACTL,
224 V3D_SET_FIELD(0xf, V3D_SLCACTL_TVCCS) |
225 V3D_SET_FIELD(0xf, V3D_SLCACTL_TDCCS) |
226 V3D_SET_FIELD(0xf, V3D_SLCACTL_UCC) |
227 V3D_SET_FIELD(0xf, V3D_SLCACTL_ICC));
231 v3d_invalidate_caches(struct v3d_dev *v3d)
233 /* Invalidate the caches from the outside in. That way if
234 * another CL's concurrent use of nearby memory were to pull
235 * an invalidated cacheline back in, we wouldn't leave stale
236 * data in the inner cache.
239 v3d_invalidate_l2c(v3d, 0);
240 v3d_flush_l2t(v3d, 0);
241 v3d_invalidate_slices(v3d, 0);
244 /* Takes the reservation lock on all the BOs being referenced, so that
245 * at queue submit time we can update the reservations.
247 * We don't lock the RCL the tile alloc/state BOs, or overflow memory
248 * (all of which are on exec->unref_list). They're entirely private
249 * to v3d, so we don't attach dma-buf fences to them.
252 v3d_lock_bo_reservations(struct v3d_job *job,
253 struct ww_acquire_ctx *acquire_ctx)
257 ret = drm_gem_lock_reservations(job->bo, job->bo_count, acquire_ctx);
261 for (i = 0; i < job->bo_count; i++) {
262 ret = drm_gem_fence_array_add_implicit(&job->deps,
265 drm_gem_unlock_reservations(job->bo, job->bo_count,
275 * v3d_lookup_bos() - Sets up job->bo[] with the GEM objects
276 * referenced by the job.
278 * @file_priv: DRM file for this fd
279 * @job: V3D job being set up
280 * @bo_handles: GEM handles
281 * @bo_count: Number of GEM handles passed in
283 * The command validator needs to reference BOs by their index within
284 * the submitted job's BO list. This does the validation of the job's
285 * BO list and reference counting for the lifetime of the job.
287 * Note that this function doesn't need to unreference the BOs on
288 * failure, because that will happen at v3d_exec_cleanup() time.
291 v3d_lookup_bos(struct drm_device *dev,
292 struct drm_file *file_priv,
301 job->bo_count = bo_count;
303 if (!job->bo_count) {
304 /* See comment on bo_index for why we have to check
307 DRM_DEBUG("Rendering requires BOs\n");
311 job->bo = kvmalloc_array(job->bo_count,
312 sizeof(struct drm_gem_cma_object *),
313 GFP_KERNEL | __GFP_ZERO);
315 DRM_DEBUG("Failed to allocate validated BO pointers\n");
319 handles = kvmalloc_array(job->bo_count, sizeof(u32), GFP_KERNEL);
322 DRM_DEBUG("Failed to allocate incoming GEM handles\n");
326 if (copy_from_user(handles,
327 (void __user *)(uintptr_t)bo_handles,
328 job->bo_count * sizeof(u32))) {
330 DRM_DEBUG("Failed to copy in GEM handles\n");
334 spin_lock(&file_priv->table_lock);
335 for (i = 0; i < job->bo_count; i++) {
336 struct drm_gem_object *bo = idr_find(&file_priv->object_idr,
339 DRM_DEBUG("Failed to look up GEM BO %d: %d\n",
342 spin_unlock(&file_priv->table_lock);
345 drm_gem_object_get(bo);
348 spin_unlock(&file_priv->table_lock);
356 v3d_job_free(struct kref *ref)
358 struct v3d_job *job = container_of(ref, struct v3d_job, refcount);
360 struct dma_fence *fence;
363 for (i = 0; i < job->bo_count; i++) {
365 drm_gem_object_put(job->bo[i]);
369 xa_for_each(&job->deps, index, fence) {
370 dma_fence_put(fence);
372 xa_destroy(&job->deps);
374 dma_fence_put(job->irq_fence);
375 dma_fence_put(job->done_fence);
377 pm_runtime_mark_last_busy(job->v3d->drm.dev);
378 pm_runtime_put_autosuspend(job->v3d->drm.dev);
381 v3d_perfmon_put(job->perfmon);
387 v3d_render_job_free(struct kref *ref)
389 struct v3d_render_job *job = container_of(ref, struct v3d_render_job,
391 struct v3d_bo *bo, *save;
393 list_for_each_entry_safe(bo, save, &job->unref_list, unref_head) {
394 drm_gem_object_put(&bo->base.base);
400 void v3d_job_put(struct v3d_job *job)
402 kref_put(&job->refcount, job->free);
406 v3d_wait_bo_ioctl(struct drm_device *dev, void *data,
407 struct drm_file *file_priv)
410 struct drm_v3d_wait_bo *args = data;
411 ktime_t start = ktime_get();
413 unsigned long timeout_jiffies =
414 nsecs_to_jiffies_timeout(args->timeout_ns);
419 ret = drm_gem_dma_resv_wait(file_priv, args->handle,
420 true, timeout_jiffies);
422 /* Decrement the user's timeout, in case we got interrupted
423 * such that the ioctl will be restarted.
425 delta_ns = ktime_to_ns(ktime_sub(ktime_get(), start));
426 if (delta_ns < args->timeout_ns)
427 args->timeout_ns -= delta_ns;
429 args->timeout_ns = 0;
431 /* Asked to wait beyond the jiffie/scheduler precision? */
432 if (ret == -ETIME && args->timeout_ns)
439 v3d_job_init(struct v3d_dev *v3d, struct drm_file *file_priv,
440 struct v3d_job *job, void (*free)(struct kref *ref),
443 struct dma_fence *in_fence = NULL;
449 ret = pm_runtime_get_sync(v3d->drm.dev);
453 xa_init_flags(&job->deps, XA_FLAGS_ALLOC);
455 ret = drm_syncobj_find_fence(file_priv, in_sync, 0, 0, &in_fence);
459 ret = drm_gem_fence_array_add(&job->deps, in_fence);
463 kref_init(&job->refcount);
467 xa_destroy(&job->deps);
468 pm_runtime_put_autosuspend(v3d->drm.dev);
473 v3d_push_job(struct v3d_file_priv *v3d_priv,
474 struct v3d_job *job, enum v3d_queue queue)
478 ret = drm_sched_job_init(&job->base, &v3d_priv->sched_entity[queue],
483 job->done_fence = dma_fence_get(&job->base.s_fence->finished);
485 /* put by scheduler job completion */
486 kref_get(&job->refcount);
488 drm_sched_entity_push_job(&job->base, &v3d_priv->sched_entity[queue]);
494 v3d_attach_fences_and_unlock_reservation(struct drm_file *file_priv,
496 struct ww_acquire_ctx *acquire_ctx,
498 struct dma_fence *done_fence)
500 struct drm_syncobj *sync_out;
503 for (i = 0; i < job->bo_count; i++) {
504 /* XXX: Use shared fences for read-only objects. */
505 dma_resv_add_excl_fence(job->bo[i]->resv,
509 drm_gem_unlock_reservations(job->bo, job->bo_count, acquire_ctx);
511 /* Update the return sync object for the job */
512 sync_out = drm_syncobj_find(file_priv, out_sync);
514 drm_syncobj_replace_fence(sync_out, done_fence);
515 drm_syncobj_put(sync_out);
520 * v3d_submit_cl_ioctl() - Submits a job (frame) to the V3D.
522 * @data: ioctl argument
523 * @file_priv: DRM file for this fd
525 * This is the main entrypoint for userspace to submit a 3D frame to
526 * the GPU. Userspace provides the binner command list (if
527 * applicable), and the kernel sets up the render command list to draw
528 * to the framebuffer described in the ioctl, using the command lists
529 * that the 3D engine's binner will produce.
532 v3d_submit_cl_ioctl(struct drm_device *dev, void *data,
533 struct drm_file *file_priv)
535 struct v3d_dev *v3d = to_v3d_dev(dev);
536 struct v3d_file_priv *v3d_priv = file_priv->driver_priv;
537 struct drm_v3d_submit_cl *args = data;
538 struct v3d_bin_job *bin = NULL;
539 struct v3d_render_job *render;
540 struct v3d_job *clean_job = NULL;
541 struct v3d_job *last_job;
542 struct ww_acquire_ctx acquire_ctx;
545 trace_v3d_submit_cl_ioctl(&v3d->drm, args->rcl_start, args->rcl_end);
550 if (args->flags != 0 &&
551 args->flags != DRM_V3D_SUBMIT_CL_FLUSH_CACHE) {
552 DRM_INFO("invalid flags: %d\n", args->flags);
556 render = kcalloc(1, sizeof(*render), GFP_KERNEL);
560 render->start = args->rcl_start;
561 render->end = args->rcl_end;
562 INIT_LIST_HEAD(&render->unref_list);
564 ret = v3d_job_init(v3d, file_priv, &render->base,
565 v3d_render_job_free, args->in_sync_rcl);
571 if (args->bcl_start != args->bcl_end) {
572 bin = kcalloc(1, sizeof(*bin), GFP_KERNEL);
574 v3d_job_put(&render->base);
578 ret = v3d_job_init(v3d, file_priv, &bin->base,
579 v3d_job_free, args->in_sync_bcl);
581 v3d_job_put(&render->base);
586 bin->start = args->bcl_start;
587 bin->end = args->bcl_end;
588 bin->qma = args->qma;
589 bin->qms = args->qms;
590 bin->qts = args->qts;
591 bin->render = render;
594 if (args->flags & DRM_V3D_SUBMIT_CL_FLUSH_CACHE) {
595 clean_job = kcalloc(1, sizeof(*clean_job), GFP_KERNEL);
601 ret = v3d_job_init(v3d, file_priv, clean_job, v3d_job_free, 0);
608 last_job = clean_job;
610 last_job = &render->base;
613 ret = v3d_lookup_bos(dev, file_priv, last_job,
614 args->bo_handles, args->bo_handle_count);
618 ret = v3d_lock_bo_reservations(last_job, &acquire_ctx);
622 if (args->perfmon_id) {
623 render->base.perfmon = v3d_perfmon_find(v3d_priv,
626 if (!render->base.perfmon) {
632 mutex_lock(&v3d->sched_lock);
634 bin->base.perfmon = render->base.perfmon;
635 v3d_perfmon_get(bin->base.perfmon);
636 ret = v3d_push_job(v3d_priv, &bin->base, V3D_BIN);
640 ret = drm_gem_fence_array_add(&render->base.deps,
641 dma_fence_get(bin->base.done_fence));
646 ret = v3d_push_job(v3d_priv, &render->base, V3D_RENDER);
651 struct dma_fence *render_fence =
652 dma_fence_get(render->base.done_fence);
653 ret = drm_gem_fence_array_add(&clean_job->deps, render_fence);
656 clean_job->perfmon = render->base.perfmon;
657 v3d_perfmon_get(clean_job->perfmon);
658 ret = v3d_push_job(v3d_priv, clean_job, V3D_CACHE_CLEAN);
663 mutex_unlock(&v3d->sched_lock);
665 v3d_attach_fences_and_unlock_reservation(file_priv,
669 last_job->done_fence);
672 v3d_job_put(&bin->base);
673 v3d_job_put(&render->base);
675 v3d_job_put(clean_job);
680 mutex_unlock(&v3d->sched_lock);
682 drm_gem_unlock_reservations(last_job->bo,
683 last_job->bo_count, &acquire_ctx);
686 v3d_job_put(&bin->base);
687 v3d_job_put(&render->base);
689 v3d_job_put(clean_job);
695 * v3d_submit_tfu_ioctl() - Submits a TFU (texture formatting) job to the V3D.
697 * @data: ioctl argument
698 * @file_priv: DRM file for this fd
700 * Userspace provides the register setup for the TFU, which we don't
701 * need to validate since the TFU is behind the MMU.
704 v3d_submit_tfu_ioctl(struct drm_device *dev, void *data,
705 struct drm_file *file_priv)
707 struct v3d_dev *v3d = to_v3d_dev(dev);
708 struct v3d_file_priv *v3d_priv = file_priv->driver_priv;
709 struct drm_v3d_submit_tfu *args = data;
710 struct v3d_tfu_job *job;
711 struct ww_acquire_ctx acquire_ctx;
714 trace_v3d_submit_tfu_ioctl(&v3d->drm, args->iia);
716 job = kcalloc(1, sizeof(*job), GFP_KERNEL);
720 ret = v3d_job_init(v3d, file_priv, &job->base,
721 v3d_job_free, args->in_sync);
727 job->base.bo = kcalloc(ARRAY_SIZE(args->bo_handles),
728 sizeof(*job->base.bo), GFP_KERNEL);
730 v3d_job_put(&job->base);
736 spin_lock(&file_priv->table_lock);
737 for (job->base.bo_count = 0;
738 job->base.bo_count < ARRAY_SIZE(args->bo_handles);
739 job->base.bo_count++) {
740 struct drm_gem_object *bo;
742 if (!args->bo_handles[job->base.bo_count])
745 bo = idr_find(&file_priv->object_idr,
746 args->bo_handles[job->base.bo_count]);
748 DRM_DEBUG("Failed to look up GEM BO %d: %d\n",
750 args->bo_handles[job->base.bo_count]);
752 spin_unlock(&file_priv->table_lock);
755 drm_gem_object_get(bo);
756 job->base.bo[job->base.bo_count] = bo;
758 spin_unlock(&file_priv->table_lock);
760 ret = v3d_lock_bo_reservations(&job->base, &acquire_ctx);
764 mutex_lock(&v3d->sched_lock);
765 ret = v3d_push_job(v3d_priv, &job->base, V3D_TFU);
768 mutex_unlock(&v3d->sched_lock);
770 v3d_attach_fences_and_unlock_reservation(file_priv,
771 &job->base, &acquire_ctx,
773 job->base.done_fence);
775 v3d_job_put(&job->base);
780 mutex_unlock(&v3d->sched_lock);
781 drm_gem_unlock_reservations(job->base.bo, job->base.bo_count,
784 v3d_job_put(&job->base);
790 * v3d_submit_csd_ioctl() - Submits a CSD (texture formatting) job to the V3D.
792 * @data: ioctl argument
793 * @file_priv: DRM file for this fd
795 * Userspace provides the register setup for the CSD, which we don't
796 * need to validate since the CSD is behind the MMU.
799 v3d_submit_csd_ioctl(struct drm_device *dev, void *data,
800 struct drm_file *file_priv)
802 struct v3d_dev *v3d = to_v3d_dev(dev);
803 struct v3d_file_priv *v3d_priv = file_priv->driver_priv;
804 struct drm_v3d_submit_csd *args = data;
805 struct v3d_csd_job *job;
806 struct v3d_job *clean_job;
807 struct ww_acquire_ctx acquire_ctx;
810 trace_v3d_submit_csd_ioctl(&v3d->drm, args->cfg[5], args->cfg[6]);
812 if (!v3d_has_csd(v3d)) {
813 DRM_DEBUG("Attempting CSD submit on non-CSD hardware\n");
817 job = kcalloc(1, sizeof(*job), GFP_KERNEL);
821 ret = v3d_job_init(v3d, file_priv, &job->base,
822 v3d_job_free, args->in_sync);
828 clean_job = kcalloc(1, sizeof(*clean_job), GFP_KERNEL);
830 v3d_job_put(&job->base);
835 ret = v3d_job_init(v3d, file_priv, clean_job, v3d_job_free, 0);
837 v3d_job_put(&job->base);
844 ret = v3d_lookup_bos(dev, file_priv, clean_job,
845 args->bo_handles, args->bo_handle_count);
849 ret = v3d_lock_bo_reservations(clean_job, &acquire_ctx);
853 if (args->perfmon_id) {
854 job->base.perfmon = v3d_perfmon_find(v3d_priv,
856 if (!job->base.perfmon) {
862 mutex_lock(&v3d->sched_lock);
863 ret = v3d_push_job(v3d_priv, &job->base, V3D_CSD);
867 ret = drm_gem_fence_array_add(&clean_job->deps,
868 dma_fence_get(job->base.done_fence));
872 ret = v3d_push_job(v3d_priv, clean_job, V3D_CACHE_CLEAN);
875 mutex_unlock(&v3d->sched_lock);
877 v3d_attach_fences_and_unlock_reservation(file_priv,
881 clean_job->done_fence);
883 v3d_job_put(&job->base);
884 v3d_job_put(clean_job);
889 mutex_unlock(&v3d->sched_lock);
891 drm_gem_unlock_reservations(clean_job->bo, clean_job->bo_count,
894 v3d_job_put(&job->base);
895 v3d_job_put(clean_job);
901 v3d_gem_init(struct drm_device *dev)
903 struct v3d_dev *v3d = to_v3d_dev(dev);
904 u32 pt_size = 4096 * 1024;
907 for (i = 0; i < V3D_MAX_QUEUES; i++)
908 v3d->queue[i].fence_context = dma_fence_context_alloc(1);
910 spin_lock_init(&v3d->mm_lock);
911 spin_lock_init(&v3d->job_lock);
912 mutex_init(&v3d->bo_lock);
913 mutex_init(&v3d->reset_lock);
914 mutex_init(&v3d->sched_lock);
915 mutex_init(&v3d->cache_clean_lock);
917 /* Note: We don't allocate address 0. Various bits of HW
918 * treat 0 as special, such as the occlusion query counters
919 * where 0 means "disabled".
921 drm_mm_init(&v3d->mm, 1, pt_size / sizeof(u32) - 1);
923 v3d->pt = dma_alloc_wc(v3d->drm.dev, pt_size,
925 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
927 drm_mm_takedown(&v3d->mm);
928 dev_err(v3d->drm.dev,
929 "Failed to allocate page tables. "
930 "Please ensure you have CMA enabled.\n");
934 v3d_init_hw_state(v3d);
935 v3d_mmu_set_page_table(v3d);
937 ret = v3d_sched_init(v3d);
939 drm_mm_takedown(&v3d->mm);
940 dma_free_coherent(v3d->drm.dev, 4096 * 1024, (void *)v3d->pt,
948 v3d_gem_destroy(struct drm_device *dev)
950 struct v3d_dev *v3d = to_v3d_dev(dev);
954 /* Waiting for jobs to finish would need to be done before
957 WARN_ON(v3d->bin_job);
958 WARN_ON(v3d->render_job);
960 drm_mm_takedown(&v3d->mm);
962 dma_free_coherent(v3d->drm.dev, 4096 * 1024, (void *)v3d->pt,