1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2015-2018 Broadcom */
4 #include <linux/delay.h>
5 #include <linux/mutex.h>
6 #include <linux/spinlock_types.h>
7 #include <linux/workqueue.h>
9 #include <drm/drm_encoder.h>
10 #include <drm/drm_gem.h>
11 #include <drm/drm_gem_shmem_helper.h>
12 #include <drm/gpu_scheduler.h>
14 #include "uapi/drm/v3d_drm.h"
17 struct platform_device;
20 #define GMP_GRANULARITY (128 * 1024)
22 /* Enum for each of the V3D queues. */
31 #define V3D_MAX_QUEUES (V3D_CACHE_CLEAN + 1)
33 struct v3d_queue_state {
34 struct drm_gpu_scheduler sched;
40 /* Performance monitor object. The perform lifetime is controlled by userspace
41 * using perfmon related ioctls. A perfmon can be attached to a submit_cl
42 * request, and when this is the case, HW perf counters will be activated just
43 * before the submit_cl is submitted to the GPU and disabled when the job is
44 * done. This way, only events related to a specific job will be counted.
47 /* Tracks the number of users of the perfmon, when this counter reaches
48 * zero the perfmon is destroyed.
52 /* Protects perfmon stop, as it can be invoked from multiple places. */
55 /* Number of counters activated in this perfmon instance
56 * (should be less than DRM_V3D_MAX_PERF_COUNTERS).
60 /* Events counted by the HW perf counters. */
61 u8 counters[DRM_V3D_MAX_PERF_COUNTERS];
63 /* Storage for counter values. Counters are incremented by the
64 * HW perf counter values every time the perfmon is attached
65 * to a GPU job. This way, perfmon users don't have to
66 * retrieve the results after each job if they want to track
67 * events covering several submissions. Note that counter
68 * values can't be reset, but you can fake a reset by
69 * destroying the perfmon and creating a new one.
75 struct drm_device drm;
77 /* Short representation (e.g. 33, 41) of the V3D tech version
83 void __iomem *hub_regs;
84 void __iomem *core_regs[3];
85 void __iomem *bridge_regs;
86 void __iomem *gca_regs;
88 struct delayed_work clk_down_work;
89 unsigned long clk_up_rate, clk_down_rate;
90 struct mutex clk_lock;
94 struct reset_control *reset;
96 /* Virtual and DMA addresses of the single shared page table. */
100 /* Virtual and DMA addresses of the MMU's scratch page. When
101 * a read or write is invalid in the MMU, it will be
105 dma_addr_t mmu_scratch_paddr;
106 /* virtual address bits from V3D to the MMU. */
109 /* Number of V3D cores. */
112 /* Allocator managing the address space. All units are in
118 struct work_struct overflow_mem_work;
120 struct v3d_bin_job *bin_job;
121 struct v3d_render_job *render_job;
122 struct v3d_tfu_job *tfu_job;
123 struct v3d_csd_job *csd_job;
125 struct v3d_queue_state queue[V3D_MAX_QUEUES];
127 /* Spinlock used to synchronize the overflow memory
128 * management against bin job submission.
132 /* Used to track the active perfmon if any. */
133 struct v3d_perfmon *active_perfmon;
135 /* Protects bo_stats */
136 struct mutex bo_lock;
138 /* Lock taken when resetting the GPU, to keep multiple
139 * processes from trying to park the scheduler threads and
142 struct mutex reset_lock;
144 /* Lock taken when creating and pushing the GPU scheduler
145 * jobs, to keep the sched-fence seqnos in order.
147 struct mutex sched_lock;
149 /* Lock taken during a cache clean and when initiating an L2
150 * flush, to keep L2 flushes from interfering with the
151 * synchronous L2 cleans.
153 struct mutex cache_clean_lock;
161 static inline struct v3d_dev *
162 to_v3d_dev(struct drm_device *dev)
164 return container_of(dev, struct v3d_dev, drm);
168 v3d_has_csd(struct v3d_dev *v3d)
170 return v3d->ver >= 41;
173 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev)
175 /* The per-fd struct, which tracks the MMU mappings. */
176 struct v3d_file_priv {
184 struct drm_sched_entity sched_entity[V3D_MAX_QUEUES];
188 struct drm_gem_shmem_object base;
190 struct drm_mm_node node;
192 /* List entry for the BO's position in
193 * v3d_render_job->unref_list
195 struct list_head unref_head;
198 static inline struct v3d_bo *
199 to_v3d_bo(struct drm_gem_object *bo)
201 return (struct v3d_bo *)bo;
205 struct dma_fence base;
206 struct drm_device *dev;
207 /* v3d seqno for signaled() test */
209 enum v3d_queue queue;
212 static inline struct v3d_fence *
213 to_v3d_fence(struct dma_fence *fence)
215 return (struct v3d_fence *)fence;
218 #define V3D_READ(offset) readl(v3d->hub_regs + offset)
219 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset)
221 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset)
222 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset)
224 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset)
225 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset)
227 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
228 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset)
231 struct drm_sched_job base;
233 struct kref refcount;
237 /* This is the array of BOs that were looked up at the start
240 struct drm_gem_object **bo;
243 /* Array of struct dma_fence * to block on before submitting this job.
246 unsigned long last_dep;
248 /* v3d fence to be signaled by IRQ handler when the job is complete. */
249 struct dma_fence *irq_fence;
251 /* scheduler fence for when the job is considered complete and
252 * the BO reservations can be released.
254 struct dma_fence *done_fence;
256 /* Pointer to a performance monitor object if the user requested it,
259 struct v3d_perfmon *perfmon;
261 /* Callback for the freeing of the job on refcount going to 0. */
262 void (*free)(struct kref *ref);
268 /* GPU virtual addresses of the start/end of the CL job. */
271 u32 timedout_ctca, timedout_ctra;
273 /* Corresponding render job, for attaching our overflow memory. */
274 struct v3d_render_job *render;
276 /* Submitted tile memory allocation start/size, tile state. */
280 struct v3d_render_job {
283 /* GPU virtual addresses of the start/end of the CL job. */
286 u32 timedout_ctca, timedout_ctra;
288 /* List of overflow BOs used in the job that need to be
289 * released once the job is complete.
291 struct list_head unref_list;
297 struct drm_v3d_submit_tfu args;
303 u32 timedout_batches;
305 struct drm_v3d_submit_csd args;
309 * __wait_for - magic wait macro
311 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
312 * important that we check the condition again after having timed out, since the
313 * timeout could be due to preemption or similar and we've never had a chance to
314 * check the condition before the timeout.
316 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
317 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
318 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
322 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
324 /* Guarantee COND check prior to timeout */ \
331 ret__ = -ETIMEDOUT; \
334 usleep_range(wait__, wait__ * 2); \
335 if (wait__ < (Wmax)) \
341 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
343 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
345 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
347 /* nsecs_to_jiffies64() does not guard against overflow */
348 if (NSEC_PER_SEC % HZ &&
349 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
350 return MAX_JIFFY_OFFSET;
352 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
356 struct drm_gem_object *v3d_create_object(struct drm_device *dev, size_t size);
357 void v3d_free_object(struct drm_gem_object *gem_obj);
358 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv,
360 int v3d_create_bo_ioctl(struct drm_device *dev, void *data,
361 struct drm_file *file_priv);
362 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data,
363 struct drm_file *file_priv);
364 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data,
365 struct drm_file *file_priv);
366 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev,
367 struct dma_buf_attachment *attach,
368 struct sg_table *sgt);
371 void v3d_debugfs_init(struct drm_minor *minor);
374 extern const struct dma_fence_ops v3d_fence_ops;
375 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue);
378 int v3d_gem_init(struct drm_device *dev);
379 void v3d_gem_destroy(struct drm_device *dev);
380 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data,
381 struct drm_file *file_priv);
382 int v3d_submit_tfu_ioctl(struct drm_device *dev, void *data,
383 struct drm_file *file_priv);
384 int v3d_submit_csd_ioctl(struct drm_device *dev, void *data,
385 struct drm_file *file_priv);
386 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data,
387 struct drm_file *file_priv);
388 void v3d_job_put(struct v3d_job *job);
389 void v3d_reset(struct v3d_dev *v3d);
390 void v3d_invalidate_caches(struct v3d_dev *v3d);
391 void v3d_clean_caches(struct v3d_dev *v3d);
394 int v3d_irq_init(struct v3d_dev *v3d);
395 void v3d_irq_enable(struct v3d_dev *v3d);
396 void v3d_irq_disable(struct v3d_dev *v3d);
397 void v3d_irq_reset(struct v3d_dev *v3d);
400 int v3d_mmu_get_offset(struct drm_file *file_priv, struct v3d_bo *bo,
402 int v3d_mmu_set_page_table(struct v3d_dev *v3d);
403 void v3d_mmu_insert_ptes(struct v3d_bo *bo);
404 void v3d_mmu_remove_ptes(struct v3d_bo *bo);
407 int v3d_sched_init(struct v3d_dev *v3d);
408 void v3d_sched_fini(struct v3d_dev *v3d);
411 void v3d_perfmon_get(struct v3d_perfmon *perfmon);
412 void v3d_perfmon_put(struct v3d_perfmon *perfmon);
413 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon);
414 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon,
416 struct v3d_perfmon *v3d_perfmon_find(struct v3d_file_priv *v3d_priv, int id);
417 void v3d_perfmon_open_file(struct v3d_file_priv *v3d_priv);
418 void v3d_perfmon_close_file(struct v3d_file_priv *v3d_priv);
419 int v3d_perfmon_create_ioctl(struct drm_device *dev, void *data,
420 struct drm_file *file_priv);
421 int v3d_perfmon_destroy_ioctl(struct drm_device *dev, void *data,
422 struct drm_file *file_priv);
423 int v3d_perfmon_get_values_ioctl(struct drm_device *dev, void *data,
424 struct drm_file *file_priv);