drivers/gpu/drm/v3d/v3d_drv.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Copyright (C) 2014-2018 Broadcom */
   3
   4 /**
   5  * DOC: Broadcom V3D Graphics Driver
   6  *
   7  * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs.
   8  * For V3D 2.x support, see the VC4 driver.
   9  *
  10  * The V3D GPU includes a tiled render (composed of a bin and render
  11  * pipelines), the TFU (texture formatting unit), and the CSD (compute
  12  * shader dispatch).
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/device.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/reset.h>
  24
  25 #include <drm/drm_drv.h>
  26 #include <drm/drm_fb_cma_helper.h>
  27 #include <drm/drm_fb_helper.h>
  28 #include <drm/drm_managed.h>
  29 #include <uapi/drm/v3d_drm.h>
  30
  31 #include "v3d_drv.h"
  32 #include "v3d_regs.h"
  33
  34 #define DRIVER_NAME "v3d"
  35 #define DRIVER_DESC "Broadcom V3D graphics"
  36 #define DRIVER_DATE "20180419"
  37 #define DRIVER_MAJOR 1
  38 #define DRIVER_MINOR 0
  39 #define DRIVER_PATCHLEVEL 0
  40
  41 #ifdef CONFIG_PM
  42 static int v3d_runtime_suspend(struct device *dev)
  43 {
  44         struct drm_device *drm = dev_get_drvdata(dev);
  45         struct v3d_dev *v3d = to_v3d_dev(drm);
  46
  47         v3d_irq_disable(v3d);
  48
  49         clk_disable_unprepare(v3d->clk);
  50
  51         return 0;
  52 }
  53
  54 static int v3d_runtime_resume(struct device *dev)
  55 {
  56         struct drm_device *drm = dev_get_drvdata(dev);
  57         struct v3d_dev *v3d = to_v3d_dev(drm);
  58         int ret;
  59
  60         ret = clk_prepare_enable(v3d->clk);
  61         if (ret != 0)
  62                 return ret;
  63
  64         /* XXX: VPM base */
  65
  66         v3d_mmu_set_page_table(v3d);
  67         v3d_irq_enable(v3d);
  68
  69         return 0;
  70 }
  71 #endif
  72
  73 static const struct dev_pm_ops v3d_pm_ops = {
  74         SET_RUNTIME_PM_OPS(v3d_runtime_suspend, v3d_runtime_resume, NULL)
  75 };
  76
  77 static int v3d_get_param_ioctl(struct drm_device *dev, void *data,
  78                                struct drm_file *file_priv)
  79 {
  80         struct v3d_dev *v3d = to_v3d_dev(dev);
  81         struct drm_v3d_get_param *args = data;
  82         static const u32 reg_map[] = {
  83                 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG,
  84                 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1,
  85                 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2,
  86                 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3,
  87                 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0,
  88                 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1,
  89                 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2,
  90         };
  91
  92         if (args->pad != 0)
  93                 return -EINVAL;
  94
  95         /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need
  96          * to explicitly allow it in the "the register in our
  97          * parameter map" check.
  98          */
  99         if (args->param < ARRAY_SIZE(reg_map) &&
 100             (reg_map[args->param] ||
 101              args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) {
 102                 u32 offset = reg_map[args->param];
 103
 104                 if (args->value != 0)
 105                         return -EINVAL;
 106
 107                 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 &&
 108                     args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) {
 109                         args->value = V3D_CORE_READ(0, offset);
 110                 } else {
 111                         args->value = V3D_READ(offset);
 112                 }
 113                 return 0;
 114         }
 115
 116
 117         switch (args->param) {
 118         case DRM_V3D_PARAM_SUPPORTS_TFU:
 119                 args->value = 1;
 120                 return 0;
 121         case DRM_V3D_PARAM_SUPPORTS_CSD:
 122                 args->value = v3d_has_csd(v3d);
 123                 return 0;
 124         case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH:
 125                 args->value = 1;
 126                 return 0;
 127         case DRM_V3D_PARAM_SUPPORTS_PERFMON:
 128                 args->value = (v3d->ver >= 40);
 129                 return 0;
 130         default:
 131                 DRM_DEBUG("Unknown parameter %d\n", args->param);
 132                 return -EINVAL;
 133         }
 134 }
 135
 136 static int
 137 v3d_open(struct drm_device *dev, struct drm_file *file)
 138 {
 139         struct v3d_dev *v3d = to_v3d_dev(dev);
 140         struct v3d_file_priv *v3d_priv;
 141         struct drm_gpu_scheduler *sched;
 142         int i;
 143
 144         v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL);
 145         if (!v3d_priv)
 146                 return -ENOMEM;
 147
 148         v3d_priv->v3d = v3d;
 149
 150         for (i = 0; i < V3D_MAX_QUEUES; i++) {
 151                 sched = &v3d->queue[i].sched;
 152                 drm_sched_entity_init(&v3d_priv->sched_entity[i],
 153                                       DRM_SCHED_PRIORITY_NORMAL, &sched,
 154                                       1, NULL);
 155         }
 156
 157         v3d_perfmon_open_file(v3d_priv);
 158         file->driver_priv = v3d_priv;
 159
 160         return 0;
 161 }
 162
 163 static void
 164 v3d_postclose(struct drm_device *dev, struct drm_file *file)
 165 {
 166         struct v3d_file_priv *v3d_priv = file->driver_priv;
 167         enum v3d_queue q;
 168
 169         for (q = 0; q < V3D_MAX_QUEUES; q++) {
 170                 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]);
 171         }
 172
 173         v3d_perfmon_close_file(v3d_priv);
 174         kfree(v3d_priv);
 175 }
 176
 177 DEFINE_DRM_GEM_FOPS(v3d_drm_fops);
 178
 179 /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP
 180  * protection between clients.  Note that render nodes would be be
 181  * able to submit CLs that could access BOs from clients authenticated
 182  * with the master node.  The TFU doesn't use the GMP, so it would
 183  * need to stay DRM_AUTH until we do buffer size/offset validation.
 184  */
 185 static const struct drm_ioctl_desc v3d_drm_ioctls[] = {
 186         DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
 187         DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW),
 188         DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW),
 189         DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW),
 190         DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW),
 191         DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW),
 192         DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
 193         DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
 194         DRM_IOCTL_DEF_DRV(V3D_PERFMON_CREATE, v3d_perfmon_create_ioctl, DRM_RENDER_ALLOW),
 195         DRM_IOCTL_DEF_DRV(V3D_PERFMON_DESTROY, v3d_perfmon_destroy_ioctl, DRM_RENDER_ALLOW),
 196         DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_VALUES, v3d_perfmon_get_values_ioctl, DRM_RENDER_ALLOW),
 197 };
 198
 199 static const struct drm_driver v3d_drm_driver = {
 200         .driver_features = (DRIVER_GEM |
 201                             DRIVER_RENDER |
 202                             DRIVER_SYNCOBJ),
 203
 204         .open = v3d_open,
 205         .postclose = v3d_postclose,
 206
 207 #if defined(CONFIG_DEBUG_FS)
 208         .debugfs_init = v3d_debugfs_init,
 209 #endif
 210
 211         .gem_create_object = v3d_create_object,
 212         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 213         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 214         .gem_prime_import_sg_table = v3d_prime_import_sg_table,
 215         .gem_prime_mmap = drm_gem_prime_mmap,
 216
 217         .ioctls = v3d_drm_ioctls,
 218         .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls),
 219         .fops = &v3d_drm_fops,
 220
 221         .name = DRIVER_NAME,
 222         .desc = DRIVER_DESC,
 223         .date = DRIVER_DATE,
 224         .major = DRIVER_MAJOR,
 225         .minor = DRIVER_MINOR,
 226         .patchlevel = DRIVER_PATCHLEVEL,
 227 };
 228
 229 static const struct of_device_id v3d_of_match[] = {
 230         { .compatible = "brcm,7268-v3d" },
 231         { .compatible = "brcm,7278-v3d" },
 232         { .compatible = "brcm,2711-v3d" },
 233         {},
 234 };
 235 MODULE_DEVICE_TABLE(of, v3d_of_match);
 236
 237 static int
 238 map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name)
 239 {
 240         struct resource *res =
 241                 platform_get_resource_byname(v3d_to_pdev(v3d), IORESOURCE_MEM, name);
 242
 243         *regs = devm_ioremap_resource(v3d->drm.dev, res);
 244         return PTR_ERR_OR_ZERO(*regs);
 245 }
 246
 247 static int v3d_platform_drm_probe(struct platform_device *pdev)
 248 {
 249         struct device *dev = &pdev->dev;
 250         struct drm_device *drm;
 251         struct v3d_dev *v3d;
 252         int ret;
 253         u32 mmu_debug;
 254         u32 ident1;
 255         u64 mask;
 256
 257
 258         v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm);
 259         if (IS_ERR(v3d))
 260                 return PTR_ERR(v3d);
 261
 262         drm = &v3d->drm;
 263
 264         platform_set_drvdata(pdev, drm);
 265
 266         ret = map_regs(v3d, &v3d->hub_regs, "hub");
 267         if (ret)
 268                 return ret;
 269
 270         ret = map_regs(v3d, &v3d->core_regs[0], "core0");
 271         if (ret)
 272                 return ret;
 273
 274         mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
 275         mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));
 276         ret = dma_set_mask_and_coherent(dev, mask);
 277         if (ret)
 278                 return ret;
 279
 280         v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH);
 281
 282         ident1 = V3D_READ(V3D_HUB_IDENT1);
 283         v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 +
 284                     V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV));
 285         v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
 286         WARN_ON(v3d->cores > 1); /* multicore not yet implemented */
 287
 288         v3d->reset = devm_reset_control_get_exclusive(dev, NULL);
 289         if (IS_ERR(v3d->reset)) {
 290                 ret = PTR_ERR(v3d->reset);
 291
 292                 if (ret == -EPROBE_DEFER)
 293                         return ret;
 294
 295                 v3d->reset = NULL;
 296                 ret = map_regs(v3d, &v3d->bridge_regs, "bridge");
 297                 if (ret) {
 298                         dev_err(dev,
 299                                 "Failed to get reset control or bridge regs\n");
 300                         return ret;
 301                 }
 302         }
 303
 304         v3d->clk = devm_clk_get(dev, NULL);
 305         if (IS_ERR_OR_NULL(v3d->clk)) {
 306                 if (PTR_ERR(v3d->clk) != -EPROBE_DEFER)
 307                         dev_err(dev, "Failed to get clock (%ld)\n", PTR_ERR(v3d->clk));
 308                 return PTR_ERR(v3d->clk);
 309         }
 310         v3d->clk_up_rate = clk_get_max_rate(v3d->clk);
 311         /* For downclocking, drop it to the minimum frequency we can get from
 312          * the CPRMAN clock generator dividing off our parent.  The divider is
 313          * 4 bits, but ask for just higher than that so that rounding doesn't
 314          * make cprman reject our rate.
 315          */
 316         v3d->clk_down_rate =
 317                 (clk_get_rate(clk_get_parent(v3d->clk)) / (1 << 4)) + 10000;
 318
 319         if (v3d->ver < 41) {
 320                 ret = map_regs(v3d, &v3d->gca_regs, "gca");
 321                 if (ret)
 322                         return ret;
 323         }
 324
 325         v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr,
 326                                         GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
 327         if (!v3d->mmu_scratch) {
 328                 dev_err(dev, "Failed to allocate MMU scratch page\n");
 329                 return -ENOMEM;
 330         }
 331
 332
 333         ret = v3d_gem_init(drm);
 334         if (ret)
 335                 goto dma_free;
 336
 337         ret = v3d_irq_init(v3d);
 338         if (ret)
 339                 goto gem_destroy;
 340
 341         ret = drm_dev_register(drm, 0);
 342         if (ret)
 343                 goto irq_disable;
 344
 345         ret = clk_set_min_rate(v3d->clk, v3d->clk_down_rate);
 346         WARN_ON_ONCE(ret != 0);
 347
 348         return 0;
 349
 350 irq_disable:
 351         v3d_irq_disable(v3d);
 352 gem_destroy:
 353         v3d_gem_destroy(drm);
 354 dma_free:
 355         dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr);
 356         return ret;
 357 }
 358
 359 static int v3d_platform_drm_remove(struct platform_device *pdev)
 360 {
 361         struct drm_device *drm = platform_get_drvdata(pdev);
 362         struct v3d_dev *v3d = to_v3d_dev(drm);
 363
 364         drm_dev_unregister(drm);
 365
 366         v3d_gem_destroy(drm);
 367
 368         dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch,
 369                     v3d->mmu_scratch_paddr);
 370
 371         return 0;
 372 }
 373
 374 static struct platform_driver v3d_platform_driver = {
 375         .probe          = v3d_platform_drm_probe,
 376         .remove         = v3d_platform_drm_remove,
 377         .driver         = {
 378                 .name   = "v3d",
 379                 .of_match_table = v3d_of_match,
 380                 .pm = &v3d_pm_ops,
 381         },
 382 };
 383
 384 module_platform_driver(v3d_platform_driver);
 385
 386 MODULE_ALIAS("platform:v3d-drm");
 387 MODULE_DESCRIPTION("Broadcom V3D DRM Driver");
 388 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
 389 MODULE_LICENSE("GPL v2");