drivers/gpu/drm/v3d/v3d_drv.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Copyright (C) 2014-2018 Broadcom */
   3
   4 /**
   5  * DOC: Broadcom V3D Graphics Driver
   6  *
   7  * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs.
   8  * For V3D 2.x support, see the VC4 driver.
   9  *
  10  * The V3D GPU includes a tiled render (composed of a bin and render
  11  * pipelines), the TFU (texture formatting unit), and the CSD (compute
  12  * shader dispatch).
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/device.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/reset.h>
  23 #include <drm/drm_fb_cma_helper.h>
  24 #include <drm/drm_fb_helper.h>
  25
  26 #include "uapi/drm/v3d_drm.h"
  27 #include "v3d_drv.h"
  28 #include "v3d_regs.h"
  29
  30 #define DRIVER_NAME "v3d"
  31 #define DRIVER_DESC "Broadcom V3D graphics"
  32 #define DRIVER_DATE "20180419"
  33 #define DRIVER_MAJOR 1
  34 #define DRIVER_MINOR 0
  35 #define DRIVER_PATCHLEVEL 0
  36
  37 #ifdef CONFIG_PM
  38 static int v3d_runtime_suspend(struct device *dev)
  39 {
  40         struct drm_device *drm = dev_get_drvdata(dev);
  41         struct v3d_dev *v3d = to_v3d_dev(drm);
  42
  43         v3d_irq_disable(v3d);
  44
  45         clk_disable_unprepare(v3d->clk);
  46
  47         return 0;
  48 }
  49
  50 static int v3d_runtime_resume(struct device *dev)
  51 {
  52         struct drm_device *drm = dev_get_drvdata(dev);
  53         struct v3d_dev *v3d = to_v3d_dev(drm);
  54         int ret;
  55
  56         ret = clk_prepare_enable(v3d->clk);
  57         if (ret != 0)
  58                 return ret;
  59
  60         /* XXX: VPM base */
  61
  62         v3d_mmu_set_page_table(v3d);
  63         v3d_irq_enable(v3d);
  64
  65         return 0;
  66 }
  67 #endif
  68
  69 static const struct dev_pm_ops v3d_pm_ops = {
  70         SET_RUNTIME_PM_OPS(v3d_runtime_suspend, v3d_runtime_resume, NULL)
  71 };
  72
  73 static int v3d_get_param_ioctl(struct drm_device *dev, void *data,
  74                                struct drm_file *file_priv)
  75 {
  76         struct v3d_dev *v3d = to_v3d_dev(dev);
  77         struct drm_v3d_get_param *args = data;
  78         static const u32 reg_map[] = {
  79                 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG,
  80                 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1,
  81                 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2,
  82                 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3,
  83                 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0,
  84                 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1,
  85                 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2,
  86         };
  87
  88         if (args->pad != 0)
  89                 return -EINVAL;
  90
  91         /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need
  92          * to explicitly allow it in the "the register in our
  93          * parameter map" check.
  94          */
  95         if (args->param < ARRAY_SIZE(reg_map) &&
  96             (reg_map[args->param] ||
  97              args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) {
  98                 u32 offset = reg_map[args->param];
  99
 100                 if (args->value != 0)
 101                         return -EINVAL;
 102
 103                 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 &&
 104                     args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) {
 105                         args->value = V3D_CORE_READ(0, offset);
 106                 } else {
 107                         args->value = V3D_READ(offset);
 108                 }
 109                 return 0;
 110         }
 111
 112
 113         switch (args->param) {
 114         case DRM_V3D_PARAM_SUPPORTS_TFU:
 115                 args->value = 1;
 116                 return 0;
 117         case DRM_V3D_PARAM_SUPPORTS_CSD:
 118                 args->value = v3d_has_csd(v3d);
 119                 return 0;
 120         case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH:
 121                 args->value = 1;
 122                 return 0;
 123         default:
 124                 DRM_DEBUG("Unknown parameter %d\n", args->param);
 125                 return -EINVAL;
 126         }
 127 }
 128
 129 static int
 130 v3d_open(struct drm_device *dev, struct drm_file *file)
 131 {
 132         struct v3d_dev *v3d = to_v3d_dev(dev);
 133         struct v3d_file_priv *v3d_priv;
 134         struct drm_sched_rq *rq;
 135         int i;
 136
 137         v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL);
 138         if (!v3d_priv)
 139                 return -ENOMEM;
 140
 141         v3d_priv->v3d = v3d;
 142
 143         for (i = 0; i < V3D_MAX_QUEUES; i++) {
 144                 rq = &v3d->queue[i].sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
 145                 drm_sched_entity_init(&v3d_priv->sched_entity[i], &rq, 1, NULL);
 146         }
 147
 148         file->driver_priv = v3d_priv;
 149
 150         return 0;
 151 }
 152
 153 static void
 154 v3d_postclose(struct drm_device *dev, struct drm_file *file)
 155 {
 156         struct v3d_file_priv *v3d_priv = file->driver_priv;
 157         enum v3d_queue q;
 158
 159         for (q = 0; q < V3D_MAX_QUEUES; q++) {
 160                 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]);
 161         }
 162
 163         kfree(v3d_priv);
 164 }
 165
 166 static const struct file_operations v3d_drm_fops = {
 167         .owner = THIS_MODULE,
 168         .open = drm_open,
 169         .release = drm_release,
 170         .unlocked_ioctl = drm_ioctl,
 171         .mmap = v3d_mmap,
 172         .poll = drm_poll,
 173         .read = drm_read,
 174         .compat_ioctl = drm_compat_ioctl,
 175         .llseek = noop_llseek,
 176 };
 177
 178 /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP
 179  * protection between clients.  Note that render nodes would be be
 180  * able to submit CLs that could access BOs from clients authenticated
 181  * with the master node.  The TFU doesn't use the GMP, so it would
 182  * need to stay DRM_AUTH until we do buffer size/offset validation.
 183  */
 184 static const struct drm_ioctl_desc v3d_drm_ioctls[] = {
 185         DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
 186         DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW),
 187         DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW),
 188         DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW),
 189         DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW),
 190         DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW),
 191         DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
 192         DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
 193 };
 194
 195 static const struct vm_operations_struct v3d_vm_ops = {
 196         .fault = v3d_gem_fault,
 197         .open = drm_gem_vm_open,
 198         .close = drm_gem_vm_close,
 199 };
 200
 201 static struct drm_driver v3d_drm_driver = {
 202         .driver_features = (DRIVER_GEM |
 203                             DRIVER_RENDER |
 204                             DRIVER_PRIME |
 205                             DRIVER_SYNCOBJ),
 206
 207         .open = v3d_open,
 208         .postclose = v3d_postclose,
 209
 210 #if defined(CONFIG_DEBUG_FS)
 211         .debugfs_init = v3d_debugfs_init,
 212 #endif
 213
 214         .gem_free_object_unlocked = v3d_free_object,
 215         .gem_vm_ops = &v3d_vm_ops,
 216
 217         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 218         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 219         .gem_prime_import = drm_gem_prime_import,
 220         .gem_prime_export = drm_gem_prime_export,
 221         .gem_prime_res_obj = v3d_prime_res_obj,
 222         .gem_prime_get_sg_table = v3d_prime_get_sg_table,
 223         .gem_prime_import_sg_table = v3d_prime_import_sg_table,
 224         .gem_prime_mmap = v3d_prime_mmap,
 225
 226         .ioctls = v3d_drm_ioctls,
 227         .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls),
 228         .fops = &v3d_drm_fops,
 229
 230         .name = DRIVER_NAME,
 231         .desc = DRIVER_DESC,
 232         .date = DRIVER_DATE,
 233         .major = DRIVER_MAJOR,
 234         .minor = DRIVER_MINOR,
 235         .patchlevel = DRIVER_PATCHLEVEL,
 236 };
 237
 238 static const struct of_device_id v3d_of_match[] = {
 239         { .compatible = "brcm,7268-v3d" },
 240         { .compatible = "brcm,7278-v3d" },
 241         { .compatible = "brcm,2711-v3d" },
 242         {},
 243 };
 244 MODULE_DEVICE_TABLE(of, v3d_of_match);
 245
 246 static int
 247 map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name)
 248 {
 249         struct resource *res =
 250                 platform_get_resource_byname(v3d->pdev, IORESOURCE_MEM, name);
 251
 252         *regs = devm_ioremap_resource(v3d->dev, res);
 253         return PTR_ERR_OR_ZERO(*regs);
 254 }
 255
 256 static int v3d_platform_drm_probe(struct platform_device *pdev)
 257 {
 258         struct device *dev = &pdev->dev;
 259         struct drm_device *drm;
 260         struct v3d_dev *v3d;
 261         int ret;
 262         u32 ident1;
 263
 264         dev->coherent_dma_mask = DMA_BIT_MASK(36);
 265
 266         v3d = kzalloc(sizeof(*v3d), GFP_KERNEL);
 267         if (!v3d)
 268                 return -ENOMEM;
 269         v3d->dev = dev;
 270         v3d->pdev = pdev;
 271         drm = &v3d->drm;
 272
 273         ret = map_regs(v3d, &v3d->hub_regs, "hub");
 274         if (ret)
 275                 goto dev_free;
 276
 277         ret = map_regs(v3d, &v3d->core_regs[0], "core0");
 278         if (ret)
 279                 goto dev_free;
 280
 281         ident1 = V3D_READ(V3D_HUB_IDENT1);
 282         v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 +
 283                     V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV));
 284         v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
 285         WARN_ON(v3d->cores > 1); /* multicore not yet implemented */
 286
 287         v3d->reset = devm_reset_control_get_exclusive(dev, NULL);
 288         if (IS_ERR(v3d->reset)) {
 289                 ret = PTR_ERR(v3d->reset);
 290
 291                 if (ret == -EPROBE_DEFER)
 292                         goto dev_free;
 293
 294                 v3d->reset = NULL;
 295                 ret = map_regs(v3d, &v3d->bridge_regs, "bridge");
 296                 if (ret) {
 297                         dev_err(dev,
 298                                 "Failed to get reset control or bridge regs\n");
 299                         goto dev_free;
 300                 }
 301         }
 302
 303         v3d->clk = devm_clk_get(dev, NULL);
 304         if (IS_ERR(v3d->clk)) {
 305                 if (ret != -EPROBE_DEFER)
 306                         dev_err(dev, "Failed to get clock\n");
 307                 goto dev_free;
 308         }
 309         v3d->clk_up_rate = clk_get_rate(v3d->clk);
 310         /* For downclocking, drop it to the minimum frequency we can get from
 311          * the CPRMAN clock generator dividing off our parent.  The divider is
 312          * 4 bits, but ask for just higher than that so that rounding doesn't
 313          * make cprman reject our rate.
 314          */
 315         v3d->clk_down_rate =
 316                 (clk_get_rate(clk_get_parent(v3d->clk)) / (1 << 4)) + 10000;
 317
 318         if (v3d->ver < 41) {
 319                 ret = map_regs(v3d, &v3d->gca_regs, "gca");
 320                 if (ret)
 321                         goto dev_free;
 322         }
 323
 324         v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr,
 325                                         GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
 326         if (!v3d->mmu_scratch) {
 327                 dev_err(dev, "Failed to allocate MMU scratch page\n");
 328                 ret = -ENOMEM;
 329                 goto dev_free;
 330         }
 331
 332
 333         ret = drm_dev_init(&v3d->drm, &v3d_drm_driver, dev);
 334         if (ret)
 335                 goto dma_free;
 336
 337         platform_set_drvdata(pdev, drm);
 338         drm->dev_private = v3d;
 339
 340         ret = v3d_gem_init(drm);
 341         if (ret)
 342                 goto dev_destroy;
 343
 344         ret = v3d_irq_init(v3d);
 345         if (ret)
 346                 goto gem_destroy;
 347
 348         ret = drm_dev_register(drm, 0);
 349         if (ret)
 350                 goto irq_disable;
 351
 352         ret = clk_set_rate(v3d->clk, v3d->clk_down_rate);
 353         WARN_ON_ONCE(ret != 0);
 354
 355         return 0;
 356
 357 irq_disable:
 358         v3d_irq_disable(v3d);
 359 gem_destroy:
 360         v3d_gem_destroy(drm);
 361 dev_destroy:
 362         drm_dev_put(drm);
 363 dma_free:
 364         dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr);
 365 dev_free:
 366         kfree(v3d);
 367         return ret;
 368 }
 369
 370 static int v3d_platform_drm_remove(struct platform_device *pdev)
 371 {
 372         struct drm_device *drm = platform_get_drvdata(pdev);
 373         struct v3d_dev *v3d = to_v3d_dev(drm);
 374
 375         drm_dev_unregister(drm);
 376
 377         v3d_gem_destroy(drm);
 378
 379         drm_dev_put(drm);
 380
 381         dma_free_wc(v3d->dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr);
 382
 383         return 0;
 384 }
 385
 386 static struct platform_driver v3d_platform_driver = {
 387         .probe          = v3d_platform_drm_probe,
 388         .remove         = v3d_platform_drm_remove,
 389         .driver         = {
 390                 .name   = "v3d",
 391                 .of_match_table = v3d_of_match,
 392                 .pm = &v3d_pm_ops,
 393         },
 394 };
 395
 396 static int __init v3d_drm_register(void)
 397 {
 398         return platform_driver_register(&v3d_platform_driver);
 399 }
 400
 401 static void __exit v3d_drm_unregister(void)
 402 {
 403         platform_driver_unregister(&v3d_platform_driver);
 404 }
 405
 406 module_init(v3d_drm_register);
 407 module_exit(v3d_drm_unregister);
 408
 409 MODULE_ALIAS("platform:v3d-drm");
 410 MODULE_DESCRIPTION("Broadcom V3D DRM Driver");
 411 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
 412 MODULE_LICENSE("GPL v2");