drivers/gpu/drm/v3d/v3d_drv.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Copyright (C) 2014-2018 Broadcom */
   3
   4 /**
   5  * DOC: Broadcom V3D Graphics Driver
   6  *
   7  * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs.
   8  * For V3D 2.x support, see the VC4 driver.
   9  *
  10  * The V3D GPU includes a tiled render (composed of a bin and render
  11  * pipelines), the TFU (texture formatting unit), and the CSD (compute
  12  * shader dispatch).
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/device.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/reset.h>
  24
  25 #include <drm/drm_drv.h>
  26 #include <drm/drm_fb_cma_helper.h>
  27 #include <drm/drm_fb_helper.h>
  28 #include <drm/drm_managed.h>
  29 #include <uapi/drm/v3d_drm.h>
  30
  31 #include "v3d_drv.h"
  32 #include "v3d_regs.h"
  33
  34 #define DRIVER_NAME "v3d"
  35 #define DRIVER_DESC "Broadcom V3D graphics"
  36 #define DRIVER_DATE "20180419"
  37 #define DRIVER_MAJOR 1
  38 #define DRIVER_MINOR 0
  39 #define DRIVER_PATCHLEVEL 0
  40
  41 #ifdef CONFIG_PM
  42 static int v3d_runtime_suspend(struct device *dev)
  43 {
  44         struct drm_device *drm = dev_get_drvdata(dev);
  45         struct v3d_dev *v3d = to_v3d_dev(drm);
  46
  47         v3d_irq_disable(v3d);
  48
  49         clk_disable_unprepare(v3d->clk);
  50
  51         return 0;
  52 }
  53
  54 static int v3d_runtime_resume(struct device *dev)
  55 {
  56         struct drm_device *drm = dev_get_drvdata(dev);
  57         struct v3d_dev *v3d = to_v3d_dev(drm);
  58         int ret;
  59
  60         ret = clk_prepare_enable(v3d->clk);
  61         if (ret != 0)
  62                 return ret;
  63
  64         /* XXX: VPM base */
  65
  66         v3d_mmu_set_page_table(v3d);
  67         v3d_irq_enable(v3d);
  68
  69         return 0;
  70 }
  71 #endif
  72
  73 static const struct dev_pm_ops v3d_pm_ops = {
  74         SET_RUNTIME_PM_OPS(v3d_runtime_suspend, v3d_runtime_resume, NULL)
  75 };
  76
  77 static int v3d_get_param_ioctl(struct drm_device *dev, void *data,
  78                                struct drm_file *file_priv)
  79 {
  80         struct v3d_dev *v3d = to_v3d_dev(dev);
  81         struct drm_v3d_get_param *args = data;
  82         static const u32 reg_map[] = {
  83                 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG,
  84                 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1,
  85                 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2,
  86                 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3,
  87                 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0,
  88                 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1,
  89                 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2,
  90         };
  91
  92         if (args->pad != 0)
  93                 return -EINVAL;
  94
  95         /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need
  96          * to explicitly allow it in the "the register in our
  97          * parameter map" check.
  98          */
  99         if (args->param < ARRAY_SIZE(reg_map) &&
 100             (reg_map[args->param] ||
 101              args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) {
 102                 u32 offset = reg_map[args->param];
 103
 104                 if (args->value != 0)
 105                         return -EINVAL;
 106
 107                 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 &&
 108                     args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) {
 109                         args->value = V3D_CORE_READ(0, offset);
 110                 } else {
 111                         args->value = V3D_READ(offset);
 112                 }
 113                 return 0;
 114         }
 115
 116
 117         switch (args->param) {
 118         case DRM_V3D_PARAM_SUPPORTS_TFU:
 119                 args->value = 1;
 120                 return 0;
 121         case DRM_V3D_PARAM_SUPPORTS_CSD:
 122                 args->value = v3d_has_csd(v3d);
 123                 return 0;
 124         case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH:
 125                 args->value = 1;
 126                 return 0;
 127         default:
 128                 DRM_DEBUG("Unknown parameter %d\n", args->param);
 129                 return -EINVAL;
 130         }
 131 }
 132
 133 static int
 134 v3d_open(struct drm_device *dev, struct drm_file *file)
 135 {
 136         struct v3d_dev *v3d = to_v3d_dev(dev);
 137         struct v3d_file_priv *v3d_priv;
 138         struct drm_gpu_scheduler *sched;
 139         int i;
 140
 141         v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL);
 142         if (!v3d_priv)
 143                 return -ENOMEM;
 144
 145         v3d_priv->v3d = v3d;
 146
 147         for (i = 0; i < V3D_MAX_QUEUES; i++) {
 148                 sched = &v3d->queue[i].sched;
 149                 drm_sched_entity_init(&v3d_priv->sched_entity[i],
 150                                       DRM_SCHED_PRIORITY_NORMAL, &sched,
 151                                       1, NULL);
 152         }
 153
 154         file->driver_priv = v3d_priv;
 155
 156         return 0;
 157 }
 158
 159 static void
 160 v3d_postclose(struct drm_device *dev, struct drm_file *file)
 161 {
 162         struct v3d_file_priv *v3d_priv = file->driver_priv;
 163         enum v3d_queue q;
 164
 165         for (q = 0; q < V3D_MAX_QUEUES; q++) {
 166                 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]);
 167         }
 168
 169         kfree(v3d_priv);
 170 }
 171
 172 DEFINE_DRM_GEM_FOPS(v3d_drm_fops);
 173
 174 /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP
 175  * protection between clients.  Note that render nodes would be be
 176  * able to submit CLs that could access BOs from clients authenticated
 177  * with the master node.  The TFU doesn't use the GMP, so it would
 178  * need to stay DRM_AUTH until we do buffer size/offset validation.
 179  */
 180 static const struct drm_ioctl_desc v3d_drm_ioctls[] = {
 181         DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
 182         DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW),
 183         DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW),
 184         DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW),
 185         DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW),
 186         DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW),
 187         DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
 188         DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
 189 };
 190
 191 static struct drm_driver v3d_drm_driver = {
 192         .driver_features = (DRIVER_GEM |
 193                             DRIVER_RENDER |
 194                             DRIVER_SYNCOBJ),
 195
 196         .open = v3d_open,
 197         .postclose = v3d_postclose,
 198
 199 #if defined(CONFIG_DEBUG_FS)
 200         .debugfs_init = v3d_debugfs_init,
 201 #endif
 202
 203         .gem_create_object = v3d_create_object,
 204         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 205         .prime_fd_to_handle = v3d_drm_gem_prime_fd_to_handle,
 206         .gem_prime_import_sg_table = v3d_prime_import_sg_table,
 207         .gem_prime_mmap = drm_gem_prime_mmap,
 208
 209         .ioctls = v3d_drm_ioctls,
 210         .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls),
 211         .fops = &v3d_drm_fops,
 212
 213         .name = DRIVER_NAME,
 214         .desc = DRIVER_DESC,
 215         .date = DRIVER_DATE,
 216         .major = DRIVER_MAJOR,
 217         .minor = DRIVER_MINOR,
 218         .patchlevel = DRIVER_PATCHLEVEL,
 219 };
 220
 221 static const struct of_device_id v3d_of_match[] = {
 222         { .compatible = "brcm,7268-v3d" },
 223         { .compatible = "brcm,7278-v3d" },
 224         { .compatible = "brcm,2711-v3d" },
 225         {},
 226 };
 227 MODULE_DEVICE_TABLE(of, v3d_of_match);
 228
 229 static int
 230 map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name)
 231 {
 232         struct resource *res =
 233                 platform_get_resource_byname(v3d_to_pdev(v3d), IORESOURCE_MEM, name);
 234
 235         *regs = devm_ioremap_resource(v3d->drm.dev, res);
 236         return PTR_ERR_OR_ZERO(*regs);
 237 }
 238
 239 static int v3d_platform_drm_probe(struct platform_device *pdev)
 240 {
 241         struct device *dev = &pdev->dev;
 242         struct drm_device *drm;
 243         struct v3d_dev *v3d;
 244         int ret;
 245         u32 mmu_debug;
 246         u32 ident1;
 247
 248
 249         v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm);
 250         if (IS_ERR(v3d))
 251                 return PTR_ERR(v3d);
 252
 253         drm = &v3d->drm;
 254
 255         platform_set_drvdata(pdev, drm);
 256
 257         ret = map_regs(v3d, &v3d->hub_regs, "hub");
 258         if (ret)
 259                 return ret;
 260
 261         ret = map_regs(v3d, &v3d->core_regs[0], "core0");
 262         if (ret)
 263                 return ret;
 264
 265         mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
 266         dma_set_mask_and_coherent(dev,
 267                 DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH)));
 268         v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH);
 269
 270         ident1 = V3D_READ(V3D_HUB_IDENT1);
 271         v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 +
 272                     V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV));
 273         v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
 274         WARN_ON(v3d->cores > 1); /* multicore not yet implemented */
 275
 276         v3d->reset = devm_reset_control_get_exclusive(dev, NULL);
 277         if (IS_ERR(v3d->reset)) {
 278                 ret = PTR_ERR(v3d->reset);
 279
 280                 if (ret == -EPROBE_DEFER)
 281                         return ret;
 282
 283                 v3d->reset = NULL;
 284                 ret = map_regs(v3d, &v3d->bridge_regs, "bridge");
 285                 if (ret) {
 286                         dev_err(dev,
 287                                 "Failed to get reset control or bridge regs\n");
 288                         return ret;
 289                 }
 290         }
 291
 292         v3d->clk = devm_clk_get(dev, NULL);
 293         if (IS_ERR_OR_NULL(v3d->clk)) {
 294                 if (PTR_ERR(v3d->clk) != -EPROBE_DEFER)
 295                         dev_err(dev, "Failed to get clock (%ld)\n", PTR_ERR(v3d->clk));
 296                 return PTR_ERR(v3d->clk);
 297         }
 298         v3d->clk_up_rate = clk_get_rate(v3d->clk);
 299         /* For downclocking, drop it to the minimum frequency we can get from
 300          * the CPRMAN clock generator dividing off our parent.  The divider is
 301          * 4 bits, but ask for just higher than that so that rounding doesn't
 302          * make cprman reject our rate.
 303          */
 304         v3d->clk_down_rate =
 305                 (clk_get_rate(clk_get_parent(v3d->clk)) / (1 << 4)) + 10000;
 306
 307         if (v3d->ver < 41) {
 308                 ret = map_regs(v3d, &v3d->gca_regs, "gca");
 309                 if (ret)
 310                         return ret;
 311         }
 312
 313         v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr,
 314                                         GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
 315         if (!v3d->mmu_scratch) {
 316                 dev_err(dev, "Failed to allocate MMU scratch page\n");
 317                 return -ENOMEM;
 318         }
 319
 320
 321         ret = v3d_gem_init(drm);
 322         if (ret)
 323                 goto dma_free;
 324
 325         ret = v3d_irq_init(v3d);
 326         if (ret)
 327                 goto gem_destroy;
 328
 329         ret = drm_dev_register(drm, 0);
 330         if (ret)
 331                 goto irq_disable;
 332
 333         ret = clk_set_rate(v3d->clk, v3d->clk_down_rate);
 334         WARN_ON_ONCE(ret != 0);
 335
 336         return 0;
 337
 338 irq_disable:
 339         v3d_irq_disable(v3d);
 340 gem_destroy:
 341         v3d_gem_destroy(drm);
 342 dma_free:
 343         dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr);
 344         return ret;
 345 }
 346
 347 static int v3d_platform_drm_remove(struct platform_device *pdev)
 348 {
 349         struct drm_device *drm = platform_get_drvdata(pdev);
 350         struct v3d_dev *v3d = to_v3d_dev(drm);
 351
 352         drm_dev_unregister(drm);
 353
 354         v3d_gem_destroy(drm);
 355
 356         dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch,
 357                     v3d->mmu_scratch_paddr);
 358
 359         return 0;
 360 }
 361
 362 static struct platform_driver v3d_platform_driver = {
 363         .probe          = v3d_platform_drm_probe,
 364         .remove         = v3d_platform_drm_remove,
 365         .driver         = {
 366                 .name   = "v3d",
 367                 .of_match_table = v3d_of_match,
 368                 .pm = &v3d_pm_ops,
 369         },
 370 };
 371
 372 module_platform_driver(v3d_platform_driver);
 373
 374 MODULE_ALIAS("platform:v3d-drm");
 375 MODULE_DESCRIPTION("Broadcom V3D DRM Driver");
 376 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
 377 MODULE_LICENSE("GPL v2");