drivers/gpu/drm/v3d/v3d_debugfs.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Copyright (C) 2014-2018 Broadcom */
   3
   4 #include <linux/circ_buf.h>
   5 #include <linux/ctype.h>
   6 #include <linux/debugfs.h>
   7 #include <linux/seq_file.h>
   8
   9 #include <drm/drm_debugfs.h>
  10
  11 #include "v3d_drv.h"
  12 #include "v3d_regs.h"
  13
  14 #define REGDEF(reg) { reg, #reg }
  15 struct v3d_reg_def {
  16         u32 reg;
  17         const char *name;
  18 };
  19
  20 static const struct v3d_reg_def v3d_hub_reg_defs[] = {
  21         REGDEF(V3D_HUB_AXICFG),
  22         REGDEF(V3D_HUB_UIFCFG),
  23         REGDEF(V3D_HUB_IDENT0),
  24         REGDEF(V3D_HUB_IDENT1),
  25         REGDEF(V3D_HUB_IDENT2),
  26         REGDEF(V3D_HUB_IDENT3),
  27         REGDEF(V3D_HUB_INT_STS),
  28         REGDEF(V3D_HUB_INT_MSK_STS),
  29
  30         REGDEF(V3D_MMU_CTL),
  31         REGDEF(V3D_MMU_VIO_ADDR),
  32         REGDEF(V3D_MMU_VIO_ID),
  33         REGDEF(V3D_MMU_DEBUG_INFO),
  34 };
  35
  36 static const struct v3d_reg_def v3d_gca_reg_defs[] = {
  37         REGDEF(V3D_GCA_SAFE_SHUTDOWN),
  38         REGDEF(V3D_GCA_SAFE_SHUTDOWN_ACK),
  39 };
  40
  41 static const struct v3d_reg_def v3d_core_reg_defs[] = {
  42         REGDEF(V3D_CTL_IDENT0),
  43         REGDEF(V3D_CTL_IDENT1),
  44         REGDEF(V3D_CTL_IDENT2),
  45         REGDEF(V3D_CTL_MISCCFG),
  46         REGDEF(V3D_CTL_INT_STS),
  47         REGDEF(V3D_CTL_INT_MSK_STS),
  48         REGDEF(V3D_CLE_CT0CS),
  49         REGDEF(V3D_CLE_CT0CA),
  50         REGDEF(V3D_CLE_CT0EA),
  51         REGDEF(V3D_CLE_CT1CS),
  52         REGDEF(V3D_CLE_CT1CA),
  53         REGDEF(V3D_CLE_CT1EA),
  54
  55         REGDEF(V3D_PTB_BPCA),
  56         REGDEF(V3D_PTB_BPCS),
  57
  58         REGDEF(V3D_GMP_STATUS),
  59         REGDEF(V3D_GMP_CFG),
  60         REGDEF(V3D_GMP_VIO_ADDR),
  61
  62         REGDEF(V3D_ERR_FDBGO),
  63         REGDEF(V3D_ERR_FDBGB),
  64         REGDEF(V3D_ERR_FDBGS),
  65         REGDEF(V3D_ERR_STAT),
  66 };
  67
  68 static const struct v3d_reg_def v3d_csd_reg_defs[] = {
  69         REGDEF(V3D_CSD_STATUS),
  70         REGDEF(V3D_CSD_CURRENT_CFG0),
  71         REGDEF(V3D_CSD_CURRENT_CFG1),
  72         REGDEF(V3D_CSD_CURRENT_CFG2),
  73         REGDEF(V3D_CSD_CURRENT_CFG3),
  74         REGDEF(V3D_CSD_CURRENT_CFG4),
  75         REGDEF(V3D_CSD_CURRENT_CFG5),
  76         REGDEF(V3D_CSD_CURRENT_CFG6),
  77 };
  78
  79 static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused)
  80 {
  81         struct drm_info_node *node = (struct drm_info_node *)m->private;
  82         struct drm_device *dev = node->minor->dev;
  83         struct v3d_dev *v3d = to_v3d_dev(dev);
  84         int i, core;
  85
  86         for (i = 0; i < ARRAY_SIZE(v3d_hub_reg_defs); i++) {
  87                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
  88                            v3d_hub_reg_defs[i].name, v3d_hub_reg_defs[i].reg,
  89                            V3D_READ(v3d_hub_reg_defs[i].reg));
  90         }
  91
  92         if (v3d->ver < 41) {
  93                 for (i = 0; i < ARRAY_SIZE(v3d_gca_reg_defs); i++) {
  94                         seq_printf(m, "%s (0x%04x): 0x%08x\n",
  95                                    v3d_gca_reg_defs[i].name,
  96                                    v3d_gca_reg_defs[i].reg,
  97                                    V3D_GCA_READ(v3d_gca_reg_defs[i].reg));
  98                 }
  99         }
 100
 101         for (core = 0; core < v3d->cores; core++) {
 102                 for (i = 0; i < ARRAY_SIZE(v3d_core_reg_defs); i++) {
 103                         seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
 104                                    core,
 105                                    v3d_core_reg_defs[i].name,
 106                                    v3d_core_reg_defs[i].reg,
 107                                    V3D_CORE_READ(core,
 108                                                  v3d_core_reg_defs[i].reg));
 109                 }
 110
 111                 if (v3d_has_csd(v3d)) {
 112                         for (i = 0; i < ARRAY_SIZE(v3d_csd_reg_defs); i++) {
 113                                 seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
 114                                            core,
 115                                            v3d_csd_reg_defs[i].name,
 116                                            v3d_csd_reg_defs[i].reg,
 117                                            V3D_CORE_READ(core,
 118                                                          v3d_csd_reg_defs[i].reg));
 119                         }
 120                 }
 121         }
 122
 123         return 0;
 124 }
 125
 126 static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused)
 127 {
 128         struct drm_info_node *node = (struct drm_info_node *)m->private;
 129         struct drm_device *dev = node->minor->dev;
 130         struct v3d_dev *v3d = to_v3d_dev(dev);
 131         u32 ident0, ident1, ident2, ident3, cores;
 132         int core;
 133
 134
 135         ident0 = V3D_READ(V3D_HUB_IDENT0);
 136         ident1 = V3D_READ(V3D_HUB_IDENT1);
 137         ident2 = V3D_READ(V3D_HUB_IDENT2);
 138         ident3 = V3D_READ(V3D_HUB_IDENT3);
 139         cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
 140
 141         seq_printf(m, "Revision:   %d.%d.%d.%d\n",
 142                    V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER),
 143                    V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV),
 144                    V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPREV),
 145                    V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPIDX));
 146         seq_printf(m, "MMU:        %s\n",
 147                    (ident2 & V3D_HUB_IDENT2_WITH_MMU) ? "yes" : "no");
 148         seq_printf(m, "TFU:        %s\n",
 149                    (ident1 & V3D_HUB_IDENT1_WITH_TFU) ? "yes" : "no");
 150         seq_printf(m, "TSY:        %s\n",
 151                    (ident1 & V3D_HUB_IDENT1_WITH_TSY) ? "yes" : "no");
 152         seq_printf(m, "MSO:        %s\n",
 153                    (ident1 & V3D_HUB_IDENT1_WITH_MSO) ? "yes" : "no");
 154         seq_printf(m, "L3C:        %s (%dkb)\n",
 155                    (ident1 & V3D_HUB_IDENT1_WITH_L3C) ? "yes" : "no",
 156                    V3D_GET_FIELD(ident2, V3D_HUB_IDENT2_L3C_NKB));
 157
 158         for (core = 0; core < cores; core++) {
 159                 u32 misccfg;
 160                 u32 nslc, ntmu, qups;
 161
 162                 ident0 = V3D_CORE_READ(core, V3D_CTL_IDENT0);
 163                 ident1 = V3D_CORE_READ(core, V3D_CTL_IDENT1);
 164                 ident2 = V3D_CORE_READ(core, V3D_CTL_IDENT2);
 165                 misccfg = V3D_CORE_READ(core, V3D_CTL_MISCCFG);
 166
 167                 nslc = V3D_GET_FIELD(ident1, V3D_IDENT1_NSLC);
 168                 ntmu = V3D_GET_FIELD(ident1, V3D_IDENT1_NTMU);
 169                 qups = V3D_GET_FIELD(ident1, V3D_IDENT1_QUPS);
 170
 171                 seq_printf(m, "Core %d:\n", core);
 172                 seq_printf(m, "  Revision:     %d.%d\n",
 173                            V3D_GET_FIELD(ident0, V3D_IDENT0_VER),
 174                            V3D_GET_FIELD(ident1, V3D_IDENT1_REV));
 175                 seq_printf(m, "  Slices:       %d\n", nslc);
 176                 seq_printf(m, "  TMUs:         %d\n", nslc * ntmu);
 177                 seq_printf(m, "  QPUs:         %d\n", nslc * qups);
 178                 seq_printf(m, "  Semaphores:   %d\n",
 179                            V3D_GET_FIELD(ident1, V3D_IDENT1_NSEM));
 180                 seq_printf(m, "  BCG int:      %d\n",
 181                            (ident2 & V3D_IDENT2_BCG_INT) != 0);
 182                 seq_printf(m, "  Override TMU: %d\n",
 183                            (misccfg & V3D_MISCCFG_OVRTMUOUT) != 0);
 184         }
 185
 186         return 0;
 187 }
 188
 189 static int v3d_debugfs_bo_stats(struct seq_file *m, void *unused)
 190 {
 191         struct drm_info_node *node = (struct drm_info_node *)m->private;
 192         struct drm_device *dev = node->minor->dev;
 193         struct v3d_dev *v3d = to_v3d_dev(dev);
 194
 195         mutex_lock(&v3d->bo_lock);
 196         seq_printf(m, "allocated bos:          %d\n",
 197                    v3d->bo_stats.num_allocated);
 198         seq_printf(m, "allocated bo size (kb): %ld\n",
 199                    (long)v3d->bo_stats.pages_allocated << (PAGE_SHIFT - 10));
 200         mutex_unlock(&v3d->bo_lock);
 201
 202         return 0;
 203 }
 204
 205 static int v3d_measure_clock(struct seq_file *m, void *unused)
 206 {
 207         struct drm_info_node *node = (struct drm_info_node *)m->private;
 208         struct drm_device *dev = node->minor->dev;
 209         struct v3d_dev *v3d = to_v3d_dev(dev);
 210         uint32_t cycles;
 211         int core = 0;
 212         int measure_ms = 1000;
 213
 214         if (v3d->ver >= 40) {
 215                 V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3,
 216                                V3D_SET_FIELD(V3D_PCTR_CYCLE_COUNT,
 217                                              V3D_PCTR_S0));
 218                 V3D_CORE_WRITE(core, V3D_V4_PCTR_0_CLR, 1);
 219                 V3D_CORE_WRITE(core, V3D_V4_PCTR_0_EN, 1);
 220         } else {
 221                 V3D_CORE_WRITE(core, V3D_V3_PCTR_0_PCTRS0,
 222                                V3D_PCTR_CYCLE_COUNT);
 223                 V3D_CORE_WRITE(core, V3D_V3_PCTR_0_CLR, 1);
 224                 V3D_CORE_WRITE(core, V3D_V3_PCTR_0_EN,
 225                                V3D_V3_PCTR_0_EN_ENABLE |
 226                                1);
 227         }
 228         msleep(measure_ms);
 229         cycles = V3D_CORE_READ(core, V3D_PCTR_0_PCTR0);
 230
 231         seq_printf(m, "cycles: %d (%d.%d Mhz)\n",
 232                    cycles,
 233                    cycles / (measure_ms * 1000),
 234                    (cycles / (measure_ms * 100)) % 10);
 235
 236
 237         return 0;
 238 }
 239
 240 struct v3d_gem_info_data {
 241         struct drm_file *filp;
 242         struct seq_file *m;
 243 };
 244
 245 static int v3d_gem_one_info(int id, void *ptr, void *data)
 246 {
 247         struct drm_gem_object *obj = (struct drm_gem_object *)ptr;
 248         struct v3d_gem_info_data *gem_info_data = data;
 249         struct v3d_file_priv *v3d_priv = gem_info_data->filp->driver_priv;
 250         struct drm_v3d_file_private *pid_priv = &v3d_priv->priv;
 251
 252         if (!obj) {
 253                 DRM_ERROR("failed to get drm_gem_object\n");
 254                 return -EFAULT;
 255         }
 256
 257         drm_gem_object_get(obj);
 258
 259         seq_printf(gem_info_data->m,
 260                         "%5d\t%5d\t%4d\t%4d\t\t%4d\t0x%08zx\t0x%x\t%4d\t%4d\t\t"
 261                         "%4d\t\t0x%p\t%6d\n",
 262                         pid_priv->pid,
 263                         pid_priv->tgid,
 264                         id,
 265                         kref_read(&obj->refcount) - 1,
 266                         obj->handle_count,
 267                         obj->size,
 268                         0,
 269                         0,
 270                         obj->dma_buf ? 1 : 0,
 271                         obj->import_attach ? 1 : 0,
 272                         obj,
 273                         obj->name);
 274
 275         drm_gem_object_put(obj);
 276
 277         return 0;
 278 }
 279
 280 int v3d_debugfs_gem_info(struct seq_file *m, void *data)
 281 {
 282         struct drm_info_node *node = (struct drm_info_node *)m->private;
 283         struct drm_minor *minor = node->minor;
 284         struct drm_device *drm_dev = minor->dev;
 285         struct v3d_gem_info_data gem_info_data;
 286         struct drm_file *filp;
 287
 288         gem_info_data.m = m;
 289
 290         seq_puts(gem_info_data.m,
 291                         "pid\ttgid\thandle\trefcount\thcount\tsize\t\tflags\t"
 292                         "pfnmap\texport_to_fd\timport_from_fd\tobj_addr\t\t"
 293                         "name\n");
 294
 295         mutex_lock(&drm_dev->struct_mutex);
 296         list_for_each_entry(filp, &drm_dev->filelist, lhead) {
 297                 gem_info_data.filp = filp;
 298
 299                 spin_lock(&filp->table_lock);
 300                 idr_for_each(&filp->object_idr, v3d_gem_one_info,
 301                                 &gem_info_data);
 302                 spin_unlock(&filp->table_lock);
 303         }
 304         mutex_unlock(&drm_dev->struct_mutex);
 305
 306         return 0;
 307 }
 308
 309 static const struct drm_info_list v3d_debugfs_list[] = {
 310         {"v3d_ident", v3d_v3d_debugfs_ident, 0},
 311         {"v3d_regs", v3d_v3d_debugfs_regs, 0},
 312         {"measure_clock", v3d_measure_clock, 0},
 313         {"bo_stats", v3d_debugfs_bo_stats, 0},
 314         {"gpu_gem_info", v3d_debugfs_gem_info, 0},
 315 };
 316
 317 void
 318 v3d_debugfs_init(struct drm_minor *minor)
 319 {
 320         drm_debugfs_create_files(v3d_debugfs_list,
 321                                  ARRAY_SIZE(v3d_debugfs_list),
 322                                  minor->debugfs_root, minor);
 323 }