drivers/gpu/drm/tilcdc/tilcdc_drv.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 /* LCDC DRM driver, based on da8xx-fb */
  19
  20 #include <linux/component.h>
  21 #include <linux/pinctrl/consumer.h>
  22 #include <linux/suspend.h>
  23 #include <drm/drm_atomic.h>
  24 #include <drm/drm_atomic_helper.h>
  25
  26 #include "tilcdc_drv.h"
  27 #include "tilcdc_regs.h"
  28 #include "tilcdc_tfp410.h"
  29 #include "tilcdc_panel.h"
  30 #include "tilcdc_external.h"
  31
  32 #include "drm_fb_helper.h"
  33
  34 static LIST_HEAD(module_list);
  35
  36 void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
  37                 const struct tilcdc_module_ops *funcs)
  38 {
  39         mod->name = name;
  40         mod->funcs = funcs;
  41         INIT_LIST_HEAD(&mod->list);
  42         list_add(&mod->list, &module_list);
  43 }
  44
  45 void tilcdc_module_cleanup(struct tilcdc_module *mod)
  46 {
  47         list_del(&mod->list);
  48 }
  49
  50 static struct of_device_id tilcdc_of_match[];
  51
  52 static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
  53                 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
  54 {
  55         return drm_fb_cma_create(dev, file_priv, mode_cmd);
  56 }
  57
  58 static void tilcdc_fb_output_poll_changed(struct drm_device *dev)
  59 {
  60         struct tilcdc_drm_private *priv = dev->dev_private;
  61         drm_fbdev_cma_hotplug_event(priv->fbdev);
  62 }
  63
  64 int tilcdc_atomic_check(struct drm_device *dev,
  65                         struct drm_atomic_state *state)
  66 {
  67         int ret;
  68
  69         ret = drm_atomic_helper_check_modeset(dev, state);
  70         if (ret)
  71                 return ret;
  72
  73         ret = drm_atomic_helper_check_planes(dev, state);
  74         if (ret)
  75                 return ret;
  76
  77         /*
  78          * tilcdc ->atomic_check can update ->mode_changed if pixel format
  79          * changes, hence will we check modeset changes again.
  80          */
  81         ret = drm_atomic_helper_check_modeset(dev, state);
  82         if (ret)
  83                 return ret;
  84
  85         return ret;
  86 }
  87
  88 static int tilcdc_commit(struct drm_device *dev,
  89                   struct drm_atomic_state *state,
  90                   bool async)
  91 {
  92         int ret;
  93
  94         ret = drm_atomic_helper_prepare_planes(dev, state);
  95         if (ret)
  96                 return ret;
  97
  98         drm_atomic_helper_swap_state(state, true);
  99
 100         /*
 101          * Everything below can be run asynchronously without the need to grab
 102          * any modeset locks at all under one condition: It must be guaranteed
 103          * that the asynchronous work has either been cancelled (if the driver
 104          * supports it, which at least requires that the framebuffers get
 105          * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
 106          * before the new state gets committed on the software side with
 107          * drm_atomic_helper_swap_state().
 108          *
 109          * This scheme allows new atomic state updates to be prepared and
 110          * checked in parallel to the asynchronous completion of the previous
 111          * update. Which is important since compositors need to figure out the
 112          * composition of the next frame right after having submitted the
 113          * current layout.
 114          */
 115
 116         drm_atomic_helper_commit_modeset_disables(dev, state);
 117
 118         drm_atomic_helper_commit_planes(dev, state, false);
 119
 120         drm_atomic_helper_commit_modeset_enables(dev, state);
 121
 122         drm_atomic_helper_wait_for_vblanks(dev, state);
 123
 124         drm_atomic_helper_cleanup_planes(dev, state);
 125
 126         drm_atomic_state_free(state);
 127
 128         return 0;
 129 }
 130
 131 static const struct drm_mode_config_funcs mode_config_funcs = {
 132         .fb_create = tilcdc_fb_create,
 133         .output_poll_changed = tilcdc_fb_output_poll_changed,
 134         .atomic_check = tilcdc_atomic_check,
 135         .atomic_commit = tilcdc_commit,
 136 };
 137
 138 static int modeset_init(struct drm_device *dev)
 139 {
 140         struct tilcdc_drm_private *priv = dev->dev_private;
 141         struct tilcdc_module *mod;
 142
 143         drm_mode_config_init(dev);
 144
 145         priv->crtc = tilcdc_crtc_create(dev);
 146
 147         list_for_each_entry(mod, &module_list, list) {
 148                 DBG("loading module: %s", mod->name);
 149                 mod->funcs->modeset_init(mod, dev);
 150         }
 151
 152         dev->mode_config.min_width = 0;
 153         dev->mode_config.min_height = 0;
 154         dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
 155         dev->mode_config.max_height = 2048;
 156         dev->mode_config.funcs = &mode_config_funcs;
 157
 158         return 0;
 159 }
 160
 161 #ifdef CONFIG_CPU_FREQ
 162 static int cpufreq_transition(struct notifier_block *nb,
 163                                      unsigned long val, void *data)
 164 {
 165         struct tilcdc_drm_private *priv = container_of(nb,
 166                         struct tilcdc_drm_private, freq_transition);
 167         if (val == CPUFREQ_POSTCHANGE) {
 168                 if (priv->lcd_fck_rate != clk_get_rate(priv->clk)) {
 169                         priv->lcd_fck_rate = clk_get_rate(priv->clk);
 170                         tilcdc_crtc_update_clk(priv->crtc);
 171                 }
 172         }
 173
 174         return 0;
 175 }
 176 #endif
 177
 178 /*
 179  * DRM operations:
 180  */
 181
 182 static int tilcdc_unload(struct drm_device *dev)
 183 {
 184         struct tilcdc_drm_private *priv = dev->dev_private;
 185
 186         tilcdc_crtc_dpms(priv->crtc, DRM_MODE_DPMS_OFF);
 187
 188         tilcdc_remove_external_encoders(dev);
 189
 190         drm_fbdev_cma_fini(priv->fbdev);
 191         drm_kms_helper_poll_fini(dev);
 192         drm_mode_config_cleanup(dev);
 193         drm_vblank_cleanup(dev);
 194
 195         pm_runtime_get_sync(dev->dev);
 196         drm_irq_uninstall(dev);
 197         pm_runtime_put_sync(dev->dev);
 198
 199 #ifdef CONFIG_CPU_FREQ
 200         cpufreq_unregister_notifier(&priv->freq_transition,
 201                         CPUFREQ_TRANSITION_NOTIFIER);
 202 #endif
 203
 204         if (priv->clk)
 205                 clk_put(priv->clk);
 206
 207         if (priv->mmio)
 208                 iounmap(priv->mmio);
 209
 210         flush_workqueue(priv->wq);
 211         destroy_workqueue(priv->wq);
 212
 213         dev->dev_private = NULL;
 214
 215         pm_runtime_disable(dev->dev);
 216
 217         return 0;
 218 }
 219
 220 static size_t tilcdc_num_regs(void);
 221
 222 static int tilcdc_load(struct drm_device *dev, unsigned long flags)
 223 {
 224         struct platform_device *pdev = dev->platformdev;
 225         struct device_node *node = pdev->dev.of_node;
 226         struct tilcdc_drm_private *priv;
 227         struct tilcdc_module *mod;
 228         struct resource *res;
 229         u32 bpp = 0;
 230         int ret;
 231
 232         priv = devm_kzalloc(dev->dev, sizeof(*priv), GFP_KERNEL);
 233         if (priv)
 234                 priv->saved_register =
 235                         devm_kcalloc(dev->dev, tilcdc_num_regs(),
 236                                      sizeof(*priv->saved_register), GFP_KERNEL);
 237         if (!priv || !priv->saved_register) {
 238                 dev_err(dev->dev, "failed to allocate private data\n");
 239                 return -ENOMEM;
 240         }
 241
 242         dev->dev_private = priv;
 243
 244         priv->is_componentized =
 245                 tilcdc_get_external_components(dev->dev, NULL) > 0;
 246
 247         priv->wq = alloc_ordered_workqueue("tilcdc", 0);
 248         if (!priv->wq) {
 249                 ret = -ENOMEM;
 250                 goto fail_unset_priv;
 251         }
 252
 253         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 254         if (!res) {
 255                 dev_err(dev->dev, "failed to get memory resource\n");
 256                 ret = -EINVAL;
 257                 goto fail_free_wq;
 258         }
 259
 260         priv->mmio = ioremap_nocache(res->start, resource_size(res));
 261         if (!priv->mmio) {
 262                 dev_err(dev->dev, "failed to ioremap\n");
 263                 ret = -ENOMEM;
 264                 goto fail_free_wq;
 265         }
 266
 267         priv->clk = clk_get(dev->dev, "fck");
 268         if (IS_ERR(priv->clk)) {
 269                 dev_err(dev->dev, "failed to get functional clock\n");
 270                 ret = -ENODEV;
 271                 goto fail_iounmap;
 272         }
 273
 274 #ifdef CONFIG_CPU_FREQ
 275         priv->lcd_fck_rate = clk_get_rate(priv->clk);
 276         priv->freq_transition.notifier_call = cpufreq_transition;
 277         ret = cpufreq_register_notifier(&priv->freq_transition,
 278                         CPUFREQ_TRANSITION_NOTIFIER);
 279         if (ret) {
 280                 dev_err(dev->dev, "failed to register cpufreq notifier\n");
 281                 goto fail_put_clk;
 282         }
 283 #endif
 284
 285         if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
 286                 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
 287
 288         DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
 289
 290         if (of_property_read_u32(node, "ti,max-width", &priv->max_width))
 291                 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
 292
 293         DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
 294
 295         if (of_property_read_u32(node, "ti,max-pixelclock",
 296                                         &priv->max_pixelclock))
 297                 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
 298
 299         DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
 300
 301         pm_runtime_enable(dev->dev);
 302
 303         /* Determine LCD IP Version */
 304         pm_runtime_get_sync(dev->dev);
 305         switch (tilcdc_read(dev, LCDC_PID_REG)) {
 306         case 0x4c100102:
 307                 priv->rev = 1;
 308                 break;
 309         case 0x4f200800:
 310         case 0x4f201000:
 311                 priv->rev = 2;
 312                 break;
 313         default:
 314                 dev_warn(dev->dev, "Unknown PID Reg value 0x%08x, "
 315                                 "defaulting to LCD revision 1\n",
 316                                 tilcdc_read(dev, LCDC_PID_REG));
 317                 priv->rev = 1;
 318                 break;
 319         }
 320
 321         pm_runtime_put_sync(dev->dev);
 322
 323         ret = modeset_init(dev);
 324         if (ret < 0) {
 325                 dev_err(dev->dev, "failed to initialize mode setting\n");
 326                 goto fail_cpufreq_unregister;
 327         }
 328
 329         platform_set_drvdata(pdev, dev);
 330
 331         if (priv->is_componentized) {
 332                 ret = component_bind_all(dev->dev, dev);
 333                 if (ret < 0)
 334                         goto fail_mode_config_cleanup;
 335
 336                 ret = tilcdc_add_external_encoders(dev, &bpp);
 337                 if (ret < 0)
 338                         goto fail_component_cleanup;
 339         }
 340
 341         if ((priv->num_encoders == 0) || (priv->num_connectors == 0)) {
 342                 dev_err(dev->dev, "no encoders/connectors found\n");
 343                 ret = -ENXIO;
 344                 goto fail_external_cleanup;
 345         }
 346
 347         ret = drm_vblank_init(dev, 1);
 348         if (ret < 0) {
 349                 dev_err(dev->dev, "failed to initialize vblank\n");
 350                 goto fail_external_cleanup;
 351         }
 352
 353         pm_runtime_get_sync(dev->dev);
 354         ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0));
 355         pm_runtime_put_sync(dev->dev);
 356         if (ret < 0) {
 357                 dev_err(dev->dev, "failed to install IRQ handler\n");
 358                 goto fail_vblank_cleanup;
 359         }
 360
 361         list_for_each_entry(mod, &module_list, list) {
 362                 DBG("%s: preferred_bpp: %d", mod->name, mod->preferred_bpp);
 363                 bpp = mod->preferred_bpp;
 364                 if (bpp > 0)
 365                         break;
 366         }
 367
 368         drm_helper_disable_unused_functions(dev);
 369         priv->fbdev = drm_fbdev_cma_init(dev, bpp,
 370                         dev->mode_config.num_crtc,
 371                         dev->mode_config.num_connector);
 372         if (IS_ERR(priv->fbdev)) {
 373                 ret = PTR_ERR(priv->fbdev);
 374                 goto fail_irq_uninstall;
 375         }
 376
 377         drm_kms_helper_poll_init(dev);
 378
 379         return 0;
 380
 381 fail_irq_uninstall:
 382         pm_runtime_get_sync(dev->dev);
 383         drm_irq_uninstall(dev);
 384         pm_runtime_put_sync(dev->dev);
 385
 386 fail_vblank_cleanup:
 387         drm_vblank_cleanup(dev);
 388
 389 fail_mode_config_cleanup:
 390         drm_mode_config_cleanup(dev);
 391
 392 fail_component_cleanup:
 393         if (priv->is_componentized)
 394                 component_unbind_all(dev->dev, dev);
 395
 396 fail_external_cleanup:
 397         tilcdc_remove_external_encoders(dev);
 398
 399 fail_cpufreq_unregister:
 400         pm_runtime_disable(dev->dev);
 401 #ifdef CONFIG_CPU_FREQ
 402         cpufreq_unregister_notifier(&priv->freq_transition,
 403                         CPUFREQ_TRANSITION_NOTIFIER);
 404
 405 fail_put_clk:
 406 #endif
 407         clk_put(priv->clk);
 408
 409 fail_iounmap:
 410         iounmap(priv->mmio);
 411
 412 fail_free_wq:
 413         flush_workqueue(priv->wq);
 414         destroy_workqueue(priv->wq);
 415
 416 fail_unset_priv:
 417         dev->dev_private = NULL;
 418
 419         return ret;
 420 }
 421
 422 static void tilcdc_lastclose(struct drm_device *dev)
 423 {
 424         struct tilcdc_drm_private *priv = dev->dev_private;
 425         drm_fbdev_cma_restore_mode(priv->fbdev);
 426 }
 427
 428 static irqreturn_t tilcdc_irq(int irq, void *arg)
 429 {
 430         struct drm_device *dev = arg;
 431         struct tilcdc_drm_private *priv = dev->dev_private;
 432         return tilcdc_crtc_irq(priv->crtc);
 433 }
 434
 435 static void tilcdc_irq_preinstall(struct drm_device *dev)
 436 {
 437         tilcdc_clear_irqstatus(dev, 0xffffffff);
 438 }
 439
 440 static int tilcdc_irq_postinstall(struct drm_device *dev)
 441 {
 442         struct tilcdc_drm_private *priv = dev->dev_private;
 443
 444         /* enable FIFO underflow irq: */
 445         if (priv->rev == 1) {
 446                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_UNDERFLOW_INT_ENA);
 447         } else {
 448                 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG,
 449                            LCDC_V2_UNDERFLOW_INT_ENA |
 450                            LCDC_V2_END_OF_FRAME0_INT_ENA |
 451                            LCDC_FRAME_DONE | LCDC_SYNC_LOST);
 452         }
 453
 454         return 0;
 455 }
 456
 457 static void tilcdc_irq_uninstall(struct drm_device *dev)
 458 {
 459         struct tilcdc_drm_private *priv = dev->dev_private;
 460
 461         /* disable irqs that we might have enabled: */
 462         if (priv->rev == 1) {
 463                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
 464                                 LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA);
 465                 tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_V1_END_OF_FRAME_INT_ENA);
 466         } else {
 467                 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
 468                         LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA |
 469                         LCDC_V2_END_OF_FRAME0_INT_ENA |
 470                         LCDC_FRAME_DONE | LCDC_SYNC_LOST);
 471         }
 472 }
 473
 474 static int tilcdc_enable_vblank(struct drm_device *dev, unsigned int pipe)
 475 {
 476         return 0;
 477 }
 478
 479 static void tilcdc_disable_vblank(struct drm_device *dev, unsigned int pipe)
 480 {
 481         return;
 482 }
 483
 484 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_PM_SLEEP)
 485 static const struct {
 486         const char *name;
 487         uint8_t  rev;
 488         uint8_t  save;
 489         uint32_t reg;
 490 } registers[] =         {
 491 #define REG(rev, save, reg) { #reg, rev, save, reg }
 492                 /* exists in revision 1: */
 493                 REG(1, false, LCDC_PID_REG),
 494                 REG(1, true,  LCDC_CTRL_REG),
 495                 REG(1, false, LCDC_STAT_REG),
 496                 REG(1, true,  LCDC_RASTER_CTRL_REG),
 497                 REG(1, true,  LCDC_RASTER_TIMING_0_REG),
 498                 REG(1, true,  LCDC_RASTER_TIMING_1_REG),
 499                 REG(1, true,  LCDC_RASTER_TIMING_2_REG),
 500                 REG(1, true,  LCDC_DMA_CTRL_REG),
 501                 REG(1, true,  LCDC_DMA_FB_BASE_ADDR_0_REG),
 502                 REG(1, true,  LCDC_DMA_FB_CEILING_ADDR_0_REG),
 503                 REG(1, true,  LCDC_DMA_FB_BASE_ADDR_1_REG),
 504                 REG(1, true,  LCDC_DMA_FB_CEILING_ADDR_1_REG),
 505                 /* new in revision 2: */
 506                 REG(2, false, LCDC_RAW_STAT_REG),
 507                 REG(2, false, LCDC_MASKED_STAT_REG),
 508                 REG(2, true, LCDC_INT_ENABLE_SET_REG),
 509                 REG(2, false, LCDC_INT_ENABLE_CLR_REG),
 510                 REG(2, false, LCDC_END_OF_INT_IND_REG),
 511                 REG(2, true,  LCDC_CLK_ENABLE_REG),
 512 #undef REG
 513 };
 514
 515 static size_t tilcdc_num_regs(void)
 516 {
 517         return ARRAY_SIZE(registers);
 518 }
 519 #else
 520 static size_t tilcdc_num_regs(void)
 521 {
 522         return 0;
 523 }
 524 #endif
 525
 526 #ifdef CONFIG_DEBUG_FS
 527 static int tilcdc_regs_show(struct seq_file *m, void *arg)
 528 {
 529         struct drm_info_node *node = (struct drm_info_node *) m->private;
 530         struct drm_device *dev = node->minor->dev;
 531         struct tilcdc_drm_private *priv = dev->dev_private;
 532         unsigned i;
 533
 534         pm_runtime_get_sync(dev->dev);
 535
 536         seq_printf(m, "revision: %d\n", priv->rev);
 537
 538         for (i = 0; i < ARRAY_SIZE(registers); i++)
 539                 if (priv->rev >= registers[i].rev)
 540                         seq_printf(m, "%s:\t %08x\n", registers[i].name,
 541                                         tilcdc_read(dev, registers[i].reg));
 542
 543         pm_runtime_put_sync(dev->dev);
 544
 545         return 0;
 546 }
 547
 548 static int tilcdc_mm_show(struct seq_file *m, void *arg)
 549 {
 550         struct drm_info_node *node = (struct drm_info_node *) m->private;
 551         struct drm_device *dev = node->minor->dev;
 552         return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
 553 }
 554
 555 static struct drm_info_list tilcdc_debugfs_list[] = {
 556                 { "regs", tilcdc_regs_show, 0 },
 557                 { "mm",   tilcdc_mm_show,   0 },
 558                 { "fb",   drm_fb_cma_debugfs_show, 0 },
 559 };
 560
 561 static int tilcdc_debugfs_init(struct drm_minor *minor)
 562 {
 563         struct drm_device *dev = minor->dev;
 564         struct tilcdc_module *mod;
 565         int ret;
 566
 567         ret = drm_debugfs_create_files(tilcdc_debugfs_list,
 568                         ARRAY_SIZE(tilcdc_debugfs_list),
 569                         minor->debugfs_root, minor);
 570
 571         list_for_each_entry(mod, &module_list, list)
 572                 if (mod->funcs->debugfs_init)
 573                         mod->funcs->debugfs_init(mod, minor);
 574
 575         if (ret) {
 576                 dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
 577                 return ret;
 578         }
 579
 580         return ret;
 581 }
 582
 583 static void tilcdc_debugfs_cleanup(struct drm_minor *minor)
 584 {
 585         struct tilcdc_module *mod;
 586         drm_debugfs_remove_files(tilcdc_debugfs_list,
 587                         ARRAY_SIZE(tilcdc_debugfs_list), minor);
 588
 589         list_for_each_entry(mod, &module_list, list)
 590                 if (mod->funcs->debugfs_cleanup)
 591                         mod->funcs->debugfs_cleanup(mod, minor);
 592 }
 593 #endif
 594
 595 static const struct file_operations fops = {
 596         .owner              = THIS_MODULE,
 597         .open               = drm_open,
 598         .release            = drm_release,
 599         .unlocked_ioctl     = drm_ioctl,
 600 #ifdef CONFIG_COMPAT
 601         .compat_ioctl       = drm_compat_ioctl,
 602 #endif
 603         .poll               = drm_poll,
 604         .read               = drm_read,
 605         .llseek             = no_llseek,
 606         .mmap               = drm_gem_cma_mmap,
 607 };
 608
 609 static struct drm_driver tilcdc_driver = {
 610         .driver_features    = (DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET |
 611                                DRIVER_PRIME),
 612         .load               = tilcdc_load,
 613         .unload             = tilcdc_unload,
 614         .lastclose          = tilcdc_lastclose,
 615         .irq_handler        = tilcdc_irq,
 616         .irq_preinstall     = tilcdc_irq_preinstall,
 617         .irq_postinstall    = tilcdc_irq_postinstall,
 618         .irq_uninstall      = tilcdc_irq_uninstall,
 619         .get_vblank_counter = drm_vblank_no_hw_counter,
 620         .enable_vblank      = tilcdc_enable_vblank,
 621         .disable_vblank     = tilcdc_disable_vblank,
 622         .gem_free_object_unlocked = drm_gem_cma_free_object,
 623         .gem_vm_ops         = &drm_gem_cma_vm_ops,
 624         .dumb_create        = drm_gem_cma_dumb_create,
 625         .dumb_map_offset    = drm_gem_cma_dumb_map_offset,
 626         .dumb_destroy       = drm_gem_dumb_destroy,
 627
 628         .prime_handle_to_fd     = drm_gem_prime_handle_to_fd,
 629         .prime_fd_to_handle     = drm_gem_prime_fd_to_handle,
 630         .gem_prime_import       = drm_gem_prime_import,
 631         .gem_prime_export       = drm_gem_prime_export,
 632         .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
 633         .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
 634         .gem_prime_vmap         = drm_gem_cma_prime_vmap,
 635         .gem_prime_vunmap       = drm_gem_cma_prime_vunmap,
 636         .gem_prime_mmap         = drm_gem_cma_prime_mmap,
 637 #ifdef CONFIG_DEBUG_FS
 638         .debugfs_init       = tilcdc_debugfs_init,
 639         .debugfs_cleanup    = tilcdc_debugfs_cleanup,
 640 #endif
 641         .fops               = &fops,
 642         .name               = "tilcdc",
 643         .desc               = "TI LCD Controller DRM",
 644         .date               = "20121205",
 645         .major              = 1,
 646         .minor              = 0,
 647 };
 648
 649 /*
 650  * Power management:
 651  */
 652
 653 #ifdef CONFIG_PM_SLEEP
 654 static int tilcdc_pm_suspend(struct device *dev)
 655 {
 656         struct drm_device *ddev = dev_get_drvdata(dev);
 657         struct tilcdc_drm_private *priv = ddev->dev_private;
 658         unsigned i, n = 0;
 659
 660         drm_kms_helper_poll_disable(ddev);
 661
 662         /* Select sleep pin state */
 663         pinctrl_pm_select_sleep_state(dev);
 664
 665         if (pm_runtime_suspended(dev)) {
 666                 priv->ctx_valid = false;
 667                 return 0;
 668         }
 669
 670         /* Disable the LCDC controller, to avoid locking up the PRCM */
 671         priv->saved_dpms_state = tilcdc_crtc_current_dpms_state(priv->crtc);
 672         tilcdc_crtc_dpms(priv->crtc, DRM_MODE_DPMS_OFF);
 673
 674         /* Save register state: */
 675         for (i = 0; i < ARRAY_SIZE(registers); i++)
 676                 if (registers[i].save && (priv->rev >= registers[i].rev))
 677                         priv->saved_register[n++] = tilcdc_read(ddev, registers[i].reg);
 678
 679         priv->ctx_valid = true;
 680
 681         return 0;
 682 }
 683
 684 static int tilcdc_pm_resume(struct device *dev)
 685 {
 686         struct drm_device *ddev = dev_get_drvdata(dev);
 687         struct tilcdc_drm_private *priv = ddev->dev_private;
 688         unsigned i, n = 0;
 689
 690         /* Select default pin state */
 691         pinctrl_pm_select_default_state(dev);
 692
 693         if (priv->ctx_valid == true) {
 694                 /* Restore register state: */
 695                 for (i = 0; i < ARRAY_SIZE(registers); i++)
 696                         if (registers[i].save &&
 697                             (priv->rev >= registers[i].rev))
 698                                 tilcdc_write(ddev, registers[i].reg,
 699                                              priv->saved_register[n++]);
 700         }
 701
 702         tilcdc_crtc_dpms(priv->crtc, priv->saved_dpms_state);
 703
 704         drm_kms_helper_poll_enable(ddev);
 705
 706         return 0;
 707 }
 708 #endif
 709
 710 static const struct dev_pm_ops tilcdc_pm_ops = {
 711         SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
 712 };
 713
 714 /*
 715  * Platform driver:
 716  */
 717
 718 static int tilcdc_bind(struct device *dev)
 719 {
 720         return drm_platform_init(&tilcdc_driver, to_platform_device(dev));
 721 }
 722
 723 static void tilcdc_unbind(struct device *dev)
 724 {
 725         struct drm_device *ddev = dev_get_drvdata(dev);
 726
 727         /* Check if a subcomponent has already triggered the unloading. */
 728         if (!ddev->dev_private)
 729                 return;
 730
 731         drm_put_dev(dev_get_drvdata(dev));
 732 }
 733
 734 static const struct component_master_ops tilcdc_comp_ops = {
 735         .bind = tilcdc_bind,
 736         .unbind = tilcdc_unbind,
 737 };
 738
 739 static int tilcdc_pdev_probe(struct platform_device *pdev)
 740 {
 741         struct component_match *match = NULL;
 742         int ret;
 743
 744         /* bail out early if no DT data: */
 745         if (!pdev->dev.of_node) {
 746                 dev_err(&pdev->dev, "device-tree data is missing\n");
 747                 return -ENXIO;
 748         }
 749
 750         ret = tilcdc_get_external_components(&pdev->dev, &match);
 751         if (ret < 0)
 752                 return ret;
 753         else if (ret == 0)
 754                 return drm_platform_init(&tilcdc_driver, pdev);
 755         else
 756                 return component_master_add_with_match(&pdev->dev,
 757                                                        &tilcdc_comp_ops,
 758                                                        match);
 759 }
 760
 761 static int tilcdc_pdev_remove(struct platform_device *pdev)
 762 {
 763         int ret;
 764
 765         ret = tilcdc_get_external_components(&pdev->dev, NULL);
 766         if (ret < 0)
 767                 return ret;
 768         else if (ret == 0)
 769                 drm_put_dev(platform_get_drvdata(pdev));
 770         else
 771                 component_master_del(&pdev->dev, &tilcdc_comp_ops);
 772
 773         return 0;
 774 }
 775
 776 static struct of_device_id tilcdc_of_match[] = {
 777                 { .compatible = "ti,am33xx-tilcdc", },
 778                 { },
 779 };
 780 MODULE_DEVICE_TABLE(of, tilcdc_of_match);
 781
 782 static struct platform_driver tilcdc_platform_driver = {
 783         .probe      = tilcdc_pdev_probe,
 784         .remove     = tilcdc_pdev_remove,
 785         .driver     = {
 786                 .name   = "tilcdc",
 787                 .pm     = &tilcdc_pm_ops,
 788                 .of_match_table = tilcdc_of_match,
 789         },
 790 };
 791
 792 static int __init tilcdc_drm_init(void)
 793 {
 794         DBG("init");
 795         tilcdc_tfp410_init();
 796         tilcdc_panel_init();
 797         return platform_driver_register(&tilcdc_platform_driver);
 798 }
 799
 800 static void __exit tilcdc_drm_fini(void)
 801 {
 802         DBG("fini");
 803         platform_driver_unregister(&tilcdc_platform_driver);
 804         tilcdc_panel_fini();
 805         tilcdc_tfp410_fini();
 806 }
 807
 808 module_init(tilcdc_drm_init);
 809 module_exit(tilcdc_drm_fini);
 810
 811 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
 812 MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
 813 MODULE_LICENSE("GPL");